KR19980014838A - PCM format conversion device in PABX - Google Patents

Abstract

The present invention relates to a PCM format (Pulse Code Modulation Format) converter in a PABX. More particularly, the present invention relates to an apparatus for converting a PCM format into an identical format without delaying a time slot, To a PCM format conversion apparatus in a private branch exchange.

Conventional PABXs have difficulty in interfacing with each other in the case of using different coding schemes and have to be performed using an additional device after PCM conversion in order to interface with each other, .

According to the present invention, it is possible to convert the PCM format of the Arow or Murow format to enable an interface between PBXs using different formats without delaying time slots, so that no additional operation is required after PCM conversion, Of PCM can be accommodated at the same time.

Description

PCM format conversion device in PABX

The present invention relates to a PCM format (Pulse Code Modulation Format) converter in a PABX. More particularly, the present invention relates to an apparatus for converting a PCM format into an identical format without delaying a time slot, To a PCM format conversion apparatus in a private branch exchange.

Generally, the PCM is a modulation scheme that quantizes the amplitude of a signal wave and emits a pulse according to a binary code by displaying the quantized number in a binary notation. The PCM is a modulation scheme for Sampling, Quantizing, Encoding . According to the Nyquist theorem in the sampling step during the three steps, if the analog signal which is greatly limited is sampled at a rate more than twice the highest frequency, the original analog signal can be reproduced from the sampled pulse signal. The sampled value is coded with a digital number. There are two coding schemes, A-law and μ-law.

In this way, PCM is most advantageous for signal transmission through noisy channel because it can precisely reproduce one original digital signal that can discriminate `1 'and` 0' even if some noise is mixed. In particular, even if the S / N ratio is low due to attenuation of the signal in long-distance transmission, repeaters can be restrained at a certain distance to recover the original clean PCM signal. As a result, It is the most excellent and widely used.

However, in the conventional PABX, it is difficult to interfere with each other in the case of using different coding schemes. In order to interface with each other, it is necessary to perform the PCM conversion using an additional device after the conversion, .

In order to solve the above problems, the present invention can convert the PCM format into the same format without delaying the interface between the PBXs using different formats, so that no additional operation is required after the PCM conversion, Which can accommodate two types of PCM at the same time.

According to an aspect of the present invention, A serial / parallel shift register which receives the first clock signal and converts parallel serial PCM data of the input aurate or murow type into parallel and outputs parallel PCM data bits; A flip-flop that receives a second clock signal and simultaneously receives parallel PCM data bits input from the serial / parallel shift register; A tri-state buffer receiving the third clock signal and simultaneously outputting the latched parallel PCM data bits input through odd-numbered and eighth output terminals of the flip-flop; A tri-state inverter receiving the third clock signal and inverting the parallel PCM data bits input through even-numbered output terminals except for the eighth bit of the flip-flop, and outputting the inverted parallel PCM data bits; State buffer and a 3-state inverter, receives a third clock signal, stores a signal input from the 3-state buffer and the 3-state inverter, receives an address clock signal, and stores 32 time slots at each address; And outputs the generated first clock signal to the serial / parallel shift register, generates the second clock signal, and outputs the generated first clock signal to the flip- Flop for generating the third clock signal, outputting the third clock signal to the tri-state buffer and the tri-state inverter, and generating and outputting the fourth clock signal; And a bottleneck / serial shift register which receives the clock signal and a fourth clock signal input from the clock generator, loads stored data bits input from the RAM into serial PCM data, and outputs the serial PCM data.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration circuit diagram showing an apparatus for converting a PCM format in a PABX according to an embodiment of the present invention; FIG.

2 is a timing diagram of a PCM format conversion apparatus in a private branch exchange according to an embodiment of the present invention;

Description of the Related Art [0002]

11: serial / parallel shift register 12: flip-flop

13: 3 state buffer 14: 3 state inverter

15: RAM 16: Bottle / serial shift register

17: Clock generator

Hereinafter, the present invention will be described with reference to the accompanying drawings.

2 is a timing diagram of a PCM format conversion apparatus in a PABX according to an exemplary embodiment of the present invention; FIG. 2 is a timing diagram of a PCM format conversion apparatus in a PABX according to an embodiment of the present invention; FIG.

As shown in FIG. 1, the apparatus for converting a PCM format in a PABX according to an embodiment of the present invention includes a serial / parallel shift register 11, a flip flop 12, a tri-state buffer 13, A state inverter 14, a RAM 15, a bottle / serial shift register 16, and a clock generator 17.

The serial / parallel shift register 11 has a power supply terminal B, an input terminal IN, a clock terminal CLK and eight output terminals OUT0 to OUT7. And receives the first clock signal CK1 through the corresponding clock terminal CLK and receives the serial PCM data PCMIN in the form of an Arow or Murow input through the corresponding input terminal IN in parallel And outputs the parallel PCM data bits through the corresponding eight output terminals (OUT0 to OUT7).

The flip-flop 12 has a ground terminal G, a clock terminal CLK, eight input terminals IN1 to IN8 and eight output terminals OUT1 to OUT8. The second clock signal / CK2 is received through the corresponding clock terminal CLK and is input to the corresponding eight input terminals IN1 to IN8 at the rising time of the second clock signal / Parallel shift register 11 from the serial / parallel shift register 11 and latches the parallel PCM data bits through the eight output terminals OUT1 to OUT8 at the same time.

The tri-state buffer 13 receives the odd-numbered and eighth output terminals OUT1, OUT3, OUT5, OUT7 and OUT8 of the flip-flop 12 when the input third clock signal / CK3 is a low- ) Of the parallel PCM data bits.

When the input third clock signal / CK3 is a low level signal, the tri-state inverter 14 outputs the even-numbered output terminals OUT2, OUT4, and OUT6 except the eighth output terminal OUT2 of the flip- And simultaneously outputs the inverted parallel PCM data bits.

The RAM 15 has a grounded output enable terminal / OE, a chip select terminal / CS, a write terminal / WR, eight data terminals D0 to D7, and five address terminals A0- State buffer through the corresponding eight data terminals D0 to D7 when the third clock signal / CK3 input through the corresponding write terminal / WR is a low level signal, 13 and the 3-state inverter 14 and receives the address clock signals Q1 to Q5 through the 5 address terminals A0 to A4 to store 32 time slots at each address, And outputs a stored data bit when the third clock signal / CK3 inputted through the corresponding write terminal / WR is a signal of a `high` level.

The clock generator 17 receives the time slot signal / FH and the clock signal 2M to generate the clock signals Q1 to Q5, CK1 and / CK2 to / CK4. The address clock signals Q1- Q5 to the RAM 15 and outputs the first clock signal CK1 to the serial / parallel shift register 11 and the second clock signal / CK2 to the flip-flop 12 And outputs the third clock signal / CK3 to the tri-state buffer 13 and the tri-state inverter 14 and outputs the fourth clock signal / CK4.

The bottleneck / serial shift register 16 has a clock terminal CLK, a load terminal LD, eight input terminals IN0 to IN7, a serial input terminal SERIN and an output terminal OUT, Receives the clock signal 2M through the terminal CLK and receives the stored data bit from the eighth data terminal D7 of the RAM 15 through the corresponding serial input terminal SERIN, When the fourth clock signal / CK4 input from the clock generator 17 is a low level signal through the input terminals IN0 to IN7 of the RAM 15, And converts it into serial PCM data PCMOUT and outputs it through the corresponding output terminal OUT.

The operation of the PCM format conversion apparatus in the private branch exchange according to the embodiment of the present invention will be described as follows.

First, a power supply terminal B, an input terminal IN, a clock terminal CLK, and eight output terminals OUT0 to OUT7 (not shown) are connected in parallel to convert serial PCM data PCMIN inputted in the Arow or Murow form into parallel. The serial / parallel shift register 11 having the input / output terminal receives the power supply Vcc through the corresponding power terminal B and receives the first clock signal CK1 through the corresponding clock terminal CLK, Converts the parallel PCM data PCMIN inputted through the input IN to parallel and outputs the parallel PCM data bits to the flip-flop 12 through the corresponding eight output terminals OUT0 to OUT7. The clock generator 17 generates a clock signal required for converting the PCM data by receiving the time slot signal / FH and the clock signal 2M. The clock generator 17 generates the address clock signals Q1 to Q5, And outputs the first clock signal CK1 to the serial / parallel shift register 11 and the second clock signal / CK2 to the flip flop 12 and outputs the third clock signal / / CK3 to the tri-state buffer 13 and the tri-state inverter 14 to generate the fourth clock signal / CK4 and outputs the fourth clock signal / CK4 to the bottleneck / serial shift register 16.

The flip flop 12 having the ground terminal G, the clock terminal CLK, the eight input terminals IN1 to IN8 and the eight output terminals OUT1 to OUT8 is connected to the corresponding clock terminal CLK, CK2 from the serial / parallel shift register 11 through eight input terminals IN1 to IN8 at the rising time of the second clock signal / CK2 through the parallel PCM / The parallel PCM data bits are simultaneously output to the three-state buffer 13 and the three-state buffer 13 through the eight output terminals OUT1 to OUT8 after the rise time of the second clock signal / CK2, And is output to the inverter 14.

Accordingly, in order to convert to the Arow or Murow form, the tri-state buffer 13 receives the third clock signal / CK3 and the parallel PCM data bits latched from the flip-flop 12, When the third clock signal / CK3 is a signal of a low level, the decoded parallel PCM data inputted through odd-numbered and eighth output terminals OUT1, OUT3, OUT5, OUT7 and OUT8 of the flip- Bit to the RAM 15 at the same time. The 3-state inverter 14 receives the third clock signal / CK3 and the parallel PCM data bits latched from the flip-flop 12. The third clock signal / CK3 is input to the low- Level, the inverted parallel PCM data bits inputted through the even-numbered output terminals OUT2, OUT4 and OUT6 except for the eighth bit of the flip-flop 12 are inverted and output to the corresponding RAM 15 at the same time.

In this way, the grounded output enable terminal / OE, chip select terminal / CS, write terminal / WR, eight data terminals D0 to D7, and five address terminals A0 to A4 The ram 15 provided is connected to the data terminal D0 through D7 through the corresponding eight data terminals D0 through D7 when the third clock signal / CK3 input through the corresponding write terminal / WR is a low level signal. State buffer 13 and the signal input from the tri-state inverter 14 are stored. The address of the RAM 15 is input to the address clock signals Q1 to Q5 generated from the clock generator 17 through the corresponding five address terminals A0 to A4, / RTI >

The output of the stored data bits is the data bit stored before 125 (μs), which is one frame, to the recording terminal (/ WR) when an address synchronized with the PCM data is selected at the start of the new frame, And the third clock signal / CK3 input through the first input / output terminal is a signal of a high level, and is input to the bottleneck / serial shift register 16. 2, for example, the address of the RAM 15 becomes `00000` when the address clock signals Q1 to Q5 of the clock generator 17 are all` low` level signals And the data of the time slot 0 stored in the RAM 15 is output one frame before the third clock signal / CK3 is at the high level, When the clock signal (/ CK3) switches to the low level, the PCM data bits of time slot 0 of the current frame are stored. If the address of the RAM 15 is `11111`, the address clock signals Q1 to Q5 of the clock generator 17 are all` high` level signals, and the 32nd time slot is selected at this time .

The bottleneck / serial shift register 16 having a clock terminal CLK, a load terminal LD, eight input terminals IN0 to IN7, a serial input terminal SERIN and an output terminal OUT, Receives the clock signal 2M through the corresponding clock terminal CLK and receives the fourth clock signal / CK4 from the clock generator 17 through the corresponding load terminal LD, IN0 to IN7 and receives data stored in the eighth data terminal D7 of the RAM 15 through a corresponding serial input terminal SERIN. When the fourth clock signal / CK4 input from the clock generator 17 through the load terminal LD is a low level signal, the ram 15 is connected to the eight input terminals IN0- Is loaded and converted into serial PCM data, The output from the (OUT).

By doing so, the PCM format is switched and output without delay of the time slot. If a PGA (Programmable Gate Array) or ASIC (Application Specific Integrated Curcuit) is formed into a single chip, it can be applied to any system using PCM data.

As described above, according to the present invention, it is possible to convert the PCM format of the Arow or Murow format to enable an interface between the PBXs using different formats without delaying the time slots, Two types of PCM can be accommodated simultaneously.

Claims (1)

A PCM format conversion apparatus in a private switchboard, the apparatus comprising: A serial / parallel shift register (11) receiving the first clock signal (CK1) and converting serial PCM data (PCMIN) in the form of input or output signals in parallel, and outputting parallel PCM data bits; A flip-flop 12 for receiving parallel PCM data bits input from the serial / parallel shift register 11 and receiving the second clock signal / CK2; And receives the third clock signal / CK3 and simultaneously outputs the parallel PCM data bits input through the odd-numbered and eighth output terminals OUT1, OUT3, OUT5, OUT7 and OUT8 of the flip-flop 12 A tri-state buffer 13; The parallel PCM data bits inputted through the even-numbered output terminals OUT2, OUT4 and OUT6 except for the eighth bit of the flip-flop 12 are inverted and output simultaneously by receiving the third clock signal / CK3 A three-state inverter 14; State buffer 13 and the tri-state inverter 14 by receiving the third clock signal / CK3 and receives the address clock signals Q1 to Q5 to receive 32 time slots, A random access memory (RAM) 15 for storing the address; Generates the address clock signals (Q1 to Q5) and outputs the address clock signals (Q1 to Q5) to the RAM (15) by receiving the time slot signal / FH and the clock signal (2M), generates the first clock signal (CK1) / Parallel shift register 11 and generates the second clock signal / CK2 to the flip flop 12 and generates the third clock signal / CK3 to generate the third state signal / A clock generator 17 for outputting the fourth clock signal / CK4 to the tri-state inverter 14 and generating and outputting the fourth clock signal / CK4; The clock signal 2M and the fourth clock signal / CK4 input from the clock generator 17 are inputted and the stored data bits input from the RAM 15 are loaded and converted into serial PCM data PCMOUT And a bottleneck / serial shift register (16) for outputting the serial / parallel shift register (16).