KR19980014393A - How to configure the memory cell array - Google Patents

Abstract

The present invention relates to a method for constructing a memory cell array for reducing a loading effect. The contact size of the cell array and the contact size of the portion contacting the core portion are designed differently to compensate for the effect of the loading effect And a method of manufacturing the semiconductor memory device. A method of configuring a memory cell array of a semiconductor memory device includes forming a plurality of memory cell arrays with memory cells having two contacts of the same size and in order to compensate for the effect of the loading effect, And is configured as a memory cell having two contacts of different sizes.

Description

How to configure the memory cell array

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method of configuring a memory cell array to reduce a loading effect.

2. Description of the Related Art [0002] In recent years, as a semiconductor memory device has become more highly integrated and the cell area has been further reduced, contacts formed for intra-cell interlayer connection are gradually scaled down, A difference in contact size is generated between the contact portions. This phenomenon is attributed to the fact that the pattern is dense at the continuous portion of the cell array, so that the effect of the loading effect is less and the spacing of the pattern at the portion contacting the core portion is widened. It happens because of receiving.

This loading effect will be examined through the first appendix 3.

First, FIG. 1 shows a basic cell of a general static RAM.

Referring to FIG. 1, the memory cell MC1 includes high resistance load elements R1 and R2, an n-channel type driving MOSFET Q3 and Q4, and an n channel type transfer MOSFET Q1 and Q2. One end of each of the high-resistance load elements R1 and R2 is supplied with a power supply voltage and the other end thereof is connected to the drain terminals of the transistors Q3 and Q4. The source terminals of the transistors Q3 and Q4 are connected to a ground voltage. The gate terminal of the transistor Q3 is commonly connected to the node N2 which is the junction point of the high-resistance element R2 and the transistor Q4. The gate terminal of the transistor Q4 is commonly connected to the node N1 which is the junction point of the high-resistance element R1 and the transistor Q3. The current path of the MOSFET Q1 is connected between the bit line BL and the node N1, and the gate is connected to the word line WL. The current path of the transistor Q2 is connected to the bit line And the node N2, and the gate is connected to the word line WL. The nodes N1 and N2 have complementary data, and when the transistors Q1 and Q2 are turned on, the complementary data is coupled to the bit line BL, . Such a memory cell is called a 4-transistor type static memory cell.

Fig. 2 is a view showing the layout of Fig. 1 constructed in accordance with the prior art. As can be seen in the drawing, the sizes of the contacts 201 and 202 are the same. It can be seen that the gate poly GP is laid symmetrically on the active area.

FIG. 3 is a view showing an example of the structure and core of a memory cell array using FIG. 2. FIG. Referring to FIG. 3, in a portion where the memory cell array is continuous, a contact size change is small, and a contact is reduced at a portion connected to a strapping line. In the worst case, it occurs up to not open. This is because when the device becomes inoperable or becomes inoperable in the memory device, for example, a cell data error occurs due to an increase in the contact resistance value caused by a defect in the memory device or a size thereof There is no margin.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method of manufacturing a semiconductor memory device capable of improving defective devices and improving reliability.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of compensating for the influence of a loading effect by designing a contact size at a continuous portion of the cell array and a contact size at a portion contacting the core portion differently .

1 is an equivalent circuit diagram showing a basic cell of a general static RAM.

Fig. 2 shows the layout of the circuit shown in Fig. 1 according to the prior art; Fig.

FIG. 3 illustrates a memory cell array according to an embodiment of the prior art; FIG.

Figure 4 shows the layout of the circuit shown in Figure 1 in accordance with the present invention;

FIG. 5 illustrates a memory cell array according to an embodiment of the present invention. FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Also, it should be noted that the same components and parts of the drawings indicate the same reference numerals as possible whenever possible.

FIG. 4 shows an embodiment of the memory cell MC2 according to the present invention. In this embodiment, the sizes of the two contacts 401 and 402 are different. That is, the contact 401 and 402 are formed to have the same equivalent circuit as the conventional one, and the sizes of the contacts 401 and 402 are different from each other to compensate for the loading effect in the core. In this specification, the size of the contact 401 is larger than the size of the contact 402.

5 is a view illustrating a memory cell array according to an embodiment of the present invention.

Referring to FIG. 5, in a memory cell array in which memory cells are continuously formed, a memory cell MC1 according to the present invention is constituted by a memory cell MC1 as in the prior art and a core adjacent to the memory cell array.

As described above, the present invention has an advantage that the influence of the loading effect can be compensated by designing the contact size at the continuous portion of the cell array and the contact size at the portion contacting the core portion differently. Further, the present invention has an advantage that defective improvement and reliability of the device can be improved.

Claims (2)

A method of configuring a memory cell array of a semiconductor memory device, comprising: A memory cell having two contacts of different sizes is configured in a core region between the memory cell arrays so as to constitute a plurality of memory cell arrays with memory cells having two contacts of the same size and to compensate for the influence of the loading effect ≪ / RTI > 2. The method of claim 1, wherein all of the memory cells are memory cells implemented with the same equivalent circuit.