KR102715393B1 - 비휘발성 데이터 무결성의 고속 검증 - Google Patents

비휘발성 데이터 무결성의 고속 검증 Download PDF

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KR102715393B1
KR102715393B1 KR1020210080055A KR20210080055A KR102715393B1 KR 102715393 B1 KR102715393 B1 KR 102715393B1 KR 1020210080055 A KR1020210080055 A KR 1020210080055A KR 20210080055 A KR20210080055 A KR 20210080055A KR 102715393 B1 KR102715393 B1 KR 102715393B1
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South Korea
Prior art keywords
data
error rate
bit error
threshold
memory
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Korean (ko)
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KR20220066815A (ko
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자미르 란
아브라함 데이비드
샤론 에란
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샌디스크 테크놀로지스 아이엔씨.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/102—Error in check bits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Read Only Memory (AREA)
KR1020210080055A 2020-11-16 2021-06-21 비휘발성 데이터 무결성의 고속 검증 Active KR102715393B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063114103P 2020-11-16 2020-11-16
US63/114,103 2020-11-16
US17/171,657 2021-02-09
US17/171,657 US11379305B2 (en) 2020-11-16 2021-02-09 Fast verification of non-volatile data integrity

Publications (2)

Publication Number Publication Date
KR20220066815A KR20220066815A (ko) 2022-05-24
KR102715393B1 true KR102715393B1 (ko) 2024-10-08

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US (1) US11379305B2 (https=)
JP (1) JP2022079407A (https=)
KR (1) KR102715393B1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024041466A (ja) 2022-09-14 2024-03-27 キオクシア株式会社 メモリシステムおよび制御方法
US12572306B2 (en) * 2023-02-27 2026-03-10 Micron Technology, Inc. Verifying chunks of data based on read-verify commands
CN121153020A (zh) * 2023-04-24 2025-12-16 美光科技公司 具有数据验证的受管理非易失性存储器装置
US12488854B2 (en) * 2023-06-14 2025-12-02 Western Digital Technologies, Inc. Data storage device and method for host-managed data integrity
US12567478B2 (en) * 2023-09-15 2026-03-03 SK Hynix Inc. Error condition monitoring in memory systems
US20250104789A1 (en) * 2023-09-22 2025-03-27 Micron Technology, Inc. Dual-read data integrity scan in a memory sub-system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150358036A1 (en) * 2014-06-10 2015-12-10 Phison Electronics Corp. Decoding method, memory storage device and memory control circuit unit
US20180091172A1 (en) * 2016-03-04 2018-03-29 Western Digital Technologies, Inc. Ecc and raid-type decoding
US20180173655A1 (en) * 2016-12-20 2018-06-21 Sandisk Technologies Llc Multi-channel memory operations based on bit error rates

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327690A (ja) * 1992-05-21 1993-12-10 Hitachi Ltd 通信方法および装置
US5586250A (en) * 1993-11-12 1996-12-17 Conner Peripherals, Inc. SCSI-coupled module for monitoring and controlling SCSI-coupled raid bank and bank environment
US6443490B2 (en) * 1998-06-12 2002-09-03 William E. Webb Dual mode stabilizer for backhoe loaders and backhoe attachments
US7490263B2 (en) 2006-01-17 2009-02-10 Allen King Apparatus, system, and method for a storage device's enforcing write recovery of erroneous data
EP2057515B1 (en) * 2006-08-08 2018-05-02 Siemens Industry, Inc. Devices, systems, and methods for assigning a plc module address
US8307271B1 (en) 2009-09-17 2012-11-06 Emc Corporation Fast verification of data block cycle redundancy checks
US8631281B1 (en) 2009-12-16 2014-01-14 Kip Cr P1 Lp System and method for archive verification using multiple attempts
US8910031B1 (en) 2011-03-29 2014-12-09 Emc Corporation DIF-CRC based fast hashing
US8726104B2 (en) 2011-07-28 2014-05-13 Sandisk Technologies Inc. Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages
US20130031431A1 (en) * 2011-07-28 2013-01-31 Eran Sharon Post-Write Read in Non-Volatile Memories Using Comparison of Data as Written in Binary and Multi-State Formats
US8939056B1 (en) * 2012-04-20 2015-01-27 Barron Associates, Inc. Systems, devices, and/or methods for managing targeted payload descent
US8984190B2 (en) * 2013-05-23 2015-03-17 Western Digital Technologies, Inc. Methods and devices for booting a network attached storage with two logical units
US10475523B2 (en) 2013-05-31 2019-11-12 Western Digital Technologies, Inc. Updating read voltages triggered by the rate of temperature change
US9697905B2 (en) 2013-05-31 2017-07-04 Sandisk Technologies Llc Updating read voltages using syndrome weight comparisons
US9818488B2 (en) * 2015-10-30 2017-11-14 Seagate Technology Llc Read threshold voltage adaptation using bit error rates based on decoded data
US9411683B2 (en) * 2013-12-26 2016-08-09 Intel Corporation Error correction in memory
US10089177B2 (en) 2014-06-30 2018-10-02 Sandisk Technologies Llc Multi-stage decoder
US9817752B2 (en) 2014-11-21 2017-11-14 Sandisk Technologies Llc Data integrity enhancement to protect against returning old versions of data
US9886342B2 (en) * 2015-10-28 2018-02-06 Sandisk Technologies Llc Storage device operations based on bit error rate (BER) estimate
US10043582B2 (en) * 2016-02-11 2018-08-07 Seagate Technology Llc Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings
WO2018077443A1 (en) * 2016-10-31 2018-05-03 Huawei Technologies Duesseldorf Gmbh Error detection using symbol distribution in a system with distribution matching and probabilistic amplitude shaping
US10418097B2 (en) * 2017-11-27 2019-09-17 Western Digital Technologies, Inc. Non-volatile storage system with read calibration
US10534738B2 (en) * 2018-01-17 2020-01-14 Western Digital Technologies, Inc. Host bus adaptor with configurable interface
US20210168641A1 (en) * 2018-05-17 2021-06-03 Telefonaktiebolaget Lm Ericsson (Publ) Measurement Reporting for Radio Access Network

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150358036A1 (en) * 2014-06-10 2015-12-10 Phison Electronics Corp. Decoding method, memory storage device and memory control circuit unit
US20180091172A1 (en) * 2016-03-04 2018-03-29 Western Digital Technologies, Inc. Ecc and raid-type decoding
US20180173655A1 (en) * 2016-12-20 2018-06-21 Sandisk Technologies Llc Multi-channel memory operations based on bit error rates

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Publication number Publication date
JP2022079407A (ja) 2022-05-26
KR20220066815A (ko) 2022-05-24
US20220156143A1 (en) 2022-05-19
US11379305B2 (en) 2022-07-05

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