KR102670595B1 - Display device - Google Patents

Abstract

A display device is provided. The display device includes a light-emitting element, a first transistor that delivers a driving current to the light-emitting element, a second transistor connected to the first electrode of the first transistor to transmit a data signal, and a first transistor connected to the second electrode of the first transistor. It includes a third transistor having an electrode, and an auxiliary transistor connected between the second electrode of the third transistor and the gate electrode of the first transistor to transmit a data signal to the gate electrode of the first transistor. Here, the first transistor, the second transistor, and the auxiliary transistor are first type transistors, and the third transistor is a second type transistor different from the first type transistor.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more specifically, to a display device in which a pixel includes a PMOS transistor, an NMOS transistor, and a light emitting element.

The importance of display devices is increasing with the development of multimedia. In response to this, various types of display devices, such as liquid crystal displays and display devices containing self-luminous elements, are being used. Among them, a display device including a self-luminous element displays an image using the self-luminous element. A display device including a self-light emitting device includes a plurality of transistors that provide driving current to the self-light emitting device.

The transistor is usually a PMOS transistor (P-channel metal-oxide-semiconductor field-effect transistor), but research is also being conducted on the use or combination of NMOS transistor.

PMOS transistors and NMOS transistors have different characteristics. There is also a difference in whether the kickback voltage depending on the parasitic capacitance is in the plus or minus direction. Therefore, if some or all of the PMOS transistors are changed to NMOS transistors, the kickback voltage characteristics may change.

The problem to be solved by the present invention is to provide a display device that prevents the gate voltage of a transistor from dropping due to kickback.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the window description below.

A display device according to an embodiment for solving the above problem includes a light-emitting device, a first transistor that transmits a driving current to the light-emitting device, a second transistor connected to the first electrode of the first transistor to transmit a data signal, A third transistor having a first electrode connected to the second electrode of the first transistor, and connected between the second electrode of the third transistor and the gate electrode of the first transistor to transmit the data signal to the first transistor. It includes an auxiliary transistor that transmits to the gate electrode. Here, the first transistor, the second transistor, and the auxiliary transistor are first type transistors, and the third transistor is a second type transistor different from the first type transistor.

The first type transistor may be a PMOS transistor, and the second type transistor may be an NMOS transistor.

The first type transistor may be a top gate transistor whose gate electrode is disposed above the semiconductor layer, and the second type transistor may be a bottom gate transistor whose gate electrode is disposed below the semiconductor layer.

The first type transistor may include an oxide semiconductor, and the second type transistor may include polycrystalline silicon.

The display device further includes a fourth transistor connected between the gate electrode of the first transistor and an initialization voltage line, and the fourth transistor may be the second type transistor.

The display device includes a fifth transistor connected between the first electrode of the first transistor and the first power voltage line, and a sixth transistor connected between the second electrode of the first transistor and the first electrode of the light emitting device. , a seventh transistor connected between the first electrode of the light emitting device and the initialization voltage line, and a storage capacitor formed between the first electrode of the first transistor and the first power voltage line. Here, each of the fifth, sixth, and seventh transistors may be the first type transistor.

The display device further includes a first scan line and a second scan line, wherein a gate electrode of the second transistor is connected to the first scan line, a gate electrode of the auxiliary transistor is connected to the first scan line, and the second scan line is connected to the first scan line. The gate electrode of the three transistors may be connected to the second scan line.

The second transistor and the auxiliary transistor are turned on in a first period in response to a first scan signal provided through the first scan line, and the third transistor responds to a second scan signal provided through the second scan line. Thus, it can be turned on in the first section.

The second transistor and the auxiliary transistor are turned on in a first period in response to a first scan signal provided through the first scan line, and the third transistor responds to a second scan signal provided through the second scan line. Thus, it is turned on in the second section, and the second section is larger than the first section and may include the first section.

The second scan signal has a turn-on voltage level in the second section, and the second section of the second scan signal may partially overlap with the second section of the second scan signal at a previous time.

The second scan line is disposed in a first direction with respect to the first transistor in a plan view, the second scan line extends in a second direction perpendicular to the first direction, and the first scan line is based on the second scan line. may be disposed in the first direction and parallel to the second scan line, the third transistor may be disposed to partially overlap the second scan line, and the auxiliary transistor may be disposed to partially overlap the first scan line. .

The third transistor has a channel extending in the first direction, the auxiliary transistor has a channel extending in the first direction, and the channel of the auxiliary transistor is on a line different from the line extending the channel of the third transistor. can be placed.

The display device further includes a data pattern extending in the second direction, one end of the data pattern constitutes one electrode of the third transistor, and the third data pattern extends in the second direction through the first contact hole. 3 It can be connected to one electrode of the transistor.

A first insulating layer is disposed on the third transistor, the first scan line and the gate electrode of the third transistor are disposed on the first insulating layer, and the second scan line is a layer on which the first scan line is disposed. It can be placed on a different floor.

The display device includes a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line, a fifth transistor connected between the first electrode of the first transistor and the first power voltage line, and a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line. A sixth transistor connected between the second electrode and the first electrode of the light emitting diode, a seventh transistor connected between the cathode electrode of the light emitting device and the initialization voltage line, and the first electrode of the first transistor and the first electrode. It may further include a storage capacitor formed between power voltage lines, wherein each of the fourth and seventh transistors may be the second type transistor, and each of the fifth and sixth transistors may be the first type transistor.

The display device further includes a light emission control signal line connected to a gate electrode of each of the fifth to seventh transistors, and the fifth and sixth transistors emit light in response to a light emission control signal provided through the light emission control signal line. It is turned on in three sections, and the seventh transistor may be turned off in a third section in response to the light emission control signal.

In the display device, the light emitting device may be a quantum dot light emitting device.

A display device according to another embodiment for solving the above problem includes a light-emitting device, a first transistor that transmits a driving current to the light-emitting device, and a second transistor that is connected to the first electrode of the first transistor and transmits a data signal. , and a third transistor connected between the second electrode of the first transistor and the gate electrode of the first transistor to transmit the data signal to the gate electrode of the first transistor, and the third transistor is mutually It includes first and second sub-transistors connected in series with each other having different channel types.

The first type transistor may be a PMOS transistor, and the second type transistor may be an NMOS transistor.

The first type transistor may be a top gate transistor whose gate electrode is disposed above the semiconductor layer, and the second type transistor may be a bottom gate transistor whose gate electrode is disposed below the semiconductor layer.

The first type transistor may include an oxide semiconductor, and the second type transistor may include polycrystalline silicon.

In the display device, the light emitting device may be a quantum dot light emitting device.

Specific details of other embodiments are included in the detailed description and drawings.

According to the display device according to one embodiment, it is possible to effectively prevent the gate voltage of the first transistor from dropping due to kickback without significantly modifying the layout.

Effects according to the embodiments are not limited to the content exemplified above, and further various effects are included in the present specification.

1 is a block diagram of a display device according to an embodiment.
FIG. 2 is a circuit diagram of a pixel included in the display device of FIG. 1.
3A to 3C are waveform diagrams of signals provided to the pixel of FIG. 2.
Figure 4 is a layout diagram of the pixel of Figure 2.
Figure 5 is a plan view of the lower semiconductor layer included in the pixel of Figure 4.
FIG. 6 is a plan view showing the fourth and fifth conductive layers included in the pixel of FIG. 4 overlapping.
Figure 7 is a cross-sectional view taken along line II' of Figure 4.
Figure 8 is a cross-sectional view of a pixel according to another embodiment.
Figure 9 is a circuit diagram of a pixel according to another embodiment.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes instances where the element or layer is directly on top of or intervening with the other element. Like reference numerals refer to like elements throughout the specification.

Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be a second component within the technical spirit of the present invention.

Hereinafter, embodiments will be described with reference to the attached drawings. Hereinafter, the display device will be described using an organic light emitting display device as an example.

1 is a block diagram of a display device according to an embodiment.

Referring to FIG. 1, the display device 1 includes a display unit 10 including a pixel PX (or a reference pixel or unit pixel), a scan driver 20, a data driver 30, and an emission control driver 40. ) and a control unit 50.

The display device 1 (or display unit 10) includes scan lines (SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, SL41 to SL4n) (where n is an integer of 2 or more) and data lines (DL1 to DLm). (where m is an integer of 2 or more), and emission control lines EL1 to ELn, and the pixel PX includes scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n. n is an integer of 2 or more), data lines DL1 to DLm (where m is an integer of 2 or more), and emission control lines EL1 to ELn. Pixels (PX) may be arranged in a matrix form.

Scan lines (SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n) can extend in the row direction. The emission control lines EL1 to ELn may extend in the row direction. The data lines DL1 to DLm may extend in the column direction. The row direction and column direction may be interchanged.

Additionally, the display device 100 includes an initialization voltage line (or initialization voltage supply line), a first power voltage line (or first power voltage supply line), and a second power voltage line (or second power voltage supply line). can do.

The initialization voltage wiring is a wiring that supplies the initialization voltage (VINT) to the pixel (PX), and can be branched for each row and extend in the row direction. The first power voltage wire is a wire that supplies the first power voltage (ELVDD) to the pixel (PX), and may be branched for each column and extend in the column direction. The second power voltage wire is a wire that supplies a second power voltage (ELVSS) to the pixel (PX), which is different from the first power voltage, and may be arranged in a mesh shape. However, it is not limited to this, and the extension direction of the initialization voltage wire and the extension direction of the first power voltage wire can be modified in various ways.

The pixel PX may be connected to four scan lines, one data line, one emission control line, one initialization voltage line, and one first power voltage line. For example, the pixels PX (hereinafter referred to as the 11th pixel) located in the first row (or first pixel row) and the first column (or first pixel column) are the 11th, 21st, and 31st pixels. and the 41st scan lines (SL11, SL21, SL31, SL41), the first data line (DL1), the first emission control line (EL1), one initialization voltage line, and one first power voltage line.

The scan driver 20 generates first to fourth scan signals and transmits the first to fourth scan signals to the pixel PX through the scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n. can provide them. The first to fourth scanning signals will be described later with reference to FIG. 2.

The data driver 30 may provide a data signal to the pixel PX through the data lines DL1 to DLm. For example, when the first scan signal is provided to the pixel PX (i.e., the 11th pixel) in the first row and the first column through the first scan line SL11, the data signal may be provided to the 11th pixel. there is.

The emission control driver 40 may generate an emission control signal and provide the emission control signal to the pixel PX through the emission control lines EL1 to ELn. The emission control driver 40 (or the display device 1) may adjust the emission time of the pixel PX based on the emission control signal. Meanwhile, the light emission control driver 40 is shown as being implemented separately and independently from the scan driver 20, but is not limited thereto. For example, the light emission control driver 40 may be included in the scan driver 20 and implemented integrally. As another example, depending on the circuit configuration of the pixel PX, the emission control driver 40 may be omitted.

The control unit 50 changes the image signals (R, G, B) transmitted from an external device (or an external device, for example, an application processor) into image data signals (DR, DG, DB) and operates the data driver ( 30). In addition, the control unit 50 receives the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), and the clock signal (MCLK), and operates the scan driver 20, the data driver 30, and the light emission control driver 40. A control signal for controlling operation (or driving) may be generated, and the control signal may be provided to each of the scan driver 20, the data driver 30, and the light emission control driver 40. Here, the control signal is a scan drive control signal (SCS) that controls the scan driver 20, a data drive control signal (DCS) that controls the data driver 30, and a light emission drive control that controls the light emission control driver 40. May include signals (ECS).

Meanwhile, the display device 1 further includes a power supply unit (not shown), and the power supply unit generates a first power supply voltage (ELVDD), a second power supply voltage (ELVSS), and an initialization voltage (VINT), and the first power supply unit (ELVDD) The first power supply voltage (ELVDD), the second power supply voltage (ELVSS), and the initialization voltage (VINT) can be provided to the pixel (PX) through the voltage wiring, the second power voltage wiring, and the initialization voltage wiring, respectively. The first power supply voltage (ELVDD) may be a predetermined high level voltage, the second power supply voltage (ELVSS) may be a predetermined low level voltage, and the voltage level of the second power voltage (ELVSS) may be the first power voltage (ELVDD). It may be lower than the voltage level of . Meanwhile, the power supply unit may be implemented as an external voltage source.

The pixel PX may emit light with a certain luminance based on the driving current supplied to the organic light emitting device according to the data signal transmitted through the data lines DL1 to DLm.

FIG. 2 is a circuit diagram of a pixel included in the display device of FIG. 1.

Referring to FIG. 2 , the pixel PX may include a light emitting element EL, first to eighth transistors T1 to T8, and a storage capacitor CST. A data signal (DATA), a first scan signal (GW_P), a second scan signal (GW_N), a third scan signal (GI), and a fourth scan signal (GB) may be provided to the pixel (PX). Here, the third scan signal (GI) may be the same as the second scan signal (GW_N) of the previous time point or previous row, for example, the third scan signal (GI[ n]) may be the same as the second scan signal (GW_N[n-1]) provided to the pixel (PX) in the n-1th row. Similarly, the fourth scan signal (GB) may be the same as the first scan signal (GW_P) of the previous time point or previous row, for example, the fourth scan signal (GB) provided to the pixel (PX) of the nth row. [n]) may be the same as the first scan signal (GW_P[n-1]) provided to the pixel (PX) in the n-1th row.

Each of the first to eighth transistors T1 to T8 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

Each of the first to eighth transistors T1 to T8 may be a thin film transistor. Each of the first to eighth transistors T1 to T8 may be a PMOS transistor or an NMOS transistor.

In one embodiment, each of the first transistor T1, the second transistor T2, and the fifth to eighth transistors T5, T6, T7, and T8 is a PMOS transistor, and the third and fourth transistors T3 , T4) each may be an NMOS transistor. The NMOS transistor has relatively excellent turn-off characteristics compared to the PMOS transistor, and when each of the third transistor (T3) and the fourth transistor (T4) is implemented as an NMOS transistor, the driving current ( Id) leakage can be reduced.

Hereinafter, each configuration of the pixel PX will be described in detail.

First, the light emitting device EL may include an anode electrode and a cathode electrode. The anode electrode of the light emitting element EL may be connected to the fifth node N5, and the cathode electrode may be connected to the second power voltage wire.

The first transistor T1 (or driving transistor) has a first electrode connected to the first node N1, a second electrode N2 connected to the second node, and a gate electrode connected to the fourth node N4. may include. The first transistor T1 may provide the driving current Id to the light emitting device EL based on the voltage of the fourth node N4 (or the data voltage stored in the storage capacitor CST, which will be described later).

The second transistor T2 (or switching transistor) includes a first electrode connected to the data line (or receiving data (DATA)), a second electrode connected to the first node N1, and a first scan line. It may include a gate electrode connected to (for example, the first scan line SL1 shown in FIG. 1) or receiving the first scan signal GW_P. The second transistor T2 is turned on in response to the first scan signal GW_P and can transmit the data signal DATA to the first node N1.

The third transistor T3 and the eighth transistor T8 (or auxiliary transistor) are located between the second electrode and the gate electrode of the first transistor T2 (or between the second node N2 and the fourth node N4). ) The third transistor T3 and the eighth transistor T8 may be connected in series to the fourth node (DATA) transmitted through the first and second nodes (N1, N2). N4) (or storage capacitor (CST)).

The third transistor T3 (or T3_N) has a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a second scan line (e.g., in FIG. 1 It may include a gate electrode connected to the illustrated second scan line (SL21) or receiving the second scan signal (GW_N). The third transistor T3 is turned on in response to the second scan signal GW_N and can transmit the data signal DATA to the third node N3.

The eighth transistor T8 (or T3_P) includes a first electrode connected to the third node N3, a second electrode connected to the fourth node N4, and a first scan line (e.g., a first scan line (SL11)) or may include a gate electrode that receives the first scan signal (GW_P). The eighth transistor T8 is turned on in response to the first scan signal GW_P and can transmit the data signal DATA to the fourth node N4.

Meanwhile, as described above, the third transistor T3 is implemented as an NMOS transistor so that the driving current Id leaks from the second node N2 to the fourth node N4 during the light emission driving of the light emitting element EL. can be prevented. The eighth transistor T8 is implemented as a PMOS transistor, and the voltage of the fourth node N4 (or the gate electrode of the first transistor T1) is lowered by the kickback voltage of the third transistor T3. can be prevented.

The storage capacitor CST may be connected or formed between the fourth node N4 and the first power voltage ELVDD. The storage capacitor (CST) can store the provided data signal (DATA).

The fourth transistor T4 includes a first electrode connected to the fourth node N4, a second electrode connected to the initialization voltage line or receiving the initialization voltage VINT, and a third scan line (e.g., in FIG. 1 It may be connected to the illustrated third scan line (SL31) or include a gate electrode that receives the third scan signal (GI_N).

The fourth transistor T4 is turned on in response to the third scan signal GI before the data signal DATA is stored in the storage capacitor CST or after the light emitting element EL emits light, and the fourth transistor T4 is turned on in response to the third scan signal GI. The node N4 (or storage capacitor CST) can be initialized using the initialization voltage VINT.

As described above, when the fourth transistor T4 is implemented as an NMOS transistor, the voltage of the fourth node N4 can be prevented from dropping while the light emitting device EL emits light.

The fifth transistor T5 and the sixth transistor T6 (or the first and second light emission control transistors) are connected between the first power voltage line and the light emitting element EL, and are connected to the first transistor T1. It is possible to form a current movement path along which the driving current (Id) generated by moves.

The fifth transistor T5 includes a first electrode connected to the first power voltage line to receive the first power voltage ELVDD, a second electrode connected to the first node N1, and a light emission control signal line (e.g. , may include a gate electrode connected to the first emission control signal line EL1 shown in FIG. 1 or receiving an emission control signal.

Similarly, the sixth transistor T6 has a first electrode connected to the second node N2, a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting element EL), and a light emitting element. It may be connected to a control signal line (for example, the first emission control signal line EL1 shown in FIG. 1) or may include a gate electrode that receives an emission control signal.

The fifth and sixth transistors T5 and T6 are turned on in response to the light emission control signal EM. In this case, the driving current Id is provided to the light emitting element EL, and the light emitting element EL is driven. It can emit light with luminance corresponding to the current (Id).

The seventh transistor T7 includes a first electrode connected to the fifth node N5, a second electrode connected to an initialization voltage line (or initialization voltage VINT), and a fourth scan signal line (e.g., FIG. It may be connected to the fourth scan signal line (SL41) shown in 1 or may include a gate electrode that receives the fourth scan signal (GB).

The seventh transistor T7 is turned on in response to the fourth scanning signal GB before or after the light emitting element EL emits light, and is connected to the anode electrode of the light emitting element EL using the initialization voltage VINT. can be initialized. The light emitting device (EL) may have a parasitic capacitance (CP_EL) formed between the anode electrode and the cathode electrode (or the second power voltage (ELVSS)), and while the light emitting device (EL) emits light, the parasitic capacitance (CP_EL) is charged so that the anode electrode of the light emitting element (EL) can have a specific voltage. Accordingly, the light emitting device EL can be initialized through the seventh transistor T7.

Meanwhile, in FIG. 2, the eighth transistor T8 is shown as independent from the third transistor T3, but is not limited thereto. For example, the third transistor T3 and the eighth transistor T8 may be implemented or referred to as a single transistor in a dual gate form.

3A to 3C are waveform diagrams of signals provided to the pixel of FIG. 2.

Referring to FIGS. 2 and 3A, the light emission signal EM is a high level voltage (or logic high level, turn-off) in the first period PERIOD1 (for example, for a specific time from the first time point P1). voltage), and may have a low level voltage (or logic low level, turn-on voltage) in the remaining sections except for the first section (PEROD1).

The third scan signal GI (or the second previous scan signal GW_N[n-1]) may have a high level voltage between the second time point P2 and the third time point P3. The third scan signal GI is generated in the remaining sections of the first section (PERIOD1) (e.g., the section from the first time point (P1) to the second time point (P2), the section after the third time point (P3)) Can have low level voltage. The third scan signal GI (or the second previous scan signal GW_N[n-1]) may be an impulse signal having the first pulse width PW1.

In this case, the fourth transistor T4 described with reference to FIG. 2 is turned on in the section between the second time point P2 and the third time point P3, and the fourth node N4 is connected using the initialization voltage VINT. can be initialized.

The fourth scan signal GB (or the first previous scan signal GW_P[n-1]) may have a low level voltage between the fifth time point P5 and the sixth time point P6. Here, the fifth time point P5 may be after the second time point P2, and the sixth time point P6 may be before the third time point P3. The fourth scan signal (GB) is an impulse signal having a second pulse width (PW2), and the second pulse width (PW2) is smaller than the first pulse width (PW1) and may completely overlap with the first pulse width (PW1). there is.

In this case, the seventh transistor T7 described with reference to FIG. 2 is used in the section between the fifth time point P5 and the sixth time point P6 (or the second time point P2 to the third time point P3). It is turned on, and the light emitting element (EL) can be initialized using the initialization voltage (VINT).

The second scan signal GW_N (or the second current scan signal GW_N[n]) may have a high level voltage between the third time point P3 and the fourth time point P4. The second scan signal (GW_N) (or, the second current scan signal (GW_N[n])) may be an impulse signal having a first pulse width (PW1), similar to the third scan signal (GI). That is, the second scan signal (GW_N) may be a signal in which the third scan signal (GI) is delayed by the first pulse width (PW1).

The first scan signal GW_P (or the first current scan signal GW_P[n]) may have a low level voltage between the seventh time point P7 and the eighth time point P8. Here, the seventh time point P7 may be after the third time point P3, and the eighth time point P8 may be before the fourth time point P4. The first scan signal (GW_P) may be an impulse signal having a second pulse width (PW2). That is, the first scan signal (GW_P) may be a signal in which the fourth scan signal (GB) is delayed by the first pulse width (PW1).

The third transistor T3 shown in FIG. 2 is turned on at the third time point P3 in response to the second scanning signal GW_N, and in this case, the kickback voltage (or turn-on kickback) of the third transistor T3 is turned on. As a result, the third node voltage V_N3, which is the voltage of the third node N3, may temporarily increase. As the third transistor T3 is implemented as an NMOS transistor, the kickback voltage resulting from the turn-on of the third transistor T3 may occur in a positive direction.

Thereafter, the eighth transistor T8 is turned on at the seventh time point P7 in response to the first scanning signal GW_P, and in this case, the third transistor T8 is turned on by the kickback voltage (or turn-on kickback) of the eighth transistor T8. The node voltage V_N3 may temporarily drop (or drop). As the eighth transistor T8 is implemented as a PMOS transistor, the kickback voltage resulting from the turn-on of the eighth transistor T8 may occur in a negative direction. Meanwhile, when the capacity of the eighth transistor T8 is similar to that of the third transistor T3 and the arrangement position of the eighth transistor T8 in the cross-sectional view is similar to that of the third transistor T3, the eighth transistor T8 ) may be equal to or similar to the kickback voltage of the third transistor T3.

While the third transistor T3 and the eighth transistor T8 are turned on (that is, in the section between the seventh time point P7 and the eighth time point P8), the data signal DATA is transmitted to the second node N2 ) is transmitted to the fourth node (N4) through the third node (N3), and the third node voltage (V_N3) (and the voltage of the fourth node (N4)) is linear according to the transmission of the data signal (DATA). may increase dramatically.

Thereafter, the eighth transistor T8 is turned off at the eighth time point P5 in response to the first scan signal GW_P, and in this case, the third node voltage V_N3 is increased by the kickback voltage of the eighth transistor T8. This may temporarily increase.

The third transistor T3 is turned off at the fourth time point P4 in response to the second scan signal GW_N, and in this case, the third transistor T3 is turned off by the kickback voltage (or turn-off kickback) of the fourth transistor T4. The node voltage (V_N3) may drop.

In the pixel circuit shown in FIG. 2, when the second node N2 and the third node N3 are connected only to the third transistor T3, the kickback voltage of the third transistor T3 at the third time point P4 As a result, the voltage of the fourth node N4 (that is, the gate voltage of the first transistor T1) decreases, and thus the pixel PX may emit light with a luminance different from the desired luminance.

Accordingly, the eighth transistor T8 is additionally disposed between the second node N2 and the third node N3 of the pixel PX, and the eighth transistor T8 is turned on in the section in which the third transistor T3 is turned on. ) can be turned on and off to compensate for a drop in the third node voltage V_N3 (or the gate voltage of the first transistor T1) due to the kickback voltage of the third transistor T3.

Meanwhile, in FIG. 3A, the second scan signal (GW_N) is shown as not overlapping with the third scan signal (GI), but this is an example and is not limited thereto.

For example, with reference to FIG. 3B , the high level voltage of the second scan signal GW_N may transition to the ninth time point P9, which is before the third time point P3. In this case, in the section between the ninth time point P9 and the third time point P3 (i.e., during the first time D1), the second scan signal GW_N may overlap with the third scan signal GI. there is. Meanwhile, the first scan signal (GW_P) may transition to a low level voltage at the third time point (P3) and may transition to a high level voltage at the tenth time point (P10). That is, the first scan signal (GW_P) may be included in or overlap the second scan signal (GW_N), but may not overlap the third scan signal (GI).

Additionally, in FIG. 3A, the second scan signal (GW_N) is shown as having a width greater than the width of the first scan signal (GW_P), but this is an example and is not limited thereto.

For example, referring to FIG. 3C, the first to fourth scan signals (GW_P, GW_N, GI, GB) may have the same width.

As described with reference to FIGS. 3A to 3C, the first scan signal (GW_P) overlaps the second scan signal (GW_N), and the third transistor (T3) operates in response to the second scan signal (GW_N). The kickback voltage due to may be compensated by the kickback voltage caused by the eighth transistor T8 operating in response to the first scan signal GW_P.

Figure 4 is a layout diagram of the pixel of Figure 2. Figure 5 is a plan view of the lower semiconductor layer included in the pixel of Figure 4. FIG. 6 is a plan view showing the fourth and fifth conductive layers included in the pixel of FIG. 4 overlapping. Figure 7 is a cross-sectional view taken along line II' of Figure 4.

In the following embodiments, some of the components are given new reference numerals to easily explain the arrangement and coupling relationship between the components, even if they are substantially the same as the components mentioned in FIGS. 1 and 2.

Referring to FIGS. 2 and 4 to 7 , the pixel may include first to eighth transistors T1 to T8, a storage capacitor CST, and a light emitting element EL.

The first to eighth transistors T1 to T8 may include a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. The first transistor (T1), the second transistor (T2), and the fifth to eighth transistors (T5, T6, T7, and T8), which are PMOS transistors, are top gate type transistors in which the gate electrode is disposed above the semiconductor layer. The third transistor T3 and fourth transistor T4, which are NMOS transistors, may be bottom gate type transistors in which the gate electrode is disposed lower than the semiconductor layer.

The storage capacitor (CST) may include conductive layers forming electrodes and an insulating layer disposed between the conductive layers.

The light emitting device EL may include a conductive layer forming an anode electrode and a cathode electrode and a light emitting layer disposed between them.

In some embodiments, the light-emitting layer of the light-emitting device EL may be an organic light-emitting layer. That is, in some embodiments, the light emitting device (EL) may be an organic light emitting diode.

Alternatively, in some other embodiments, the light-emitting layer of the light-emitting device EL may include a quantum dot material. That is, in some other embodiments, the light emitting device EL may be a quantum dot light emitting diode.

The quantum dot may be a particulate material that emits a specific color as electrons transition from the conduction band to the valence band.

The quantum dot may be a semiconductor nanocrystal material. The quantum dots have a specific band gap depending on their composition and size and can emit light with a unique wavelength. Examples of the semiconductor nanocrystals of the quantum dots include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or combinations thereof.

Group II-VI compounds include binary compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, and mixtures thereof A tri-element compound selected from the group consisting of; and a tetraelement compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof.

Group III-V compounds include binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; A ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb, GaAlNP and mixtures thereof; and a tetraelement compound selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof.

Group IV-VI compounds include binary compounds selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; A ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and a quaternary element compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements may be selected from the group consisting of Si, Ge, and mixtures thereof. The group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

At this time, the di-element compound, tri-element compound, or quaternary compound may exist in the particle at a uniform concentration, or may exist in the same particle with a partially different concentration distribution. Additionally, one quantum dot may have a core/shell structure surrounding other quantum dots. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center.

In some embodiments, quantum dots may have a core-shell structure including a core including the above-described nanocrystals and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer to maintain semiconductor properties by preventing chemical denaturation of the core and/or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be single or multi-layered. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of the shell of the quantum dot include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

For example, the oxides of the metal or non-metal include SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZnO, MnO, Mn ₂ O ₃ , Mn ₃ O ₄ , CuO, FeO, Fe ₂ O ₃ , Fe ₃ O ₄ , Examples may include binary compounds such as CoO, Co ₃ O ₄ , NiO, or ternary compounds such as MgAl ₂ O ₄ , CoFe ₂ O ₄ , NiFe ₂ O ₄ , and CoMn ₂ O ₄ , but the present invention is limited thereto. That is not the case.

In addition, the semiconductor compounds include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc. However, the present invention is not limited thereto.

When the light-emitting layer of the light-emitting device (EL) includes quantum dots, the light emitted by the light-emitting device (EL) has an emission wavelength spectrum of about 45 nm or less, or about 40 nm or less, or about 30 nm or less. ), through which the color purity and color reproducibility of the colors displayed by the display device can be further improved.

Electrical connections between components may be made by wiring made of a conductive layer and/or vias made of a conductive material. The above-described conductive material, conductive layer, semiconductor layer, insulating layer, light emitting layer, etc. are disposed on the substrate 810.

The pixel PX includes a substrate 910, a buffer layer 920, a lower semiconductor layer 100, a first insulating layer 810, a first conductive layer 200, a second insulating layer 820, and a second conductive layer. (300), third insulating layer 830, upper semiconductor layer 400, third conductive layer 500, fourth insulating layer 840, fourth conductive layer 600, fifth insulating layer 850 And a fifth conductive layer 700, including a substrate 910, a buffer layer 920, a lower semiconductor layer 100, a first insulating layer 810, a first conductive layer 200, a second insulating layer ( 820), second conductive layer 300, third insulating layer 830, upper semiconductor layer 400, third conductive layer 500, fourth insulating layer 840, fourth conductive layer 600, The fifth insulating layer 850 and the fifth conductive layer 700 may be sequentially disposed or stacked.

Each of the above-described layers may be made of a single layer, but may also be made of a stacked layer including a plurality of layers. Additional layers may be placed between each layer.

Substrate 910 supports layers disposed thereon. If the display device 1 is a back or double-sided emitting type, a transparent substrate can be used. When the display device 1 is a top-emitting type, not only a transparent substrate, but also a translucent or opaque substrate may be used.

The substrate 910 may be made of an insulating material such as glass, quartz, or polymer resin. Examples of the polymer materials include polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), and polyethylene napthalate (PEN). ), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate ( cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The substrate 910 may include a metal material.

The substrate 910 may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. An example of a material that makes up a flexible substrate may be polyimide (PI), but is not limited thereto.

The buffer layer 920 may be disposed on the entire surface of the substrate 910. The buffer layer 920 may prevent impurity ions from diffusing, prevent moisture or external air from penetrating, and perform a surface planarization function. The buffer layer 920 may include silicon nitride, silicon oxide, or silicon oxynitride. The buffer layer 920 may be omitted depending on the type of substrate 910 or process conditions.

The lower semiconductor layer 100 is an active layer forming a channel for the first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8.

The lower semiconductor layer 100 may be separated from each other for each pixel, but is not limited to this. For example, two pixels adjacent to each other in the row direction have a pixel structure where the left and right sides are inverted, and the two pixels are one lower semiconductor. The floor 100 may be shared.

The lower semiconductor layer 100 may include first and second lower semiconductor patterns that are separated from each other within the pixel PX.

The lower semiconductor layer 100 includes a first vertical portion 110, a second vertical portion 120, a third vertical portion 130 extending generally in the column direction, and a horizontal portion 140 extending generally in the row direction. It can be included. The first vertical portion 110, the second vertical portion 120, and the horizontal portion 140 may be physically connected to form a first lower semiconductor pattern. The third vertical portion 130 may form a second lower semiconductor pattern.

The first vertical portion 110 is disposed adjacent to the left side of the pixel, the second vertical portion 120 is disposed adjacent to the right side of the pixel, and the third vertical portion 130 is disposed adjacent to the left side of the pixel. You can. The first vertical part 110, the second vertical part 120, and the third vertical part 130 may be arranged to be spaced apart from each other. The length of the second vertical portion 120 in the column direction may be longer than the length of the first vertical portion 110 and may also be longer than the length of the third vertical portion 130. Additionally, the length of the first vertical portion 110 may be longer than the length of the third vertical portion 130.

The horizontal portion 140 may connect one end (eg, upper end) of the first vertical portion 110 and a middle portion of the second vertical portion 120 . In this specification, the “upper portion 121” of the second vertical portion 120 refers to a portion located above the connection portion with the horizontal portion 140 in a plan view based on FIG. 4, and the “lower portion 122” refers to a portion located above the plane. Each part may refer to a part located below the connection part with the upper horizontal part 140.

The horizontal portion 140 may connect the first vertical portion 110 and the second vertical portion 120 at the shortest distance, but as shown in FIG. 5, the first bent portion 131 on the left and the second bent portion on the right It may include a bent portion 132. The total length of the horizontal portion 140 may be increased through multiple bending.

The third vertical portion 130 may be spaced apart from the first and second vertical portions 110 and 120 and the horizontal portion 140 and may be arranged in an island shape.

The channel of the first transistor (T1) is disposed in the horizontal portion 140, the channel of the second transistor (T2) is disposed in the upper portion 121 of the second vertical portion 120, and the fifth transistor (T5) The channel of the sixth transistor T6 is disposed in the lower portion 122 of the second vertical portion 120, the channel of the eighth transistor T8 is disposed in the first vertical portion 110, and the channel of the eighth transistor T8 is disposed in the lower portion 122 of the second vertical portion 120. 3 may be placed in the vertical portion 130. The channel of the seventh transistor T7 is not shown, but may be disposed below the first vertical portion 120.

The lower semiconductor layer 100 may include polycrystalline silicon. Polycrystalline silicon can be formed by crystallizing amorphous silicon. Examples of the crystallization method include rapid thermal annealing (RTA) method, solid phase crystallzation (SPC) method, excimer laser annealing (ELA) method, metal induced crystallzation (MIC) method, metal induced lateral crystallzation (MILC) method, and sequential crystallization (SLS) method. lateral solidification method, etc., but is not limited thereto. As another example, the lower semiconductor layer 100 may include single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, etc.

In the lower semiconductor layer 100, a region (source/drain region) connected to the source/drain electrodes of each of the first, second, and fifth to eighth transistors (T1, T2, T5, T6, T7, and T8) is It may be doped with impurity ions (p-type impurity ions in the case of PMOS transistors). A trivalent dopant such as boron (B) can be used as a p-type impurity ion.

The first insulating layer 810 is disposed on the lower semiconductor layer 100 and may be generally disposed over the entire surface of the substrate 910. The first insulating layer 810 may be a gate insulating film with a gate insulating function.

The first insulating layer 810 may include a silicon compound, metal oxide, etc. For example, the first insulating layer 810 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These can be used alone or in combination with each other. The first insulating layer 810 may be a single film or a multilayer film made of a stacked film of different materials.

The first conductive layer 200 is disposed on the first insulating layer 810. The first conductive layer 200 includes a first scan line 210 that transmits the first scan signal (GW_P), an emission control line 220 that transmits an emission control signal (EM), and a gate of the first transistor (T1). It may include an electrode 230.

The first scan line 210 includes the gate electrode of the second transistor T2 and the gate electrode of the eighth transistor T8, and the emission control line 220 includes the gate electrode of the fifth transistor T5 and the sixth transistor T5. It may include a gate electrode (T6).

Each of the first scan line 210 and the emission control line 220 may extend along the row direction. Each of the first scanning line 210 and the first emission control line 220 may extend along the row direction beyond the boundary of the pixel PX to neighboring pixels.

The first scan line 210 may be located above the pixel in a plan view. The first scan line 210 overlaps the upper portion 121 of the second vertical portion 120 of the lower semiconductor layer 100, and the first scan line 210 and the second vertical portion ( The gate electrode of the second transistor T2 may be formed in the overlapping area where 120) overlaps. The second vertical portion 120 of the lower semiconductor layer 100 located above the overlapping region becomes the first electrode region (or the region where the first electrode is formed) of the second transistor T2, The second vertical portion 120 of the lower semiconductor layer 100 located below the overlapping region may be the second electrode region of the second transistor T2.

Similarly, the first scan line 210 overlaps the third vertical portion 130 of the lower semiconductor layer 100, and the first scan line 210 and the third vertical portion 130 of the lower semiconductor layer 100 The gate electrode of the eighth transistor T8 may be formed in the overlapping region. The third vertical portion 130 of the lower semiconductor layer 100 located above the overlapping area becomes the first electrode area of the eighth transistor T8, and the lower semiconductor layer located below the overlapping area. The third vertical portion 130 of 100 may be the second electrode of the eighth transistor T8.

The emission control line 220 may be located below the pixel on a plane. The emission control line 220 may be located lower than the first scan line 210 . The emission control line 220 may overlap the lower portion 122 of the first vertical portion 110 and the second vertical portion 120 of the lower semiconductor layer 100.

The gate electrode of the sixth transistor T6 may be formed in an overlapping area where the emission control line 220 and the first vertical portion 110 of the lower semiconductor layer 100 overlap. The first vertical portion 110 of the lower semiconductor layer 100 located above the overlap area becomes the second electrode area of the sixth transistor T6, and the lower portion located below the overlap area The first vertical portion 110 of the semiconductor layer 100 may become the first electrode area of the sixth transistor T6.

Similarly, the gate electrode of the fifth transistor T5 may be formed in an overlapping area where the emission control line 220 and the lower portion 122 of the second vertical portion 120 of the lower semiconductor layer 100 overlap. . The second vertical portion 120 of the lower semiconductor layer 100 located above the overlapping area becomes the first electrode area of the fifth transistor T5, and the lower part located below the overlapping area The second vertical portion 120 of the semiconductor layer 100 may become the second electrode area of the fifth transistor T5.

The gate electrode of the second transistor (T2), the gate electrode of the fifth transistor (T5), and the gate electrode of the sixth transistor (T6) may be wider than the peripheral line at the corresponding portion, but is not limited thereto.

The gate electrode 230 of the first transistor T1 may be located in the center of the pixel. The gate electrode 230 of the first transistor T1 may be located between the first scan line 210 and the emission control line 220 in a plan view. The gate electrode 230 of the first transistor T1 is separated for each pixel and may be arranged in an island shape.

The gate electrode 230 of the first transistor T1 may overlap the horizontal portion 140 of the lower semiconductor layer 100. The horizontal portion 140 of the lower semiconductor layer 100 located on the left side based on the overlap area where the gate electrode 230 of the first transistor T1 and the horizontal portion 140 of the lower semiconductor layer 100 overlap. becomes the first electrode area of the first transistor T1, and the horizontal portion 140 of the lower semiconductor layer 100 located on the right side may become the second electrode area of the first transistor T1.

The first conductive layer 200 is made of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( It may contain one or more metals selected from Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 200 may be a single layer or a multilayer layer.

The second insulating layer 820 is disposed on the first conductive layer 200 and may be generally disposed over the entire surface of the substrate 910. The second insulating layer 820 serves to insulate the first conductive layer 200 and the second conductive layer 300 and may be an interlayer insulating film.

The second insulating layer 820 is made of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, acrylic resin (polyacrylates resin), or epoxy resin. ), phenolic resin, polyamides resin, polyimides rein, unsaturated polyesters resin, polyphenylenethers resin, polyphenyl It may contain an organic insulating material such as polyphenylenesulfides resin or benzocyclobutene (BCB). The second insulating layer 820 may be a single film or a multilayer film made of a stacked film of different materials.

The second conductive layer 300 is disposed on the second insulating layer 820. The second conductive layer 300 includes an initialization voltage line 310 that transmits the initialization voltage (VINT), a second scan line 320 that transmits a second scan signal (GW_N), and a third scan signal (GI) that transmits the third scan signal (GI). 3 It may include a scan line 330 and an electrode line 340 of a storage capacitor (CST). Additionally, the second conductive layer 300 may include gate wiring of the third and fourth transistors T3 and T4.

Each of the initialization voltage line 310, the second scan line 320, the third scan line 330, and the storage capacitor electrode line 340 may extend along the row direction. The initialization voltage line 310, the second scan line 320, the third scan line 330, and the storage capacitor electrode line 340 may each extend along the row direction beyond the pixel boundary to neighboring pixels.

The initialization voltage line 310 may be located at the top of the pixel on a plane.

The second scan line 320 may be located above the first scan line 210 and below the initialization voltage line 310 in a plan view. The second scan line 320 may include the gate electrode of the third transistor T3.

The third scan line 330 may be located below the initialization voltage line 310 and above the second scan line 320 in a plan view. The third scan line 330 may include the gate electrode of the fourth transistor T4.

Meanwhile, the gate electrode of the third transistor T3 and the gate electrode of the fourth transistor T4 may be wider than the peripheral line, but the width is not limited thereto.

The electrode line 340 of the storage capacitor (CST) crosses the center of the pixel and may be located between the second scanning line 320 and the emission control line 220 in a plan view. The electrode line 340 of the storage capacitor CST may be arranged to overlap the gate electrode 230 of the first transistor T1 with the second insulating layer 820 interposed therebetween. The gate electrode 230 of the first transistor T1 becomes the first electrode of the storage capacitor CST, and the extended area of the electrode line 340 of the storage capacitor CST overlapping with this becomes the first electrode of the storage capacitor CST. It becomes two electrodes, and the second insulating layer 820 interposed between them can be a dielectric of a storage capacitor (CST).

The electrode line 340 of the storage capacitor may be expanded in width in an area overlapping the gate electrode 230 of the first transistor T1. The electrode line 340 of the storage capacitor CST may include an opening that overlaps the gate electrode 230 of the first transistor T1 in the expanded area.

The second conductive layer 300 is made of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( It may contain one or more metals selected from Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

The third insulating layer 830 may be disposed on the second conductive layer 300 and cover the second conductive layer 300. The third insulating layer 830 may be disposed substantially over the entire surface of the substrate 910. The third insulating layer 830 may be a gate insulating film with a gate insulating function. The third insulating layer 830 may include the same material as the first insulating layer 810, or may include one or more materials selected from the materials exemplified as constituent materials of the first insulating layer 810. The third insulating layer 830 may be a single film or a multilayer film made of a stacked film of different materials.

The upper semiconductor layer 400 may be disposed on the third insulating layer 830. The upper semiconductor layer 400 may include first and second upper semiconductor patterns 410 and 420 that are separated from each other within the pixel PX.

The first upper semiconductor pattern 410 may be disposed to overlap the gate electrode of the third transistor T3 to form a channel of the third transistor T3. Similarly, the second upper semiconductor pattern 420 may be disposed to overlap the gate electrode of the fourth transistor T4 to form a channel of the fourth transistor T4. The first upper semiconductor pattern 410 may have a rectangular shape, but is not limited thereto.

The upper semiconductor layer 400 may include an oxide semiconductor. For example, the upper semiconductor layer 400 is a binary compound (ABx) or ternary compound containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. It may include a compound (ABxCy) and a four-component compound (ABxCyDz). In one embodiment, the upper semiconductor layer 400 may include ITZO (oxide containing indium, tin, and titanium) or IGZO (oxide containing indium, gallium, and tin).

The third conductive layer 500 may include first to fourth data patterns 510, 520, 530, and 540.

The first to fourth data patterns 510, 520, 530, and 540 may be physically spaced apart from each other. Each of the first to fourth data patterns 510, 520, 530, and 540 electrically connects separated portions of the first, third, fourth, and eighth transistors T1, T3, T4, and T8. , may form the first or second electrode of an NMOS transistor (for example, the third transistor T3). When the third conductive layer 500 overlaps the upper semiconductor layer 400, the third conductive layer 500 may contact the top surface of the upper semiconductor layer 400 directly or through an ohmic contact layer.

The first data pattern 510 may overlap the gate electrode 230 of the first transistor T1. In the overlapping area (i.e., the area where the first data pattern 510 and the gate electrode 230 of the first transistor T1 overlap), the third insulating layer 830 and the second insulating layer 820 are penetrated. A first contact hole (CNT1) exposing the gate electrode 240 of the first transistor (T1) may be formed. The first data pattern 510 may be electrically connected to the gate electrode 240 of the first transistor (T1) through the first contact hole (CNT1).

The first contact hole CNT1 may be located within the opening of the electrode line 340 of the storage capacitor CST. Inside the first contact hole (CNT1), the first data pattern 510 and the electrode line 340 of the storage capacitor (CST) adjacent thereto may be insulated from each other through the third insulating layer 830.

The first data pattern 510 extends upward from the overlapping area with the gate electrode 240 of the first transistor T1, and may overlap while being insulated from the second scan line 320. The first data pattern 510 extends further upward, and the first data pattern 510 overlaps the lower side of the third vertical portion 130 (or the second lower semiconductor pattern) of the lower semiconductor layer 100. You can.

In the area overlapping the first data pattern 510 and the third vertical portion 130 of the lower semiconductor layer 100, an eighth transistor ( A second contact hole (CNT2) exposing the second electrode of T8) may be formed. The first data pattern 510 may be electrically connected to the second electrode of the eighth transistor T8 through the second contact hole CNT2.

Additionally, the first data pattern 510 extends further upward, and the first data pattern 510 may overlap the second upper semiconductor pattern 420 . A portion of the first data pattern 510 that overlaps the second upper semiconductor pattern 420 may form the first electrode of the fourth transistor T4.

The second data pattern 520 may overlap the first vertical portion 110 (or horizontal portion 140) of the lower semiconductor layer 100. In the area where the second data pattern 520 and the first vertical portion 110 of the lower semiconductor layer 100 overlap, the lower semiconductor layer ( A third contact hole (CNT3) exposing the first vertical portion 110 of 100 may be formed. The second data pattern 520 may be electrically connected to the second electrode of the first transistor T1 and/or the second electrode of the sixth transistor T6 through the third contact hole CNT3.

The second data pattern 520 extends upward and may overlap the first upper semiconductor pattern 410 . A portion of the second data pattern 520 that overlaps the first upper semiconductor pattern 410 may form the first electrode of the third transistor T3.

The third data pattern 530 may overlap the first upper semiconductor pattern 410 . A portion of the third data pattern 530 that overlaps the first upper semiconductor pattern 410 may form the second electrode of the third transistor T3.

Additionally, the third data pattern 530 may overlap the third vertical portion 130 of the lower semiconductor layer 100. In the area where the third data pattern 530 and the first upper semiconductor pattern 410 overlap, the third vertical layer of the lower semiconductor layer 100 penetrates the first to third insulating layers 810, 820, and 830. A fourth contact hole (CNT4) exposing the portion 130 may be formed. The third data pattern 530 may be electrically connected to the first electrode of the eighth transistor T8 through the fourth contact hole CNT4.

The fourth data pattern 540 may overlap the second upper semiconductor pattern 420. A portion of the fourth data pattern 540 that overlaps the second upper semiconductor pattern 420 may form the second electrode of the fourth transistor T4. The fourth data pattern 540 extends upward and may overlap the initialization voltage line 310. In the area where the fourth data pattern 540 overlaps the initialization voltage line 310, a fourteenth contact hole (CNT14) that penetrates the third insulating layer 830 and exposes the initialization voltage line 310 may be formed. The fourth data pattern 540 may be connected to the initialization voltage line (VINT) through the 14th contact hole (CNT14).

The third conductive layer 500 is made of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), and neodymium ( It may contain one or more metals selected from Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 500 may be a single layer or a multilayer layer. For example, the third conductive layer 500 may be formed in a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, etc.

The fourth insulating layer 840 is disposed on the third conductive layer 500 and may be generally disposed over the entire surface of the substrate 910. The fourth insulating layer 840 may be an interlayer insulating film that insulates the third conductive layer 500 and the fourth conductive layer 600. The fourth insulating layer 840 may include the same material as the above-described second insulating layer 820, or may include one or more materials selected from the materials exemplified as constituent materials of the second insulating layer 820. The fourth insulating layer 840 may be a single layer or a multilayer layer made of a stack of different materials.

The fourth conductive layer 600 is disposed on the fourth insulating layer 840. The fourth conductive layer 600 includes the first power voltage line 610 that supplies the first power voltage ELVDD, the bridge line 620 of the initialization voltage line 310, and the fifth and sixth data patterns 630. 640).

As shown in FIG. 6 , the first power voltage line 610 may extend in the row direction through the center of the pixel PX. The first power voltage line 610 may extend along the row direction beyond the boundary of a pixel to a neighboring pixel. The first power voltage line 610 may extend upward from one of the two sides of the pixel PX and may extend downward from the other side of the pixel PX. For example, the first power voltage line 610 may extend upward from the left center portion of the pixel PX and may extend rightward from the center right portion of the pixel PX. The first power voltage wire 610 may also extend along the column direction beyond the boundary of a pixel to a neighboring pixel.

The first power voltage line 610 may cover most of the pixel PX except for the bridge line 620 and the fifth and sixth data patterns 630 and 640. That is, the width of the first power voltage wire 610 can be formed as wide as possible, and in this case, a relatively uniform current can be supplied to the pixels through the first power voltage wire 610, and the display device ( 1) The long range luminance uniformity (LRU) may be 90% or more. In addition, the first power voltage wiring 610, that is, a direct current voltage wiring, is formed between the gate electrode 240 of the first transistor T1 and a data line to be described later, to prevent crosstalk caused by the data line. It can be shielded or reduced.

The bridge wiring 620 may overlap the initialization voltage line 310 and extend downward.

The fifth data pattern 630 may overlap the upper portion 121 of the second vertical portion 120 of the lower semiconductor layer 100. In the area where the fifth data pattern 630 overlaps the upper portion 121 of the second vertical portion 120 of the lower semiconductor layer 100, first to fourth insulating layers 810, 820, 830, and 840 ) may be formed to penetrate the sixth contact hole (CNT6) to expose the lower semiconductor layer 100. The fifth data pattern 630 may be electrically connected to the first electrode of the second transistor T2 through the sixth contact hole CNT6.

The sixth data pattern 640 may overlap the first vertical portion 110 of the lower semiconductor layer 100. A fifth contact hole CNT5 may be formed in an area where the sixth data pattern 640 overlaps the first vertical portion 110 of the lower semiconductor layer 100. The sixth data pattern 640 may be electrically connected to the first electrode of the sixth transistor T6 through the fifth contact hole CNT5.

The fourth conductive layer 600 is made of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), and neodymium ( It may contain one or more metals selected from Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 600 may be a single layer or a multilayer layer. For example, the fourth conductive layer 600 may be formed in a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, etc.

The fifth insulating layer 850 is disposed on the fourth conductive layer 600 and may be generally disposed over the entire surface of the substrate 910. The fifth insulating layer 850 may insulate the fourth conductive layer 600 and the fifth conductive layer 700. The fifth insulating layer 850 may include the same material as the above-described second insulating layer 820, or may include one or more materials selected from the materials exemplified as constituent materials of the second insulating layer 820. The fifth insulating layer 850 may be a single film or a multilayer film made of a stacked film of different materials.

The fifth conductive layer 700 is disposed on the fifth insulating layer 850. The fifth conductive layer 700 may include a data line 710 and a via electrode 720.

The data line 710 is disposed on the right side of the pixel PX and may extend along the column direction. The data line 710 may overlap the fifth data pattern 630. In the area where the data line 710 overlaps the fifth data pattern 630, a 21st contact hole (CNT21) that penetrates the fifth insulating layer 850 and exposes the fifth data pattern 630 may be formed. there is. In this case, the data line 710 is electrically connected to the fifth data pattern 630 through the 21st contact hole (CNT21), and also through the fifth data pattern 630 and the 11th contact hole (CNT11). It may be electrically connected to the first electrode of the second transistor T2.

The via electrode 720 may overlap the sixth data pattern 640. In the area where the via electrode 720 overlaps the sixth data pattern 640, a twenty-second contact hole (CNT22) that penetrates the fifth insulating layer 850 and exposes the sixth data pattern 640 may be formed. there is. In this case, the via electrode 720 is electrically connected to the sixth data pattern 640 through the 22nd contact hole (CNT22), and is also electrically connected to the sixth data pattern 640 and the 12th contact hole (CNT12). It may be electrically connected to the second electrode of the sixth transistor T6.

The fifth conductive layer 700 is made of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), and neodymium ( It may contain one or more metals selected from Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fifth conductive layer 700 may be a single layer or a multilayer layer. For example, the fifth conductive layer 700 may be formed in a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, etc.

The sixth insulating layer 860 is disposed on the fifth conductive layer 700 and may be generally disposed over the entire surface of the substrate 910. The sixth insulating layer 860 may insulate the fifth conductive layer 700 and the light emitting device EL. The sixth insulating layer 860 may include the same material as the above-described second insulating layer 820, or may include one or more materials selected from the materials exemplified as constituent materials of the second insulating layer 820. The sixth insulating layer 860 may be a single film or a multilayer film made of a stacked film of different materials.

The anode electrode (ANODE) of the light emitting device (EL) may be disposed on the sixth insulating layer 860. The anode electrode (ANODE) may overlap the via electrode (720). In the area where the anode electrode (ANODE) overlaps the via electrode 720, a contact hole (not shown) is formed through the sixth insulating layer 860 to expose the via electrode 720, and the anode electrode (ANODE) may be electrically connected to the via electrode 720 through a contact hole (not shown).

Additionally, the anode electrode ANODE may be disposed to overlap the third and fourth transistors T3 and T4. In this case, the anode electrode ANODE may block external light from entering from the top of the third and fourth transistors T3 and T4 (i.e., bottom gate type transistors).

A pixel defining layer (PDL) is disposed along the edge of the anode electrode (ANODE), and although not shown, a cathode electrode (CATHOD) of the light emitting device (EL) may be disposed on top of the anode electrode (ANODE).

As described with reference to FIGS. 4 to 6, each of the first, second, fifth to eighth transistors (T1, T2, T5, T6, T7, and T8) is a top gate type PMOS transistor, and the third and each of the fourth transistors T3 and T4 may be a bottom gate type NMOS transistor. In the plan view, from the top to the bottom of the pixel PX, the initialization voltage line 310, the third scan line 330, the first scan line 210, the second scan line 320, and the emission control line 220 are arranged sequentially. , the third transistor T3 is disposed to overlap the second scan line 320, and the eighth transistor T8 is disposed to overlap the first scan line 210 on the upper side of the pixel PX than the third transistor T3. can be placed. Additionally, the third transistor T3, the eighth transistor T8, and the fourth transistor T4 may be sequentially arranged from left to right of the pixel PX.

Meanwhile, in FIG. 7, each of the third and fourth transistors T3 and T4 is shown as a bottom gate type NMOS transistor, but is not limited thereto. For example, each of the third and fourth transistors T3 and T4 may be a top gate type NMOS transistor.

Figure 8 is a cross-sectional view of a pixel according to another embodiment.

Referring to FIGS. 2, 4, 7, and 8, the second scan line 320_1 (or the third conductive layer) is connected to the first upper semiconductor pattern 410 (or the upper semiconductor pattern) instead of the second insulating layer 820. It may be disposed on the semiconductor layer 400.

A gate insulating layer GI3 may be disposed on the first upper semiconductor pattern 410 (or upper semiconductor pattern 400). The gate insulating layer GI3 may be disposed only in an area on the first upper semiconductor pattern 410 that overlaps the second scan line 320_1.

The second scan line 320_1 may be disposed on the gate insulating layer GI3.

Although not shown, the fourth transistor T4 may have a stacked structure that is substantially the same as that of the third transistor T3.

Accordingly, the third transistor T3 (and the fourth transistor T4) may also be implemented as a top gate type NMOS transistor.

Figure 9 is a circuit diagram of a pixel according to another embodiment.

Referring to FIGS. 2 and 9 , the pixel PX_1 is different from the pixel PX of FIG. 2 in that it includes the ninth transistor T9 instead of the seventh transistor T7.

The light emitting element (EL), the storage capacitor (CST), and the first to sixth and eighth transistors (T1 to T6, T8) are the light emitting element (EL), the storage capacitor (CST), and the first transistors (T1 to T6, T8) described with reference to FIG. 2. Since it is substantially the same as the sixth to eighth transistors T1 to T6 and T8, overlapping description will not be repeated.

The ninth transistor T9 has a first electrode connected to the fifth node N5, a second electrode connected to an initialization voltage line (or initialization voltage (VINT)), and a light emission control signal line or a light emission control signal (EM). ) may include a gate electrode that receives.

The ninth transistor T9 may be an NMOS transistor. The ninth transistor T9 receives the emission control signal EM in the same way as the fifth transistor T5 and the sixth transistor T6, but the fifth transistor T5 and the sixth transistor T6 are PMOS transistors. ) may be turned on in a section different from the turn-on section (or turn-on timing) of ). For example, when the emission control signal EM is a high level voltage (or logic high level), the ninth transistor T9 is turned on and the fifth transistor T5 and the sixth transistor T6 are turned off. You can. As another example, when the emission control signal EM is a low level voltage (or logic low level), the ninth transistor T9 may be turned off and the fifth transistor T5 and the sixth transistor T6 may be turned on. there is. Therefore, at the light emission point when the fifth transistor T5 and the sixth transistor T6 are turned on, the initialization operation by the ninth transistor T9 is not performed, and the fifth transistor T5 and the sixth transistor T6 are turned on. An initialization operation may be performed by the ninth transistor T9 at a non-light-emitting time when it is turned off.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

1: Display device
10: display part
20: Scan driving unit
30: data driving unit
40: Light emission control driving unit
50: control unit
100: Lower semiconductor layer
200: first conductive layer
300: second conductive layer
400: upper semiconductor layer
500: third conductive layer
600: fourth conductive layer

Claims (22)

light emitting device;
a first transistor that delivers driving current to the light emitting device;
a second transistor connected to the first electrode of the first transistor to transmit a data signal;
a third transistor having a first electrode connected to a second electrode of the first transistor; and
An auxiliary transistor connected between the second electrode of the third transistor and the gate electrode of the first transistor to transmit the data signal to the gate electrode of the first transistor,
The first transistor, the second transistor, and the auxiliary transistor are first type transistors,
The third transistor is a second type transistor different from the first type transistor,
Further comprising a first scanning line,
The gate electrode of the second transistor is connected to the first scan line,
A display device wherein the gate electrode of the auxiliary transistor is connected to the first scan line. The method of claim 1, wherein the first type transistor is a PMOS transistor,
A display device in which the second type transistor is an NMOS transistor. The method of claim 1, wherein the first type transistor is a top gate transistor in which a gate electrode is disposed above the semiconductor layer,
The second type transistor is a bottom gate transistor whose gate electrode is disposed lower than the semiconductor layer. The method of claim 1, wherein the first type transistor includes an oxide semiconductor,
A display device in which the second type transistor includes polycrystalline silicon. The method of claim 1, further comprising a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line,
The fourth transistor is the second type transistor. According to clause 5,
A fifth transistor connected between the first electrode of the first transistor and the first power voltage line,
A sixth transistor connected between the second electrode of the first transistor and the first electrode of the light emitting device,
A seventh transistor connected between the first electrode of the light emitting device and the initialization voltage line, and
It further includes a storage capacitor formed between the first electrode of the first transistor and the first power voltage line,
Each of the fifth, sixth and seventh transistors is the first type transistor. According to claim 1,
further comprising a second scanning line,
A display device wherein the gate electrode of the third transistor is connected to the second scan line. The method of claim 7, wherein the second transistor and the auxiliary transistor are turned on in a first section in response to a first scan signal provided through the first scan line,
The third transistor is turned on in the first period in response to a second scan signal provided through the second scan line. The method of claim 7, wherein the second transistor and the auxiliary transistor are turned on in a first section in response to a first scan signal provided through the first scan line,
The third transistor is turned on in a second period in response to a second scan signal provided through the second scan line,
The second section is larger than the first section and includes the first section. The method of claim 9, wherein the second scan signal has a turn-on voltage level in the second section,
The display device wherein the second section of the second scan signal partially overlaps the second section of the second scan signal at a previous time. The method of claim 7, wherein the second scan line is disposed in a first direction with respect to the first transistor in a plan view, and the second scan line extends in a second direction perpendicular to the first direction,
The first scan line is disposed in the first direction with respect to the second scan line and is parallel to the second scan line,
The third transistor is disposed to partially overlap the second scan line,
The display device wherein the auxiliary transistor is disposed to partially overlap the first scan line. 12. The method of claim 11, wherein the third transistor has a channel extending in the first direction,
The auxiliary transistor has a channel extending in the first direction,
A display device in which the channel of the auxiliary transistor is disposed on a line different from the line along which the channel of the third transistor extends. According to claim 12,
Further comprising a data pattern extending in the second direction,
A display device wherein one end of the data pattern constitutes one electrode of the third transistor, and the data pattern is connected to one electrode of the third transistor through a first contact hole. The method of claim 7, wherein a first insulating layer is disposed on the third transistor,
The first scan line and the gate electrode of the third transistor are disposed on the first insulating layer,
The display device wherein the second scan line is disposed on a different layer from the layer on which the first scan line is disposed. According to claim 1,
A fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line,
A fifth transistor connected between the first electrode of the first transistor and the first power voltage line,
A sixth transistor connected between the second electrode of the first transistor and the first electrode of the light emitting device,
A seventh transistor connected between the cathode electrode of the light emitting device and the initialization voltage line, and
It further includes a storage capacitor formed between the first electrode of the first transistor and the first power voltage line,
Each of the fourth and seventh transistors is the second type transistor, and each of the fifth and sixth transistors is the first type transistor. According to claim 15,
Further comprising a light emission control signal line connected to the gate electrode of each of the fifth to seventh transistors,
The fifth and sixth transistors are turned on in the third section in response to a light emission control signal provided through a light emission control signal line,
A display device in which the seventh transistor is turned off in a third period in response to the emission control signal. According to claim 1,
A display device in which the light-emitting device is a quantum dot light-emitting device. light emitting device;
a first transistor that delivers driving current to the light emitting device;
a second transistor connected to the first electrode of the first transistor to transmit a data signal; and
A third transistor connected between the second electrode of the first transistor and the gate electrode of the first transistor to transmit the data signal to the gate electrode of the first transistor,
The third transistor includes first and second sub-transistors having different channel types and connected in series to each other,
Further comprising a first scanning line,
A display device wherein the gate electrode of the second transistor and the gate electrode of the first sub-transistor are connected to the first scan line. 19. The method of claim 18, wherein the first sub-transistor is a PMOS transistor,
A display device in which the second sub-transistor is an NMOS transistor. The method of claim 18, wherein the first sub-transistor is a top gate transistor whose gate electrode is disposed above the semiconductor layer,
The second sub-transistor is a bottom gate transistor whose gate electrode is disposed below the semiconductor layer. 19. The method of claim 18, wherein the first sub-transistor includes an oxide semiconductor,
A display device in which the second sub-transistor includes polycrystalline silicon. The display device of claim 18, wherein the light emitting device is a quantum dot light emitting device.

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