KR20220092721A - Display apparatus - Google Patents

Abstract

The present invention provides a display device having a reduced non-display area. According to the present invention, the display device comprises: a substrate in which a transmissive area, a display area surrounding at least a portion of the transmissive area, a non-display area between the transmissive area and the display area, and a peripheral area outside the display area are defined; a plurality of pixels arranged along pixel rows and pixel columns on the display area; a plurality of initialization gate lines and a plurality of compensation gate lines respectively arranged in the pixel rows; a plurality of gate driving circuits arranged in a column direction on the peripheral area; and a plurality of gate connection lines arranged on the non-display area. A k^th gate driving circuit among the plurality of gate driving circuits simultaneously drives m^th and (m+1)^th initialization gate lines among the plurality of initialization gate lines, and n^th and (n+1)^th compensation gate lines among the plurality of compensation gate lines. Each of the m^th and (m+1)^th initialization gate lines and the n^th and (n+1)^th compensation gate lines has a first portion and a second portion physically separated by the transmissive area, and first portions of the n^th and (n+1)^th compensation gate lines and second portions of the n^th and (n+1)^th compensation gate lines are electrically connected to each other through a first gate connection line of the plurality of gate connection lines.

Description

Display apparatus

The present invention relates to a display device.

A display device is a device that visually displays data. The display device is used as a display of small products such as mobile phones, and is also used as a display of large products such as televisions.

Such a display device includes a substrate divided into a display area and a non-display area, and the gate line and the data line are insulated from each other in the display area. A plurality of pixel areas are defined in the display area, and pixels respectively disposed in the plurality of pixel areas receive electrical signals from gate lines and data lines crossing each other to display an image to the outside and emit light. A thin film transistor and a pixel electrode electrically connected to the thin film transistor are provided in each pixel region or each of pixel regions, and a counter electrode is provided in common to the pixel regions . The non-display area may include various wirings that transmit electrical signals to pixels in the display area, a gate driver, and pads to which the data driver and the controller may be connected.

2. Description of the Related Art In recent years, display devices have diversified their uses. In addition, the thickness of the display device is thin and the weight is light, and the range of its use is widening. As the number of users increases, research on providing visual satisfaction to users is being actively conducted, and one of them is to expand the display area of the display device. Various studies are being attempted to expand the display area.

SUMMARY Embodiments of the present invention provide a display device having a reduced non-display area. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

According to one aspect of the present invention, there is provided a substrate comprising: a substrate in which a transparent area, a display area surrounding at least a portion of the transparent area, a non-display area between the transparent area and the display area, and a peripheral area outside the display area are defined; a plurality of pixels arranged along pixel rows and pixel columns on the display area; a plurality of initialization gate lines and a plurality of compensation gate lines respectively arranged in the pixel rows; a plurality of gate driving circuits arranged in a column direction on the peripheral region; and a plurality of gate connection lines disposed on the non-display area, wherein a kth gate driving circuit among the plurality of gate driving circuits is an mth and m+1th initialization gate line among the plurality of initialization gate lines. and simultaneously driving nth and n+1th compensation gate lines among the plurality of compensation gate lines, the mth and m+1th initialization gate lines and the nth and n+1th compensation gate lines each of which has a first portion and a second portion physically spaced apart by the transmission region, and the first portions of the n-th and n+1-th compensation gate lines and the n-th and n+1-th compensation gates The second portions of the lines are electrically connected to each other through a first gate connection line among the plurality of gate connection lines, wherein k and n are natural numbers, and m is a natural number greater than n+1. ) is provided.

According to an example, an even number of pixel rows may be disposed between the n+1th pixel row and the mth pixel row.

According to an example, the first portions of the mth and m+1th initialization gate lines and the second portions of the mth and m+1th initialization gate lines are a second one of the plurality of gate connection lines They may be electrically connected to each other through a gate connection line.

According to an example, the first gate connection line may electrically connect the first portions of the m-th and m+1th initialization gate lines and the second portions of the m-th and m+1th initialization gate lines to each other. It may be characterized by connecting.

According to an example, two pixel rows are disposed between an n+1th pixel row and an mth pixel row, and nth and n+1th initialization gate lines among the plurality of initialization gate lines drive the plurality of gates. are simultaneously driven by the k-2th gate driving circuit of the circuits, and the mth and m+1th compensation gate lines of the plurality of compensation gate lines are the k+2th gate driving circuit of the plurality of gate driving circuits can be driven simultaneously.

According to an example, the mth pixel row may be a pixel row following the n+1th pixel row.

According to an example, the first gate connection line may electrically connect the first portions of the m-th and m+1th initialization gate lines and the second portions of the m-th and m+1th initialization gate lines to each other. can be connected

According to an example, the first portions of the mth and m+1th initialization gate lines and the second portions of the mth and m+1th initialization gate lines are a second one of the plurality of gate connection lines They may be electrically connected to each other through a gate connection line.

According to an example, nth and n+1th initialization gate lines among the plurality of initialization gate lines are simultaneously driven by a k−1th gate driving circuit among the plurality of gate driving circuits, and the plurality of compensation gates Among the lines, the mth and m+1th compensation gate lines may be simultaneously driven by the k+1th gate driving circuit among the plurality of gate driving circuits.

According to an example, m+1 may be equal to 2k.

According to an example, the k-th gate driving circuit is disposed at one side of the peripheral region, and a first portion of the m-th and m+1th initialization gate lines and the nth and n+1th compensation gate lines a one-side gate driving circuit configured to output a first gate signal to the ? and a second gate disposed on the other side of the peripheral region, the same as the first gate signal, in second portions of the mth and m+1th initialization gate lines and the nth and n+1th compensation gate lines It may include a second gate driving circuit configured to output a signal.

In an example, the display device may include a plurality of scan lines respectively arranged in the pixel rows; a plurality of scan driving circuits arranged in a column direction on the peripheral area and sequentially driving the plurality of scan lines; and a plurality of scan connection lines disposed on the non-display area, wherein each of the nth and n+1th scan lines among the plurality of scan lines is physically spaced apart from each other by the transparent area. a portion and a second portion, wherein the first portion of the n-th scan line and the second portion of the n-th scan line are electrically connected to each other through a first scan connection line among the plurality of scan connection lines; , the first portion of the n+1th scan line and the second portion of the n+1th scan line may be electrically connected to each other through a second scan connection line among the plurality of scan connection lines.

In an example, the first scan connection line may include a first scan connection electrode electrically connecting the first portion of the n-th scan line and the second portion of the n-th scan line to each other; and a second scan connection electrode electrically connecting the first portion of the nth scan line and the second portion of the nth scan line to each other.

In an example, the display device may include: a first conductive layer including the first scan connection electrode; a semiconductor layer on the first conductive layer; and a second conductive layer disposed on the semiconductor layer and including the second scan connection electrode.

In an example, the display device may include: a plurality of emission control lines respectively arranged in the pixel rows; and a plurality of light emission control driving circuits arranged along a column direction on the peripheral area, wherein each of the nth and n+1th light emission control lines among the plurality of light emission control lines is formed by the transmissive area It has a first portion and a second portion that are physically spaced apart and electrically insulated, and the first portions of the nth and n+1th light emission control lines are disposed on one side of the peripheral region of the plurality of light emission control driving circuits. a second light emission control driving circuit disposed at the same time, and the second portions of the nth and n+1th light emission control lines are disposed on the other side of the peripheral region among the plurality of light emission control driving circuits They can be simultaneously driven by the light emission control driving circuit.

In an example, the display device may include: a plurality of emission control lines respectively arranged in the pixel rows; a plurality of light emission control driving circuits arranged along a column direction on the peripheral area; and a light emission control connection line disposed on the non-display area, wherein each of the nth and n+1th light emission control lines among the plurality of light emission control lines is a first light emission control line that is physically spaced apart by the transmissive area has a first portion and a second portion, wherein the first portions of the nth and n+1th emission control lines and the second portions of the nth and n+1th emission control lines connect the emission control connection line through which they can be electrically connected to each other.

According to an example, each of the pixels disposed in an nth pixel row among the plurality of pixels may include: a light emitting device; a driving transistor for controlling a current flowing to the light emitting device according to a gate-source voltage; a scan transistor that transmits a data voltage to the driving transistor in response to a scan signal; a gate initialization transistor configured to apply an initialization voltage to the gate of the driving transistor in response to a signal transmitted through an nth initialization gate line among the plurality of initialization gate lines; and a compensation transistor that connects a drain and a gate of the driving transistor to each other in response to a signal transmitted through the n-th compensation gate line.

In an example, conductivity types of the gate initialization transistor and the compensation transistor may be opposite to those of the scan transistor.

In an example, the display device may include: a first semiconductor layer including an active region of the scan transistor; a second semiconductor layer including an active region of the gate initialization transistor and an active region of the compensation transistor; and at least one conductive layer between the first semiconductor layer and the second semiconductor layer.

According to an example, the first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

According to an example, the on-section length of the signal transmitted through the n-th compensation gate line may be equal to or greater than twice the on-section length of the scan signal.

According to an example, the substrate may have a through hole corresponding to the transmission region.

According to another aspect of the present invention, there is provided a substrate comprising: a substrate in which a transmissive region, a display region surrounding at least a portion of the transmissive region, a non-display region between the transmissive region and the display region, and a peripheral region outside the display region are defined; a plurality of pixels arranged along pixel rows and pixel columns on the display area; a plurality of gate lines respectively arranged in the pixel rows; and a plurality of gate connection lines disposed on the non-display area, and each of mth and m+1th gate lines and nth and n+1th gate lines among the plurality of gate lines is the transmissive region has a first portion and a second portion physically spaced apart by The first portions of the m and m+1th gate lines and the second portions of the mth and m+1th gate lines are electrically connected to each other through a first gate connection line among the plurality of gate connection lines A display device (n is a natural number and m is a natural number greater than n+1) is provided.

According to an example, the first portions of the nth and n+1th gate lines and the second portions of the nth and n+1th gate lines are connected to a second gate connection line among the plurality of gate connection lines They may be electrically connected to each other through a line.

In an example, the first gate connection line may electrically connect the first portions of the nth and n+1th gate lines and the second portions of the nth and n+1th gate lines to each other. have.

According to an example, the second portions of the mth and m+1th and nth and n+1th gate lines may be connected to each other in the peripheral region.

Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for carrying out the invention.

According to an embodiment of the present invention made as described above, a display device having a reduced non-display area can be implemented. Of course, the scope of the present invention is not limited by these effects.

1 is a perspective view schematically illustrating an electronic device according to an embodiment of the present invention.
FIG. 2 is an exemplary cross-sectional view taken along line II′ of the electronic device of FIG. 1 .
3 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.
4 is an enlarged plan view schematically illustrating a display device according to another exemplary embodiment.
5 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.
6 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.
7 is an enlarged plan view schematically illustrating a display device according to another exemplary embodiment.
8 is an equivalent circuit diagram schematically illustrating one pixel of a display device according to an exemplary embodiment.
9 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.
10 is a timing diagram for explaining a method of driving a plurality of pixels according to an embodiment of the present invention.
11 is a timing diagram for explaining a method of driving a plurality of pixels according to another embodiment of the present invention.
12 and 13 are exemplary cross-sectional views taken along II-II′ of the display device of FIG. 9 .

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

In the following embodiments, terms such as 1st, 2nd, etc. are used for the purpose of distinguishing one component from another without limiting meaning.

In the following embodiments, the singular expression includes the plural expression unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and do not exclude in advance the possibility that one or more other features or components will be added. .

In the following embodiments, when it is said that a part such as a film, region, or component is on or on another part, other films, regions, components, etc. are interposed in the middle as well as directly on the other part. Including cases where

In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

In cases where certain embodiments may be implemented otherwise, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

In the present specification, "A and/or B" refers to A, B, or A and B. And, "at least one of A and B" represents the case of A, B, or A and B.

In the following embodiments, when a film, region, or component is connected, when the film, region, or component is directly connected, or/and in the middle of another film, region, or component It includes cases where they are interposed and indirectly connected. For example, in the present specification, when it is said that a film, region, component, etc. are electrically connected, when the film, region, component, etc. are directly electrically connected, and/or another film, region, component, etc. is interposed therebetween. This indicates an indirect electrical connection.

The x-axis, y-axis, and z-axis are not limited to three axes on a Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

1 is a perspective view schematically illustrating an electronic device according to an embodiment of the present invention.

Referring to FIG. 1 , an electronic device 1 is a device that displays a moving image or still image, and includes a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, and an electronic notebook. , electronic books, portable multimedia players (PMPs), navigation devices, portable electronic devices such as UMPCs (Ultra Mobile PCs), etc. It can be used as a screen.

In addition, the electronic device 1 according to an embodiment is a wearable device such as a smart watch, a watch phone, a glasses display, and a head mounted display (HMD). can be used

The electronic device 1 according to another embodiment includes a dashboard of a vehicle, a center information display (CID) disposed on a center fascia or dashboard of a vehicle, and a room mirror display in place of a side mirror of the vehicle. display), as entertainment for the rear seat of a car, can be used as a display placed on the back of the front seat. 1 illustrates that the electronic device 1 according to an embodiment is used as a smart phone for convenience of description.

The electronic device 1 may have a rectangular shape in plan view. For example, the electronic device 1 may have a rectangular planar shape having a short side in a ±x direction and a long side in a ±y direction as shown in FIG. 1 . An edge where the short side in the ±x direction and the long side in the ±y direction meet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the electronic device 1 is not limited to a rectangle, and may be formed in other polygonal, elliptical, or irregular shapes.

The electronic device 1 may include a transmissive area TA and a display area DA at least partially surrounding the transmissive area TA. The electronic device 1 includes a non-display area NDA positioned between the transparent area TA and the display area DA, and a peripheral area PA to surround the outside of the display area DA, for example, the display area DA. ) may be included.

The transmission area TA may be located inside the display area DA. In an embodiment, the transmission area TA may be disposed on the upper left side of the display area DA as shown in FIG. 1 . Alternatively, the transmission area TA may be disposed in various ways, such as disposed in the center of the display area DA or disposed at the right side of the display area DA. In the plan view of the present specification, "left", "right", "top", and "bottom" indicate directions when the electronic device 1 is viewed from a vertical direction of the electronic device 1 . For example, "left" indicates a -x direction, "right" indicates a +x direction, "top" indicates a +y direction, and "bottom" indicates a -y direction. 1 illustrates that one transmission area TA is disposed, as another embodiment, a plurality of transmission areas TA may be provided.

The electronic device 1 may provide an image using a plurality of pixels PXs disposed in the display area DA. Each of the pixels PX may include a display element. Each of the pixels PX may include a display element such as an organic light-emitting diode (OLED). Each pixel PX may emit, for example, red, green, blue, or white light through the organic light emitting diode. Hereinafter, in the present specification, each pixel PX means a sub-pixel emitting a different color, and each pixel PX may be, for example, one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. can

FIG. 2 is an exemplary cross-sectional view taken along line II′ of the electronic device of FIG. 1 .

Referring to FIG. 2 , the electronic device 1 may include a display device 10 and a component 70 disposed in the transparent area TA of the display device 10 . The display device 10 and the component 70 may be accommodated in the housing HS.

The display device 10 may include a display element layer 20 , an input sensing layer 40 , an optical function layer 50 , and a cover window 60 .

The display element layer 20 may include display elements (or light emitting elements) that emit light to display an image. The display element may comprise a light emitting diode, for example an organic light emitting diode comprising an organic light emitting layer.

In another embodiment, the light emitting diode may be an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode may include a PN junction diode comprising inorganic semiconductor based materials. When a voltage is applied to the PN junction diode in a forward direction, holes and electrons are injected, and energy generated by recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The inorganic light emitting diode may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light emitting diode may be referred to as a micro LED. In another embodiment, the display element layer 20 may include a quantum dot light emitting diode.

That is, the emission layer of the display element layer 20 may include an organic material, include an inorganic material, include quantum dots, include an organic material and quantum dots, or include an inorganic material and quantum dots.

The input sensing layer 40 may acquire coordinate information according to an external input, for example, a touch event. The input sensing layer 40 may include a sensing electrode or a touch electrode and signal lines connected to the sensing electrode. The input sensing layer 40 may be disposed over the display element layer 20 . The input sensing layer 40 may sense an external input using a mutual cap method and/or a self cap method.

The input sensing layer 40 may be directly formed on the display element layer 20 , or may be separately formed and then coupled through an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be continuously formed after the process of forming the display element layer 20 . In this case, the adhesive layer may not be interposed between the input sensing layer 40 and the display element layer 20 . can 2 shows the input sensing layer 40 interposed between the display element layer 20 and the optical functional layer 50 , however, in another embodiment, the input sensing layer 40 is disposed over the optical functional layer 50 . can be

The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce reflectance of light (external light) incident toward the display device 10 from the outside through the cover window 60 . The anti-reflection layer may include a retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type. The polarizer may also be a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a predetermined arrangement.

In another embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged in consideration of the color of light emitted from each of the light emitting diodes of the display element layer 20 . In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light respectively reflected from the first and second reflective layers may destructively interfere, and thus external light reflectance may be reduced.

The optical function layer 50 may include a lens layer. The lens layer may improve light output efficiency of light emitted from the display element layer 20 or reduce color deviation. The lens layer may include a layer having a concave or convex lens shape, and/or a plurality of layers having different refractive indices. The optical function layer 50 may include all of the above-described anti-reflection layer and the lens layer, or any one of them.

The display device 10 may include an opening 10H. In this regard, FIG. 2 shows that the display element layer 20 , the input sensing layer 40 , and the optical function layer 50 include first to third openings 20H, 40H, and 50H, respectively, and first to It is shown that the third openings 20H, 40H, 50H overlap each other.

The first opening 20H may pass through the bottom surface from the top surface of the display element layer 20 , and the second opening 40H may penetrate the bottom surface from the top surface of the input sensing layer 40 , and the third The opening 50H may pass through the bottom surface from the top surface of the optical function layer 50 .

The opening 10H of the display device 10 , for example, the first to third openings 20H, 40H, and 50H may be positioned to overlap each other in the transmission area TA. The sizes (or diameters) of the first to third openings 20H, 40H, and 50H may be the same as each other. As another example, the sizes (or diameters) of the first to third openings 20H, 40H, and 50H may be different from each other.

In another embodiment, at least one of the display element layer 20 , the input sensing layer 40 , and the optical function layer 50 may not include an opening. For example, any one or two components selected from the display element layer 20 , the input sensing layer 40 , and the optical function layer 50 may not include an opening.

The cover window 60 may be disposed on the optical functional layer 50 . The cover window 60 may be coupled to the optical functional layer 50 through an adhesive layer such as an optical clear adhesive (OCA) interposed therebetween. The cover window 60 may include a glass material or a plastic material. The plastic material may include polyether sulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. .

The cover window 60 may include a window having flexibility. For example, the cover window 60 may include a polyimide window or an ultra-thin glass window.

The transparent area TA may be a kind of component area (eg, a sensor area, a camera area, a speaker area, etc.) in which the component 70 for adding various functions to the electronic device 1 is located. The component 70 may be disposed to overlap the opening 10H of the display device 10 .

Component 70 may include electronic elements. For example, component 70 may be an electronic element using light or sound. For example, the electronic element is a sensor that uses light such as an infrared sensor, a camera that captures an image by receiving light, a sensor that measures a distance or recognizes a fingerprint by outputting and sensing light or sound, a small lamp that outputs light, or , a speaker outputting sound, and the like.

Electronic elements using light may use light of various wavelength bands, such as visible light, infrared light, ultraviolet light, and the like. The transmission area TA may correspond to an area through which light output from the component 70 or traveling toward the electronic element from the outside can transmit.

In another embodiment, when the electronic device 1 is used as a smart watch or a vehicle dashboard, the component 70 is a member including a watch hand or a needle indicating predetermined information (eg, vehicle speed, etc.) can be In this case, the cover window 60 may include an opening located in the transmission area TA, unlike that shown in FIG. 2 , so that the component 70 such as a needle can be exposed to the outside. Alternatively, even when the electronic device 1 includes a component 70 such as a speaker, the cover window 60 may include an opening corresponding to the transmission area TA.

3 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.

Referring to FIG. 3 , the display device 10 may include a transparent area TA, a display area DA, a non-display area NDA, and a peripheral area PA. The non-display area NDA may surround at least a portion of the transmission area TA. The non-display area NDA is an area in which a display element such as an organic light emitting diode emitting light is not disposed. Signal lines that provide a signal to may pass. The display device 10 may include an opening 10H corresponding to the transmission area TA.

Since the display device 10 includes the substrate 100 , the substrate 100 includes (or defines) the transmissive area TA, the display area DA, the non-display area NDA, and the peripheral area PA. you might say do Also, the substrate 100 may include an opening corresponding to the transmission area TA.

The display device 10 may include a plurality of pixels PXs disposed in the display area DA. The pixels PX may be arranged along pixel rows and pixel columns. Each of the pixel rows may extend in a row direction (eg, a ±x direction), and each of the pixel columns may extend in a column direction (eg, a ±y direction).

The display device 10 may display an image using light emitted from the light emitting diode of each pixel PX, for example, red, green, and blue light. The light emitting diode of each pixel PX may include an organic light emitting diode OLED, which will be described later with reference to FIG. 8 , and each organic light emitting diode OLED may be electrically connected to the pixel circuit PC. 8 illustrates that the light emitting diode includes an organic light emitting diode (OLED), as another embodiment, the display device 10 may include the inorganic light emitting diode described above instead of the organic light emitting diode (OLED). As described.

Each of the pixels PX may be electrically connected to external circuits disposed in the peripheral area PA. A plurality of gate driving circuits GDC may be disposed in the peripheral area PA. The gate driving circuits GDC may be arranged along the column direction (eg, ±x direction) on the peripheral area PA as shown in FIG. 3 .

The gate driving circuits GDC may be connected to a plurality of compensation gate lines GC and a plurality of initialization gate lines GI respectively arranged in pixel rows. The gate driving circuits GDC may be respectively connected to the compensation gate lines GC and the initialization gate lines GI extending in the row direction (eg, the ±x direction).

The compensation gate lines GC may be respectively connected to the pixels PX located in the same row. The compensation gate lines GC may sequentially transmit electrical signals to the pixels PX located in the same row, respectively. For example, as shown in FIG. 3 , an n-th compensation gate line GCn among the plurality of compensation gate lines GC may be connected to the n-th pixels PXn positioned in an n-th row, and Electrical signals may be sequentially transmitted to the pixels PXn. Also, an n+1-th compensation gate line GCn+1 among the plurality of compensation gate lines GC may be connected to the n+1-th pixels PXn+1 positioned in an n+1-th row, Electrical signals may be sequentially transmitted to the n+1 pixels PXn+1. Here, n is a natural number.

The initialization gate lines GI may be respectively connected to the pixels PX located in the same row. The initialization gate lines GI may sequentially transmit electrical signals to the pixels PX located in the same row, respectively. For example, as shown in FIG. 3 , an m-th initialization gate line GIm among the plurality of initialization gate lines GI may be connected to m-th pixels PXm positioned in an m-th row, and may be an m-th initialization gate line GIm. Electrical signals may be sequentially transmitted to the pixels PXm. Also, an m+1th initialization gate line GIm+1 among the plurality of initialization gate lines GI may be connected to the m+1th pixels PXm+1 positioned in the m+1th row, Electrical signals may be sequentially transmitted to the m+1 pixels PXm+1. Here, m is a natural number greater than n+1.

Since m is greater than n+1, a plurality of pixel rows may be disposed between the n+1th pixel row and the mth pixel row. For example, an even number of pixel rows may be disposed between the n+1th pixel row and the mth pixel row. For example, two pixel rows may be disposed between the n+1th pixel row and the mth pixel row.

Alternatively, the mth pixel row may be a pixel row following the n+1th pixel row. That is, m may be n+2.

In an embodiment, each of the gate driving circuits GDC may simultaneously drive a plurality of compensation gate lines GC and simultaneously drive a plurality of initialization gate lines GI. The compensation gate lines GC and the initialization gate lines GI driven by the same gate driving circuit GDC may be connected to each other in the peripheral area PA.

For example, as shown in FIG. 3 , the k-th gate driving circuit GDCk among the plurality of gate driving circuits GDC includes the n-th compensation gate line GCn and the n-th compensation gate line GCn among the plurality of compensation gate lines GC. The n+1 compensation gate line GCn+1 and the mth initialization gate line GIm and the m+1th initialization gate line GIm+1 among the plurality of initialization gate lines GI may be simultaneously driven. . The nth compensation gate line GCn, the n+1th compensation gate line GCn+1, the mth initialization gate line GIm, and the m+1th initialization gate line GIm+1 are in the peripheral area PA. can be connected to each other in Here, k is a natural number.

3 illustrates that each of the gate driving circuits GDC simultaneously drives the two compensation gate lines GC and the two initialization gate lines GI, but each of the gate driving circuits GDC simultaneously drives The number of compensation gate lines GC and/or the number of initialization gate lines GI may be variously changed.

In an embodiment, each of the compensation gate lines GC adjacent to the transmission area TA in the row direction (eg, ±x direction) among the plurality of compensation gate lines GC is in the transmission area TA. It may have a first portion and a second portion that are physically spaced apart by the For example, as illustrated in FIG. 3 , an n-th compensation gate line GCn among the plurality of compensation gate lines GC is physically separated from a first portion GCan and a second portion by the transmission area TA. It may have a portion GCbn. An n+1th compensation gate line GCn+1 among the plurality of compensation gate lines GC is a first portion GCan+1 and a second portion GCbn+1 that are physically spaced apart by the transmission area TA. ) can have

In an embodiment, among the plurality of initialization gate lines GI, initialization gate lines GI adjacent to the transmissive area TA in the row direction (eg, ±x direction) are physically formed by the transmissive area TA. It may have a first portion and a second portion spaced apart from each other. For example, as shown in FIG. 3 , an m-th initialization gate line GIm among the plurality of initialization gate lines GI is physically separated from a first portion GIam and a second portion by the transmission area TA. It may have a portion (GIbm). An m+1th initialization gate line GIm+1 among the plurality of initialization gate lines GI is a first portion GIam+1 and a second portion GIbm+1 that are physically spaced apart by the transmission area TA. ) can have

A plurality of gate connection lines GCL may be disposed on the non-display area NDA between the transparent area TA and the display area DA. The gate connection lines GCL may bypass the non-display area NDA along the edge of the opening 10H of the display device 10 formed in the transparent area TA, respectively.

The gate connection lines GCL may electrically connect first portions of the compensation gate lines GC and second portions of the compensation gate lines GC that are spaced apart from each other, respectively. Also, the gate connection lines GCL may electrically connect first portions of the initialization gate lines GI and second portions of the initialization gate lines GI that are spaced apart from each other.

For example, as shown in FIG. 3 , the first part GCan of the n-th compensation gate line GCn and the first part GCan+1 of the n+1-th compensation gate line GCn+1; The second portion GCbn of the n-th compensation gate line GCn and the second portion GCbn+1 of the n+1-th compensation gate line GCn+1 are the first of the plurality of gate connection lines GCL. They may be electrically connected to each other through the gate connection line GCL1 . In addition, the first portion GIam of the mth initialization gate line GIm, the first portion GIam+1 of the m+1th initialization gate line GIm+1, and the mth initialization gate line GIm The second portion GIbm and the second portion GIbm+1 of the m+1th initialization gate line GIm+1 are connected to each other through the second gate connection line GCL2 among the plurality of gate connection lines GCL. may be electrically connected.

As such, first and second portions of the compensation gate lines GC driven by the same gate driving circuit GDC among the plurality of compensation gate lines GC are connected to each other through one gate connection line GCL. may be electrically connected. First portions and second portions of the initialization gate lines GI driven by the same gate driving circuit GDC among the plurality of initialization gate lines GI are electrically connected to each other through one gate connection line GCL. can be connected In this case, since the number of gate connection lines GCL bypassing the transmission area TA is reduced, the non-display area NDA may be reduced. Accordingly, the display area DA may be relatively increased.

The first portions of the compensation gate lines GC and the second portions of the compensation gate lines GC spaced apart from each other by the transmission area TA are respectively connected through the gate connection lines GCL, and thus the compensation gate line GC ) may be transmitted to the second portion of the electrical signal. Since the first portions of the initialization gate lines GI and the second portions of the initialization gate lines GI spaced apart from each other by the transmission area TA are respectively connected through the gate connection lines GCL, the initialization gate line GI ) may be transmitted to the second portion of the electrical signal.

3 illustrates that the gate driving circuits GDC are disposed on one side of the peripheral area PA, as another embodiment, the gate driving circuits GDC may also be disposed on the other side of the peripheral area PA. That is, the gate driving circuits GDC may be disposed on one side of the peripheral area PA and/or the other side of the peripheral area PA. 9, which will be described later, illustrates a case in which the gate driving circuits GDC are respectively disposed on one side and the other side of the peripheral area PA.

The gate driving circuits GDC disposed at the other side of the peripheral area PA may be connected to second portions of the compensation gate lines GC and second portions of the initialization gate lines GI. The gate driving circuits GDC disposed on the other side of the peripheral area PA may drive the second portions of the compensation gate lines GC and the second portions of the initialization gate lines GI.

When the transmission area TA is formed on one side of the display area DA, the lengths of the first portions of the compensation gate lines GC may be different from the lengths of the second portions of the compensation gate lines GC. For example, when the transmission area TA is disposed on the upper left side of the display area DA, the length of the second portions of the compensation gate lines GC may be greater than the length of the first portions of the compensation gate lines GC. . A load difference of an electrical signal (eg, a scan signal) may occur due to the length difference, but the first portions of the compensation gate lines GC and the second portions of the compensation gate lines GC are connected to the gate connection line ( Since they are respectively connected to each other through GCL), the load difference can be canceled. Although the description has been made based on the compensation gate line GC, the initialization gate line GI may be equally applied.

4 is an enlarged plan view schematically illustrating a display device according to another exemplary embodiment. FIG. 4 is a modified embodiment of FIG. 3, and there is a difference in the structure of the gate connection line.

Referring to FIG. 4 , each of the gate driving circuits GDC may simultaneously drive a plurality of compensation gate lines GC and simultaneously drive a plurality of initialization gate lines GI. For example, the kth gate driving circuit GDCk of the plurality of gate driving circuits GDC may include an nth compensation gate line GCn and an n+1th compensation gate line GCn among the plurality of compensation gate lines GC. GCn+1) and an mth initialization gate line GIm and an m+1th initialization gate line GIm+1 among the plurality of initialization gate lines GI may be simultaneously driven. Here, k and n are natural numbers, and m is a natural number greater than n+1.

In an embodiment, the compensation gate lines GC and the initialization gate line GI are driven by the same gate driving circuit GDC among the plurality of compensation gate lines GC and the plurality of initialization gate lines GI. ) may be electrically connected to each other through one gate connection line GCL.

For example, as described above, the kth gate driving circuit GDCk includes the nth compensation gate line GCn, the n+1th compensation gate line GCn+1, the mth initialization gate line GIm, and the mth gate driving circuit GDCk. The m+1 initialization gate line GIm+1 may be simultaneously driven. In this case, the first portion GCan of the nth compensation gate line GCn, the first portion GCan+1 of the n+1th compensation gate line GCn+1, and the mth initialization gate line GIm The first portion GIam, the first portion GIam+1 of the m+1-th initialization gate line GIm+1, and the second portion GCbn of the n-th compensation gate line GCn, n+1 The second portion GCbn+1 of the compensation gate line GCn+1, the second portion GIbm of the mth initialization gate line GIm, and the second portion of the m+1th initialization gate line GIm+1 The portions GIbm+1 may be electrically connected to each other through the gate connection line GCL.

As such, the first and second portions of the compensation gate lines GC and initialization gate lines GI driven by the same gate driving circuit GDC are electrically connected to each other through one gate connection line GCL. When connected, the number of gate connection lines GCL bypassing the transmission area TA is reduced, so that the non-display area NDA may be reduced. Accordingly, the display area DA may be relatively increased. Also, a load difference due to a difference in length between the first and second portions of the compensation gate lines GC and the initialization gate lines GI may be reduced (or offset).

5 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.

Referring to FIG. 5 , a plurality of scan driving circuits SDC may be disposed in the peripheral area PA. The scan driving circuits SDC may be arranged along the column direction (eg, ±x direction) on the peripheral area PA as shown in FIG. 3 .

The scan driving circuits SDC may be connected to a plurality of scan lines GW respectively arranged in pixel rows. The scan driving circuits SDC may be respectively connected to the scan lines GW extending in the row direction (eg, the ±x direction). The scan driving circuits SDC may sequentially drive the scan lines GW.

The scan lines GW may be respectively connected to the pixels PX located in the same row. The scan lines GW may sequentially transmit electrical signals to the pixels PX located in the same row, respectively. For example, as shown in FIG. 5 , an n-th scan line GWn among the plurality of scan lines GW may be connected to the n-th pixels PXn positioned in the n-th row, and the n-th pixel ( Electrical signals may be sequentially transmitted to the PXn). Also, an n+1-th scan line GWn+1 among the plurality of scan lines GW may be connected to the n+1-th pixels PXn+1 positioned in an n+1-th row, and an n+th scan line GWn+1. An electrical signal may be sequentially transmitted to one pixel PXn+1. Here, n is a natural number.

In an embodiment, each of the scan lines GW adjacent to the transmissive area TA in the row direction (eg, ±x direction) among the plurality of scan lines GW is physically formed by the transmissive area TA. It may have a first portion and a second portion spaced apart from each other. For example, as shown in FIG. 5 , the n-th scan line GWn among the plurality of scan lines GW includes a first portion GWan and a second portion (GWan) that are physically spaced apart by the transmission area TA. GWbn). An n+1th scan line GWn+1 among the plurality of scan lines GW includes a first portion GWan+1 and a second portion GWbn+1 that are physically spaced apart by the transmission area TA. can have

A plurality of scan connection lines SCL may be disposed on the non-display area NDA between the transparent area TA and the display area DA. The scan connection lines SCL may each bypass the non-display area NDA along the edge of the opening 10H of the display device 10 formed in the transparent area TA.

The scan connection lines SCL may electrically connect first portions of the scan lines GW spaced apart from each other and second portions of the scan lines GW.

For example, as shown in FIG. 5 , the first part GWan of the n-th scan line GWn and the second part GWbn of the n-th scan line GWn are connected to a plurality of scan connection lines SCL. Among them, they may be electrically connected to each other through the first scan connection line SCL1 . In addition, the first part GWan+1 of the n+1th scan line GWn+1 and the second part GWbn+1 of the n+1th scan line GWn+1 include a plurality of scan connection lines ( Among the SCLs, they may be electrically connected to each other through a second scan connection line SCL2 .

The first portions of the scan lines GW and the second portions of the scan lines GW spaced apart from each other by the transmission area TA are respectively connected through the scan connection lines SCL. An electrical signal may be transmitted to the two parts.

5 illustrates that the scan driving circuits SDC are disposed on one side of the peripheral area PA, as another embodiment, the scan driving circuits SDC may also be disposed on the other side of the peripheral area PA. That is, the scan driving circuits SDC may be disposed on one side of the peripheral area PA and/or the other side of the peripheral area PA. 9, which will be described later, illustrates a case in which the scan driving circuits SDC are respectively disposed on one side and the other side of the peripheral area PA.

The scan driving circuits SDC disposed on the other side of the peripheral area PA may be connected to second portions of the scan lines GW. The scan driving circuits SDC disposed on the other side of the peripheral area PA may drive second portions of the scan lines GW.

When the transmission area TA is formed on one side of the display area DA, the lengths of the first portions of the scan lines GW and the lengths of the second portions of the scan lines GW may be different. For example, when the transmission area TA is disposed on the upper left side of the display area DA, the lengths of the second portions of the scan lines GW may be greater than the lengths of the first portions of the scan lines GW. A load difference of an electrical signal (eg, a scan signal) may occur due to the length difference, but the first portions of the scan lines GW and the second portions of the scan lines GW are connected to the scan connection line SCL. Since they are respectively connected to each other through the poles, the load difference can be reduced.

6 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment.

Referring to FIG. 6 , a plurality of emission control driving circuits EDC may be disposed in the peripheral area PA. The light emission control driving circuits EDC may be arranged along the column direction (eg, ±x direction) on the peripheral area PA as shown in FIG. 6 .

The emission control driving circuits EDC may be connected to a plurality of emission control lines EM respectively arranged in pixel rows. Each of the emission control driving circuits EDC may be connected to the emission control lines EM extending in a row direction (eg, a ±x direction).

The emission control driving circuits EDC may be respectively disposed on one side and the other side of the peripheral area PA. Among the plurality of light emission control driving circuits EDC, the light emission control driving circuits EDC disposed on one side of the peripheral area PA are referred to as a first light emission control driving circuit EDC1 and are disposed on the other side of the peripheral area PA. The disposed emission control driving circuits EDC may be referred to as a second emission control driving circuit EDC2 .

The emission control lines EM may be respectively connected to the pixels PX located in the same row. The emission control lines EM may sequentially transmit electrical signals to the pixels PX located in the same row, respectively. For example, as shown in FIG. 6 , an n-th emission control line EMn among the plurality of emission control lines EM may be connected to the n-th pixels PXn positioned in an n-th row, Electrical signals may be sequentially transmitted to the pixels PXn. In addition, an n+1th emission control line EMn+1 among the plurality of emission control lines EM may be connected to the n+1th pixels PXn+1 positioned in an n+1th row, Electrical signals may be sequentially transmitted to the n+1 pixels PXn+1. Here, n is a natural number.

In an embodiment, each of the emission control lines EM adjacent to the transmission area TA in the row direction (eg, ±x direction) among the plurality of emission control lines EM is in the transmission area TA. It may have a first portion and a second portion that are physically spaced apart by the For example, as shown in FIG. 6 , the n-th emission control line EMn among the plurality of emission control lines EM is a first portion EMan and a second portion physically spaced apart by the transmission area TA. It may have a portion EMbn. An n+1th emission control line EMn+1 among the plurality of emission control lines EM is a first portion EMan+1 and a second portion EMbn+1 that are physically spaced apart by the transmission area TA. ) can have

First portions of the emission control lines EM are driven by the first emission control driving circuits EDC1 disposed on one side of the peripheral area PA, and second portions of the emission control lines EM are disposed on the peripheral area PA. It may be driven by the second emission control driving circuits EDC2 disposed on the other side of the PA.

In an embodiment, each of the emission control driving circuits EDC may simultaneously drive the plurality of emission control lines EM. The emission control lines EM driven by the same emission control driving circuit EDC may be connected to each other in the peripheral area PA.

For example, as shown in FIG. 6 , the first emission control driving circuit EDC1 disposed on one side of the peripheral area PA among the plurality of emission control driving circuits EDC is the nth emission control line EMn. The first portion EMan of , and the first portion EMan+1 of the n+1th emission control line EMn+1 may be simultaneously driven. Among the plurality of light emission control driving circuits EDC, the second light emission control driving circuit EDC2 disposed on the other side of the peripheral area PA includes a second portion EMbn of the nth light emission control line EMn and an n+th light emission control driving circuit EDC2 . The second portion EMbn+1 of one emission control line EMn+1 may be simultaneously driven.

6 illustrates that each of the emission control driving circuits EDC drives the two emission control lines EM at the same time, but the number of emission control lines EM simultaneously driven by each of the emission control driving circuits EDC. can be variously changed.

7 is an enlarged plan view schematically illustrating a display device according to another exemplary embodiment. FIG. 7 is a modified embodiment of FIG. 6 , and there is a difference in the structure of the light emission control connection line.

Referring to FIG. 7 , a plurality of emission control connection lines ECL may be disposed on the non-display area NDA between the transparent area TA and the display area DA. The emission control connection lines ECL may each bypass the non-display area NDA along the edge of the opening 10H of the display device 10 formed in the transmission area TA.

The emission control connection lines ECL may electrically connect first portions of the emission control lines EM and second portions of the emission control lines EM that are spaced apart from each other.

For example, as shown in FIG. 7 , the first portion EMan of the nth emission control line EMn and the first portion EMan+1 of the n+1th emission control line EMn+1; The second portion EMbn of the nth emission control line EMn and the second portion EMbn+1 of the n+1th emission control line EMn+1 are electrically connected to each other through the emission control connection line ECL. can be connected

As such, the first and second portions of the emission control lines EM driven by the same emission control driving circuit EDC among the plurality of emission control lines EM connect one emission control connection line ECL. through which they can be electrically connected to each other.

Although FIG. 7 illustrates that the emission control driving circuits EDC are disposed on one side and the other side of the peripheral area PA, respectively, in another embodiment, the emission control driving circuits EDC may be disposed on one side or the other side of the peripheral area PA. It may be disposed on the other side. That is, one of the first emission control driving circuits EDC1 and the second emission control driving circuits EDC2 may be omitted.

8 is an equivalent circuit diagram schematically illustrating one pixel of a display device according to an exemplary embodiment.

Referring to FIG. 8 , one pixel PX may include a pixel circuit PC and a light emitting device electrically connected to the pixel circuit PC. For example, the light emitting device may be an organic light emitting diode (OLED).

As shown in FIG. 8 , the pixel circuit PC may include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The thin film transistors T1 to T7 and the storage capacitor Cst may be connected to the signal lines GW, GC, GI, GB, EM, and DL, the initialization voltage line VIL, and the driving voltage line PL. In some embodiments, at least one of the signal lines GW, GC, GI, GB, EM, and DL, the initialization voltage line VIL, and/or the driving voltage line PL are shared by neighboring pixels PXs. can be

The thin film transistor includes a driving thin film transistor T1, a scan thin film transistor T2, a compensation thin film transistor T3, a gate initialization thin film transistor T4, an operation control thin film transistor T5, a light emission control thin film transistor T6, and an anode initialization. A thin film transistor T7 may be included.

Some of the plurality of thin film transistors T1 to T7 may be provided as n-channel MOSFETs (NMOS), and others may be provided as p-channel MOSFETs (PMOS).

For example, as shown in FIG. 8 , the compensation thin film transistor T3 and the gate initialization thin film transistor T4 among the plurality of thin film transistors T1 to T7 are provided as n-channel MOSFETs (NMOSs), and the rest are It may be provided as a p-channel MOSFET (PMOS).

In another embodiment, of the plurality of thin film transistors T1 to T7 , the compensation thin film transistor T3 , the gate initialization thin film transistor T4 , and the anode initialization thin film transistor T7 are provided as an n-channel MOSFET (NMOS). and the remainder may be provided as a PMOS (p-channel MOSFET). Alternatively, only one of the plurality of thin film transistors T1 to T7 may be provided as an NMOS and the rest may be provided as a PMOS. Alternatively, all of the plurality of thin film transistors T1 to T7 may be formed of NMOS.

The signal line includes the scan line GW transmitting the scan signal Sgw, the compensation gate line GC transmitting the compensation signal Sgc, and the initialization gate transmitting the initialization signal Sgi to the gate initialization thin film transistor T4. Line GI, the emission control line EM for transferring the emission control signal Sem to the operation control thin film transistor T5 and the emission control thin film transistor T6, and the subsequent scan signal Sgb to the anode initialization thin film transistor T7 ), a next scan line GB, and a data line DL that crosses the scan line GW and transmits the data signal Dm.

The driving voltage line PL transfers the driving voltage ELVDD to the driving thin film transistor T1 , and the initialization voltage line VIL transfers the initialization voltage Vint for initializing the driving thin film transistor T1 and the anode.

The gate of the driving thin film transistor T1 is connected to the storage capacitor Cst, the source of the driving thin film transistor T1 is connected to the driving voltage line PL via the operation control thin film transistor T5, and the driving thin film transistor T1 The drain of T1 is electrically connected to the anode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the scan thin film transistor T2 and supplies the driving current I _OLED to the organic light emitting diode OLED.

The gate of the scan thin film transistor T2 is connected to the scan line GW, the source of the scan thin film transistor T2 is connected to the data line DL, and the drain of the scan thin film transistor T2 is connected to the driving thin film transistor T1 . ) while being connected to the driving voltage line PL via the operation control thin film transistor T5. The scan thin film transistor T2 is turned on according to the scan signal Sgw transmitted through the scan line GW and uses the data signal Dm transmitted to the data line DL as a source of the driving thin film transistor T1 . Performs a switching operation to transmit.

The gate of the compensation thin film transistor T3 is connected to the compensation gate line GC. The drain of the compensation thin film transistor T3 is connected to the drain of the driving thin film transistor T1 and connected to the anode of the organic light emitting diode OLED via the emission control thin film transistor T6. The source of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst and the gate of the driving thin film transistor T1 . Also, the source of the compensation thin film transistor T3 is connected to the drain of the gate initialization thin film transistor T4 . The compensation thin film transistor T3 is turned on according to the compensation signal Sgc received through the compensation gate line GC to electrically connect the gate and the drain of the driving thin film transistor T1 to connect the driving thin film transistor T1. Connect the diode.

The gate of the gate initialization thin film transistor T4 is connected to the initialization gate line GI. The source of the gate initialization thin film transistor T4 is connected to the source of the anode initialization thin film transistor T7 and the initialization voltage line VIL. The drain of the gate initialization thin film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the source of the compensation thin film transistor T3, and the gate of the driving thin film transistor T1. The gate initialization thin film transistor T4 is turned on according to the initialization signal Sgi received through the initialization gate line GI, and transmits the initialization voltage Vint to the gate of the driving thin film transistor T1 to transmit the driving thin film transistor ( An initialization operation for initializing the voltage of the gate of T1) is performed.

The gate of the operation control thin film transistor T5 is connected to the emission control line EM, the source of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the drain of the operation control thin film transistor T5 is driven The source of the thin film transistor T1 and the drain of the scan thin film transistor T2 are connected.

The gate of the emission control thin film transistor T6 is connected to the emission control line EM, and the source of the emission control thin film transistor T6 is connected to the drain of the driving thin film transistor T1 and the drain of the compensation thin film transistor T3, , the drain of the emission control thin film transistor T6 is electrically connected to the drain of the anode initialization thin film transistor T7 and the anode of the organic light emitting diode (OLED).

The operation control thin film transistor T5 and the light emission control thin film transistor T6 are simultaneously turned on according to the light emission control signal Sem received through the light emission control line EM, so that the driving voltage ELVDD is applied to the organic light emitting diode ( OLED) to allow the driving current I _OLED to flow through the organic light emitting diode (OLED).

The gate of the anode initialization thin film transistor T7 is then connected to the scan line GB, and the drain of the anode initialization thin film transistor T7 is connected to the drain of the emission control thin film transistor T6 and the anode of the organic light emitting diode OLED. and the source of the anode initialization thin film transistor T7 is connected to the source of the gate initialization thin film transistor T4 and the initialization voltage line VIL. After being transmitted through the scan line GB, the anode initialization thin film transistor T7 is turned on according to the scan signal Sgb to initialize the anode of the organic light emitting diode OLED.

Thereafter, the scan signal Sgb may be substantially synchronized with the scan signal Sgw. According to another example, the subsequent scan signal Sgb may be substantially synchronized with the scan signal Sgw of the next row. For example, the subsequent scan line GB may be substantially the same as the scan line GW of the next row. Pixels PXs adjacent to each other in the column direction may share the scan line GW.

The anode initialization thin film transistor T7 may then be connected to the scan line GB as shown in FIG. 8 . As another embodiment, the anode initialization thin film transistor T7 may be connected to the emission control line EM and driven according to the emission control signal Sem. Meanwhile, the positions of the source and drain of each of the thin film transistors may be changed according to the type (p-type or n-type) of the transistor.

The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 . The lower electrode CE1 of the storage capacitor Cst is connected to the gate of the driving thin film transistor T1 , and the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may store a charge corresponding to a difference between the gate voltage of the driving thin film transistor T1 and the driving voltage ELVDD.

Although not shown in FIG. 8 , the pixel circuit PC may include a boost capacitor including a first electrode and a second electrode. A first electrode of the boost capacitor may be connected to a gate and a scan line GW of the scan thin film transistor T2 , and a second electrode may be connected to a source of the compensation thin film transistor T3 .

A detailed operation of each pixel PX according to an exemplary embodiment is as follows.

During the initialization period, when the initialization signal Sgi is supplied through the initialization gate line GI, the gate initialization thin film transistor T4 is turned on in response to the initialization signal Sgi, and the initialization voltage line VIL ), the driving thin film transistor T1 is initialized by the initialization voltage Vint.

During the data programming period, when the scan signal Sgw and the compensation signal Sgc are supplied through the scan line GW and the compensation gate line GC, the scan thin film corresponds to the scan signal Sgw and the compensation signal Sgc. The transistor T2 and the compensation thin film transistor T3 are turned on. At this time, the driving thin film transistor T1 is diode-connected by the turned-on compensation thin film transistor T3 and is forward biased.

Then, in the data signal Dm supplied from the data line DL, the compensation voltage (Dm + Vth, Vth is a negative value) that is reduced by the threshold voltage Vth of the driving thin film transistor T1 is driven. It is applied to the gate of the thin film transistor T1.

A driving voltage ELVDD and a compensation voltage Dm + Vth are applied to both ends of the storage capacitor Cst, and a charge corresponding to a voltage difference between both ends is stored in the storage capacitor Cst.

During the light emission period, the operation control thin film transistor T5 and the light emission control thin film transistor T6 are turned on by the light emission control signal Sem supplied from the light emission control line EM. The driving current I _OLED is generated according to the voltage difference between the gate voltage of the driving thin film transistor T1 and the driving voltage ELVDD, and the driving current I _OLED is transmitted through the light emission control thin film transistor T6 to the organic light emitting diode ( OLED).

In the present embodiment, at least one of the plurality of thin film transistors T1 to T7 may include a semiconductor layer including an oxide, and the rest may include a semiconductor layer including silicon.

Specifically, the driving thin film transistor T1, which directly affects the brightness of the display device, is configured to include a semiconductor layer made of polycrystalline silicon having high reliability, thereby realizing a high-resolution display device.

On the other hand, since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. That is, since the color change of the image according to the voltage drop is not large even during low-frequency driving, low-frequency driving is possible.

As described above, since the oxide semiconductor has an advantage of a small leakage current, among the compensation thin film transistor T3 connected to the gate of the driving thin film transistor T1 , the gate initialization thin film transistor T4 , and the anode initialization thin film transistor T7 . By employing at least one of the oxide semiconductors, it is possible to prevent leakage current flowing to the gate of the driving thin film transistor T1, and at the same time to reduce power consumption.

9 is an enlarged plan view schematically illustrating a display device according to an exemplary embodiment. Specifically, FIG. 9 shows compensation gate lines and initialization gate lines of FIG. 3 , scan lines of FIG. 5 , and emission control lines of FIG. 6 .

Referring to FIG. 9 , a plurality of gate driving circuits GDC ( FIG. 3 ), a plurality of scan driving circuits SDC, and a plurality of light emission control driving circuits EDC may be disposed in the peripheral area PA. . The gate driving circuits GDC, the scan driving circuits SDC, and the light emission control driving circuit EDC are arranged in the column direction (eg, ±x direction) on the peripheral area PA as shown in FIG. 9 . can be arranged according to

Also, the gate driving circuits GDC, the scan driving circuits SDC, and the emission control driving circuit EDC may be respectively disposed on one side and the other side of the peripheral area PA. As described above with reference to FIGS. 3 to 5 and 7 , the gate driving circuits GDC, the scan driving circuits SDC, and the light emission control driving circuit EDC are provided on one side or the other side of the peripheral area PA, respectively. may be placed. That is, the gate driving circuits GDC, the scan driving circuits SDC, and the light emission control driving circuit EDC disposed on one side of the peripheral area PA are omitted or the gate disposed on one side of the peripheral area PA. The driving circuits GDC, the scan driving circuits SDC, and the light emission control driving circuit EDC may be omitted.

Among the plurality of pixels PX ( FIG. 3 ), the n-th pixels PXn disposed in the n-th pixel row are an n-th compensation gate line GCn ( FIG. 3 ), an n-th scan line GWn ( FIG. 5 ), and an n-th pixel row. It may be connected to the initialization gate line GIn and the n-th emission control line EMn ( FIG. 6 ). Among the plurality of pixels PX, the n+1th pixels PXn+1 disposed in the n+1th pixel row include the n+1th compensation gate line GCn+1 ( FIG. 3 ) and the n+1th scan line. (GWn+1, FIG. 5 ), the n+1th initialization gate line GIn+1, and the n+1th emission control line EMn+1 ( FIG. 6 ). Here, n is a natural number.

In an embodiment, although not shown in FIG. 9 , the n+1th scan line GWn+1 may be connected to the nth pixels PXn. The n-th pixels PXn and the n+1-th pixels PXn+1 may share the n+1-th scan line GWn+1. As described above in FIG. 8 , the anode initialization thin film transistor T7 included in each of the n-th pixels PXn may be turned on through the n+1-th scan line GWn+1 of the next row, and organic light emitting diodes are emitted. The anode of the diode (OLED) can be initialized.

Among the plurality of pixels PX, the m-th pixels PXm disposed in the m-th pixel row are an m-th compensation gate line GCm, an m-th scan line GWm, and an m-th initialization gate line GIm ( FIG. 3 ). , and the mth emission control line EMm. Among the plurality of pixels PX, the m+1th pixels PXm+1 disposed in the m+1th pixel row are the m+1th compensation gate line GCm+1 and the m+1th scan line GWm+. 1), the m+1th initialization gate line GIm+1 ( FIG. 3 ), and the m+1th emission control line EMm+1. Here, m is a natural number greater than n+1.

In an embodiment, although not shown in FIG. 9 , the m+1th scan line GWm+1 may be connected to the mth pixels PXm. The mth pixels PXm and the m+1th pixels PXm+1 may share the m+1th scan line GWm+1. As described above in FIG. 8 , the anode initialization thin film transistor T7 included in each of the m-th pixels PXm may be turned on through the m+1-th scan line GWm+1 in the next row, and organic light emitting diodes are emitted. The anode of the diode (OLED) can be initialized.

The nth compensation gate line GCn, the n+1th compensation gate line GCn+1, the mth initialization gate line GIm, and the m+1th initialization gate line GIm+1 are the kth gate driving circuits. (GDCk) can be connected. The nth compensation gate line GCn, the n+1th compensation gate line GCn+1, the mth initialization gate line GIm, and the m+1th initialization gate line GIm+1 are the kth gate driving circuits. (GDCk) can be driven simultaneously. Here, k is a natural number.

9 , the first portion GCan of the nth compensation gate line GCn, the first portion GCan+1 of the n+1th compensation gate line GCn+1, and the mth initialization gate The first portion GIam of the line GIm and the first portion GIam+1 of the m+1th initialization gate line GIm+1 are the k-th gate driving circuit disposed at one side of the peripheral area PA. (GDCk) and can be driven simultaneously. The second portion GCbn of the nth compensation gate line GCn, the second portion GCbn+1 of the n+1th compensation gate line GCn+1, and the second portion of the mth initialization gate line GIm (GIbm) and the second portion GIbm+1 of the m+1th initialization gate line GIm+1 are connected to the k-th gate driving circuit GDCk disposed on the other side of the peripheral area PA and simultaneously driven can be

In other words, the k-th gate driving circuit GDCk disposed at one side of the peripheral area PA may include the first portion GCan of the n-th compensation gate line GCn and the n+1-th compensation gate line GCn+1. in the first portion GCan+1, the first portion GIam of the mth initialization gate line GIm, and the first portion GIam+1 of the m+1th initialization gate line GIm+1 The k-th gate driving circuit GDCk configured to output the first gate signal and disposed on the other side of the peripheral area PA includes the second portion GCbn of the n-th compensation gate line GCn and the n+1-th compensation gate. The second portion GCbn+1 of the line GCn+1, the second portion GIbm of the mth initialization gate line GIm, and the second portion GIm+1 of the m+1th initialization gate line GIm+1 GIbm+1) may be configured to output the same second gate signal as the first gate signal.

The first portion GCan of the n-th compensation gate line GCn, the first portion GCan+1 of the n+1-th compensation gate line GCn+1, and the second portion of the n-th compensation gate line GCn The portion GCbn and the second portion GCbn+1 of the n+1th compensation gate line GCn+1 may be connected to each other through the first gate connection line GCL1 . The first portion GIam of the mth initialization gate line GIm, the first portion GIam+1 of the m+1th initialization gate line GIm+1, and the second portion GIm of the mth initialization gate line GIm The portion GIbm and the second portion GIbm+1 of the m+1th initialization gate line GIm+1 may be connected to each other through the second gate connection line GCL2 .

The nth scan line GWn, the n+1th scan line GWn+1, the mth scan line GWm, and the m+1th scan line GWm+1 are respectively connected to the scan driving circuits SDC. can be connected The scan driving circuits SDC sequentially connect the nth scan line GWn, the n+1th scan line GWn+1, the mth scan line GWm, and the m+1th scan line GWm+1. can drive

9 , a first portion GWan of an nth scan line GWn, a first portion GWan+1 of an n+1th scan line GWn+1, and an mth scan line GWm ) and the first part GWam+1 of the m+1th scan line GWm+1 are respectively connected to the scan driving circuits SDCs disposed at one side of the peripheral area PA. They may be connected and sequentially driven. The second portion GWbn of the nth scan line GWn, the second portion GWbn+1 of the n+1th scan line GWn+1, and the second portion GWbm of the mth scan line GWm , and the second portion GWbm+1 of the m+1th scan line GWm+1 may be sequentially driven by being connected to the scan driving circuits SDC disposed at one side of the peripheral area PA, respectively. .

The nth emission control line EMn, the n+1th emission control line EMn+1, the mth emission control line EMm, and the m+1th emission control line EMm+1 are the emission control driving circuits, respectively. (EDCs) can be connected. The nth emission control line EMn and the n+1th emission control line EMn+1 may be connected to the same emission control driving circuit EDC to be simultaneously driven. The mth emission control line EMm and the m+1th emission control line EMm+1 may be connected to the same emission control driving circuit EDC and driven simultaneously.

9 , the first portion EMan of the nth emission control line EMn, the first portion EMan+1 of the n+1th emission control line EMn+1, and the mth emission control The first portion EMam of the line EMm and the first portion EMam+1 of the m+1th emission control line EMm+1 are respectively disposed on one side of the peripheral area PA. (EDCs) can be connected. The second portion EMbn of the nth emission control line EMn, the second portion EMbn+1 of the n+1th emission control line EMn+1, and the second portion of the mth emission control line EMm (EMbm) and the second portion EMbm+1 of the m+1th emission control line EMm+1 may be respectively connected to the emission control driving circuits EDCs disposed on the other side of the peripheral area PA. . The first portion EMan of the nth emission control line EMn, the first portion EMan+1 of the n+1th emission control line EMn+1, and the first portion of the mth emission control line EMm (EMam), the first portion EMam+1 of the m+1th emission control line EMm+1, and the second portion EMbn of the nth emission control line EMn, the n+1th emission control line The second part EMbn+1 of the line EMn+1, the second part EMbm of the mth emission control line EMm, and the second part EMm+1 of the m+1th emission control line EMm+1 EMbm+1) may be spaced apart from each other by the transmission area TA.

The nth initialization gate line GIn and the n+1th initialization gate line GIn+1 may be connected to the pth gate driving circuit GDCp. In addition to the nth initialization gate line GIn and the n+1th initialization gate line GIn+1, as shown in FIG. 9 , the ith compensation gate line GCi and the i+th gate driving circuit GDCp include The first compensation gate line GCi+1 may also be connected. The n-th initialization gate line GIn, the n+1-th initialization gate line GIn+1, the i-th compensation gate line GCi, and the i+1-th compensation gate line GCi+1 are the p-th gate driving circuits. (GDCp) can be driven simultaneously. Here, p is a natural number less than k, and i is a natural number less than n-1.

9 , the first portion GIan of the nth initialization gate line GIn and the first portion GIan+1 of the n+1th initialization gate line GIn+1 are formed in the peripheral area PA ) may be simultaneously driven by being connected to the p-th gate driving circuit GDCp disposed on one side of the n-th initialization gate line GIn and the second portion GIbn of the n-th initialization gate line GIn and the n+1th initialization gate line GIn+1 ), the second portion GIbn+1 may be connected to the p-th gate driving circuit GDCp disposed on the other side of the peripheral area PA to be simultaneously driven.

The first portion GIan of the nth initialization gate line GIn, the first portion GIan+1 of the n+1th initialization gate line GIn+1, and the second portion GIan of the nth initialization gate line GIn The portion GIbn and the second portion GIbn+1 of the n+1th initialization gate line GIn+1 may be connected to each other through the third gate connection line GCL3.

The mth compensation gate line GCm and the m+1th compensation gate line GCm+1 may be connected to the qth gate driving circuit GDCq. In addition to the mth compensation gate line GCm and the m+1th compensation gate line GCm+1, as shown in FIG. 9 , the qth gate driving circuit GDCq includes the jth initialization gate line GIj and the jth + The first initialization gate line GIj+1 may also be connected. The mth compensation gate line GCm, the m+1th compensation gate line GCm+1, the jth initialization gate line GIj, and the j+1th initialization gate line GIj+1 are the qth gate driving circuits. (GDCq) can be driven simultaneously. Here, q is a natural number greater than k, and j is a natural number greater than m+1.

9 , the first portion GCam of the m-th compensation gate line GCm and the first portion GCam+1 of the m+1-th compensation gate line GCm+1 are in the peripheral area PA ) may be simultaneously driven by being connected to the q-th gate driving circuit GDCq disposed on one side of the ? ), the second portion GCbm+1 may be connected to the q-th gate driving circuit GDCq disposed on the other side of the peripheral area PA to be simultaneously driven.

In an embodiment, the i+1th pixel row may be a previous pixel row of the nth pixel row. That is, i may be n-2. At this time, the nth initialization gate line GIn, the n+1th initialization gate line GIn+1, the ith compensation gate line GCi, and the i+1th compensation gate line GCi+1 are k-th 1 can be driven simultaneously by a gate driving circuit. That is, p may be k-1.

In an embodiment, the m-th pixel row may be a pixel row following the n+1-th pixel row. That is, m may be n+2. Also, the j-th pixel row may be a pixel row following the m+1-th pixel row. That is, j may be m+2. In this case, the mth compensation gate line GCm, the m+1th compensation gate line GCm+1, the jth initialization gate line GIj, and the j+1th initialization gate line GIj+1 are k+ 1 can be driven simultaneously by a gate driving circuit. That is, q may be k+1.

As such, when the i+1th pixel row is the previous pixel row of the nth pixel row and the mth pixel row is the next pixel row of the n+1th pixel row, the driving timing of the pixels PXs will be described later with reference to FIG. 10 .

In an embodiment, an even number of pixel rows may be disposed between the i+1th pixel row and the nth pixel row. For example, two pixel rows may be disposed between the i+1th pixel row and the nth pixel row. That is, i may be n-4. At this time, the nth initialization gate line GIn, the n+1th initialization gate line GIn+1, the ith compensation gate line GCi, and the i+1th compensation gate line GCi+1 are k-th It can be driven simultaneously by two gate driving circuits. That is, p may be k-2.

In an embodiment, an even number of pixel rows may be disposed between the mth pixel row and the n+1th pixel row. For example, two pixel rows may be disposed between the mth pixel row and the n+1th pixel row. That is, m may be n+4. Also, an even number of pixel rows may be disposed between the j-th pixel row and the m+1-th pixel row. For example, two pixel rows may be disposed between the j-th pixel row and the m+1-th pixel row. That is, j may be m+4. In this case, the mth compensation gate line GCm, the m+1th compensation gate line GCm+1, the jth initialization gate line GIj, and the j+1th initialization gate line GIj+1 are k+ It can be driven simultaneously by two gate driving circuits. That is, q may be k+2.

As such, when an even number of pixel rows are disposed between the i+1th pixel row and the nth pixel row, and an even number of pixel rows are disposed between the mth pixel row and the n+1th pixel row, The driving timing will be described later with reference to FIG. 11 .

In one embodiment, m+1 may be equal to 2k. One gate driving circuit GDC may drive a total of two initialization gate lines GI. As shown in FIGS. 10 and 11 , which will be described later, the on-period of the initialization gate line GI may be earlier than the on-period of the compensation gate line GC. The on-period of the initialization gate line GI may be started earlier than the on-period of the compensation gate line GC. Therefore, if you look at the order in which the gate driving circuits GDC are listed based on the initialization gate line GI, since two initialization gate lines GI are connected per one gate driving circuit GDC, m+1 is 2k and can be the same.

10 and 11 are timing diagrams for explaining a method of driving a plurality of pixels according to an embodiment of the present invention. Specifically, FIG. 10 is a timing diagram when the i+1th pixel row is the previous pixel row of the nth pixel row in FIG. 9, and the mth pixel row is the next pixel row of the n+1th pixel row in FIG. 9 is a timing diagram illustrating a case in which an even number of pixel rows are disposed between an i+1th pixel row and an nth pixel row and an even number of pixel rows are disposed between the mth pixel row and an n+1th pixel row.

10 and 11 , during the off-period (or data programming period) of the light emission control signal transmitted to the nth and n+1th light emission control lines EMn and EMn+1, respectively, the nth and nth The initialization signal transmitted to the n+1 initialization gate lines GIn and GIn+1, respectively, the compensation signal transmitted to the n-th and n+1-th compensation gate lines GCn and GCn+1, respectively, and the n-th and n+th compensation gate lines GCn and GCn+1, respectively On-periods of each scan signal transmitted to one scan line GWn and GWn+1 may proceed.

The on-period of the initialization signal transmitted to the n-th and n+1-th initialization gate lines GIn and GIn+1, respectively, corresponds to the case where the initialization signal is at a high level, and the n-th and n+1-th compensation gate lines The on-period of the compensation signal transmitted to (GCn, GCn+1) corresponds to a case in which the compensation signal is at a high level, and is transmitted to the nth and n+1th scan lines GWn and GWn+1, respectively. The on-period of the scan signal may correspond to a case in which the scan signal is at a low level. As described above in FIG. 8 , the initialization signal may be applied to the gate initialization thin film transistor T4 , the compensation signal may be applied to the compensation thin film transistor T3 , and the scan signal may be applied to the scan thin film transistor T2 . In this case, it may be assumed that the compensation thin film transistor T3 and the gate initialization thin film transistor T4 are NMOS, and the scan thin film transistor T2 is a PMOS. Accordingly, the on-period of the initialization signal corresponds to a case in which the initialization signal is at a high level, an on-period of the compensation signal corresponds to a case in which the compensation signal is at a high level, and the on-period of the scan signal corresponds to a case in which the compensation signal is at a high level. It may correspond to a case in which the scan signal is at a low level.

In an embodiment, the high level of the initialization signal transmitted to the nth and n+1th initialization gate lines GIn and GIn+1, respectively, and the nth and n+1th compensation gate lines GCn and GCn+1 The high levels of the compensation signals respectively transmitted to the ? may be sequentially formed.

For example, when the i+1th pixel row is the previous pixel row of the nth pixel row and the mth pixel row is the next pixel row of the n+1th pixel row, as shown in FIG. 10 , the high level of the initialization signal and the high level of the compensation signal may be continuously formed. That is, after the on-period of the initialization signal has passed, the on-period of the compensation signal may proceed (or start) immediately. In other words, a falling edge of the initialization signal may correspond to a rising edge of the compensation signal.

As another example, when an even number of pixel rows are disposed between the i+1th pixel row and the nth pixel row, and an even number of pixel rows are disposed between the mth pixel row and the n+1th pixel row, as shown in FIG. 11 . As described above, an off-period may be formed between the high level of the initialization signal and the high level of the compensation signal. That is, after the on-period of the initialization signal passes and the off-period of at least one or more of the initialization signals pass, the on-period of the compensation signal may start. In other words, the falling edge of the initialization signal may not correspond to the rising edge of the compensation signal.

While the compensation signal transmitted to the nth and n+1th compensation gate lines GCn and GCn+1 respectively is in the on-period, the signal transmitted to the nth scan line GWn and the n+1th scan line GWn Signals transferred to +1) may each be on-period.

In one embodiment, as shown in FIGS. 10 and 11 , the on-section length t1 of the compensation signal is twice the on-section length t2 of the signal transmitted to the n-th scan line GWn; may be equal to or greater than this. The on-section length t1 of the compensation signal may be equal to or greater than twice the on-section length t3 of the signal transmitted to the n+1th scan line GWn+1. The on-interval length t1 of the compensation signal is the on-interval length t2 of the signal transmitted to the nth scan line GWn and the on-interval length t2 of the signal transmitted to the n+1th scan line GWn+1. It may be equal to or greater than the sum of the section lengths t3.

So far, the nth and n+1th emission control lines EMn and EMn+1, the nth and n+1th initialization gate lines GIn, GIn+1, and the nth and n+1th compensation gate lines GCn , GCn+1), and the nth and n+1th scan lines GWn and GWn+1 have been described as the basis, but the mth and m+1th emission control lines EMm, EMm+1, the mth and The m+1th initialization gate lines GIm, GIm+1, the mth and m+1th compensation gate lines GCm, GCm+1, and the mth and m+1th scan lines GWm, GWm+1 can be applied in the same way.

However, the off-period of the emission control signal transmitted to the mth and m+1th emission control lines EMm and EMm+1, respectively, is applied to the nth and n+1th emission control lines EMn and EMn+1, respectively. The off-period of the transmitted light emission control signal may proceed after the progress. The on-period of the initialization signal transmitted to the m-th and m+1-th initialization gate lines GIm and GIm+1, respectively, is the initialization signal transmitted to the n-th and n+1th initialization gate lines GIn and GIn+1, respectively. It may proceed after the on-period of the signal has progressed. The on-period of the compensation signal transmitted to the m-th and m+1-th compensation gate lines GCm and GCm+1, respectively, is transmitted to the n-th and n+1-th compensation gate lines GCn and GCn+1, respectively. It may proceed after the on-period of the signal has progressed. The on-period of the scan signal transmitted to the mth and m+1th scan lines GWm and GWm+1, respectively, corresponds to the on-period of the scan signal transmitted to the nth and n+1th scan lines GWn and GWn+1, respectively. It may proceed after the on-section has been performed.

In one embodiment, as shown in FIGS. 10 and 11 , the on-period of the compensation signal of the nth and n+1th compensation gate lines GCn and GCn+1 and the mth and m+1th initialization gates On-periods of the initialization signals of the lines GIm and GIm+1 may be substantially the same. As described above in FIG. 9 , the nth and n+1th compensation gate lines GCn and GCn+1 and the mth and m+1th initialization gate lines GIm and GIm+1 are connected to the kth gate driving circuit ( GDCk), so that the on-periods of the respective signals may be substantially the same.

12 and 13 are exemplary cross-sectional views taken along II-II′ of the display device of FIG. 9 . Specifically, FIGS. 12 and 13 exemplarily show cross-sections of a portion of a display area and a portion of a non-display area.

12 and 13 , the first scan connection line SCL1 may include a first scan connection electrode SCL1a and a second scan connection electrode SCL1b. The first scan connection electrode SCL1a electrically connects the first part GWan ( FIG. 9 ) of the n-th scan line GWn ( FIG. 9 ) and the second part GWbn ( FIG. 9 ) of the n-th scan line GW to each other. , and the second scan connection electrode SCL1b may electrically connect the first portion GWan of the n-th scan line GWn and the second portion GWbn of the n-th scan line GWn to each other. The first scan connection electrode SCL1a and the second scan connection electrode SCL1b may overlap each other as shown in FIGS. 12 and 13 .

Although the description is based on the first scan connection line SCL1 , the second scan connection line SCL2 , the third scan connection line SCL3 ( FIG. 9 ), and the fourth scan connection line SCL4 may be equally applied. . Taking the second scan connection line SCL2 as an example, the second scan connection line SCL2 may include a third scan connection electrode SCL2a and a fourth scan connection electrode SCL2b. The third scan connection electrode SCL2a includes a first portion GWan+1 ( FIG. 9 ) of the n+1-th scan line GWn+1 ( FIG. 9 ) and a second portion of the n+1-th scan line GWn+1 ( GWn+1 ). The portions GWbn+1 ( FIG. 9 ) are electrically connected to each other, and the fourth scan connection electrode SCL2b is connected to the first portion GWan+1 and the n+1-th scan line GWn+1 of the n+1-th scan line GWn+1. The second portion GWbn+1 of the scan line GWn+1 may be electrically connected to each other. The third scan connection electrode SCL2a and the fourth scan connection electrode SCL2b may overlap each other as shown in FIGS. 12 and 13 .

Hereinafter, components included in the display device according to the stacked structure will be described in more detail with reference to FIGS. 12 and 13 , and the first gate connection line GCL1 , the first scan connection line SCL1 , and the third gate connection line A positional relationship between the GCL3 and the second scan connection line SCL2 will be described.

The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. When the substrate 100 has flexible or bendable characteristics, the substrate 100 may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, or polyethylene. Polymer resins such as polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate may include

The substrate 100 may have a single-layer or multi-layer structure of the above material, and may further include an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111 . The barrier layer may serve to prevent or minimize penetration of impurities from the substrate 100 or the like into the first semiconductor layer Act1 and the second semiconductor layer Act2 . The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic/inorganic composite, and may have a single-layer or multi-layer structure of an inorganic material and an organic material.

A channel lower electrode (not shown) may be interposed between the barrier layer and the buffer layer 111 . The channel lower electrode may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may be formed as a multi-layer or a single layer including the above material. For example, the channel lower electrode may have a multilayer structure of Ti/Al/Ti.

The channel lower electrode CBE may overlap the channel region C1 of the first semiconductor layer Act1 . The channel lower electrode may be configured to be connected to the driving voltage line PL described above in FIG. 8 to apply the driving voltage ELVDD. When a pixel circuit including an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS) is driven through the channel lower electrode to which the driving voltage ELVDD is applied, unnecessary charges are accumulated in the first semiconductor layer Act1. it can be prevented As a result, characteristics of the first thin film transistor TFT1 including the first semiconductor layer Act1 may be stably maintained.

A first semiconductor layer Act1 may be disposed on the buffer layer 111 . The first semiconductor layer Act1 may include amorphous silicon or polysilicon. The first semiconductor layer Act1 may include a channel region C1 and a source region S1 and a drain region D1 disposed on both sides of the channel region C1 . The first semiconductor layer Act1 may be formed of a single layer or multiple layers.

A first gate insulating layer 113 and a second gate insulating layer 115 may be stacked on the substrate 100 to cover the first semiconductor layer Act1 . The first gate insulating layer 113 and the second gate insulating layer 115 are silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

A first conductive layer CL1 may be disposed on the first gate insulating layer 113 . The first conductive layer CL1 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and is formed as a multi-layer or single layer including the above material. can be For example, the first conductive layer CL1 may have a multilayer structure of Ti/Al/Ti.

The first conductive layer CL1 includes a first gate electrode G1 that at least partially overlaps with the first semiconductor layer Act1, a lower electrode CE1 of the storage capacitor Cst, a first scan connection electrode SCL1a, and A third scan connection electrode SCL2a may be included. The first gate electrode G1 may overlap the channel region C1 of the first semiconductor layer Act1 . The first gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst are disposed in the display area DA, and the first scan connection electrode SCL1a and the third scan connection electrode SCL2a are in the non-display area (NDA) may be deployed.

A second conductive layer CL2 may be disposed on the second gate insulating layer 115 . The second conductive layer CL2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and is formed as a multilayer or single layer including the above material. can be For example, the second conductive layer CL2 may have a multilayer structure of Ti/Al/Ti.

The second conductive layer CL2 includes a lower gate electrode G2a of the second gate electrode G2 , an upper electrode CE2 of the storage capacitor Cst, a first gate connection line GCL1 , and a second gate connection line (GCL2). The lower gate electrode G2a of the second gate electrode G2 and the upper electrode CE2 of the storage capacitor Cst are disposed in the display area DA, and the first gate connection line GCL1 and the second gate connection line GCL2 may be disposed in the non-display area NDA. The upper electrode CE2 of the storage capacitor Cst may at least partially overlap the first gate electrode G1 .

The lower gate electrode G2a of the second gate electrode G2 may be disposed to overlap the second semiconductor layer Act2 including the oxide semiconductor material. Since the second semiconductor layer Act2 including the oxide semiconductor material has a weak property to light, the lower gate electrode G2a is photosensitive to the second semiconductor layer Act2 by external light incident from the substrate 100 side. It is possible to prevent a change in device characteristics of the second thin film transistor TFT2 including the oxide semiconductor material by induced current.

12 shows the first scan connection electrode SCL1a and the third scan connection electrode SCL2a are disposed on the same layer as the first gate electrode G1, and the first gate connection line GCL1 and the third gate connection line (GCL1) Although GCL3 is illustrated to be disposed on the same layer as the upper electrode CE2 , this is only an example and various modifications are possible.

For example, as shown in FIG. 13 , the first gate connection line GCL1 and the third gate connection line GCL3 are disposed on the same layer as the first gate electrode G1 , and the first scan connection electrode SCL1a ) and the third scan connection electrode SCL2a may be disposed on the same layer as the upper electrode CE2 . That is, the first conductive layer CL1 includes the first gate connection line GCL1 and the third gate connection line GCL3 , and the second conductive layer CL2 includes the first scan connection electrode SCL1a and the third gate connection line GCL3 . A scan connection electrode SCL2a may be included.

In an embodiment, the storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 , and may overlap the first thin film transistor TFT1 as shown in FIGS. 12 and 13 . For example, the first gate electrode G1 of the first thin film transistor TFT1 may function as the lower electrode CE1 of the storage capacitor Cst. Unlike this, the storage capacitor Cst does not overlap the first thin film transistor TFT1 and may exist separately.

The upper electrode CE2 of the storage capacitor Cst overlaps the lower electrode CE1 with the second gate insulating layer 115 interposed therebetween, and forms a capacitance. In this case, the second gate insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

A first interlayer insulating layer 117 may be provided on the second gate insulating layer 115 to cover the upper electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer 117 is silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

A second semiconductor layer Act2 may be disposed on the first interlayer insulating layer 117 . The second semiconductor layer Act2 may include an oxide semiconductor material. The second semiconductor layer Act2 may include, for example, indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), or germanium (Ge). , chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and may include an oxide of at least one material selected from the group including zinc (Zn).

For example, the second semiconductor layer Act2 may be an InSnZnO (ITZO) semiconductor layer, an InGaZnO (IGZO) semiconductor layer, or the like. Since the oxide semiconductor has a wide band gap (about 3.1 eV), high carrier mobility, and low leakage current, the voltage drop is not large even if the driving time is long. The advantage is that there is not much change.

The second semiconductor layer Act2 may include a channel region C2 and a source region S2 and a drain region D2 disposed on both sides of the channel region C2 .

A third gate insulating layer 119 may be disposed on the second semiconductor layer Act2 . The third gate insulating layer 119 is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

12 and 13 illustrate that the third gate insulating layer 119 is disposed over the entire surface of the substrate 100 so as to cover the second semiconductor layer Act2, as another embodiment, the third gate insulating layer 119 The layer 119 may be patterned to overlap a portion of the second semiconductor layer Act2 . For example, the third gate insulating layer 119 may be patterned to overlap the channel region C2 of the second semiconductor layer Act2 .

A third conductive layer CL3 may be disposed on the third gate insulating layer 119 . The third conductive layer CL3 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and is formed as a multi-layer or single layer including the above material. can be For example, the third conductive layer CL3 may have a multilayer structure of Ti/Al/Ti.

The third conductive layer CL3 includes an upper gate electrode G2b, a second scan connection electrode SCL1b, and a fourth scan connection electrode SCL2b of the second gate electrode that at least partially overlap the second semiconductor layer Act2 may include The upper gate electrode G2b of the second gate electrode may overlap the channel region C2 of the second semiconductor layer Act2.

In an embodiment, the second gate electrode G2 may include a lower gate electrode G2a and an upper gate electrode G2b. The second gate electrode G2 may be a multi-line. 12 and 13 illustrate that the second gate electrode G2 is a multi-wire, but in another embodiment, the second gate electrode G2 may be a single wire. For example, one of the lower gate electrode G2a and the upper gate electrode G2b may be omitted.

In an embodiment, the first scan connection line SCL1 includes a first scan connection electrode SCL1a and a second scan connection electrode SCL1b, and the second scan connection line SCL2 includes a third scan connection electrode (SCL2a) and a fourth scan connection electrode (SCL2b) may be included. Each of the first scan connection line SCL1 and the second scan connection line SCL2 may be a multi-wire. Load reduction may be possible by configuring the first scan connection line SCL1 and the second scan connection line SCL2 as multiple wirings, respectively.

12 and 13 show that the first scan connection line SCL1 and the second scan connection line SCL2 are multiple wirings, and the first gate connection line GCL1 and the third gate connection line GCL3 are single wirings. Although illustrated, as another embodiment, the first scan connection line SCL1 and the second scan connection line SCL2 are a single wiring, and the first gate connection line GCL1 and the third gate connection line GCL3 are multi-layered. It may be wiring. As another embodiment, the first scan connection line SCL1 , the second scan connection line SCL2 , the first gate connection line GCL1 , and the third gate connection line GCL3 may be a multi-wire or a single wire. .

In an embodiment, as shown in FIGS. 12 and 13 , the first gate connection line GCL1 and the first scan connection line SCL1 adjacent to each other may be disposed on different layers. In this case, the separation distance between the first gate connection line GCL1 and the first scan connection line SCL1 in a direction perpendicular to the z-axis (eg, the horizontal direction of the substrate) is the first gate connection line GCL1 and the first It may be smaller than when the scan connection lines SCL1 are disposed on the same layer. Accordingly, an area occupied by the first gate connection line GCL1 and the first scan connection line SCL1 may be reduced. An area of the non-display area NDA in which the first gate connection line GCL1 and the first scan connection line SCL1 are disposed may be reduced. Although the description has been made based on the first gate connection line GCL1 and the first scan connection line SCL1 , the same may be applied to the third gate connection line GCL3 and the second scan connection line SCL2 .

In an embodiment, the first thin film transistor TFT1 may correspond to the driving thin film transistor T1 described above with reference to FIG. 8 . Except that the first thin film transistor TFT1 overlaps the upper electrode CE2 , the first thin film transistor TFT1 is a scan thin film transistor T2 , an operation control thin film transistor T5 , and a light emission control thin film transistor T6 . , or may correspond to the anode initialization thin film transistor T7. In other words, the first semiconductor layer Act1 includes the active region of the driving thin film transistor T1 , the active region of the scan thin film transistor T2 , the active region of the operation control thin film transistor T5 , and the light emission control thin film transistor T6 . It may include an active region or an active region of the anode initialization thin film transistor T7.

In an embodiment, the second thin film transistor TFT2 may correspond to the compensation thin film transistor T3 or the gate initialization thin film transistor T4 described above with reference to FIG. 8 . In other words, the second semiconductor layer Act2 may include an active region of the compensation thin film transistor T3 or an active region of the gate initialization thin film transistor T4 .

A second interlayer insulating layer 121 may be provided on the third gate insulating layer 119 to cover the third conductive layer CL3 . The second interlayer insulating layer 121 is silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

A first connection electrode layer CM1 may be disposed on the second interlayer insulating layer 121 . The first connection electrode layer CM1 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and is formed as a multilayer or single layer including the above material. can be For example, the first connection electrode layer CM1 may have a multilayer structure of Ti/Al/Ti.

The first connection electrode layer CM1 may be connected to at least one of the source region S1 and the drain region D1 of the first semiconductor layer Act1 . The first connection electrode layer CM1 may be connected to at least one of the source region S2 and the drain region D2 of the second semiconductor layer Act2 .

The first connection electrode layer CM1 may be covered with an inorganic protective layer (not shown). The inorganic protective layer may be a single film or a multilayer film of silicon nitride (SiN _X ) and silicon oxide (SiO _X ). The inorganic protective layer may be introduced to cover and protect some wirings disposed on the second interlayer insulating layer 121 .

A planarization layer 123 may be disposed on the second interlayer insulating layer 121 , and a light emitting device 200 may be disposed on the planarization layer 123 .

The planarization layer 123 may be formed as a single layer or a multilayer film made of an organic material, and provides a flat top surface. The planarization layer 120 is a general general-purpose polymer such as Benzocyclobutene (BCB), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer , imide-based polymers, arylether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

The planarization layer 123 may be provided in multiple layers to include a first planarization layer 123a and a second planarization layer 123b. In this case, the second connection electrode layer CM2 may be interposed between the first planarization layer 123a and the second planarization layer 123b. The second connection electrode layer CM2 may be connected to the first connection electrode layer CM1 through a contact hole formed in the first planarization layer 123a, and electrically connect the light emitting device 200 and the first thin film transistor TFT1 to each other. can

The light emitting device 200 may be disposed on the planarization layer 123 . The light emitting device 200 may include a pixel electrode 210 , an intermediate layer 220 including an organic emission layer, and a counter electrode 230 .

The pixel electrode 210 may be a (semi)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, and a transparent or translucent electrode layer formed on the reflective layer. can do. The transparent or translucent electrode layer includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ; indium oxide), and indium gallium. At least one selected from the group consisting of indium gallium oxide (IGO) or aluminum zinc oxide (AZO) may be included. In some embodiments, the pixel electrode 210 may be formed of ITO/Ag/ITO.

A pixel defining layer 125 may be disposed on the planarization layer 123 . In addition, the pixel defining layer 125 increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 to prevent arcs from occurring at the edge of the pixel electrode 210 . may play a role in preventing

The pixel defining layer 125 is made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by spin coating or the like.

The intermediate layer 220 may be disposed in the opening formed by the pixel defining layer 125 . The intermediate layer 220 may include an organic light emitting layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic light emitting layer may be a low molecular weight organic material or a high molecular weight organic material, and below and above the organic light emitting layer, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), Alternatively, a functional layer such as an electron injection layer (EIL) may be optionally further disposed.

The intermediate layer 220 may be disposed to correspond to each of the plurality of pixel electrodes 210 . However, the present invention is not limited thereto. Various modifications are possible for the intermediate layer 220 to include an integral layer over the plurality of pixel electrodes 210 .

The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and is formed of a metal thin film having a small work function including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. can be formed. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In ₂ O ₃ may be further disposed on the metal thin film. The opposite electrode 230 may be disposed over the display area DA and may be disposed on the intermediate layer 220 and the pixel defining layer 125 . The counter electrode 230 may be integrally formed in the plurality of light emitting devices 200 to correspond to the plurality of pixel electrodes 210 .

The light emitting device 200 may be covered with an encapsulation layer (not shown). The encapsulation layer may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.

The inorganic encapsulation layer may include at least one inorganic material selected from among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer and the second inorganic encapsulation layer may be a single layer or a multilayer including the above-described material. The organic encapsulation layer may include a polymer-based material. The polymer-based material may include polymethyl methacrylate, an acrylic resin such as polyacrylic acid, an epoxy resin, polyimide, polyethylene, and the like. In an embodiment, the organic encapsulation layer may include an acrylate polymer.

So far, the first gate connection line GCL1, the first scan connection line SCL1, the third gate connection line GCL3, and the second scan connection line SCL2 have been described as the reference, but the second gate connection line ( GCL2 ( FIG. 9 ), the third scan connection line SCL3 ( FIG. 9 ), the fourth gate connection line GCL4 ( FIG. 9 ), and the fourth scan connection line SCL4 may be equally applied.

So far, only the display device has been mainly described, but the present invention is not limited thereto. For example, a method of manufacturing a display device for manufacturing such a display device will also fall within the scope of the present invention.

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1: electronic device
10: display device
100: substrate
TA: transmission area
DA: display area
NDA: non-display area
PA: surrounding area
PX: Pixel
GI: initialization gate line
GC: compensation gate line
GW: scan line
EM: luminescence control line
GDC: gate drive circuit
SDC: Scan Driving Circuit
EDC: light emission control driving circuit
GCL: gate connection line
SCL: scan connection line
ECL: light emission control connection line

Claims (26)

a substrate having a transmissive region, a display region surrounding at least a portion of the transmissive region, a non-display region between the transmissive region and the display region, and a peripheral region outside the display region;
a plurality of pixels arranged along pixel rows and pixel columns on the display area;
a plurality of initialization gate lines and a plurality of compensation gate lines respectively arranged in the pixel rows;
a plurality of gate driving circuits arranged in a column direction on the peripheral region; and
a plurality of gate connection lines disposed on the non-display area;
A kth gate driving circuit among the plurality of gate driving circuits may include mth and m+1th initialization gate lines among the plurality of initialization gate lines, and nth and n+1th among the plurality of compensation gate lines. driving the compensation gate lines at the same time,
Each of the mth and m+1th initialization gate lines and the nth and n+1th compensation gate lines have a first portion and a second portion that are physically spaced apart by the transmissive region;
The first portions of the nth and n+1th compensation gate lines and the second portions of the nth and n+1th compensation gate lines are connected through a first gate connection line of the plurality of gate connection lines A display device, characterized in that they are electrically connected to each other (k and n are natural numbers, and m is a natural number greater than n+1). According to claim 1,
A display device in which an even number of pixel rows is disposed between an n+1th pixel row and an mth pixel row. 3. The method of claim 2,
The first portions of the mth and m+1th initialization gate lines and the second portions of the mth and m+1th initialization gate lines are connected to each other through a second gate connection line among the plurality of gate connection lines. A display device, characterized in that electrically connected to each other. 3. The method of claim 2,
The first gate connection line electrically connects the first portions of the mth and m+1th initialization gate lines and the second portions of the mth and m+1th initialization gate lines to each other. display device. According to claim 1,
Two pixel rows are disposed between the n+1th pixel row and the mth pixel row,
nth and n+1th initialization gate lines of the plurality of initialization gate lines are simultaneously driven by a k-2th gate driving circuit of the plurality of gate driving circuits;
The display device of claim 1, wherein mth and m+1th compensation gate lines of the plurality of compensation gate lines are simultaneously driven by a k+2th gate driving circuit of the plurality of gate driving circuits. According to claim 1,
The m-th pixel row is a pixel row following the n+1-th pixel row. 7. The method of claim 6,
The first gate connection line electrically connects the first portions of the mth and m+1th initialization gate lines and the second portions of the mth and m+1th initialization gate lines to each other. display device. 7. The method of claim 6,
The first portions of the mth and m+1th initialization gate lines and the second portions of the mth and m+1th initialization gate lines are connected to each other through a second gate connection line among the plurality of gate connection lines. A display device, characterized in that electrically connected to each other. According to claim 1,
nth and n+1th initialization gate lines of the plurality of initialization gate lines are simultaneously driven by a k−1th gate driving circuit of the plurality of gate driving circuits;
The display device of claim 1, wherein mth and m+1th compensation gate lines of the plurality of compensation gate lines are simultaneously driven by a k+1th gate driving circuit of the plurality of gate driving circuits. According to claim 1,
and m+1 is equal to 2k. According to claim 1,
The k-th gate driving circuit comprises:
One side gate disposed at one side of the peripheral region and configured to output a first gate signal to first portions of the mth and m+1th initialization gate lines and the nth and n+1th compensation gate lines drive circuit; and
A second gate signal that is disposed on the other side of the peripheral region and is identical to the first gate signal in second portions of the m-th and m+1-th initialization gate lines and the n-th and n+1-th compensation gate lines and a second gate driving circuit configured to output According to claim 1,
a plurality of scan lines respectively arranged in the pixel rows;
a plurality of scan driving circuits arranged in a column direction on the peripheral area and sequentially driving the plurality of scan lines; and
Further comprising a plurality of scan connection lines disposed on the non-display area,
Each of the nth and n+1th scan lines among the plurality of scan lines has a first portion and a second portion physically spaced apart by the transmissive region,
The first portion of the n-th scan line and the second portion of the n-th scan line are electrically connected to each other through a first scan connection line among the plurality of scan connection lines,
The first portion of the n+1th scan line and the second portion of the n+1th scan line are electrically connected to each other through a second scan connection line among the plurality of scan connection lines display device. 13. The method of claim 12,
The first scan connection line is
a first scan connection electrode electrically connecting the first portion of the n-th scan line and the second portion of the n-th scan line to each other; and
and a second scan connection electrode electrically connecting the first portion of the nth scan line and the second portion of the nth scan line to each other. 14. The method of claim 13,
a first conductive layer including the first scan connection electrode;
a semiconductor layer on the first conductive layer; and
and a second conductive layer disposed on the semiconductor layer and including the second scan connection electrode. According to claim 1,
a plurality of light emission control lines respectively arranged in the pixel rows; and
Further comprising a plurality of light emission control driving circuits arranged in a column direction on the peripheral region,
Each of the nth and n+1th emission control lines among the plurality of emission control lines has a first portion and a second portion that are physically spaced apart by the transmissive region and are electrically insulated,
the first portions of the nth and n+1th emission control lines are simultaneously driven by a first emission control driving circuit disposed at one side of the peripheral region among the plurality of emission control driving circuits;
and the second portions of the nth and n+1th emission control lines are simultaneously driven by a second emission control driving circuit disposed on the other side of the peripheral region among the plurality of emission control driving circuits. Device. According to claim 1,
a plurality of light emission control lines respectively arranged in the pixel rows;
a plurality of light emission control driving circuits arranged along a column direction on the peripheral area; and
Further comprising a light emission control connection line disposed on the non-display area,
Each of the nth and n+1th emission control lines among the plurality of emission control lines has a first portion and a second portion that are physically spaced apart by the transmissive region;
The first portions of the nth and n+1th emission control lines and the second portions of the nth and n+1th emission control lines are electrically connected to each other through the emission control connection line display device. According to claim 1,
Each of the pixels arranged in the nth pixel row among the plurality of pixels,
light emitting element;
a driving transistor for controlling a current flowing to the light emitting device according to a gate-source voltage;
a scan transistor that transmits a data voltage to the driving transistor in response to a scan signal;
a gate initialization transistor configured to apply an initialization voltage to the gate of the driving transistor in response to a signal transmitted through an nth initialization gate line among the plurality of initialization gate lines; and
and a compensation transistor configured to connect a drain and a gate of the driving transistor to each other in response to a signal transmitted through the n-th compensation gate line. 18. The method of claim 17,
A conductivity type of the gate initialization transistor and the compensation transistor is opposite to a conductivity type of the scan transistor. 18. The method of claim 17,
a first semiconductor layer including an active region of the scan transistor;
a second semiconductor layer including an active region of the gate initialization transistor and an active region of the compensation transistor; and
The display device further comprising at least one conductive layer between the first semiconductor layer and the second semiconductor layer. 20. The method of claim 19,
The first semiconductor layer includes a silicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material. 18. The method of claim 17,
The on-section length of the signal transmitted through the n-th compensation gate line is equal to or greater than twice the on-section length of the scan signal. According to claim 1,
The substrate has a through hole corresponding to the transmission region. a substrate having a transmissive region, a display region surrounding at least a portion of the transmissive region, a non-display region between the transmissive region and the display region, and a peripheral region outside the display region;
a plurality of pixels arranged along pixel rows and pixel columns on the display area;
a plurality of gate lines respectively arranged in the pixel rows;
a plurality of gate connection lines disposed on the non-display area;
Each of the mth and m+1th gate lines and the nth and n+1th gate lines among the plurality of gate lines has a first portion and a second portion physically spaced apart from each other by the transmissive region;
the first portions of the m-th and m+1-th, n-th and n+1-th gate lines are connected to each other in the peripheral region;
The first portions of the mth and m+1th gate lines and the second portions of the mth and m+1th gate lines are electrically connected to each other through a first gate connection line among the plurality of gate connection lines A display device, characterized in that connected to (n is a natural number, m is a natural number greater than n+1). 24. The method of claim 23,
The first portions of the nth and n+1th gate lines and the second portions of the nth and n+1th gate lines are electrically connected to each other through a second gate connection line among the plurality of gate connection lines A display device, characterized in that connected to. 24. The method of claim 23,
the first gate connection line electrically connects the first portions of the n-th and n+1-th gate lines and the second portions of the n-th and n+1-th gate lines to each other Device. 24. The method of claim 23,
The second portions of the m-th and m+1-th, and n-th and n+1-th gate lines are connected to each other in the peripheral region.

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