KR102669051B1 - Method for manufacturing vertical stacked microdisplay panel - Google Patents

Abstract

The present invention relates to a method of manufacturing a vertically stacked microdisplay panel that does not require an alignment process of an LED stack and a CMOS electrode pad, and includes a support wafer and a group 3-5 compound semiconductor disposed on the support wafer through epitaxy. A first step of preparing a plurality of front wafers including a grown light emitting part, each emitting different colors, and preparing a back wafer with a plurality of CMOS electrode pads aligned on the upper surface; a second step of vertically stacking the plurality of light emitting units and the bonding layer on the back wafer by repeatedly bonding the front wafer to the back wafer through a bonding layer and then removing the support wafer; and a third step in which the plurality of LED stacks are aligned on the plurality of CMOS electrode pads by etching the stacked plurality of light emitting units and the bonding layer to separate them into predetermined units.
According to the present invention, unlike the existing monolithic integration or hybridization method that has alignment issues, the stack on the engineering monolithic epitaxial wafer is etched to separate it into preset units, so that the plurality of LED stacks are formed into a plurality of CMOS electrode pads. Since they are aligned on the image, it is possible to use not only small-diameter wafers of 6 inches or less, but also large-diameter wafers of 8 inches or more, which has the effect of significantly increasing product yield. In addition, according to the present invention, since the bonding layer and the ohmic contact electrode are made of ceramic material rather than metal, the possibility of electrical short circuit failure is significantly low, and device reliability is significantly increased. In addition, in the plasma dry process for aligning the LED stack, etching is easy and there is no problem of re-deposition of etching by-products. In addition, according to the present invention, the light emitting part, the bonding layer, and the ohmic contact electrode are all transparent and visible light is transmitted, so there is an effect of eliminating alignment error issues in the exposure process.

Description

Vertically stacked microdisplay panel manufacturing method {METHOD FOR MANUFACTURING VERTICAL STACKED MICRODISPLAY PANEL}

The present invention relates to a method of manufacturing a vertically stacked microdisplay panel. More specifically, the present invention relates to a method of manufacturing a vertically stacked microdisplay panel, and more specifically, to a method of manufacturing a LED stack and a CMOS electrode through an engineering monolithic epitaxy wafer using a ceramic material when bonding a front wafer and a back wafer. This relates to a vertically stacked microdisplay panel manufacturing method for manufacturing an LEDoS microdisplay panel that does not require a pad alignment process.

The types that implement the Metaverse that have recently been attracting attention include VR (Virtual Reality), AR (Augmented Reality), MR (Mixed Reality), and XR (eXtended Reality). It is classified into four types. Among them, the Metaverse ecosystem is expected to develop in the future centered on XR, a reality that connects VR, AR, and MR. In order to effectively implement this, 1-inch Devices (smart glasses, head-mounted displays, etc.) that include microdisplays with a diagonal length of less than 100 cm as a core component are required. In particular, the development of high-performance microdisplay panel technology is absolutely necessary to provide the greatest sense of immersion, visibility, and convenience to XR users and minimize dizziness.

As shown in FIG. 1, the conventional microdisplay panel 10 is a technology that combines a Si CMOS semiconductor wafer process and a high-resolution, high-brightness ultra-small display process. The conventional microdisplay panel 10 includes a plurality of CMOS electrode pads. A Si CMOS wafer (11) having a (100) crystal plane of 8" or more provided with (12), and a transparent wafer (13) of less than 6" provided with microLED electrode pads (14) and a plurality of microLED chips (15). It can have a structure joined through a conductive junction 16, and types of microdisplay panels expected to be applied to XR devices include liquid crystal (LC)-based LCoS (LC on Si) and OLED (Organic Light-Emitting). Diode)-based OLEDoS (OLED on Si), LEDoS (LED on Si) based on ultra-small microLED with a pixel size of less than 5㎛, etc. In the case of VR with low pixel density displays, the focus is on LCoS and OLEDoS. It has been developed and mass-produced.

However, with the development of metaverse implementation technology, the need for lightweight AR, MR, and XR devices using high pixel density microdisplay panels is increasing, and in response to these needs, theoretically ideal devices are being developed based on the superiority of inorganic properties. There is an urgent need to develop LEDoS technology, which is attracting attention as a solution, but the microdisplay panel platform for this has not yet been established.

LEDoS, based on ultra-small microLED with a pixel size of less than 5㎛, has the advantage of excellent power-to-performance ratio and short response speed when applied to XR devices, and is composed of inorganic materials, has a long lifespan and is efficient. It has the advantage of reducing heat generation and enabling long-term battery use by using electric power. In particular, XR devices have a very short distance between the display and the eyes, so it is easy to feel discomfort such as dizziness even if there is a slight delay in image conversion, so compared to LCoS and OLEDoS, which have a response speed of microseconds, nanosecond LEDoS, which has a response speed of ), is evaluated as most suitable for XR devices.

Furthermore, the biggest reason why LEDoS is attracting attention in AR, MR, and XR devices, unlike VR, is believed to be its brightness and luminous efficiency. Due to the nature of smart glasses that can be worn regardless of location, high brightness is an essential condition so that they can operate normally even in outdoor environments such as sunlight. In theory, microLED supports luminance of tens to millions of nits. OLED is organic, while microLED is inorganic, so it has the advantage of high luminous efficiency.

However, despite the above-mentioned advantages, the biggest reason why ultra-small microLED-based LEDoS with a pixel size of less than 5㎛ has not established itself as a major component of XR devices is that mass production is difficult. In other words, LEDoS requires millions of ultra-small microLEDs to be fixed on a Si CMOS wafer, so the process difficulty is high and the yield is very low, leading to an increase in manufacturing costs and high component prices. This is reflected in the final consumer price and supplied as expensive XR devices. This makes it difficult to meet market demand.

Meanwhile, as shown in Figure 2, until recently, the development of LEDoS using group 3-5 compound (GaN, GaP, etc.) microLED light sources was ① a monolithic wafer (or unit die) consisting of a microLED array on a Si CMOS wafer. Through traditional approaches such as monolithic integration or ② hybridization between wafers (or unit dies) on Si CMOS wafers or blue, green, and red light source wafers (or unit dies) on which microLED arrays are fabricated. has been developed

One of the biggest obstacles to the development of LEDoS using blue, green, and red microLED light sources composed of group 3-5 compounds to date is that it is not easy to secure a solution for pixels smaller than 5㎛, but recently, monolithic integration technology has been developed. A 5㎛-level pixel has been successfully demonstrated using a 5㎛-level pixel, and a demonstration product partially developed based on hybridization technology was manufactured using a sapphire flip chip to achieve a 10㎛-level pixel, and in addition, France's Cea- Leti has proven that it is possible to reduce pixels to the 5㎛ level in the same way by using micro tube wiring in hybridization technology. However, both monolithic integration technology and hybridization technology are impractical solutions that pose significant difficulties in mass production in terms of quality and yield, making mass production difficult.

The above-described monolithic integration technology and hybridization technology separately design and manufacture a front plane wafer composed of a group 3-5 compound microLED array and a Si CMOS back plane wafer composed of numerous IC electrode pad arrays. It has the common feature of a subsequent assembly method, which is a microLED array manufactured at unit die-level or wafer-level on a Si CMOS wafer. Since ultra-fine alignment is required, alignment is limited to the precision of the process-related devices, which has a significant impact on pixel and pitch limitations between pixels, making mass production difficult. There is. Accordingly, in order to manufacture LEDoS with high-resolution, high-brightness, high-speed driving blue, green, and red microLED light sources with pixels of less than 5㎛ and pitch of less than 3㎛, a new alternative solution that can avoid the ultra-fine alignment constraints described above is needed. This is a necessary situation.

Accordingly, several impressive demonstration products with 6㎛ pixels have recently been produced using engineering monolithic epitaxy wafers manufactured through a low-temperature metal bonding process between Si CMOS wafers and microLED array wafers. Although it has been released, mass production is assessed to be impossible due to low quality and yield issues due to low-temperature metal bonding, and the use of small-diameter wafers of 6 inches or less. Above all, when producing ultra-fine pixels of less than 3㎛ for microdisplays using conventional engineering monolithic epitaxial wafers using metal bonding, even more difficulties are encountered during patterning and etching.

As another example, we have recently made great progress in solving the problem of limiting the brightness and resolution of LEDoS using Group 3-5 compound microLED light sources, while also providing mass production and low-cost manufacturing solutions through the use of 12-inch large-diameter Si CMOS wafers. A new engineering monolithic epitaxial wafer approach has been proposed. As shown in FIG. 3, specifically, the process using the engineering monolithic epitaxial wafer is carried out through the following four-step process: ① Final microdisplay panel on a 12-inch Si blank wafer (black Si wafer) LED epitaxies cut into (100) sizes (4 mm × 6 mm) are aligned and glued at the unit die level, and the LED growth wafer and buffer layer are removed and planarized, leaving only a 1.5 μm thick LED active layer on the large-diameter Si blank wafer. ② The LED active layer remaining on the Si blank wafer is bonded to the Si CMOS wafer at the wafer level through multi-layer metal bonding, ③ the 12-inch Si blank wafer is removed, and ④ the microLED array that functions as a pixel is placed on the Si CMOS wafer. Produced by direct patterning.

However, in step ①, when bonding the LED epitaxial die onto the Si blank wafer, there is a limitation that it must be aligned and bonded on a Si CMOS IC wafer of the same size, and in step ②, multilayers containing low melting point metals (Sn, In) are used. When bonding with metal, it is relatively easy for low melting point metal components to overflow and discharge, resulting in a short circuit between the microLED sub-pixel arrays in the panel or in the electrical connection with the CMOS IC electrode pad array in close proximity. Problems exist, and in step ④, accurate ultra-fine patterning is difficult due to the opaque multi-layer metal bonding layer, and defects occur due to re-deposition of multi-layer metal layer by-products generated in the plasma dry process. .

In other words, the engineering monolithic epitaxial wafer approach presented in the above-mentioned technologies is evaluated as providing a solution that takes one step closer to implementing LEDoS based on ultra-small microLEDs with a pixel size of less than 5㎛, but the metal (low-temperature) use in wafer bonding , multilayer), there are quality and yield issues, and it is very difficult to produce high-resolution microdisplays with ultra-fine pixels of less than 3㎛, and there are also problems with some alignment processes, so a new alternative is needed. This is the situation.

Republic of Korea Patent Publication No. 10-2018-0009116

The purpose of the present invention is to solve the above-described conventional problems, and when bonding the front wafer and the back wafer, the LED stack and the CMOS electrode pad are used through an engineering monolithic epitaxy wafer using a ceramic material. To provide a vertically stacked microdisplay panel manufacturing method for manufacturing an LEDoS microdisplay panel that does not require an alignment process.

The above object is, according to the present invention, in the method of manufacturing a vertically stacked microdisplay panel that does not require an alignment process of the LED stack and the CMOS electrode pad, a support wafer and a Group 3-5 compound semiconductor disposed on the support wafer. A first step of preparing a plurality of front wafers including epitaxially grown light emitting parts, each emitting different colors, and preparing a back wafer with a plurality of CMOS electrode pads aligned on the upper surface; a second step of vertically stacking the plurality of light emitting units and the bonding layer on the back wafer by repeatedly bonding the front wafer to the back wafer through a bonding layer and then removing the support wafer; and a third step in which the plurality of LED stacks are respectively aligned on the plurality of CMOS electrode pads by etching the plurality of stacked light emitting units and the bonding layer to separate them into preset units. Vertically stacked microdisplay. This is achieved by a panel manufacturing method.

Additionally, the bonding layer may be formed of an optically transparent and electrically conductive ceramic material.

Additionally, the ceramic material may be transparent conductive oxide (TCO), transparent conductive nitride (TCN), or transparent conductive oxynitride (TCON).

Additionally, the plurality of front wafers may include a first front wafer emitting a first color, a second front wafer emitting a second color different from the first color, and a second front wafer different from the first color and the second color. It may include a third front wafer that emits a third color.

In addition, a fourth step of forming a common electrode on the plurality of LED stacks and forming a color filter on the common electrode may be further included.

Additionally, in the second step, before bonding the front wafer onto the back wafer, the surfaces of the bonding layer of the front wafer and the bonding layer of the back wafer may be polished and planarized, respectively.

Additionally, the support wafer and the back wafer may be silicon (Si) wafers.

In addition, the light emitting unit is disposed between a first semiconductor region having first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and between the first semiconductor region and the second semiconductor region, It may include an active region that generates light using recombination of electrons and holes.

Additionally, an ohmic contact electrode may be formed on at least one of the upper or lower surfaces of the light emitting unit to make ohmic contact and be electrically connected to the light emitting unit.

Additionally, the ohmic contact electrode may be formed of an optically transparent and electrically conductive material.

Additionally, the surface of the ohmic contact electrode may be polished and flattened.

According to the present invention, unlike the existing monolithic integration or hybridization method that has alignment issues, the stack on the engineering monolithic epitaxial wafer is etched to separate it into preset units, so that the plurality of LED stacks are formed into a plurality of CMOS electrode pads. Since they are aligned on the image, it is possible to use not only small-diameter wafers of 6 inches or less, but also large-diameter wafers of 8 inches or more, which has the effect of significantly increasing product yield.

In addition, according to the present invention, since the bonding layer and the ohmic contact electrode are made of ceramic material rather than metal, the possibility of electrical short circuit failure is significantly low, and device reliability is significantly increased. In addition, in the plasma dry process for aligning the LED stack, etching is easy and there is no problem of re-deposition of etching by-products. Moreover, because of the ease of etching described above, it provides a much advantageous advantage in manufacturing high-resolution microdisplays with ultra-fine pixels of less than 3㎛.

In addition, according to the present invention, the light emitting part, the bonding layer, and the ohmic contact electrode are all transparent and visible light is transmitted, so there is an effect of eliminating alignment error issues in the exposure process.

Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within the range apparent to those skilled in the art from the contents described below.

Figure 1 shows the structure of a microdisplay panel of the prior art;
Figure 2 shows a prior art LEDoS development approach;
Figure 3 illustrates an approach using a prior art engineered monolithic epitaxial wafer;
Figure 4 is a flow chart of a vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention;
Figure 5 shows a vertically stacked microdisplay panel manufactured according to a vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention;
Figures 6 and 7 show a process in which a plurality of front wafers are manufactured in an n-side up form in the vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention;
Figures 8 and 9 show a process in which a plurality of front wafers are manufactured in a p-side up form in the vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention;
10 to 12 illustrate a process of manufacturing a vertically stacked microdisplay panel according to a method of manufacturing a vertically stacked microdisplay panel according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail through illustrative drawings. When adding reference numerals to components in each drawing, it should be noted that identical components are given the same reference numerals as much as possible even if they are shown in different drawings.

Additionally, when describing embodiments of the present invention, if detailed descriptions of related known configurations or functions are judged to impede understanding of the embodiments of the present invention, the detailed descriptions will be omitted.

Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, or order of the component is not limited by the term.

From now on, with reference to the attached drawings, a vertically stacked microdisplay panel manufacturing method (S100) according to an embodiment of the present invention will be described in detail.

Figure 4 is a flow chart of a vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention, and Figure 5 is a vertically stacked microdisplay panel manufactured according to a vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention. 6 and 7 show a process in which a plurality of front wafers are manufactured in an n-side up form in the vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention, and FIGS. 8 and 9 shows a process in which a plurality of front wafers are manufactured in a p-side up form in the vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention, and Figures 10 to 12 show a process according to an embodiment of the present invention. It shows the process of manufacturing a vertically stacked microdisplay panel according to the vertically stacked microdisplay panel manufacturing method.

As shown in FIGS. 4 to 12, the present invention relates to a method (S100) for manufacturing a vertically stacked microdisplay panel that does not require an alignment process of the LED stack and the CMOS electrode pad 121, and is an embodiment of the present invention. The vertically stacked microdisplay panel manufacturing method (S100) according to the example includes a first step (S110), a second step (S120), a third step (S130), and a fourth step (S140).

The first step (S110) is a step of preparing a plurality of front wafers 110 and back wafers 120.

In more detail, the plurality of front wafers 110 each emit different colors, and the plurality of front wafers 110 include a first front wafer 210 that emits a first color, and a first color different from the first color. It may include a second front wafer 310 that emits two colors, and a third front wafer 410 that emits a third color different from the first color and the second color. At this time, the first color may refer to red, the second color may refer to green, and the third color may refer to blue, but are not limited thereto.

In more detail, the first front wafer 210, the second front wafer 310, and the third front wafer 410 each include a support wafer 111 and a light emitting unit disposed on top of the support wafer 111. 112 (including the first light emitting unit 212, the second light emitting unit 312, and the third light emitting unit 412).

The support wafer 111 supports the light emitting unit 112 disposed on the upper portion, and the support wafer 111 is used to prevent quality issues due to differences in thermal expansion coefficient when bonding with the back wafer 120, which will be described later. It is prepared as a silicon (Si) wafer having a (111), (110) or (100) crystal plane.

The light emitting unit 112 generates light and can emit blue light, green light, or red light. In the present invention, when the light emitting unit 112 emits blue light or green light, it is group 3 among group 3-5 compound semiconductors. Group (Al, Ga, In) nitride semiconductors: indium nitride (InN), indium gallium nitride (InGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum gallium indium nitride (AlGaInN) Binary, ternary, and quaternary compounds such as these can be grown epitaxially by placing them in an appropriate position and order on the first growth wafer (G).

In particular, in order to emit blue or green light, high-quality Group 3 nitride semiconductors of indium gallium nitride (InGaN) with a high indium (In) composition are used to produce gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), It should be preferentially formed on a Group 3 nitride semiconductor composed of aluminum gallium indium nitride (AlGaInN), but is not limited to this.

In addition, in the present invention, when the light emitting unit 112 emits red light, indium phosphide (InP) and indium gallium phosphide (InGaP), which are group 3 (Al, Ga, In) phosphide semiconductors among group 3-5 compound semiconductors, are used. , binary, ternary, and quaternary compounds such as gallium phosphide (GaP), aluminum indium phosphide (AlInP), aluminum gallium phosphide (AlGaP), aluminum phosphide (AlP), and aluminum gallium indium phosphide (AlGaInP) were first grown on wafers ( G) It can be grown epitaxially by placing it in the appropriate position and order.

In particular, in order to emit red light, high-quality Group 3 phosphide semiconductors of indium gallium phosphide (InGaP) with a high indium (In) composition are used to produce red light. It should be preferentially formed on a Group 3 phosphide semiconductor composed of aluminum (AlP) and aluminum gallium indium phosphide (AlGaInP), but is not limited to this.

In more detail, the light emitting unit 112 includes a first semiconductor region 1121 (e.g., a p-type semiconductor region), an active region 1123 (e.g., Multi Quantum Wells, MQWs), and a second semiconductor region. It includes a region 1122 (e.g., an n-type semiconductor region), in which a second semiconductor region 1122, an active region 1123, and a first semiconductor region 1121 are formed on the growth wafer G in that order. It may have an epitaxially grown structure, and may ultimately include several multi-layered Group 3 nitrides, and may have an overall thickness of typically about 5.0 to 8.0 ㎛, but is not limited thereto.

Each of the first semiconductor region 1121, the active region 1123, and the second semiconductor region 1122 may be made of a single layer or multiple layers, and although not shown, the light emitting portion 112 may be epitaxially formed on the top of the growth wafer (G). Prior to growth, necessary layers such as a buffer layer may be added to improve the quality of the epitaxially grown light emitting portion 112. For example, the buffer layer usually has a thickness of around 4.0㎛ and includes a compliant layer composed of a nucleation layer and an undoped semiconductor region to relieve stress and improve thin film quality. It can be composed of: In addition, when removing the growth wafer (G) using a laser lift off (LLO) technique, a sacrificial layer may be provided between the nucleation layer and the undoped semiconductor region, and the seed A layer can also function as a sacrificial layer.

The second semiconductor region 1122 has second conductivity (n-type) and is formed on the growth wafer (G). This second semiconductor region 1122 may have a thickness of 2.0 to 3.5 ㎛.

The active region 1123 generates light using recombination of electrons and holes, and is formed on the second semiconductor region 1122. This active region 1123 may have a multi-layer thickness of several tens of nm.

The first semiconductor region 1121 has first conductivity (p-type) and is formed on the active region 1123. This first semiconductor region 1121 may have a multi-layer thickness of several tens of nm to several μm, and its upper surface has gallium (Ga) polarity.

That is, the active region 1123 is interposed between the first semiconductor region 1121 and the second semiconductor region 1122, and the holes of the first semiconductor region 1121, which is a p-type semiconductor region, and the second semiconductor region, which is an n-type semiconductor region, When electrons in the semiconductor region 1122 are recombined in the active region 1123, light is generated.

In addition, before bonding the front wafer 110 and the back wafer 120 through the bonding layer 130, at least one of the upper or lower surface of the light emitting portion 112 is contacted with ohmic contact (ohmic contact) with the light emitting portion 112. An ohmic contact electrode 113 with transparent conductivity that is electrically connected can be formed, which will be described later.

Meanwhile, the front wafer 110 of the present invention is manufactured in an n-side up form in which the second semiconductor region 1122 with second conductivity (n-type) is exposed to the outside, or has a first conductivity (p-type). The first semiconductor region 1121 may be manufactured in a p-side up form exposed to the outside.

As shown in Figures 6 and 7, when the front wafer 110 of the present invention is manufactured in an n-side up form in which the second semiconductor region 1122 with second conductivity (n-type) is exposed to the outside. is a case where the growth wafer (G) is removed through one bonding, and the process is as follows.

First, when the light emitting unit 112 emits blue light or green light, Sapphire (α-) is an optically transparent wafer with high temperature and heat resistance that transmits 100% of the laser beam (single wavelength light) without absorption (in theory). phase Al ₂ O ₃ ) The light emitting portion 112 is epitaxially grown by stacking the second semiconductor region 1122, the active region 1123, and the first semiconductor region 1121 in that order on the growth wafer (G). 1 An ohmic contact electrode 113 with transparent conductivity is formed on the upper surface of the semiconductor region 1121, and then ohmic contact is made with a silicon (Si) support wafer 111 having a (111), (110) or (100) crystal plane. The electrode 113 is bonded through the bonding layer (B). Thereafter, the growth wafer (G) is separated from the light emitting portion 112 using a laser lift off (LLO) technique, and the second semiconductor region 1122 is etched to reduce the thickness of the second semiconductor region 1122. After reducing, an ohmic contact electrode 113 with transparent conductivity is formed on the lower surface of the second semiconductor region 1122 of which the thickness has been reduced, and a bonding layer 130 is deposited on the lower ohmic contact electrode 113. The n-side up type front wafer 110 is prepared by forming it.

On the other hand, the blue or green light emitting part 112 can be formed on silicon (Si) having a (111) crystal plane instead of the sapphire (α-phase Al ₂ O ₃ ) growth wafer (G). The silicon (Si) growth wafer (G) can be separated and removed using mechanical polishing or chemical etching techniques (Chemical Lift Off, CLO).

In addition, when the light emitting unit 112 emits red light, the second semiconductor region 1122 and the active region 1123 are formed on the gallium arsenide (GaAs) growth wafer (G). ) and the first semiconductor region 1121 are sequentially stacked to epitaxially grow the light emitting portion 112, and an ohmic contact electrode 113 with transparent conductivity is formed on the upper surface of the first semiconductor region 1121, A silicon (Si) support wafer 111 having a (111), (110) or (100) crystal plane and an ohmic contact electrode 113 are bonded through a bonding layer (B). Thereafter, the growth wafer (G) is separated from the light emitting portion 112 using a chemical lift off (CLO) technique, and the second semiconductor region 1122 is etched to reduce the thickness of the second semiconductor region 1122. After reducing, an ohmic contact electrode 113 with transparent conductivity is formed on the lower surface of the second semiconductor region 1122 of which the thickness has been reduced, and a bonding layer 130 is deposited on the lower ohmic contact electrode 113. The n-side up type front wafer 110 is prepared by forming it.

Accordingly, when the front wafer 110 has an n-side up shape, a silicon (Si) support wafer 111 having a (111), (110), or (100) crystal plane, a bonding layer (B), and an ohmic contact It has a structure in which the electrode 113, the first semiconductor region 1121, the active region 1123, the second semiconductor region 1122, the ohmic contact electrode 113, and the bonding layer 130 are stacked in that order, and the silicon The (Si) support wafer 111 has no difference in thermal expansion coefficient when bonded to the silicon (Si) back wafer 120, thereby contributing to stabilizing the quality of the vertically stacked microdisplay panel.

In addition, as shown in FIGS. 8 and 9, the front wafer 110 of the present invention is manufactured in a p-side up form in which the first semiconductor region 1121 with first conductivity (p type) is exposed to the outside. In this case, the growth wafer (G) and temporary wafer (T) are removed through two bonding processes, and the process is as follows.

First, when the light emitting unit 112 emits blue light or green light, Sapphire (α-) is an optically transparent wafer with high temperature and heat resistance that transmits 100% of the laser beam (single wavelength light) without absorption (in theory). phase Al ₂ O ₃ ) The light emitting portion 112 is epitaxially grown by stacking the second semiconductor region 1122, the active region 1123, and the first semiconductor region 1121 in that order on the growth wafer (G). 1 An ohmic contact electrode 113 with transparent conductivity is formed on the upper surface of the semiconductor region 1121, and then ohmic contact is made with a silicon (Si) temporary wafer (T) having a (111), (110), or (100) crystal plane. The electrode 113 is adhered through the adhesive layer (A). Thereafter, the growth wafer (G) is separated from the light emitting portion 112 using a laser lift off (LLO) technique, and the second semiconductor region 1122 is etched to reduce the thickness of the second semiconductor region 1122. After reducing, an ohmic contact electrode 113 with transparent conductivity is formed on the lower surface of the second semiconductor region 1122 of which the thickness has been reduced, and silicon (111), (110), or (100) having a crystal plane is formed. Si) The support wafer 111 and the ohmic contact electrode 113 are bonded to each other through the bonding layer (B). Afterwards, the temporary wafer (T) is separated from the adhesive layer (A) using a chemical lift off (CLO) technique, the adhesive layer (A) is removed by etching, and the adhesive layer is formed on the upper ohmic contact electrode 113. A front wafer 110 in a p-side up shape is prepared by depositing (130) to form it.

On the other hand, the blue or green light emitting part 112 can be formed on silicon (Si) having a (111) crystal plane instead of the sapphire (α-phase Al ₂ O ₃ ) growth wafer (G). The silicon (Si) growth wafer (G) and the support wafer 111 are separated and removed by mechanical polishing or chemical etching (Chemical Lift Off, CLO).

In addition, when the light emitting unit 112 emits red light, the second semiconductor region 1122, the active region 1123, and the first semiconductor region 1121 are sequentially formed on the gallium arsenide (GaAs) growth wafer (G). The light-emitting portion 112 is epitaxially grown by stacking, and an ohmic contact electrode 113 with transparent conductivity is formed on the upper surface of the first semiconductor region 1121, and then (111), (110), or (100) crystal plane. The silicon (Si) support wafer 111 and the ohmic contact electrode 113 are bonded through the bonding layer (B). Thereafter, the growth wafer (G) is separated from the light emitting portion 112 using a chemical lift off (CLO) technique, and the second semiconductor region 1122 is etched to reduce the thickness of the second semiconductor region 1122. After reducing, an ohmic contact electrode 113 with transparent conductivity is formed on the lower surface of the second semiconductor region 1122 of which the thickness has been reduced, and silicon (111), (110), or (100) having a crystal plane is formed. Si) The support wafer 111 and the ohmic contact electrode 113 are bonded to each other through the bonding layer (B). Afterwards, the temporary wafer (T) is separated from the adhesive layer (A) using a laser lift off (LLO) technique, the adhesive layer (A) is removed by etching, and the adhesive layer is formed on the upper ohmic contact electrode 113. A front wafer 110 in a p-side up shape is prepared by depositing (130) to form it.

Accordingly, when the front wafer 110 has a p-side up shape, a silicon (Si) support wafer 111 having a (111), (110), or (100) crystal plane, a bonding layer (B), and an ohmic contact It has a structure in which the electrode 113, the second semiconductor region 1122, the active region 1123, the first semiconductor region 1121, the ohmic contact electrode 113, and the bonding layer 130 are stacked in that order, and the silicon The (Si) support wafer 111 has no difference in thermal expansion coefficient when bonded to the silicon (Si) back wafer 120, thereby contributing to stabilizing the quality of the vertically stacked microdisplay panel.

Furthermore, during the manufacturing process of the front wafer 110 of the p-side up or n-side up type described above, the ohmic contact electrode 113 is placed on the surface of the first semiconductor region 1121 or the surface of the second semiconductor region 1122. Before this is formed, when the surface of the first semiconductor region 1121 is exposed (in the form of p-side up) or the surface of the second semiconductor region 1122 is exposed (in the form of n-side up), each has a smooth surface. To achieve this, the surface may be polished and smoothened through mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively.

Meanwhile, the ohmic contact electrode 113 of the front wafer 110 is formed of a transparent conductive material. When the ohmic contact electrode 113 is formed to contact the first semiconductor region 1121, which is a p-type semiconductor, the ohmic contact electrode 113 is formed of a transparent conductive material. The contact electrode 113 material may include NiO, PtO, PdO, AgO ₂ , Au, Rh ₂ O ₃ , RuO ₂ , In ₂ O ₃ , SnO ₂ , ZnO, IZO, ITO, and IGZO, and is an ohmic contact electrode. When (113) is formed to be in contact with the second semiconductor region 1122, which is an n-type semiconductor, the ohmic contact electrode 113 material is TiN, CrN, VN, In ₂ O ₃ , SnO ₂ , ZnO, IZO, ITO, and May include IGZO. Furthermore, since the surface of the second semiconductor region 1122 with nitrogen (N) polarity has a very large surface roughness compared to the surface of the first semiconductor region 1121 with gallium (Ga) polarity, ohmic contact with transparent conductivity Before forming the electrode 113, it is desirable to introduce a CMP (Chemical Mechanical Polishing) process to polish and flatten the surface of the second semiconductor region 1122.

Additionally, the surface of the ohmic contact electrode 113 formed on the front wafer 110 may also be polished and smoothened through mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively.

The back wafer 120 is an active driving IC driven by an active matrix (AM) method. It refers to a CMOS wafer with a plurality of CMOS electrode pads 121 arranged in an array on the upper surface, and includes a plurality of CMOS wafers. A passivation layer may be formed between the electrode pads 121.

Here, the back wafer 120 is prepared as a silicon (Si) wafer having a (100) crystal plane, and is preferably prepared as an 8-inch or 12-inch silicon (Si) wafer according to a standard CMOS IC process.

The second step (S120) is such that the light emitting portion 112 of the front wafer 110 is directed toward the CMOS electrode pad 121 of the back wafer 120, that is, the light emitting portion 112 of the front wafer 110 and the back wafer 110 are aligned. After bonding the front wafer 110 with the top and bottom reversed on the back wafer 120 through the bonding layer 130 so that the CMOS electrode pads 121 of the wafer 120 face each other, the support wafer 111 is removed. This is a step of stacking a plurality of light emitting units 112 and a plurality of bonding layers 130 in a vertical direction on the back wafer 120 by repeating.

Here, the support wafer 111 of the front wafer 110 is a silicon (Si) wafer having a (111), (110) or (100) crystal plane, and the back wafer 120 is also a silicon (Si) wafer having a (100) crystal plane. Because it is a wafer, there is no difference in thermal expansion coefficient during bonding, contributing to stabilizing the quality of the vertically stacked microdisplay panel.

At this time, the second step (S120) does not use high pressure or an external electric field, but uses the property of smooth surfaces to stick to each other due to van der Waals force. Accordingly, the CMP process is introduced before bonding the front wafer 110 and the back wafer 120 through the bonding layer 130, so that the roughness of each bonding surface is very low (Rq, < 0.5nm @ 2㎛). × 2㎛), and it is desirable to ensure that there are no particles such as impurities between the surfaces. To this end, in the second step (S120), before bonding the front wafer 110 and the back wafer 120, the bonding layer 130 of the front wafer 110 and the bonding layer 130 of the back wafer 120 are The surface can be polished smoothly and flatly through mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively.

Here, the bonding layer 130 is formed of a ceramic material that is optically transparent and electrically conductive, that is, has transparent conductivity. Here, the optically transparent material is made of a ceramic material that is optically transparent and electrically conductive. ) refers to Transparent (with a transmittance of 80% or more) or Translucent (with a transmittance of 50% or more), and electrically conductive means having an electrical resistance of less than 10 ^-3 Ω/cm. . Ceramic materials with such transparent conductivity include transparent conductive oxide (TCO), transparent conductive nitride (TCN), and transparent conductive oxide nitride (TCON).

At this time, when the ceramic material is a transparent conductive oxide, the ceramic material may include In ₂ O ₃ , SnO ₂ , ZnO, IZO, ITO, and IGZO, and when the ceramic material is a transparent conductive nitride, the ceramic material may include TiN or CrN. and VN, and when the ceramic material is transparent conductive oxynitride, the ceramic material may include InON, SnON, ZnON, IZON, ITON, and IGZON.

In more detail, as shown in FIGS. 10 to 12, the second step (S120) is the first light emitting unit 212 of the first front wafer 210 in the n-side up (or p-side up) form. After bonding the first front wafer 210 to the back wafer 120 through the bonding layer 130 so as to face the CMOS electrode pad 121 of the back wafer 120, chemical lift off (CLO) is performed. ) The support wafer 111 is removed using a technique, etc., and the bonding layer (B) is removed by etching.

Afterwards, ohmic contact is made so that the second light emitting unit 312 of the second front wafer 310 in the n-side up (or p-side up) form is directed toward the CMOS electrode pad 121 of the back wafer 120. After bonding the second front wafer 310 to the back wafer 120 to which the first light emitting portion 212, where the electrodes 113 are formed on the upper and lower sides, is bonded, through the bonding layer 130, a chemical lift off is performed. The support wafer 111 is removed using the Off, CLO) technique, and the bonding layer (B) is removed by etching.

Afterwards, ohmic contact is made so that the third light emitting unit 412 of the third front wafer 410 in the n-side up (or p-side up) form is directed toward the CMOS electrode pad 121 of the back wafer 120. After bonding the third front wafer 410 to the back wafer 120 to which the second light emitting portion 312, where the electrode 113 is formed on the upper and lower surfaces, is bonded, through the bonding layer 130, a chemical lift off is performed. Off, CLO) technique, etc., remove the support wafer 111 and remove the bonding layer (B) by etching, so that the back wafer, the bonding layer 130, and the ohmic contact electrode 113 are formed on the upper and lower surfaces, respectively. A second light emitting unit 312 having a bonding layer 130, a bonding layer 130, and ohmic contact electrodes 113 formed on the upper and lower surfaces, respectively, and a third light emitting part 312 having a bonding layer 130, and ohmic contact electrodes 113 formed on the upper and lower surfaces, respectively. The parts 412 have a vertically stacked structure, and the first light emitting part 212, the second light emitting part 312, and the third light emitting part 412 emit white light at the same time.

At this time, considering the wavelength of light, the first color of the first light emitting part 212 in the lower layer is red, which has a long wavelength, the second color of the second light emitting part 312 in the middle layer is green, and the third color in the upper layer is green. The third color of the light emitting unit 412 is preferably blue, which has a short wavelength, but is not limited thereto.

Thereafter, after the plurality of front wafers 110 and the back wafer 120 are bonded in the second step (S120), the bonding layer ( Heat treatment is essentially performed on the back wafer 120, the bonding layer 130 disposed on the top of the back wafer 120, the first light emitting portion 212 disposed on the top of the bonding layer 130, and the first A bonding layer 130 disposed on top of the light emitting portion 212, a second light emitting portion 312 disposed on top of the bonding layer 130, and a bonding layer disposed on top of the second light emitting portion 312. 130 and the third light emitting unit 412 disposed on top of the bonding layer 130 have a stacked structure in that order, and the first light emitting unit 212, the second light emitting unit 312, and the third light emitting unit 412 are sequentially stacked. Each light emitting unit 412 has a structure in which an ohmic contact electrode 113 with transparent conductivity is formed on at least one of the upper or lower surfaces. That is, a transparent stack layer structure is formed on a CMOS IC wafer composed of an array of CMOS electrode pads 121, thereby forming the engineering monolithic epitaxy wafer structure of the present invention.

The third step (S130) is to etch the plurality of vertically stacked light emitting units 112, bonding layer 130, and ohmic contact electrodes 113 to separate them into preset units (pixel or sub-pixel units), thereby forming a plurality of LEDs. A step of aligning the laminate by arranging it on each of the plurality of CMOS electrode pads 121. A process of aligning the conventional LED laminate of the front wafer 110 and the CMOS electrode pad 121 of the back wafer 120 with each other. This is a step to eliminate the need for this.

That is, the LED stack in the present invention is a plurality of vertically stacked light emitting units 112, bonding layer 130, and ohmic contact electrodes 113 etched in the vertical direction and then set to a preset unit (pixel or subpixel unit). means separation, and the third step (S130) is to move the light emitting portion 112, the bonding layer 130, and the ohmic contact electrode 113 in a vertical direction until the surface of the back wafer 120 or an adjacent area is exposed. A plurality of LED stacks are aligned on top of the arrayed, that is, aligned, CMOS electrode pads 121 by etching them.

At this time, the light emitting part 112, the bonding layer 130, and the ohmic contact electrode 113 of the present invention are all transparent and transmit visible light, so there is an advantage that there is no alignment error issue in the exposure process. In addition, since both the bonding layer 130 and the ohmic contact electrode 113 of the present invention are made of ceramic materials rather than metal, they are easy to etch in a plasma dry process, and the problem of re-deposition of etching by-products is eliminated. There is an advantage to not having it happen.

The fourth step (S140) is to form a mold part (M) that fills the space between the plurality of aligned LED stacks, form a common electrode 140 on the plurality of LED stacks, and apply a color filter on the common electrode 140. This is the step of forming (150) (Color filter).

More specifically, in the fourth step (S140), a mold portion (M) is formed to fill the space between the plurality of aligned LED stacks, and the mold portion (M) is etched to expose the top of the plurality of LED stacks. A vertically stacked LEDoS structure is completed by forming a common electrode 140 on the exposed top of the plurality of LED stacks and forming a color filter 150 on the common electrode 140, where the common electrode 140 is an ohmic Similar to the contact electrode 113, it can be formed of a transparent conductive material, and when the common electrode 140 is an anode, the common electrode 140 material is NiO, PtO, PdO, AgO ₂ , Au, Rh ₂ O ₃ , RuO ₂ , In ₂ O ₃ , SnO ₂ , ZnO, IZO, ITO, and IGZO. When the common electrode 140 is a cathode, the common electrode 140 material is TiN, CrN, VN, In. ₂ O ₃ , SnO ₂ , ZnO, IZO, ITO and IGZO.

Additionally, the surface of the common electrode 140 may also be polished and smoothly planarized through mechanical polishing (MP) or chemical-mechanical polishing (CMP).

In addition, the color filter 150 provides light of different wavelength bands when light emitted from the light emitting unit 112 is incident. For example, each color filter 150 may provide light such as blue light, green light, or red light. , white light can be provided in areas where the color filter 150 is not formed. Meanwhile, the wavelength band of light provided from the color filter 150 may be modified in various ways depending on the design.

The color filter 150 described above is basically a thin film containing an organic dye or pigment in a photoresist, but it is more preferable to use inorganic quantum dots to produce a microdisplay with pixels less than 3㎛. do. In particular, before forming the color filter 150 on the common electrode 140, in order to improve the quality of the thin film of the color filter 150 _, Al ₂ O ₃ , _SiN It is desirable to form a thin film below the thickness.

Furthermore, although not shown, a protection layer may be additionally formed with a transparent organic material to protect the color filter 150 from the atmospheric environment.

Figure 5 shows a vertically stacked microdisplay panel manufactured according to a vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention.

As shown in FIG. 5, one embodiment of the present invention includes the first step (S110), the second step (S120), the third step (S130), and the fourth step (S140) as described above. The vertically stacked microdisplay panel 100 manufactured according to the vertically stacked microdisplay panel manufacturing method (S100) according to the example includes a back wafer 120 with a plurality of CMOS electrode pads 121 aligned on the upper surface, and a back wafer ( A bonding layer 130 disposed on top of the bonding layer 120, a first light emitting portion 212 disposed on top of the bonding layer 130, and a bonding layer 130 disposed on top of the first light emitting portion 212. and a second light emitting unit 312 disposed on top of the bonding layer 130, a bonding layer 130 disposed on top of the second light emitting portion 312, and a second light emitting portion 312 disposed on top of the bonding layer 130. It includes a third light emitting unit 412, a common electrode 140 disposed on an upper portion of the third emitting portion 412, and a color filter 150 disposed on an upper portion of the common electrode 140. At this time, an ohmic contact electrode 113 is formed on at least one of the upper or lower surfaces of each of the first light emitting unit 212, the second light emitting unit 312, and the third light emitting unit 412, and the bonding layer 130 The ohmic contact electrode 113 is made of a ceramic material with transparent conductivity, and the plurality of vertically stacked light emitting units 112, bonding layer 130, and ohmic contact electrode 113 are etched to separate into preset units. , It has a structure in which a plurality of LED stacks are aligned on top of a plurality of aligned CMOS electrode pads 121. Accordingly, the structure of the vertically stacked LEDoS microdisplay panel 100 of the present invention is completed.

Since the following content is the same as that of the vertically stacked microdisplay panel manufacturing method (S100) according to an embodiment of the present invention described above, redundant description is omitted.

In the above, even though all the components constituting the embodiment of the present invention have been described as being combined or operated in combination, the present invention is not necessarily limited to this embodiment. That is, as long as it is within the scope of the purpose of the present invention, all of the components may be operated by selectively combining one or more of them.

In addition, terms such as “include,” “comprise,” or “have” described above mean that the corresponding component may be present, unless specifically stated to the contrary, and therefore do not exclude other components. Rather, it should be interpreted as being able to include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Commonly used terms, such as terms defined in a dictionary, should be interpreted as consistent with the contextual meaning of the related technology and, unless explicitly defined in the present invention, should not be interpreted in an idealized or overly formal sense.

The above description is merely an illustrative explanation of the technical idea of the present invention, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present invention.

Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

10: Microdisplay panel of the prior art
11: Si CMOS wafer
12: CMOS electrode pad
13: Transparent wafer
14: microLED electrode pad
15: microLED chip
16: conductive junction
S100: Vertically stacked microdisplay panel manufacturing method according to an embodiment of the present invention
S110: Step 1
S120: Second stage
S130: Third stage
S140: Step 4
100: Vertically stacked microdisplay panel according to an embodiment of the present invention
110: front wafer
111: support wafer
112: light emitting unit
1121: First semiconductor region
1122: Second semiconductor area
1123: active area
113: Ohmic contact electrode
210: first front wafer
212: first light emitting unit
310: second front wafer
312: second light emitting unit
410: Third front wafer
412: third light emitting unit
G: Growth wafer
T: Temporary wafer
A: Adhesive layer
B: bonding layer
120: back wafer
121: CMOS electrode pad
130: bonding layer
M: mold part
140: common electrode
150: Color filter

Claims (11)

In the method of manufacturing a vertically stacked microdisplay panel that does not require an alignment process between the LED stack and the CMOS electrode pad,
A support wafer, a light emitting portion disposed on the support wafer and epitaxially grown with a group 3-5 compound semiconductor, and formed on at least one of the upper or lower surface of the light emitting portion and ohmic contact (ohmic) with the light emitting portion. contact) and electrically connected, and includes an optically transparent and electrically conductive ohmic contact electrode. A plurality of front wafers, each emitting different colors, are prepared, and a plurality of CMOS electrode pads are placed on the upper surface at regular intervals. A first step of preparing aligned back wafers;
By repeatedly bonding the front wafer to the back wafer through an optically transparent and electrically conductive bonding layer and then removing the support wafer, a plurality of the light emitting units, the ohmic contact electrode, and A second step of stacking the bonding layer in a vertical direction; and
According to the positions of the plurality of CMOS electrode pads aligned at regular intervals, the plurality of stacked light emitting units, the ohmic contact electrode, and the bonding layer are etched and separated into predetermined units, thereby forming a plurality of LED stacks. A third step of aligning each of the CMOS electrode pads,
In the first step and the second step,
The light emitting portion and the ohmic contact electrode in the front wafer are not etched in preset units,
The third step is,
Using the fact that the light emitting part, the ohmic contact electrode, and the bonding layer are all optically transparent, the light emitting part, the ohmic contact electrode, and the bonding layer are preset according to the positions of the plurality of CMOS electrode pads aligned at regular intervals. A method of manufacturing a vertically stacked microdisplay panel, characterized by etching in units. In claim 1,
The bonding layer is,
A method of manufacturing a vertically stacked microdisplay panel, characterized in that it is formed of a ceramic material. In claim 2,
The ceramic material is,
A method of manufacturing a vertically stacked microdisplay panel, characterized in that it is transparent conductive oxide (TCO), transparent conductive nitride (TCN), or transparent conductive oxynitride (TCON). In claim 1,
The plurality of front wafers are:
A first front wafer emitting light of a first color, a second front wafer emitting light of a second color different from the first color, and a third front wafer emitting light of a third color different from the first color and the second color Method for manufacturing a vertically stacked microdisplay panel, comprising a wafer. In claim 1,
A method of manufacturing a vertically stacked microdisplay panel, further comprising forming a common electrode on the plurality of LED stacks and forming a color filter on the common electrode. In claim 1,
The second step is,
Before bonding the front wafer onto the back wafer, the surfaces of the bonding layer of the front wafer and the bonding layer of the back wafer are respectively polished and planarized. In claim 1,
The support wafer and the back wafer are,
A method of manufacturing a vertically stacked microdisplay panel, characterized in that it is a silicon (Si) wafer. In claim 1,
The light emitting part,
A first semiconductor region having a first conductivity, a second semiconductor region having a second conductivity different from the first conductivity, and between the first semiconductor region and the second semiconductor region, for recombination of electrons and holes. A method of manufacturing a vertically stacked microdisplay panel, including an active area that generates light using a vertically stacked microdisplay panel. delete delete In claim 1,
The ohmic contact electrode is,
A method of manufacturing a vertically stacked microdisplay panel, characterized in that the surface is polished and flattened.