KR102665982B1 - Test device and operating method thereof - Google Patents

Abstract

The present technology relates to a test device and a method of operating the same. The test device includes a data pattern generation circuit for generating program data when operating a test program and transmitting it to at least one memory die before a packaging process is performed; a data storage circuit that stores the program data; and a data comparison circuit that receives read data from a data storage device in which the at least one memory die is packaged during a test read operation and compares the read data with the program data stored in the data storage circuit to generate a pass or fail signal. Includes.

Description

Test device and operating method thereof {TEST DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to a test device and a method of operating the same, and more specifically, to a test device and a method of operating the same that perform a test operation of a data storage device.

Recently, the paradigm for the computer environment is shifting to ubiquitous computing, which allows computer systems to be used anytime, anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers is rapidly increasing. Such portable electronic devices generally use a memory system using a memory device, that is, a data storage device. Data storage devices are used as main or auxiliary storage devices in portable electronic devices.

Data storage devices using memory devices have the advantage of having excellent stability and durability because they do not have mechanical driving parts, and also have very fast information access speeds and low power consumption. Examples of memory systems with these advantages include data storage devices such as USB (Universal Serial Bus) memory devices, memory cards with various interfaces, and solid state drives (SSD).

Memory devices are largely divided into volatile memory devices and nonvolatile memory devices.

Non-volatile memory devices have relatively slow writing and reading speeds, but retain stored data even when the power supply is cut off. Therefore, non-volatile memory devices are used to store data that must be maintained regardless of whether power is supplied or not. Non-volatile memory devices include Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash memory, and Phase change memory (PRAM). Random Access Memory), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NAND type.

The above-mentioned data storage device can be formed by packaging a plurality of memory dies (DIE) on which flash memory is formed. To test the reliability of the data storage device, a test operation is performed on the memory die before packaging or after packaging is completed. Test operations of the data storage device can be performed.

Embodiments of the present invention provide a test device and a method of operating the same that can improve the reliability of test operations.

A test device according to an embodiment of the present invention includes a data pattern generation circuit for generating program data when operating a test program and transmitting it to at least one memory die before a packaging process is performed; a data storage circuit that stores the program data; and a data comparison circuit that receives read data from a data storage device in which the at least one memory die is packaged during a test read operation and compares the read data with the program data stored in the data storage circuit to generate a pass or fail signal. Includes.

A method of operating a test device according to an embodiment of the present invention includes performing a test program operation on at least one memory die on which an electronic circuit is formed; performing a read operation on a data storage circuit manufactured by packaging the at least one memory die; and determining the result of the test operation by comparing program data programmed during the test program operation with read data read as a result of the read operation.

According to this technology, by performing a test program operation in a memory die state before packaging a data storage device and performing a test lead operation in a state in which a plurality of memory dies are packaged, damage occurring during the packaging operation is eliminated through the test operation. It can be detected.

1 is a configuration diagram illustrating a test device and a memory die according to an embodiment of the present invention.
Figure 2 is a configuration diagram for explaining a test device and a data storage device according to an embodiment of the present invention.
Figure 3 is a configuration diagram for explaining a test device according to an embodiment of the present invention.
FIG. 4 is a configuration diagram for explaining the memory die of FIGS. 1 and 2.
FIG. 5 is a diagram for explaining the memory block of FIG. 4.
Figure 6 is a diagram for explaining an embodiment of a three-dimensional memory block.
Figure 7 is a diagram for explaining another embodiment of a three-dimensional memory block.
Figure 8 is a flowchart for explaining a test method using a test device according to an embodiment of the present invention.
Figure 9 is a diagram for explaining another embodiment of a memory system.
FIG. 10 is a diagram for explaining another embodiment of a memory system.
FIG. 11 is a diagram for explaining another embodiment of a memory system.
FIG. 12 is a diagram for explaining another embodiment of a memory system.

Specific structural and functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification or application are merely illustrative for the purpose of explaining the embodiments according to the concept of the present invention, and the implementation according to the concept of the present invention The examples may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

Since embodiments according to the concept of the present invention can make various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiments according to the concept of the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms such as first and/or second may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component, for example, without departing from the scope of rights according to the concept of the present invention, a first component may be named a second component, and similarly The second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between. Other expressions that describe the relationship between components, such as "between" and "immediately between" or "neighboring" and "directly adjacent to" should be interpreted similarly.

The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate the existence of a described feature, number, step, operation, component, part, or combination thereof, but are not intended to indicate the presence of one or more other features or numbers. It should be understood that this does not exclude in advance the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings they have in the context of the related technology, and unless clearly defined in this specification, should not be interpreted in an idealized or overly formal sense. No.

In describing the embodiments, description of technical content that is well known in the technical field to which the present invention belongs and that is not directly related to the present invention will be omitted. This is to convey the gist of the present invention more clearly without obscuring it by omitting unnecessary explanation.

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings in order to explain in detail enough to enable those skilled in the art of the present invention to easily implement the technical idea of the present invention. .

1 is a configuration diagram illustrating a test device and a memory die according to an embodiment of the present invention.

Referring to FIG. 1, when a test program is operated, the test device 10 is connected to the memory die 20 and controls the test operation of the memory die 20. For example, the test device 10 transmits program data (DATA_P) to the memory die 20 when a test program is operated and controls the memory die 20 so that the program data (DATA_P) is stored in the memory die 20. can do.

The program data (DATA_P) may be data with a certain data pattern or random data with a random pattern. The test device 10 generates data with a certain data pattern or random data as program data (DATA_P), and data identical to the program data (DATA_P) transmitted to the memory die 20 is also stored inside the test device 10. Save.

The memory die 20 is a semiconductor wafer or substrate with integrated electronic circuits cut and processed, and may include a plurality of memory cells in which data is stored. The memory die 20 is a semiconductor chip or semiconductor die. Accordingly, program data DATA_P transmitted from the test device 10 may be stored in memory cells included in the memory die 20.

Figure 2 is a configuration diagram for explaining a test device and a data storage device according to an embodiment of the present invention.

Referring to FIG. 2, during the test lead operation, the test device 10 is connected to the data storage device 100 and controls the test operation of the data storage device 100. For example, during a test read operation, the test device 10 receives read data (DATA_R) from the data storage device 100 and performs a test operation. That is, the test device 10 performs a test operation that compares the program data (DATA_P in FIG. 1) stored during the test program operation with the read data (DATA_R) transmitted from the data storage device 100 during the test read operation.

The data storage device 100 may include a memory device 50 including at least one memory die 20 of FIG. 1 and a controller 40 for controlling overall operations of the memory device 50. That is, the data storage device 100 can be manufactured by packaging the controller 40 and at least one memory die, and the memory dies 20 may receive damage such as heat and shock during the packaging process.

Additionally, the data storage device 100 may upload a firmware image to the controller 40 after the packaging process.

Figure 3 is a configuration diagram for explaining a test device according to an embodiment of the present invention.

Referring to FIG. 3, the test device 10 may be configured to include a data pattern generation circuit 11, a data storage block 12, and a data comparison circuit 13.

The data pattern generation circuit 11 generates and outputs program data (DATA_P) when a test program is operated during a test operation. The program data (DATA_P) may be data with a certain data pattern or random data with a random pattern. Program data (DATA_P) is transmitted to the memory die 20 of FIG. 1.

The data storage block 12 receives program data (DATA_P) generated in the data pattern generation circuit 11 when a test program is operated and stores it. Afterwards, the data storage block 12 outputs the stored program data (DATA_P) to the data comparison circuit 13 during the test read operation.

The data comparison circuit 13 compares the read data (DATA_R) transmitted from the data storage device 100 of FIG. 2 and the program data (DATA_P) transmitted from the data storage block 12 during the test read operation during the test operation, A pass or fail signal (PASS/FAIL) is output depending on the comparison result. For example, the data comparison circuit 13 generates a pass signal when the program data (DATA_P) and the read data (DATA_R) are the same or the number of different bits among the program data (DATA_P) and the read data (DATA_R) is less than the set number of bits. (PASS) is generated and printed. Additionally, the data comparison circuit 13 generates and outputs a fail signal (FAIL) when the number of different bits among the program data (DATA_P) and the read data (DATA_R) is greater than the set number of bits.

FIG. 4 is a diagram for explaining the memory die 20 of FIGS. 1 and 2.

Referring to FIG. 4 , the memory die 20 may include a memory cell array 300 in which data is stored. The memory die 20 performs a program operation to store data in the memory cell array 300, a read operation to output the stored data, and an erase operation to erase the stored data. It may include peripheral circuits 200 configured to perform. The memory die 20 may include control logic 400 that controls the peripheral circuits 200.

The memory cell array 300 may include a plurality of memory blocks (MB1 to MBk; 310 (k is a positive integer)). Local lines (LL) and bit lines (BL1 to BLm; m is a positive integer) may be connected to each of the memory blocks (MB1 to MBk) 310. For example, the local lines LL include a first select line, a second select line, and a plurality of word lines arranged between the first and second select lines ( word lines). Additionally, the local lines LL may include dummy lines arranged between the first selection line and the word lines, and between the second selection line and the word lines. Here, the first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, local lines LL may include word lines, drain and source select lines, and source lines (SL). For example, the local lines LL may further include dummy lines. For example, local lines LL may further include pipe lines. The local lines LL may be respectively connected to the memory blocks MB1 to MBk 310, and the bit lines BL1 to BLm may be commonly connected to the memory blocks MB1 to MBk 310. Memory blocks (MB1 to MBk; 310) may be implemented in a two-dimensional or three-dimensional structure. For example, in the two-dimensional memory blocks 310, memory cells may be arranged in a direction parallel to the substrate. For example, in the three-dimensional memory blocks 310, memory cells may be stacked perpendicular to the substrate.

The peripheral circuits 200 may be configured to perform program, read, and erase operations of the selected memory block 310 under the control of the control logic 400. For example, the peripheral circuits 200 include a voltage generating circuit (210), a row decoder (220), a page buffer group (230), and a column decoder (240). , may include an input/output circuit (250), a pass/fail check circuit (260), and a source line driver (270).

The voltage generation circuit 210 may generate various operating voltages Vop used for program, read, and erase operations in response to the operation signal OP_CMD. Additionally, the voltage generation circuit 210 may selectively discharge the local lines LL in response to the operation signal OP_CMD. For example, the voltage generation circuit 210 may generate a program voltage, a verification voltage, a pass voltage, and a selection transistor operating voltage under the control of the control logic 400.

The row decoder 220 may transmit operating voltages Vop to local lines LL connected to the selected memory block 310 in response to the control signals AD_signals. For example, the row decoder 220 transmits the operating voltages (e.g., program voltage, verification voltage, pass voltage, etc.) generated by the voltage generation circuit 210 in response to the row decoder control signals (AD_signals) to local lines. It can be selectively applied to word lines among (LL).

During the program voltage application operation, the row decoder 220 applies the program voltage generated by the voltage generation circuit 210 to the selected word line among the local lines LL in response to the control signals (AD_signals), and the voltage generation circuit ( The pass voltage generated in step 210) is applied to the remaining unselected word lines. In addition, the row decoder 220 applies the read voltage generated by the voltage generation circuit 210 to the selected word line among the local lines LL in response to the control signals (AD_signals) during a read operation, and the voltage generation circuit 210 ) is applied to the remaining unselected word lines.

The page buffer group 230 may include a plurality of page buffers (PB1 to PBm) 231 connected to bit lines (BL1 to BLm). Page buffers (PB1 to PBm; 231) may operate in response to page buffer control signals (PBSIGNALS). For example, the page buffers (PB1 to PBm; 231) temporarily store data to be programmed during a program operation, or sense the voltage or current of the bit lines (BL1 to BLm) during a read or verify operation. You can.

The column decoder 240 may transfer data between the input/output circuit 250 and the page buffer group 230 in response to the column address (CADD). For example, the column decoder 240 may exchange data with the page buffers 231 through data lines DL, or exchange data with the input/output circuit 250 through column lines CL. .

The input/output circuit 250 may transmit an internal command (CMD) and an address (ADD) received from the outside to the control logic 400, or exchange data (DATA) with the column decoder 240.

During a read operation or a verify operation, the pass/fail determination unit 260 generates a reference current in response to the allow bit (VRY_BIT<#>) and receives the data received from the page buffer group 230. A pass signal (PASS) or a fail signal (FAIL) can be output by comparing the sensing voltage (VPB) and the reference voltage generated by the reference current.

The source line driver 270 is connected to a memory cell included in the memory cell array 300 through a source line (SL) and can control the voltage applied to the source line (SL). The source line driver 270 may receive the source line control signal (CTRL_SL) from the control logic 400 and control the source line voltage applied to the source line (SL) based on the source line control signal (CTRL_SL). You can.

The control logic 400 sends an operation signal (OP_CMD), control signals (AD_signals), page buffer control signals (PBSIGNALS), and a permission bit (VRY_BIT<#>) in response to the internal command (CMD) and address (ADD). By outputting, the peripheral circuits 200 can be controlled. Additionally, the control logic 400 may determine whether the verification operation passed or failed in response to a pass or fail signal (PASS or FAIL).

FIG. 5 is a diagram for explaining the memory block of FIG. 4.

Referring to FIG. 5 , the memory block 310 may have a plurality of word lines arranged in parallel between a first selection line and a second selection line connected to each other. Here, the first selection line may be a source selection line (SSL), and the second selection line may be a drain selection line (DSL). In more detail, the memory block 310 may include a plurality of strings (ST) connected between the bit lines BL1 to BLm and the source line SL. The bit lines BL1 to BLm may be respectively connected to the strings ST, and the source line SL may be commonly connected to the strings ST. Since the strings ST may be configured identically to each other, the string ST connected to the first bit line BL1 will be described in detail as an example.

The string (ST) may include a source selection transistor (SST), a plurality of memory cells (F1 to F16), and a drain selection transistor (DST) connected in series between the source line (SL) and the first bit line (BL1). You can. One string (ST) may include at least one source select transistor (SST) and at least one drain select transistor (DST), and may also include more memory cells (F1 to F16) than shown in the drawing.

The source of the source selection transistor (SST) may be connected to the source line (SL), and the drain of the drain selection transistor (DST) may be connected to the first bit line (BL1). The memory cells F1 to F16 may be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gates of the source select transistors (SST) included in the different strings (ST) may be connected to the source select line (SSL), and the gates of the drain select transistors (DST) may be connected to the drain select line (DSL). and the gates of the memory cells F1 to F16 may be connected to a plurality of word lines WL1 to WL16. Among memory cells included in different strings ST, a group of memory cells connected to the same word line may be referred to as a physical page (PPG). Accordingly, the memory block 310 may include as many physical pages (PPG) as the number of word lines (WL1 to WL16).

One memory cell can store 1 bit of data. This is commonly called a single level cell (SLC). In this case, one physical page (PPG) can store one logical page (LPG) data. One logical page (LPG) data may include as many data bits as the number of cells included in one physical page (PPG). Additionally, one memory cell can store two or more bits of data. This is commonly called a multi-level cell (MLC). In this case, one physical page (PPG) can store data of two or more logical pages (LPG).

Figure 6 is a diagram for explaining an embodiment of a three-dimensional memory block.

Referring to FIG. 6 , the memory cell array 300 may include a plurality of memory blocks (MB1 to MBk) 310. The memory block 310 may include a number of strings (ST11 to ST1m, ST21 to ST2m). As an embodiment, each of the plurality of strings (ST11 to ST1m, ST21 to ST2m) may be formed in a 'U' shape. Within the first memory block MB1, m strings may be arranged in the row direction (X direction). In FIG. 6, two strings are shown arranged in the column direction (Y direction), but this is for convenience of explanation, and three or more strings may be arranged in the column direction (Y direction).

Each of the plurality of strings (ST11 to ST1m, ST21 to ST2m) includes at least one source selection transistor (SST), first to nth memory cells (MC1 to MCn), a pipe transistor (PT), and at least one drain selection transistor. (DST) may be included.

The source and drain selection transistors (SST and DST) and the memory cells (MC1 to MCn) may have similar structures. For example, each of the source and drain selection transistors (SST and DST) and the memory cells (MC1 to MCn) may include a channel film, a tunnel insulating film, a charge trap film, and a blocking insulating film. For example, a pillar to provide a channel film may be provided in each string. For example, a pillar for providing at least one of a channel film, a tunnel insulating film, a charge trap film, and a blocking insulating film may be provided in each string.

The source select transistor (SST) of each string may be connected between the source line (SL) and the memory cells (MC1 to MCp).

As an embodiment, source selection transistors of strings arranged in the same row may be connected to source selection lines extending in the row direction, and source selection transistors of strings arranged in different rows may be connected to different source selection lines. In FIG. 6 , the source selection transistors of the strings ST11 to ST1m in the first row may be connected to the first source selection line SSL1. Source selection transistors of the strings ST21 to ST2m in the second row may be connected to the second source selection line SSL2.

As another example, the source selection transistors of the strings (ST11 to ST1m and ST21 to ST2m) may be commonly connected to one source selection line.

The first to nth memory cells (MC1 to MCn) of each string may be connected between the source selection transistor (SST) and the drain selection transistor (DST).

The first to nth memory cells (MC1 to MCn) may be divided into first to pth memory cells (MC1 to MCp) and p+1 to nth memory cells (MCp+1 to MCn). The first to pth memory cells MC1 to MCp may be sequentially arranged in the vertical direction (Z direction) and may be connected in series between the source selection transistor SST and the pipe transistor PT. The p+1 to nth memory cells (MCp+1 to MCn) may be sequentially arranged in the vertical direction (Z direction) and may be connected in series between the pipe transistor (PT) and the drain select transistor (DST). there is. The first to pth memory cells (MC1 to MCp) and the p+1 to nth memory cells (MCp+1 to MCn) may be connected to each other through a pipe transistor (PT). Gates of the first to nth memory cells (MC1 to MCn) of each string may be connected to the first to nth word lines (WL1 to WLn), respectively.

As an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. If a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. The gate of the pipe transistor (PT) of each string may be connected to the pipe line (PL).

The drain select transistor (DST) of each string may be connected between the bit line and the memory cells (MCp+1 to MCn). Strings arranged in the row direction may be connected to a drain selection line extending in the row direction. The drain selection transistors of the strings ST11 to ST1m in the first row may be connected to the first drain selection line DSL1. Drain selection transistors of the strings (ST21 to ST2m) in the second row may be connected to the second drain selection line (DSL2).

Strings arranged in the column direction may be connected to bit lines extending in the column direction. In FIG. 6 , the strings ST11 and ST21 in the first column may be connected to the first bit line BL1. The m-th strings (ST1m, ST2m) may be connected to the m-th bit line (BLm).

Among strings arranged in a row direction, memory cells connected to the same word line may form one page. For example, memory cells connected to the first word line WL1 among the strings ST11 to ST1m in the first row may constitute one page. Memory cells connected to the first word line (WL1) among the strings (ST21 to ST2m) in the second row may configure another page. When one of the drain selection lines DSL1 and DSL2 is selected, strings arranged in one row will be selected. When one of the word lines (WL1 to WLn) is selected, one page of the selected strings will be selected.

Referring to FIG. 7 , the memory cell array 300 may include a plurality of memory blocks (MB1 to MBk) 310. The memory block 310 may include a number of strings (ST11' to ST1m' and ST21' to ST2m'). Each of the plurality of strings (ST11'~ST1m', ST21'~ST2m') may extend along the vertical direction (Z direction). Within the memory block 310, m strings may be arranged in the row direction (X direction). In FIG. 7, two strings are shown arranged in the column direction (Y direction), but this is for convenience of explanation, and three or more strings may be arranged in the column direction (Y direction).

Each of the plurality of strings (ST11'~ST1m', ST21'~ST2m') includes at least one source selection transistor (SST), first to nth memory cells (MC1 to MCn), and at least one drain selection transistor. (DST) may be included.

The source select transistor (SST) of each string may be connected between the source line (SL) and the memory cells (MC1 to MCn). Source selection transistors of strings arranged in the same row may be connected to the same source selection line. The source selection transistors of the strings ST11' to ST1m' arranged in the first row may be connected to the first source selection line SSL1. The source selection transistors of the strings ST21' to ST2m' arranged in the second row may be connected to the second source selection line SSL2. As another example, the source selection transistors of the strings ST11' to ST1m' and ST21' to ST2m' may be commonly connected to one source selection line.

The first to nth memory cells MC1 to MCn of each string may be connected in series between the source selection transistor SST and the drain selection transistor DST. Gates of the first to nth memory cells MC1 to MCn may be connected to the first to nth word lines WL1 to WLn, respectively.

As an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. If a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. Accordingly, the reliability of data stored in the memory block 310 may be improved.

The drain select transistor (DST) of each string may be connected between the bit line and the memory cells (MC1 to MCn). Drain select transistors DST of strings arranged in the row direction may be connected to a drain select line extending in the row direction. The drain selection transistors DST of the strings CS11' to CS1m' in the first row may be connected to the first drain selection line DSL1. The drain selection transistors DST of the strings CS21' to CS2m' in the second row may be connected to the second drain selection line DSL2.

Figure 8 is a flowchart for explaining a test method using a test device according to an embodiment of the present invention.

With reference to FIGS. 1 to 8 , a test operation of a memory die and a data storage device using a test device according to an embodiment of the present invention will be described as follows.

A test program operation is performed on the memory dies 20 before performing the packaging operation (S810). The test device 10 is connected to the memory die 20, and the test pattern generation circuit 11 of the test device 10 generates program data (DATA_P) and transmits it to the connected memory die 20 to perform the test program operation. Control the memory die 20 to perform. The above-described test program operation is performed for each of the plurality of memory dies 20 when the data storage device 100 formed by subsequent packaging includes a plurality of memory dies 20. The test program operation is performed only on at least one memory block (for example, MB1) selected among the memory blocks 310 included in the memory die 20, or on all memory blocks 310 included in the memory die 20. ) can be performed by selecting.

The test device 10 stores the generated program data (DATA_P) in the data storage block 12.

When the test program operation of the memory die 20 is completed, the packaging process of the data storage device 100 is performed (S820). The packaging process is performed by packaging the memory dies 20 and the controller 40 on which the test program operation has been performed into one device.

The firmware image is uploaded to the data storage device 100 for which packaging has been completed (S830). The firmware image may be stored in a specific memory die of the memory die 20 or in a ROM area within the controller 40.

Afterwards, a test read operation of the data storage device 100 is performed (S840). The test device 10 is connected to the data storage device 100, and the data storage device 100 tests the read data (DATA_R) by performing a read operation on the data stored in the memory dies 20 when the test program is operated. Transmit to device 10.

The data storage block 12 transmits the stored program data (DATA_P) to the data comparison circuit 13 when the test program is operated. The data comparison circuit 13 performs a comparison operation to compare the program data (DATA_P) received from the data storage block 12 and the read data (DATA_R) received from the data storage device 100 (S850).

As a result of the above comparison (S860), if the program data (DATA_P) and read data (DATA_R) are the same, or the number of different bits among the program data (DATA_P) and read data (DATA_R) is less than the set number of bits (pass), the data The comparison circuit 13 generates and outputs a pass signal (PASS), and determines that the test result of the data storage device 100 is PASS according to the pass signal (PASS) (S870).

As a result of the comparison (S860), if the number of different bits among the program data (DATA_P) and the read data (DATA_R) is greater than the set number of bits (fail), the data comparison circuit 13 generates and outputs a fail signal (FAIL), According to the fail signal (FAIL), the test result of the data storage device 100 is determined to be failed (S880).

As described above, according to an embodiment of the present invention, the test device 10 performs a test program operation on memory dies before performing the packaging process, and performs a test lead operation on the data storage device after the packaging process is completed. By doing so, it is possible to perform a test operation that reflects damage caused by the packaging process.

FIG. 9 is a diagram for explaining another embodiment of the data storage device of FIG. 2.

Referring to FIG. 9, the data storage device 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The data storage device 30000 may include a memory device 1100 and a controller 1200 capable of controlling the operation of the memory device 1100. The controller 1200 may control a data access operation, such as a program operation, an erase operation, or a read operation, of the memory device 1100 according to the control of the processor 3100.

Data programmed in the memory device 1100 may be output through the display 3200 under the control of the controller 1200.

The wireless transceiver 3300 can transmit and receive wireless signals through an antenna (ANT). For example, the wireless transceiver 3300 can change a wireless signal received through an antenna (ANT) into a signal that can be processed by the processor 3100. Accordingly, the processor 3100 may process the signal output from the wireless transceiver 3300 and transmit the processed signal to the controller 1200 or the display 3200. The controller 1200 may program signals processed by the processor 3100 into the memory device 1100. Additionally, the wireless transceiver 3300 can change the signal output from the processor 3100 into a wireless signal and output the changed wireless signal to an external device through an antenna (ANT). The input device 3400 is a device that can input control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and includes a touch pad and a computer mouse. It may be implemented as a pointing device such as a mouse, a keypad, or a keyboard. The processor 3100 operates the display 3200 so that data output from the controller 1200, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output through the display 3200. Movement can be controlled.

Depending on the embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as part of the processor 3100 or may be implemented as a separate chip from the processor 3100. Additionally, the controller 1200 may be implemented using the example of the controller shown in FIG. 2 , and the memory device 1100 may be implemented using the example of the memory device shown in FIG. 2 .

Figure 10 is a diagram for explaining another embodiment of a data storage device.

Referring to FIG. 9, the data storage device 40000 may include a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), It can be implemented as a portable multimedia player (PMP), MP3 player, or MP4 player.

The data storage device 40000 may include a memory device 1100 and a controller 1200 capable of controlling data processing operations of the memory device 1100.

The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or computer mouse, a keypad, or a keyboard.

The processor 4100 can control the overall operation of the memory system 40000 and the operation of the controller 1200. Depending on the embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as part of the processor 4100 or may be implemented as a separate chip from the processor 4100. Additionally, the controller 1200 may be implemented using the example of the controller shown in FIG. 2 , and the memory device 1100 may be implemented using the example of the memory device shown in FIG. 2 .

FIG. 11 is a diagram for explaining another embodiment of a memory system.

Referring to FIG. 10, the data storage device 50000 may be implemented as an image processing device, such as a digital camera, a mobile phone with a digital camera, a smart phone with a digital camera, or a tablet PC with a digital camera. .

The data storage device 50000 includes a memory device 1100 and a controller 1200 capable of controlling data processing operations of the memory device 1100, such as program operations, erase operations, or read operations.

The image sensor 5200 of the memory system 50000 may convert optical images into digital signals, and the converted digital signals may be transmitted to the processor 5100 or the controller 1200. According to the control of the processor 5100, the converted digital signals may be output through the display 5300 or stored in the memory device 1100 through the controller 1200. Additionally, data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the controller 1200.

Depending on the embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as part of the processor 5100 or as a separate chip from the processor 5100. Additionally, the controller 1200 may be implemented using the example of the controller shown in FIG. 2 , and the memory device 1100 may be implemented using the example of the memory device shown in FIG. 2 .

FIG. 12 is a diagram for explaining another embodiment of a memory system.

Referring to FIG. 12, the data storage device 70000 may be implemented as a memory card or smart card. The data storage device 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

The controller 1200 may control the exchange of data between the memory device 1100 and the card interface 7100. Depending on the embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto. Additionally, it can be implemented using the example of the controller shown in FIG. 2 , and the memory device 1100 can be implemented using the example of the memory device shown in FIG. 2 .

The card interface 7100 can interface data exchange between the host 60000 and the controller 1200 according to the protocol of the host (HOST) 60000. Depending on the embodiment, the card interface 7100 may support the Universal Serial Bus (USB) protocol and the InterChip (IC)-USB protocol. Here, the card interface may refer to hardware capable of supporting the protocol used by the host 60000, software mounted on the hardware, or a signal transmission method.

When data storage device 70000 is connected to host interface 6200 of host 60000, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, The host interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor 6100.

In the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope and technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of this invention as well as the claims described later.

As described above, although the present invention has been described with limited examples and drawings, the present invention is not limited to the above-mentioned examples, and various modifications and variations can be made from these descriptions by those skilled in the art. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the claims and equivalents thereof as well as the claims described later.

In the above-described embodiments, all steps may be selectively performed or omitted. Additionally, in each embodiment the steps do not necessarily occur in order and may be reversed. Meanwhile, the embodiments of the present specification disclosed in the specification and drawings are merely provided as specific examples to easily explain the technical content of the present specification and aid understanding of the present specification, and are not intended to limit the scope of the present specification. In other words, it is obvious to those skilled in the art that other modifications based on the technical idea of the present specification can be implemented.

Meanwhile, the specification and drawings disclose preferred embodiments of the present invention, and although specific terms are used, these are merely used in a general sense to easily explain the technical content of the present invention and aid understanding of the present invention. It is not intended to limit the scope of the invention. In addition to the embodiments disclosed herein, it is obvious to those skilled in the art that other modifications based on the technical idea of the present invention can be implemented.

10: Test device 11: Data pattern generation circuit
12: data storage block 13: data comparison circuit
20: memory die 40: controller
50: memory device 100: data storage device

Claims (14)

a data pattern generation circuit for generating program data when a test program is operated and transmitting it to at least one memory die before a packaging process is performed;
a data storage circuit that stores the program data; and
A data comparison circuit that receives read data from a data storage device in which the at least one memory die is packaged during a test read operation and generates a pass or fail signal by comparing the read data with the program data stored in the data storage circuit. Includes,
The data comparison circuit is a test device that generates and outputs the pass signal when the number of different bits among the program data and the read data is less than a set number of bits.
◈Claim 2 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
The data pattern generation circuit is connected to the at least one memory die when the test program is operated,
The data comparison circuit is a test device connected to the data storage device when the test lead is operated.
◈Claim 3 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
A test device in which the program data has a constant data pattern or a random data pattern.
◈Claim 4 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
The data comparison circuit is a test device that generates and outputs the pass signal when the program data and the read data are the same.
◈Claim 5 was abandoned upon payment of the setup registration fee.◈ According to claim 4,
A test device wherein the data comparison circuit generates and outputs the fail signal when the number of different bits among the program data and the read data is greater than the set number of bits.
◈Claim 6 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
A test device in which the test program operation is performed only on selected memory blocks among a plurality of memory blocks included in the memory die.
◈Claim 7 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
A test device in which the test program operation is performed on all of a plurality of memory blocks included in the memory die.
performing a test program operation on at least one memory die on which an electronic circuit is formed;
performing a test lead operation on a data storage device manufactured by packaging the at least one memory die; and
Comprising program data programmed during the test program operation and read data read as a result of the test lead operation to determine the result of the test operation,
The step of determining the result of the test operation is a method of operating a test device in which a test pass is determined when the number of different bits among the program data and the read data is less than a set number of bits.
◈Claim 9 was abandoned upon payment of the setup registration fee.◈ According to claim 8,
The test device is connected to the at least one memory die when operating the test program to program the program data into the at least one memory die, and is connected to the data storage device to read from the data storage device when the test read operation is performed. A method of operating a test device for receiving the read data.
◈Claim 10 was abandoned upon payment of the setup registration fee.◈ According to claim 8,
A method of operating a test device in which the program data has a constant data pattern or a random data pattern.
◈Claim 11 was abandoned upon payment of the setup registration fee.◈ According to claim 8,
The step of determining the result of the test operation is a method of operating a test device in which the test pass is determined when the program data and the read data are the same.
◈Claim 12 was abandoned upon payment of the setup registration fee.◈ According to claim 11,
The step of determining the result of the test operation includes determining a test failure when the number of different bits among the program data and the read data is greater than the set number of bits.
◈Claim 13 was abandoned upon payment of the setup registration fee.◈ According to claim 8,
A method of operating a test device in which the test program operation is performed only on selected memory blocks among a plurality of memory blocks included in the at least one memory die.
◈Claim 14 was abandoned upon payment of the setup registration fee.◈ According to claim 8,
A method of operating a test device in which the test program operation is performed on all of a plurality of memory blocks included in the at least one memory die.

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