KR102665637B1 - Method, apparatus and program for detecting anomalies in process equipment by integrating multiple anomaly detection techniques - Google Patents

Abstract

A method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques according to various embodiments of the present invention is disclosed. The method includes: collecting bin data, PCM (Process Control Monitoring) data, a plurality of wafer maps, and FDC (Fault Detection and Classification) data collected from process equipment; extracting a preset number of specific bin data in order of high defect rate based on the bin data; Extracting a specific device with specification defects or control defects based on the PCM data; Classifying patterns in each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern; extracting whether or not there is a defect in abnormal operation of the process equipment based on the FDC data; and providing integrated results extracted based on each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data.

Description

Method, device, and program for detecting abnormalities in process equipment by integrating multiple abnormality detection techniques {METHOD, APPARATUS AND PROGRAM FOR DETECTING ANOMALIES IN PROCESS EQUIPMENT BY INTEGRATING MULTIPLE ANOMALY DETECTION TECHNIQUES}

The present invention relates to a method, device, and program for detecting abnormalities in process equipment by integrating multiple abnormality detection techniques. Specifically, the present invention relates to a method, device, and program for detecting abnormalities in process equipment by utilizing bin data, PCM data, multiple wafer maps, and FDC data. It relates to detection methods, devices and programs.

In general, factories that have established a mass production system have the manufacturing process divided into several stages in order to increase the efficiency of mass production of products, and automation equipment suitable for each process is operated and operated for each of the various stages of the division.

In the case of automated equipment, in the process of repeatedly performing the same process, situations may arise where the process is performed abnormally due to errors in the equipment itself or the influence of the surrounding environment. In a manufacturing process system where each process is continuous and organically linked, if a problem occurs in the equipment of some process, it may result in defects in the entire process and product. Accordingly, periodic detection of abnormalities in process equipment operated for each process is very important in terms of maintenance of the factory operation system.

Detection of abnormalities in process equipment can be accomplished by having an experienced operator regularly check the operation status of the equipment through various sensor process data. However, no matter how skilled a worker is, there are limits to accurately detecting abnormal data (or abnormal data) by checking all the vast amounts of sensor process data flowing in in real time, and the abnormal data detection process can take a lot of time. In addition, as factory equipment becomes more complex, such as the introduction of FA systems, the knowledge and know-how required for workers increases, and it may be difficult for inexperienced workers to identify the factors that led to the abnormal state.

Additionally, it can be done by checking the results of the process equipment as a method of detecting abnormalities in the process equipment. For example, in the case of semiconductor processing equipment, defects in the resulting wafer can be detected and analyzed to determine whether the processing equipment is abnormal. Specifically, the defect pattern of the wafer map (image) is identified and the cause of the defect is traced to determine whether there is an abnormality in the process equipment. Determining the presence or absence of four types of defect patterns, which are well-known causes of defects: circular, defective, scratch, and area, is an important task that can improve productivity by taking timely action on process equipment. However, there are various defect patterns that are not well known, and there is a problem that the productivity of the process equipment is lowered due to the inability to take action on them in a timely manner.

In the case of a wafer map with defect patterns in which the defects are not well known, a person must classify them one by one by eye, which can be difficult. For example, there may be subtle differences in the defect patterns being classified due to differences in personal opinions of each classification operator. Additionally, there may be differences in classification time between skilled and unskilled workers.

Meanwhile, as sensor process data that can be used temporarily or permanently by being stored in a database is accumulated, research is being conducted on automated processing of monitoring data from industrial equipment related to various fields. In particular, as the amount of information that can be processed increases with the development of computer technology, artificial intelligence is evolving at a rapid pace. Accordingly, research and development is underway on technologies to detect abnormalities in data using artificial intelligence. there is.

Accordingly, there is a demand in the industry for technology to detect abnormalities in process equipment. In this regard, Republic of Korea Patent Publication No. 10-2265461 discloses a manufacturing process abnormal data detection system.

The present invention was conceived in response to the above-described background technology and is intended to provide a method for detecting abnormalities in process equipment by integrating a plurality of abnormality detection techniques.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to an embodiment of the present invention to solve the problems described above, a method for detecting abnormalities in process equipment by integrating a plurality of abnormality detection techniques is disclosed. The method includes: collecting bin data, PCM (Process Control Monitoring) data, a plurality of wafer maps, and FDC (Fault Detection and Classification) data collected from process equipment; extracting a preset number of specific bin data in order of high defect rate based on the bin data; Extracting a specific device with specification defects or control defects based on the PCM data; Classifying patterns in each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern; extracting whether or not there is a defect in abnormal operation of the process equipment based on the FDC data; and providing integrated results extracted based on each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data.

In an alternative embodiment, the step of extracting a preset number of specific bin data in order of high defect rate based on the bin data includes recognizing the defect rate of each of a plurality of wafer map groups and individual wafer maps based on the bin data. steps; and extracting the preset number of specific bin data in order of the defect rate from high to high.

In an alternative embodiment, the method produces a plurality of wafer maps including defective wafer maps produced in the past before recognizing the defect rate of each of the plurality of wafer map groups and individual wafer maps based on the bin data. Collecting steps in order; Generating a plurality of wafer map groups by grouping the plurality of wafer maps into preset units; and classifying patterns of a plurality of wafer maps included in each of the plurality of wafer map groups.

In an alternative embodiment, the step of extracting a specific device in which a specification defect or a control defect has occurred based on the PCM data includes individual elements included in the wafer map corresponding to the preset number of bin data based on the PCM data. Recognizing elements; and obtaining test results for the individual devices, and extracting specific devices that have defective specifications or control defects based on the test results.

In an alternative embodiment, the step of classifying patterns of each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern includes dividing the pattern into a predefined defective pattern. Recognizing a specific wafer map group containing more than a preset number of classified wafer maps; Recognizing first process information related to production of a wafer map included in the specific wafer map group; collecting second process information related to production of other wafer maps corresponding to the first process information; and extracting defective equipment that causes defects in the wafer map based on the first process information and the second process information.

In an alternative embodiment, the method includes collecting a plurality of wafer maps produced in the past and including defective wafer maps in production order before recognizing the specific wafer map group; Generating a plurality of wafer map groups by grouping the plurality of wafer maps into preset units; and classifying patterns of a plurality of wafer maps included in each of the plurality of wafer map groups using a pre-learned classification model to classify the plurality of wafer maps. Obtaining classification results for each of the plurality of wafer maps from the classification model; Recognizing a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value or the classified pattern is determined to be an error; Obtaining a normal pattern corresponding to the specific classification result; and retraining a classifier included in the classification model by labeling the wafer map and the normal pattern corresponding to the specific classification result.

In an alternative embodiment, extracting whether abnormal operation of the process equipment is defective based on the FDC data includes: acquiring process sensor data and prior knowledge data corresponding to the process sensor data; Generating reconstruction process sensor data corresponding to the process sensor data using a deep learning model; calculating a reconstruction rate error based on the process sensor data and the reconstruction process sensor data; and detecting abnormal operation based on comparison of the reconstruction rate error and a reference threshold.

In an alternative embodiment, the step of integrating and providing extracted results based on each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data includes the bin data, the PCM data, and the plurality of wafer maps. Comparing preset conditions corresponding to each of the maps and the FDC data with results extracted based on each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data; and providing visualized information corresponding to each of the Bin data, the PCM data, the plurality of wafer maps, and the FDC data based on the comparison result.

According to one embodiment of the present invention for solving the above-described problems, a device is disclosed. The device includes: a memory storing one or more instructions; and a processor executing the one or more instructions stored in the memory, and the processor may perform the above-described methods by executing the one or more instructions.

According to one embodiment of the present invention for solving the above-described problem, a computer program is disclosed that is combined with a computer as hardware and stored in a computer-readable recording medium to perform the above-described methods.

Other specific details of the invention are included in the detailed description and drawings.

The present invention integrates a plurality of abnormality detection techniques to detect abnormalities in process equipment, thereby improving wafer quality costs through integrated analysis and increasing work efficiency related to detecting abnormalities in process equipment.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a diagram illustrating a system according to an embodiment of the present invention.
Figure 2 is a hardware configuration diagram of a computing device according to an embodiment of the present invention.
3 to 5 are flowcharts illustrating an example of a method for detecting defective equipment based on a pattern of a wafer map according to an embodiment of the present invention.
Figures 6 and 7 are diagrams for explaining an example of a wafer map pattern and a method of learning a model for classifying the pattern of the wafer map according to an embodiment of the present invention.
8 and 9 are flowcharts illustrating an example of a method for learning a model for classifying patterns of a wafer map according to various embodiments of the present invention.
10 and 11 are flowcharts illustrating an example of a method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques according to an embodiment of the present invention.
Figure 12 is a schematic diagram showing one or more network functions related to one embodiment of the present invention.

Various embodiments are now described with reference to the drawings. In this specification, various descriptions are presented to provide an understanding of the invention. However, it is clear that these embodiments may be practiced without these specific descriptions.

As used herein, the terms “component,” “module,” “system,” and the like refer to a computer-related entity, hardware, firmware, software, a combination of software and hardware, or an implementation of software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, a thread of execution, a program, and/or a computer. For example, both an application running on a computing device and the computing device can be a component. One or more components may reside within a processor and/or thread of execution. A component may be localized within one computer. A component may be distributed between two or more computers. Additionally, these components can execute from various computer-readable media having various data structures stored thereon. Components may transmit signals, for example, with one or more data packets (e.g., data and/or signals from one component interacting with other components in a local system, a distributed system, to other systems and over a network such as the Internet). Depending on the data being transmitted, they may communicate through local and/or remote processes.

Additionally, the term “or” is intended to mean an inclusive “or” and not an exclusive “or.” That is, unless otherwise specified or clear from context, “X utilizes A or B” is intended to mean one of the natural implicit substitutions. That is, either X uses A; X uses B; Or, if X uses both A and B, “X uses A or B” can apply to either of these cases. Additionally, the term “and/or” as used herein should be understood to refer to and include all possible combinations of one or more of the related listed items.

Additionally, the terms “comprise” and/or “comprising” should be understood to mean that the corresponding feature and/or element is present. However, the terms “comprise” and/or “comprising” should be understood as not excluding the presence or addition of one or more other features, elements and/or groups thereof. Additionally, unless otherwise specified or the context is clear to indicate a singular form, the singular terms herein and in the claims should generally be construed to mean “one or more.”

Those skilled in the art will additionally recognize that the various illustrative logical blocks, components, modules, circuits, means, logic, and algorithm steps described in connection with the embodiments disclosed herein may be implemented using electronic hardware, computer software, or a combination of both. It must be recognized that it can be implemented with To clearly illustrate the interchangeability of hardware and software, various illustrative components, blocks, configurations, means, logics, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented in hardware or software will depend on the specific application and design constraints imposed on the overall system. A skilled technician can implement the described functionality in a variety of ways for each specific application. However, such implementation decisions should not be construed as departing from the scope of the present invention.

The description of the presented embodiments is provided to enable anyone skilled in the art to use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments without departing from the scope of the invention. Therefore, the present invention is not limited to the embodiments presented herein. The present invention is to be interpreted in the broadest scope consistent with the principles and novel features presented herein.

In this specification, a computer refers to all types of hardware devices including at least one processor, and depending on the embodiment, it may be understood as encompassing software configurations that operate on the hardware device. For example, a computer can be understood to include, but is not limited to, a smartphone, tablet PC, desktop, laptop, and user clients and applications running on each device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

Each step described in this specification is described as being performed by a computer, but the subject of each step is not limited thereto, and depending on the embodiment, at least part of each step may be performed in a different device.

1 is a diagram illustrating a system according to an embodiment of the present invention.

Referring to FIG. 1, a system according to an embodiment of the present invention may include a computing device 100, a user terminal 200, and an external server 300. The system shown in FIG. 1 is according to one embodiment, and its components are not limited to the embodiment shown in FIG. 1, and may be added, changed, or deleted as necessary.

According to one embodiment of the present invention, the computing device 100 can detect anomalies in process equipment. For example, the computing device 100 classifies patterns in the wafer map to detect abnormalities in process equipment, learns a model to classify the patterns in the wafer map, or detects defective equipment based on the patterns in the wafer map. It can be detected. Additionally, the computing device 100 can detect abnormalities in process equipment by integrating various analysis techniques, including analysis based on patterns of the wafer map.

In one embodiment, the computing device 100 of the present invention can detect defective equipment based on the pattern of the wafer map.

Specifically, the computing device 100 may recognize a specific wafer map group that includes a preset number or more of wafer maps classified into predefined defective patterns. Here, the wafer map group may refer to a group created by grouping wafer maps corresponding to wafers by the unit in which the wafer is produced (eg, lot).

When the computing device 100 recognizes a specific wafer map group, it may recognize first process information related to the production of the wafer map included in the specific wafer map group. Here, the first process information includes a plurality of process names (i.e., names of processes used to produce wafers) corresponding to the wafer maps included in a specific wafer map group and a plurality of equipment names (i.e., , names of equipment used in the process, etc.) may be included. For example, the computing device 100 determines through which process and with what equipment the wafer map included in a specific wafer map group was produced (i.e., first process information) through the product code of the wafer map included in the specific wafer map group. It can be figured out.

When the computing device 100 recognizes the first process information, it may collect second process information related to the production of other wafer maps corresponding to the first process information. Here, the second process information may include a plurality of process names corresponding to different wafer maps and a plurality of equipment names corresponding to the plurality of process names. For example, the computing device 100 may recognize through which process and with which equipment other wafer maps were produced (i.e., second process information) through the product codes of other wafer maps.

Additionally, the computing device 100 may detect defective equipment that causes defects in the wafer map based on the first process information and the second process information.

Therefore, the computing device 100 of the present invention can easily detect defective equipment even in a semiconductor process that passes hundreds of pieces of equipment.

Hereinafter, a detailed description of how the computing device 100 detects defective equipment based on the pattern of the wafer map will be described later with reference to FIGS. 3 to 5.

In one embodiment, the computing device 100 of the present invention can learn a neural network model for classifying patterns of a wafer map.

Specifically, the computing device 100 may acquire a plurality of wafer maps from a plurality of process facilities. Additionally, the computing device 100 may learn a classification model for classifying patterns of wafer maps based on a plurality of wafer maps. Here, the classification model is a model for classifying the image of the wafer map, a feature extraction layer consisting of a plurality of convolution layers and an activation function, a pooling layer for down-sampling the feature map, and a fully connected layer for classifying the wafer map ( That is, it may be composed of a classifier), but is not limited to this.

The computing device 100 may obtain a classification result by inputting a wafer map to classify a pattern into a classification model on which learning has been completed. Additionally, the computing device 100 may recognize a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value or the classified pattern is determined to be an error. Additionally, the computing device 100 may acquire a normal pattern corresponding to a specific classification result. Additionally, the computing device 100 may retrain the classifier included in the classification model by labeling the wafer map and normal pattern corresponding to the specific classification result.

Therefore, the computing device 100 of the present invention can efficiently use human and material resources and improve model accuracy by utilizing transfer learning techniques.

Hereinafter, a detailed description of a method by which the computing device 100 trains a neural network model for classifying the pattern of the wafer map will be described with reference to FIGS. 6 and 7 .

In one embodiment, computing device 100 may integrate various analysis techniques to detect abnormalities in process equipment.

Specifically, the computing device 100 may collect bin data, process control monitoring (PCM) data, a plurality of wafer maps, and fault detection and classification (FDC) data collected from process equipment. Additionally, the computing device 100 may extract a preset number of specific bin data in order of high defect rate based on the bin data. Additionally, the computing device 100 may extract a specific device in which specification defects or control defects have occurred based on PCM data. Additionally, the computing device 100 may classify the patterns of each of the plurality of wafer maps based on the plurality of wafer maps and extract at least one specific defective device corresponding to the classified pattern. Additionally, the computing device 100 may extract defects related to abnormal operation of process equipment based on FDC data. Additionally, the computing device 100 may integrate results extracted based on bin data, PCM data, multiple wafer maps, and FDC data and provide the results to the user.

Therefore, the computing device 100 of the present invention can improve wafer quality costs through integrated analysis and increase work efficiency related to detecting abnormalities in process equipment.

Hereinafter, a detailed description of how the computing device 100 detects abnormalities in process equipment by integrating various analysis techniques will be described with reference to FIGS. 10 and 11 .

In various embodiments, the computing device 100 may provide web- or application-based services. For example, the computing device 100 may provide an abnormality detection service for process equipment. However, it is not limited to this.

Computing device 100 may include any type of computer system or computer device, such as, for example, microprocessors, mainframe computers, digital processors, portable devices, and device controllers. However, it is not limited to this.

Hereinafter, the hardware configuration of the computing device 100 will be described with reference to FIG. 2 .

Meanwhile, the user terminal 200 can be connected to the computing device 100 through the network 400, and the user or the computing device 100 uses the abnormality detection service of the process equipment provided by the computing device 100. It may be the terminal of the manager of the process facility that is the target of abnormality detection.

Here, the user terminal 200 may include, for example, various types of computer devices. For example, the user terminal 200 may refer to various terminal devices such as a smartphone, tablet PC, desktop, or laptop.

The user terminal 200 includes a display in at least a portion of the terminal, and may include an operating system for running an application or extension program-based service provided by the computing device 100. For example, the user terminal 200 may be a smart phone, but is not limited to this. The user terminal 200 is a wireless communication device that guarantees portability and mobility, and may be used for navigation, personal communication (PCS), etc. System), GSM (Global System for Mobile communications), PDC (Personal Digital Cellular), PHS (Personal Handyphone System), PDA (Personal Digital Assistant), IMT (International Mobile Telecommunication)-2000, CDMA (Code Division Multiple Access)- 2000, all types of handheld-based wireless communication devices such as W-CDMA (W-Code Division Multiple Access), Wibro (Wireless Broadband Internet) terminals, smartpads, tablet PCs, etc. It can be included.

The external server 300 can be connected to the computing device 100 through the network 400, and can transmit and receive various information/data necessary for the computing device 100 to perform various operations related to detecting abnormalities in process equipment. And, the computing device 100 can store and manage various information/data generated as the computing device 100 performs various operations related to detecting abnormalities in process equipment.

For example, the external server 300 may be a database server that stores information used in various operations related to abnormality detection of process equipment. For another example, the external server 300 may be a server (i.e., a process equipment server) that provides information used for various operations related to detecting abnormalities in process equipment.

The network 400 may refer to a connection structure that allows information exchange between nodes such as a computing device, a plurality of terminals, and servers. For example, the network 400 includes a local area network (LAN), a wide area network (WAN), the World Wide Web (WWW), a wired and wireless data communication network, a telephone network, and a wired and wireless television communication network. do.

Wireless data communication networks include 3G, 4G, 5G, 3GPP (3rd Generation Partnership Project), 5GPP (5th Generation Partnership Project), LTE (Long Term Evolution), WIMAX (World Interoperability for Microwave Access), Wi-Fi, and Internet. (Internet), LAN (Local Area Network), Wireless LAN (Wireless Local Area Network), WAN (Wide Area Network), PAN (Personal Area Network), RF (Radio Frequency), Bluetooth (Bluetooth) network, NFC (Near- Field Communication) network, satellite broadcasting network, analog broadcasting network, DMB (Digital Multimedia Broadcasting) network, etc., but is not limited thereto.

Figure 2 is a hardware configuration diagram of a computing device according to an embodiment of the present invention.

Referring to FIG. 2, the computing device 100 according to an embodiment of the present invention includes one or more processors 110 and a memory 120 that loads a computer program 151 executed by the processor 110. , it may include a bus 130, a communication interface 140, and a storage 150 that stores a computer program 151. Here, only components related to the embodiment of the present invention are shown in Figure 2. Accordingly, anyone skilled in the art to which the present invention pertains will know that other general-purpose components may be included in addition to the components shown in FIG. 2.

The processor 110 controls the overall operation of each component of the computing device 100. The processor 110 may be composed of one or more cores, and may include a central processing unit (CPU), a general purpose graphics processing unit (GPGPU), and a tensor processing unit (TPU) of the computing device. unit) may include a processor for data analysis and deep learning. Alternatively, it may be configured to include any type of processor well known in the art of the present invention.

Additionally, the processor 110 may perform operations on at least one application or program for executing methods according to embodiments of the present invention, and the computing device 100 may include one or more processors.

In various embodiments, the processor 110 includes random access memory (RAM) (not shown) and read memory (ROM) that temporarily and/or permanently store signals (or data) processed within the processor 110. -Only Memory, not shown) may be further included. Additionally, the processor 110 may be implemented in the form of a system on chip (SoC) that includes at least one of a graphics processing unit, RAM, and ROM.

Memory 120 stores various data, commands and/or information. Memory 120 may load a computer program 151 from storage 150 to execute methods/operations according to various embodiments of the present invention. When the computer program 151 is loaded into the memory 120, the processor 110 can perform the method/operation by executing one or more instructions constituting the computer program 151. The memory 120 may be implemented as a volatile memory such as RAM, but the technical scope of the present invention is not limited thereto.

Bus 130 provides communication functionality between components of computing device 100. The bus 130 may be implemented as various types of buses, such as an address bus, a data bus, and a control bus.

The communication interface 140 supports wired and wireless Internet communication of the computing device 100. Additionally, the communication interface 140 may support various communication methods other than Internet communication. To this end, the communication interface 140 may be configured to include a communication module well known in the technical field of the present invention. In some embodiments, communication interface 140 may be omitted.

Storage 150 may store the computer program 151 non-temporarily. When performing a process according to an embodiment of the present invention through the computing device 100, the storage 150 may store various information necessary to provide services or perform analysis according to the disclosed embodiment.

The storage 150 is a non-volatile memory such as Read Only Memory (ROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, a hard disk, a removable disk, or a device well known in the art to which the present invention pertains. It may be configured to include any known type of computer-readable recording medium.

The computer program 151, when loaded into the memory 120, may include one or more instructions that cause the processor 110 to perform methods/operations according to various embodiments of the present invention. That is, the processor 110 can perform the method/operation according to various embodiments of the present invention by executing the one or more instructions.

In one embodiment, computer program 151 may include one or more instructions to perform various methods related to various tasks related to training a neural network model.

The steps of the method or algorithm described in connection with embodiments of the present invention may be implemented directly in hardware, implemented as a software module executed by hardware, or a combination thereof. The software module may be RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash Memory, hard disk, removable disk, CD-ROM, or It may reside on any type of computer-readable recording medium well known in the art to which the present invention pertains.

The components of the present invention may be implemented as a program (or application) and stored in a medium in order to be executed in conjunction with a hardware computer. Components of the invention may be implemented as software programming or software elements, and similarly, embodiments may include various algorithms implemented as combinations of data structures, processes, routines or other programming constructs, such as C, C++, , may be implemented in a programming or scripting language such as Java, assembler, etc. Functional aspects may be implemented as algorithms running on one or more processors.

3 to 5 are flowcharts illustrating an example of a method for detecting defective equipment based on a pattern of a wafer map according to an embodiment of the present invention.

Referring to FIG. 3, the computing device 100 may recognize a specific wafer map group that includes more than a preset number of wafer maps classified into predefined defective patterns (S110).

Specifically, the computing device 100 may classify each pattern of wafer maps obtained from process equipment in advance and recognize wafer maps classified as defective patterns among the classified patterns. Additionally, the computing device 100 may recognize the wafer map group to which each of the wafer maps classified as defective patterns belongs. Additionally, the computing device 100 may recognize a specific wafer map group that includes more than a preset number of wafer maps classified as defective patterns.

Generally, in the case of wafer processing, it is produced in lots (LOT) containing about 25 wafers. In other words, 25 wafers included in one lot are produced using the same process and the same equipment. Therefore, wafers included in one lot are likely to have the same defect pattern, and if more than a preset number of wafer maps included in one lot are classified as defective, it indicates that there is a problem with the process or equipment related to that lot. It can be figured out. The unit, group, or bundle of wafer maps included in such a lot unit is referred to as a wafer map group in the present invention.

In one embodiment, the computing device 100 may collect a plurality of wafer maps produced in the past and including defective wafer maps in production order before recognizing a specific wafer map group. Additionally, the computing device 100 may generate a plurality of wafer map groups by grouping the plurality of wafer maps into preset units. Additionally, the computing device 100 may classify patterns of a plurality of wafer maps included in each of the plurality of wafer map groups.

In one embodiment, the computing device 100 may use a classification model to classify patterns of wafer maps included in each of a plurality of wafer map groups.

Specifically, the computing device 100 may acquire a plurality of binary images by binarizing a plurality of wafer maps and adding outlines. Additionally, the computing device 100 may recognize the pattern of each of the plurality of binary images. Additionally, the computing device 100 may define a plurality of classification patterns for classifying the wafer map based on the patterns of each of the plurality of binary images. Additionally, the computing device 100 may learn a classification model for classifying patterns in the wafer map based on a plurality of binary images and a plurality of classification patterns. Additionally, the computing device 100 may classify patterns of the plurality of wafer maps by inputting the plurality of wafer maps into the classification model. Here, when a classification model receives a specific binary image obtained by binarizing a specific wafer map to classify a pattern, the classification model may be trained to output a score value for each class corresponding to each of a plurality of classification patterns.

In one embodiment, computing device 100 may update a classification model.

Specifically, the computing device 100 may obtain classification results for each of the plurality of wafer maps from a pre-trained classification model to classify the plurality of wafer maps. Additionally, the computing device 100 may recognize a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value or the classified pattern is determined to be an error. Additionally, the computing device 100 may acquire a normal pattern corresponding to a specific classification result. Additionally, the computing device 100 may retrain the classifier included in the classification model by labeling the wafer map and the normal pattern corresponding to the specific classification result.

When the computing device 100 recognizes a specific wafer map group including a preset number or more of wafer maps classified as defective patterns, the computing device 100 may recognize first process information related to the production of the wafer map included in the specific wafer map group. There is (S120).

Specifically, the computing device 100 may collect a plurality of first process names corresponding to a specific wafer map group. Additionally, the computing device 100 may collect equipment names corresponding to each of the plurality of first process names. For example, the computing device 100 may recognize product codes of wafer maps included in a specific wafer map group. Additionally, the computing device 100 can use the product code to recognize which process and equipment the wafer maps were produced with. That is, the process information of the present invention may have a structure such as a plurality of process names and a plurality of equipment names belonging to each of the plurality of process names.

When the computing device 100 recognizes the first process information, it may collect second process information related to the production of other wafer maps corresponding to the first process information (S130). Here, the second process information may include data classified as a defective pattern and data classified as a normal pattern related to a specific wafer map group.

Specifically, referring to FIG. 4, the computing device 100 may recognize product codes of wafer maps included in a specific wafer map group (S131). Additionally, the computing device 100 may recognize other wafer maps produced through the same process as the wafer map included in a specific wafer map group, based on the product code (S132). Additionally, the computing device 100 may collect a plurality of second process names corresponding to different wafer maps (S133). And, the computing device 100 may collect a plurality of equipment names corresponding to each of the plurality of second process names (S134).

In various embodiments, when collecting second process information, the computing device 100 may collect a plurality of second process names and a plurality of equipment names corresponding to each of the plurality of second process names by dividing them into normal and defective. You can.

That is, the computing device 100 of the present invention provides various data (i.e., second process) related to wafer maps produced using the same process and equipment as the wafer production unit (e.g., lot) corresponding to a specific wafer map group. information) can be collected.

Referring again to FIG. 3, when the computing device 100 recognizes the first process information and the second process information, it detects defective equipment that causes defects in the wafer map based on the first process information and the second process information. You can do it (S140).

Specifically, referring to FIG. 5, the computing device 100 may use a group corresponding to the number of overlaps among the plurality of first process names included in the first process information and the plurality of second process names included in the second process information. A set number of higher process names can be recognized (S141).

For example, a specific wafer map group containing a preset number or more of wafer maps classified as defective patterns may be produced in the first process, second process, third process, fourth process, and fifth process, and other wafer maps may be produced in the first process, second process, third process, fourth process, and fifth process. A map can be produced through the 2nd process, 3rd process, 4th process, 6th process, and 7th process, and another wafer map can be produced by the 8th process, 9th process, 1st process, and 4th process. You can. There may be numerous processes used in the production of wafer maps, and the computing device 100 collects process information on wafer maps produced using any one of a plurality of processes used in the production of a specific wafer map group, and here Among the process names included, the higher process name can be recognized according to the number of overlaps.

Additionally, the computing device 100 may recognize each of a plurality of equipment names used in each of a preset number of upper process names (S142).

For example, if the preset number of upper process names is the first process, the second process, and the third process, the first equipment, second equipment, and third equipment used in the first process are recognized, and the second process is used in the second process. By recognizing the second equipment, third equipment, and fourth equipment used, the first equipment, second equipment, and fifth equipment used in the third process can be recognized.

Then, the computing device 100 may detect defective equipment by inputting each of the plurality of equipment names into the defective equipment detection model (S143).

In the present invention, a defective equipment detection model can be pre-trained to detect defective equipment based on the defective probability of a wafer map produced using equipment corresponding to a plurality of equipment names. For example, the computing device 100 creates a tree with equipment corresponding to the process used to produce a wafer map with a defect pattern, and uses the number of defects when the wafer map is produced using each equipment. A defective equipment detection model can be trained. For example, a defective equipment detection model is a decision tree that can be learned to determine which of at least two devices is most likely to have caused the defect.

Figures 6 and 7 are diagrams for explaining an example of a wafer map pattern and a method of learning a model for classifying the pattern of the wafer map according to an embodiment of the present invention.

According to one embodiment of the present invention, the computing device 100 may acquire a plurality of wafer maps from a plurality of process facilities. Additionally, the computing device 100 may acquire a plurality of binary images by binarizing a plurality of wafer maps and adding outlines.

In the present invention, a binary image is an image in which each pixel constituting the image is divided into 0 (black) and 255 (white) or 0 and 1, where the pixel value of a normal pixel is 0 and the pixel value of a defective pixel is 0. may be an image consisting of 255 or 1, but is not limited thereto. Meanwhile, the outline added to the binary image can be used by the computing device 100 to define a classification pattern related to the outline.

For example, referring to FIG. 6, when the wafer map as shown in (a) of FIG. 6 is acquired, the computing device 100 converts the wafer map into a binary image as shown in (b) of FIG. 6. It can be converted to .

When the computing device 100 according to one embodiment acquires a plurality of wafer maps, whether the number of the plurality of binary images corresponds to the preset number of images (for example, 10,000) for training a classification model. can be recognized. Additionally, the computing device 100 may adjust the number of binary images depending on whether they correspond to a preset number of images for learning a classification model.

Specifically, the computing device 100 may recognize the number of binary images corresponding to each of a plurality of classification patterns. Additionally, the computing device 100 may determine the number of training images for training a classification model based on the number of binary images corresponding to each of the plurality of classification patterns.

For example, the computing device 100 may determine the average value of the number of binary images corresponding to each of a plurality of classification patterns as the number of training images for training a classification model.

For example, if the number of binary images corresponding to the first pattern is 1000, the number of binary images corresponding to the second pattern is 2000, and the number of binary images corresponding to the third pattern is 1500, each number The average value of 1500 can be determined as the number of images for learning.

When the computing device 100 determines the number of training images for training a model, the number of binary images corresponding to each of the plurality of classification patterns corresponds to the number of training images. The number can be adjusted.

For example, the computing device 100 may recognize the first pattern corresponding to the number of binary images that is less than a preset number than the number of images for training. Additionally, the computing device 100 may perform data augmentation based on the binary image corresponding to the first pattern so that the number of binary images corresponding to the first pattern corresponds to the number of images for learning.

Additionally, the computing device 100 may recognize a second pattern corresponding to the number of binary images that is a preset number or more than the number of training images. Additionally, the computing device 100 may perform sampling on the binary image corresponding to the second pattern so that the number of binary images corresponding to the second pattern corresponds to the number of training images.

For example, in a state where 1500 is determined as the number of images for learning, when the number of binary images corresponding to the first pattern is 1000, the computing device 100 augments data based on the binary image corresponding to the first pattern. The number of binary images corresponding to the first pattern can be adjusted to 1500. Additionally, when the number of binary images corresponding to the second pattern is 2000, the computing device 100 may sample the binary images corresponding to the second pattern and adjust the number of binary images corresponding to the second pattern to 1500. .

Accordingly, the computing device 100 of the present invention can generate a uniform number of learning data for each plurality of patterns, thereby increasing the accuracy of the classification model. Additionally, the computing device 100 can save resources used to train a classification model.

In one embodiment, when the computing device 100 acquires a plurality of binary images, it may recognize the pattern of each of the plurality of binary images.

Specifically, the computing device 100 may recognize a plurality of defect points in each of a plurality of binary images. Additionally, the computing device 100 may perform primary clustering on defect points to generate at least one defect point cluster for each of the plurality of binary images.

For example, the computing device 100 may extract features about defect points included in each of a plurality of binary images. Here, the characteristics of the defect point may include characteristics such as location (eg, coordinates), size, and shape of the defect point.

The computing device 100 may perform primary clustering by inputting the extracted features into a clustering algorithm. The clustering algorithm can divide defect points with similar characteristics into groups (clusters) and create at least one defect point cluster. For example, the clustering algorithm may include at least one of K-means, DBSCAN, and Hierarchical clustering.

Meanwhile, when the computing device 100 generates at least one defect point cluster, each of the plurality of binary images is based on the location of the at least one defect point cluster for each of the plurality of binary images and the shape of the at least one defect point cluster. Patterns can be recognized.

In one embodiment, when the computing device 100 recognizes the pattern of each of the plurality of binary images, it may define a plurality of classification patterns for classifying the wafer map based on the pattern of each of the plurality of binary images.

Specifically, the computing device 100 may perform secondary clustering on the patterns of each of the plurality of binary images to generate at least one pattern cluster for each pattern of the plurality of binary images.

For example, the computing device 100 may extract features for patterns of each of a plurality of binary images. Here, the characteristics of the pattern may include characteristics such as pattern location (eg, coordinates), size, and shape.

The computing device 100 may perform secondary clustering by inputting the extracted features into a clustering algorithm. The clustering algorithm can divide defects with similar characteristics into groups (clusters) and create at least one pattern cluster. For example, the clustering algorithm may include at least one of K-means, DBSCAN, and Hierarchical clustering.

Meanwhile, the computing device 100 may define a specific pattern corresponding to a specific cluster including a preset number or more of binary images among at least one pattern cluster as any one pattern included in a plurality of classification patterns.

For example, referring to Figure 7, an example of a classification pattern defined based on a binary image is shown.

For example, the wafer map shown in (a) of FIG. 7 is a center pattern, which may be a defective pattern in which defects are observed in the central area.

The wafer map shown in (b) of FIG. 7 is a donut pattern, where the central area is a good product and may be a defective pattern in which defects are observed in a ring shape (i.e., donut shape) surrounding the wafer.

The wafer map shown in (c) of FIG. 7 is a local pattern, which does not include corner areas and may be a defective pattern in which defects are observed in the form of local clusters.

The wafer map shown in (d) of FIG. 7 is an edge_local pattern, which may be a defective pattern in which defects are observed in the form of local clusters while including corner areas.

The wafer map shown in (e) of FIG. 7 is an Edge_Ring pattern, which may be a defect pattern in which defects in more than 75% of the corner area are observed to be continuously connected.

The wafer map shown in (f) of FIG. 7 is a scratch pattern, which may be a defective pattern in which defects are observed across a linear or curved pattern.

The wafer map shown in (g) of FIG. 7 is a random pattern, and may be a defective pattern in which defects are observed in a random form.

The wafer map shown in (h) of FIG. 7 is a non-pattern (None_pattern), which may be a pattern in which most products are good and no defective patterns are visible.

The pattern of the wafer map described with reference to FIG. 7 is only an example to aid understanding of the present invention, and is not limited thereto, and may include more diverse patterns.

According to various embodiments of the present invention, each of the eight patterns shown in FIG. 7 may be mapped to a specific part of process equipment or a specific process step. For example, wafer maps classified as similar patterns are likely to have occurred due to the same cause (defects in specific parts or errors in specific process steps), so quality improvement measures can be performed for those patterns.

That is, when the computing device 100 acquires the wafer map, it classifies it as any one of the 13 patterns shown in FIG. 9, and selects a specific part or specific process step corresponding to the classified pattern to the user terminal 200. can be provided. In this case, the user can improve productivity by taking action on the relevant part or process step in a timely manner.

In one embodiment, when a plurality of classification patterns are defined, the computing device 100 may learn a classification model for classifying the pattern of the wafer map based on the plurality of binary images and the plurality of classification patterns.

When receiving a specific binary image obtained by binarizing a specific wafer map to classify the pattern of the present invention, it can be learned to output a score value for each class corresponding to each of a plurality of classification patterns.

Specifically, the classification model includes a first sub-model for extracting the first feature for the input image, and a second sub-model for outputting a score value for each class corresponding to each of the plurality of classification patterns predefined based on the first feature. Can include submodels. Here, the second sub-model may recognize the similarity between the first feature and the second feature of the image corresponding to each of the plurality of classification patterns, and output a score value proportional to the similarity.

In one embodiment, the computing device 100 may obtain a wafer map from the user terminal 200 or a process facility when learning of the classification model is completed. In this case, the computing device 100 may input the wafer map (specifically, a binary image obtained by binarizing the wafer map) into a pre-trained classification model. Additionally, the computing device 100 may obtain a classification result (specifically, a score value for each class) for the wafer map input from the classification model.

If the input wafer map is classified as a defective pattern rather than a normal one in the classification results, the computing device 100 may transmit the corresponding classification information to the user terminal 200, causing the processing equipment to take action in a timely manner. .

In various embodiments, the computing device 100 may perform additional classification when the input wafer map is classified as similar to each of two different patterns in the results output from the classification model.

Specifically, the computing device 100 may input a wafer map into a pre-trained classification model and obtain a score value for each class corresponding to each of a plurality of predefined classification patterns. In this case, the computing device 100 may select a preset number of patterns in order of increasing score value for each class. Additionally, the computing device 100 may calculate a difference value between the first score value of the first pattern and the second score value of the second pattern included in the preset number of patterns. In addition, when the difference value is smaller than a preset size, the computing device 100 inputs the wafer map to a pre-trained decision-making model to output one of the first pattern and the second pattern, Decision-making information can be obtained.

For example, when the patterns are completely identical, the computing device 100 sets the score value to 1 point, and when the first score value of the first pattern is 0.7 and the second score value of the second pattern is 0.67, The difference value of 0.03 between the first score value and the second score value may be recognized as being smaller than the preset size of 0.05. In this case, the computing device 100 may input the wafer map into a pre-trained decision-making model to obtain decision-making information about a specific pattern, either the first pattern or the second pattern.

The pre-trained decision-making model of the present invention may be pre-trained based on a learning wafer map and learning data labeled with classification patterns in each of the learning wafer maps.

Specifically, a pre-trained decision-making model is trained to decide on one of two patterns and can output a result with higher accuracy than a model that classifies it as one of a plurality of patterns. That is, the pre-trained decision-making model of the present invention may be a binary classification model.

Accordingly, the computing device 100 of the present invention can perform more accurate pattern classification for the wafer map.

In an additional embodiment, the computing device 100 may perform reclassification when the score value for each pattern (or class) for the wafer map input from the result output from the classification model is less than a preset value.

Specifically, the computing device 100 may input a wafer map into a pre-trained classification model and obtain a score value for each class corresponding to each of a plurality of predefined classification patterns. In this case, the computing device 100 may select a preset number of patterns in order of increasing score value for each class.

Meanwhile, if the largest score value for each class is less than a preset value, the computing device 100 may obtain a classification result by re-entering the wafer map into the pre-trained classification model.

For example, the computing device 100 determines that if the highest score value is less than 0.5 while the score value is set to 1 when the complete patterns are the same, there is a high possibility that it will not be classified as the pattern, and displays the corresponding wafer map image. This can be re-entered into the classification model.

Additionally, if the score value for each pattern (or class) is less than a preset value in the results obtained through reclassification, the computing device 100 recognizes the wafer map as a special case and sends information about the wafer map to the user terminal. It can be sent to (200).

Accordingly, the computing device 100 of the present invention can result in rapid quality improvement measures for wafer map patterns in special cases.

8 and 9 are flowcharts illustrating an example of a method for learning a model for classifying patterns of a wafer map according to an embodiment of the present invention.

Referring to FIG. 8, the computing device 100 may acquire a plurality of wafer maps from a plurality of process facilities (S210). For example, the computing device 100 may obtain a plurality of wafer maps from an external server 300 related to process equipment.

The computing device 100 may learn a classification model for classifying patterns of wafer maps based on a plurality of wafer maps (S220). Then, the computing device 100 may obtain a classification result by inputting a wafer map to classify the pattern into the learned classification model (S230).

The computing device 100 may recognize a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value or the classified pattern is determined to be an error (S240).

For example, the computing device 100 may recognize a specific classification result corresponding to the wafer map when the probability of corresponding to the classified pattern is 50% or less (that is, the score value is 0.5 or less). For another example, the computing device 100 may obtain a specific classification result determined to be an error by monitoring by an administrator.

The computing device 100 may acquire a normal pattern corresponding to a specific classification result (S250). Here, the normal pattern does not mean that the wafer map is not defective, but may mean a pattern in which the wafer map is classified as normal.

Specifically, referring to FIG. 9 , the computing device 100 may generate a plurality of classifiers by duplicating a classifier among the feature extraction layers and classifiers that constitute the learned classification model (S251). Additionally, the computing device 100 may obtain a plurality of classification results by inputting features extracted from the wafer map corresponding to a specific classification result by the feature extraction layer into a plurality of classifiers (S252). Additionally, the computing device 100 may recognize the pattern corresponding to the result with the greatest number of mutual overlaps among the plurality of classification results as a normal pattern (S253).

For example, assuming that there are a first classifier, a second classifier, a third classifier, a fourth classifier, and a fifth classifier as the plurality of classifiers, if features extracted from the wafer map corresponding to a specific classification result are input into the plurality of classifiers, , the first classifier classifies the input features using the first pattern, the second classifier classifies the input features using the first pattern, and the third classifier classifies the input features using the first pattern. And, the fourth classifier may classify the input features into a first pattern, and the fifth classifier may classify the input features into a second pattern. In this case, the computing device 100 may recognize the first pattern, which is the result with the largest number of mutual overlaps, as the normal pattern of the wafer map.

Referring again to FIG. 8, the computing device 100 may retrain the classifier included in the classification model by labeling the wafer map and normal pattern corresponding to a specific classification result (S260).

Therefore, the computing device 100 of the present invention automatically determines a normal classification result for a wafer map with incorrect classification, labels it with the wafer map, and retrains the classification model, thereby improving the accuracy of the wafer map classification model. .

10 and 11 are flowcharts illustrating an example of a method for detecting anomalies in process equipment by integrating a plurality of anomaly detection techniques according to an embodiment of the present invention.

Referring to FIG. 10, the computing device 100 may collect bin data, PCM data, a plurality of wafer maps, and FDC data collected from process equipment (S310).

The computing device 100 may extract a preset number of specific bin data in order of high defect rate based on the bin data (S320).

In the present invention, bin data may refer to data classified by preset conditions for wafers for which production has been completed (for example, in the case of DRAM, a wafer map group grouped by speed or lot). Additionally, bin data may include information about the defect rate (or yield) of wafers classified according to preset conditions.

That is, the computing device 100 can recognize the defect rate of each of a plurality of wafer map groups and individual wafer maps based on bin data. Additionally, the computing device 100 may extract a preset number of specific bin data in order of high defect rate.

In one embodiment, the computing device 100 produces a plurality of wafer maps including defective wafer maps produced in the past before recognizing the defect rate of each of the plurality of wafer map groups and individual wafer maps based on bin data. They can be collected in order. Additionally, the computing device 100 may generate a plurality of wafer map groups by grouping the plurality of wafer maps into preset units. Additionally, the computing device 100 may classify patterns of a plurality of wafer maps included in each of the plurality of wafer map groups.

The computing device 100 may extract a specific device in which a specification defect or a control defect has occurred based on the PCM data (S330).

In the present invention, PCM data may include information on whether the wafer is defective using a test pattern generated according to the type or characteristics of the wafer. For example, PCM data is obtained by testing a sample of each individual device on a wafer, and may include information on whether each individual device is defective. Additionally, PCM data may include test results such as Out of Specification (OOS) or Out of Control (OOC) for each individual device.

That is, the computing device 100 may recognize individual devices included in the wafer map corresponding to a preset number of bin data based on PCM data. Additionally, the computing device 100 may obtain test results for individual devices and extract specific devices that have specification defects or control defects based on the test results.

The computing device 100 may classify the patterns of each of the plurality of wafer maps based on the plurality of wafer maps and extract at least one specific defective device corresponding to the classified pattern (S340).

Specifically, the computing device 100 may recognize a specific wafer map group that includes a preset number or more of wafer maps classified into predefined defective patterns. Additionally, the computing device 100 may recognize first process information related to the production of a wafer map included in a specific wafer map group. Additionally, the computing device 100 may collect second process information related to the production of other wafer maps corresponding to the first process information. Additionally, the computing device 100 may extract defective equipment that causes defects in the wafer map based on the first process information and the second process information.

Hereinafter, a description of the method by which the computing device 100 extracts defective equipment using process information of the wafer map has been described above with reference to FIGS. 3 to 5, and redundant description will be omitted.

The computing device 100 may extract defects related to abnormal operation of the process equipment based on the FDC data (S350).

In the present invention, FDC data may refer to data resulting from early detection and classification of abnormal situations by monitoring the operating status and performance of process equipment. For example, the computing device 100 may detect abnormal operation of process equipment using process sensor data, and related data may be used to detect abnormalities in process equipment.

In one embodiment, the computing device 100 may detect abnormal operation of process equipment using a deep learning model.

Specifically, the computing device 100 may acquire process sensor data and prior knowledge data corresponding to the process sensor data. Additionally, the computing device 100 may utilize a deep learning model to generate reconstructed process sensor data corresponding to process sensor data. Additionally, the computing device 100 may calculate a reconstruction rate error based on process sensor data and reconstruction process sensor data. Additionally, the computing device 100 may detect abnormal operation based on comparison of the reconstruction rate error and the reference threshold.

The method by which the computing device 100 of the present invention detects abnormal operation of process equipment using a deep learning model is specifically described in Registered Patent Publication No. 10-2523458, which is incorporated by reference in its entirety in this application.

Meanwhile, the computing device 100 may provide integrated results extracted based on bin data, PCM data, multiple wafer maps, and FDC data (S360).

Specifically, referring to FIG. 11, the computing device 100 configures preset conditions corresponding to each of the bin data, PCM data, a plurality of wafer maps, and FDC data, and each of the bin data, PCM data, a plurality of wafer maps, and FDC data. The extracted results can be compared based on (S361). Then, the computing device 100 may provide visualized information corresponding to each of bin data, PCM data, a plurality of wafer maps, and FDC data based on the comparison result (S362).

For example, in the results extracted based on bin data, the computing device 100 displays red if the overall yield of the lot is less than 90%, orange if it is 90% or more and less than 95%, and green if it is 95% or more. You can. Additionally, the computing device 100 may display the results extracted based on PCM data in red if both OOS and OOC occurred or if OOS occurred, in orange if only OOC occurred, or in green if neither occurred. In addition, the computing device 100 displays red when the yield is less than 90% in the results extracted based on a plurality of wafer maps, red when the yield is more than 90% and a specific pattern appears, or random when the yield is more than 90% and less than 95%. If a pattern appears, it can be displayed in orange, and if the yield is over 95% and a random pattern or non-pattern appears, it can be displayed in green. In addition, the computing device 100 may display red if an abnormality occurred in the results extracted based on the FDC data and was determined to be defective, orange if an abnormality occurred but no wafers were judged defective, and green if no abnormality occurred. there is.

In one embodiment, the computing device 100 simultaneously provides information visualized (e.g., displayed in different colors depending on conditions) for each data to the user to enable rapid integrated analysis and further reduce wafer quality control costs. You can.

Figure 12 is a schematic diagram showing one or more network functions related to one embodiment of the present invention.

Throughout this specification, artificial intelligence model, neural network, network function, and neural network may be used with the same meaning. A neural network can generally consist of a set of interconnected computational units, which can be referred to as “nodes”. These “nodes” may also be referred to as “neurons.”

A deep neural network (DNN) may refer to a neural network that includes multiple hidden layers in addition to the input layer and output layer. Deep neural networks allow you to identify latent structures in data. In other words, it is possible to identify the potential structure of a photo, text, video, voice, or music (e.g., what object is in the photo, what the content and emotion of the text are, what the content and emotion of the voice are, etc.) . Deep neural networks include convolutional neural networks (CNN), recurrent neural networks (RNN), auto encoders, generative adversarial networks (GAN), and restricted Boltzmann machines (RBM). machine), deep belief network (DBN), Q network, U network, Siamese network, etc. The description of the deep neural network described above is only an example and the present invention is not limited thereto.

A neural network may be trained in at least one of supervised learning, unsupervised learning, and semi-supervised learning. Learning of a neural network is intended to minimize errors in output. In neural network learning, learning data is repeatedly input into the neural network, the output of the neural network and the error of the target for the learning data are calculated, and the error of the neural network is transferred from the output layer of the neural network to the input layer in the direction of reducing the error. This is the process of updating the weight of each node in the neural network through backpropagation. In the case of teacher learning, learning data in which the correct answer is labeled for each learning data is used (i.e., labeled learning data), and in the case of non-teacher learning, the correct answer may not be labeled in each learning data. That is, for example, in the case of teacher learning regarding data classification, the learning data may be data in which each learning data is labeled with a category. Labeled training data is input to the neural network, and the error can be calculated by comparing the output (category) of the neural network and the label of the training data. As another example, in the case of non-teachable learning for data classification, the error can be calculated by comparing the input training data with the neural network output. The calculated error is back-propagated in the neural network in the reverse direction (i.e., from the output layer to the input layer), and the connection weight of each node in each layer of the neural network can be updated according to back-propagation. The amount of change in the connection weight of each updated node may be determined according to the learning rate. The neural network's calculation of input data and backpropagation of errors can constitute a learning cycle (epoch). The learning rate may be applied differently depending on the number of repetitions of the learning cycle of the neural network. For example, in the early stages of neural network training, a high learning rate can be used to increase efficiency by allowing the neural network to quickly achieve a certain level of performance, and in the later stages of training, a low learning rate can be used to increase accuracy.

In the learning of neural networks, the training data can generally be a subset of real data (i.e., the data to be processed using the learned neural network), and thus the error for the training data is reduced, but the error for the real data is reduced. There may be an incremental learning cycle. Overfitting is a phenomenon in which errors in actual data increase due to excessive learning on training data. For example, a phenomenon in which a neural network that learned a cat by showing a yellow cat fails to recognize that it is a cat when it sees a non-yellow cat may be a type of overfitting. Overfitting can cause errors in machine learning algorithms to increase. To prevent such overfitting, various optimization methods can be used. To prevent overfitting, methods such as increasing the learning data, regularization, or dropout, which omits some of the network nodes during the learning process, can be applied.

The steps of the method or algorithm described in connection with embodiments of the present invention may be implemented directly in hardware, implemented as a software module executed by hardware, or a combination thereof. The software module may be RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash Memory, hard disk, removable disk, CD-ROM, or It may reside on any type of computer-readable recording medium well known in the art to which the present invention pertains.

The components of the present invention may be implemented as a program (or application) and stored in a medium in order to be executed in conjunction with a hardware computer. Components of the invention may be implemented as software programming or software elements, and similarly, embodiments may include various algorithms implemented as combinations of data structures, processes, routines or other programming constructs, such as C, C++, , may be implemented in a programming or scripting language such as Java, assembler, etc. Functional aspects may be implemented as algorithms running on one or more processors.

Those skilled in the art will understand that various illustrative logical blocks, modules, processors, means, circuits and algorithm steps described in connection with the embodiments disclosed herein can be used in electronic hardware, (for convenience) It will be understood that the implementation may be implemented by various forms of program or design code (referred to herein as “software”) or a combination of both. To clearly illustrate this interoperability of hardware and software, various illustrative components, blocks, modules, circuits and steps have been described above generally with respect to their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. A person skilled in the art may implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the present invention.

The various embodiments presented herein may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term “article of manufacture” includes a computer program, carrier, or media accessible from any computer-readable device. For example, computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, etc.), optical disks (e.g., CDs, DVDs, etc.), smart cards, and flash memory. Includes, but is not limited to, devices (e.g., EEPROM, cards, sticks, key drives, etc.). Additionally, various storage media presented herein include one or more devices and/or other machine-readable media for storing information. The term “machine-readable media” includes, but is not limited to, wireless channels and various other media capable of storing, retaining, and/or transmitting instruction(s) and/or data.

It is to be understood that the specific order or hierarchy of steps in the processes presented is an example of illustrative approaches. It is to be understood that the specific order or hierarchy of steps in processes may be rearranged within the scope of the present invention, based on design priorities. The appended method claims present elements of the various steps in a sample order but are not meant to be limited to the particular order or hierarchy presented.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims (10)

A method performed by a computing device comprising at least one processor, comprising:
Collecting bin data, PCM (Process Control Monitoring) data, multiple wafer maps, and FDC (Fault Detection and Classification) data collected from process equipment;
Collecting a plurality of wafer maps produced in the past and including defective wafer maps in production order, and grouping the plurality of wafer maps into preset units to create a plurality of wafer map groups;
Classifying patterns of each of the plurality of wafer maps included in each of the plurality of wafer map groups;
Extracting at least one specific defective device corresponding to the classified pattern;
Recognizing the defect rate of each of a plurality of wafer map groups and individual wafer maps based on the bin data;
extracting the preset number of specific bin data in order of the defect rate from highest to highest;
Extracting a specific device with specification defects or control defects based on the PCM data;
Classifying patterns in each of the plurality of wafer maps based on the plurality of wafer maps and extracting at least one specific defective device corresponding to the classified pattern;
extracting whether or not there is a defect in abnormal operation of the process equipment based on the FDC data; and
integrating and providing extracted results based on each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data;
Including,
The step of extracting at least one specific defective device includes:
Recognizing a specific wafer map group including a preset number or more of wafer maps classified into predefined defective patterns;
Recognizing first process information related to the production of a wafer map included in the specific wafer map group;
collecting second process information related to production of other wafer maps corresponding to the first process information; and
extracting defective equipment that causes defects in the wafer map based on the first process information and the second process information;
Including,
A method of detecting abnormalities in process equipment by integrating multiple abnormality detection techniques.
delete delete ◈Claim 4 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
The step of extracting a specific device with specification defects or control defects based on the PCM data,
Recognizing individual devices included in the wafer map corresponding to the preset number of bin data based on the PCM data; and
Obtaining test results for the individual devices and extracting specific devices that have specification defects or control defects based on the test results;
Including,
A method of detecting abnormalities in process equipment by integrating multiple abnormality detection techniques.
delete ◈Claim 6 was abandoned upon payment of the setup registration fee.◈ According to claim 1,
The step of classifying the patterns of each of the plurality of wafer maps is,
Classifying patterns of a plurality of wafer maps included in each of the plurality of wafer map groups using a pre-learned classification model;
Including,
Recognizing a specific classification result in which the score value corresponding to the classified pattern in the classification result is lower than a preset value or the classified pattern is determined to be an error;
Obtaining a normal pattern corresponding to the specific classification result; and
labeling the normal pattern and a wafer map corresponding to the specific classification result to retrain a classifier included in the classification model;
Containing more,
A method of detecting abnormalities in process equipment by integrating multiple abnormality detection techniques.
According to claim 1,
The step of extracting defects for abnormal operation of the process equipment based on the FDC data,
Obtaining process sensor data and prior knowledge data corresponding to the process sensor data;
Generating reconstruction process sensor data corresponding to the process sensor data using a deep learning model;
calculating a reconstruction rate error based on the process sensor data and the reconstruction process sensor data; and
detecting abnormal operation based on comparison of the reconstruction rate error with a reference threshold;
Including,
A method of detecting abnormalities in process equipment by integrating multiple abnormality detection techniques.
According to claim 1,
The step of integrating and providing extracted results based on each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data,
Results extracted based on preset conditions corresponding to each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data, and each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data. comparing; and
providing visualized information corresponding to each of the bin data, the PCM data, the plurality of wafer maps, and the FDC data based on the comparison result;
Including,
A method of detecting abnormalities in process equipment by integrating multiple abnormality detection techniques.
A memory that stores one or more instructions; and
A processor that executes the one or more instructions stored in the memory
Contains,
The processor executes the one or more instructions,
An apparatus for performing the method of claim 1.
A computer program combined with a computer as hardware and stored on a computer-readable recording medium so as to perform the method of claim 1.