KR102664031B1 - Appratus for boosting input impedance that is robust to parasitic component - Google Patents

Abstract

The present invention relates to an input impedance boosting device. The input impedance boosting device includes an analog-to-digital conversion circuit, an input capacitor connected to the input terminal and a ground line of the analog-to-digital conversion circuit, and having a first shielding metal formed at the bottom, and an analog capacitor. -A feedback capacitor connected to the positive feedback loop of the digital conversion circuit, with a second shielding metal formed at the bottom, and a first shielding metal formed between the input capacitor and the first shielding metal, and connected to both ends of the feedback capacitor. It includes an impedance boosting unit that boosts the input impedance based on the parasitic component and the second parasitic component formed between the feedback capacitor and the second shielding metal.

Description

Input impedance boosting device that is robust against parasitic components {APPRATUS FOR BOOSTING INPUT IMPEDANCE THAT IS ROBUST TO PARASITIC COMPONENT}

The present invention relates to an input impedance boosting device, and more specifically, to a technical idea of increasing the input impedance of a circuit by minimizing the influence of parasitic capacitance components.

In a voltage measurement circuit, input impedance is an important performance indicator required to prevent signal attenuation, and an input impedance boosting circuit based on a positive feedback loop was proposed to boost this input impedance.

In the above-described input impedance boosting circuit, a positive feedback loop is formed between the output and input terminals of the voltage measurement circuit, where the gain of the voltage measurement circuit is 'A', the input impedance of the voltage measurement circuit is 'Z _SEN ', and the input voltage (V The parasitic component occurring at the node to which _IN ) is applied (i.e., the node connected to the input terminal of the voltage measurement circuit) is referred to as 'Z _P ', and the impedance on the positive feedback loop for controlling the feedback current (I _FB ) is referred to as 'Z _FB '. Assuming, the input impedance is defined by the ratio of the input voltage (V _IN ) and the input current (I _IN ), and if there is no positive feedback loop, the input impedance can be expressed as 'Z _P + Z _SEN '.

Here, the positive feedback loop serves to compensate for the input current (I _IN ), and the feedback current (I _FB ) applied to the positive feedback loop is I _FB = I _P + I _SEN (where I _P is Z _P (i.e. , C _P ), the current flowing through I _SEN creates an infinite input impedance under the condition that the current flowing through Z _SEN (i.e., C _SEN ).

The input impedance increased (boosted) by the positive feedback loop can be expressed as Equation 1 below.

[Formula 1]

As can be seen in Equation 1, the positive feedback loop creates a negative capacitance term of (1-A)C _FB (where C _FB is Z _FB ), and the condition of (1-A)C _FB = C _P + C _SEN The input impedance becomes infinite. Additionally, since A is defined as a parameter of the system (or device), the input impedance can be boosted by selecting C _FB of an appropriate value.

In other words, the existing input impedance boosting circuit is a circuit that is sensitive to parasitic components. In addition, while C _SEN , A, C _FB are parameters that can be accurately controlled, C _P is a parameter that is difficult to predict, so if C _P cannot be nullified, the input impedance is limited by the parasitic component C _P .

Accordingly, the existing technology used a method of trimming C _FB to minimize the influence of _CP .

Using this trimming method, the boosted input impedance is determined by the trimming resolution, and in the case of existing technology, C _FB is used as a 9bit C _DAC to achieve an input capacitance of 60fF, i.e. a high input impedance of 200GΩ@1Hz. did.

However, the existing technology for boosting the input impedance using a trimming method has the problem of generating unnecessary area and power consumption due to the 9-bit C _DAC and additional circuit logic for trimming, and increasing circuit complexity.

Korean Patent Publication No. 10-2015-0103843, “Reserva Capacitor”.

J. Lee, G. Lee, H. Kim and S. Cho, "An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback," in IEEE Journal of Solid-State Circuits, vol. 53, no. 8, pp. 2252-2262, Aug. 2018. Y. Park, J. -H. Cha, S.-H. Han, J.-H. Park and S.-J. Kim, “A 3.8-μW/Ch, 15-GΩ Total Input Impedance Chopper Stabilized Amplifier with Dual Positive Feedback Loops and Auto-calibration Scheme,” 2021 Symposium on VLSI Circuits.

The present invention seeks to provide an input impedance boosting device that can reduce the influence of parasitic capacitance components without additional calibration or trimming processes.

In addition, the present invention seeks to provide an input impedance boosting device that can boost input impedance while minimizing the increase in cost due to power consumption and circuit area.

In addition, the present invention seeks to provide an input impedance boosting device that can achieve improved impedance boosting performance compared to existing technologies using a trimming process.

An input impedance boosting device according to an embodiment of the present invention includes an analog-to-digital conversion circuit, an input capacitor connected to the input terminal and ground line of the analog-to-digital conversion circuit, and having a first shielding metal formed at the bottom, and an analog-to-digital conversion circuit. A feedback capacitor connected to the positive feedback loop of the circuit and having a second shielding metal formed at the bottom, and a first parasitic component connected to both ends of the feedback capacitor and formed between the input capacitor and the first shielding metal, and It may include an impedance boosting unit that boosts the input impedance based on a second parasitic component formed between the feedback capacitor and the second shielding metal.

According to one side, the impedance boosting unit may boost the input impedance by copying the first parasitic component and the second parasitic component and adding them to the positive feedback loop.

According to one side, the impedance boosting unit may include a first metal connected to the first terminal of the feedback capacitor, and a third shielding metal formed below the first metal and connected to the second terminal of the feedback capacitor.

According to one side, the first shielding metal and the second shielding metal may each be connected to a ground line.

According to one side, the input impedance boosting device may further include a chopper switch connected to the input terminal of the analog-to-digital conversion circuit.

According to one side, the impedance boosting unit may further include a dummy switch connected to both ends of the feedback capacitor.

According to one side, the impedance boosting unit can boost the input impedance by copying the third parasitic component formed by the chopper switch through a dummy switch and adding it to the positive feedback loop.

According to one side, the dummy switch may be formed in the same size as the chopper switch.

According to one side, the feedback capacitor and the input capacitor may be metal-oxide-metal (MOM) capacitors.

According to one side, the analog-to-digital conversion circuit includes a linear integrator with a linear transconductance cell (linear Gm cell), a quantizer with a body-driven oscillator (body-driven VCO), and a frequency to digital converter (FDC). It may be a continuous-time delta sigma analog-to-digital conversion circuit.

According to one embodiment, the present invention can reduce the influence of parasitic capacitance components without additional calibration or trimming processes.

According to one embodiment, the present invention can boost input impedance while minimizing the increase in cost due to power consumption and circuit area.

According to one embodiment, the present invention can achieve improved impedance boosting performance compared to existing technology using a trimming process.

1 is a diagram for explaining an input impedance boosting device according to an embodiment.
2A to 2C are diagrams for explaining in more detail an input impedance boosting device according to an embodiment.
Figure 3 is a diagram for explaining the linear integrator according to an embodiment in more detail.
Figure 4 is a diagram for explaining in more detail a body driven oscillator according to an embodiment.
FIGS. 5A and 5B are diagrams for explaining performance simulation results of an input impedance boosting device according to an embodiment.

Hereinafter, various embodiments of this document are described with reference to the attached drawings.

The examples and terms used herein are not intended to limit the technology described in this document to a specific embodiment, and should be understood to include various changes, equivalents, and/or substitutes for the embodiments.

In the following description of various embodiments, if a detailed description of a related known function or configuration is judged to unnecessarily obscure the gist of the invention, the detailed description will be omitted.

The terms described below are terms defined in consideration of functions in various embodiments, and may vary depending on the intention or custom of the user or operator. Therefore, the definition should be made based on the contents throughout this specification.

In connection with the description of the drawings, similar reference numbers may be used for similar components.

Singular expressions may include plural expressions, unless the context clearly indicates otherwise.

In this document, expressions such as “A or B” or “at least one of A and/or B” may include all possible combinations of the items listed together.

Expressions such as “first,” “second,” “first,” or “second,” can modify the corresponding components regardless of order or importance and are used to distinguish one component from another. It is only used and does not limit the corresponding components.

When a component (e.g., a first) component is said to be "connected (functionally or communicatively)" or "connected" to another (e.g., second) component, it means that the component is connected to the other component. It may be connected directly to an element or may be connected through another component (e.g., a third component).

In this specification, “configured to” means “suitable for,” “having the ability to,” or “changed to,” depending on the situation, for example, in terms of hardware or software. ," can be used interchangeably with "made to," "capable of," or "designed to."

In some contexts, the expression “a device configured to” may mean that the device is “capable of” working with other devices or components.

For example, the phrase "processor configured (or set) to perform A, B, and C" refers to a processor dedicated to performing the operations (e.g., an embedded processor), or by executing one or more software programs stored on a memory device. , may refer to a general-purpose processor (e.g., CPU or application processor) capable of performing the corresponding operations.

Additionally, the term 'or' means 'inclusive or' rather than 'exclusive or'.

That is, unless otherwise stated or clear from the context, the expression 'x uses a or b' means any of the natural inclusive permutations.

In the above-described specific embodiments, components included in the invention are expressed in singular or plural numbers depending on the specific embodiment presented.

However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the above-described embodiments are not limited to singular or plural components, and even if the components expressed in plural are composed of singular or , Even components expressed as singular may be composed of plural elements.

Meanwhile, in the description of the invention, specific embodiments have been described, but of course, various modifications are possible without departing from the scope of the technical idea implied by the various embodiments.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the claims described below as well as equivalents to these claims.

1 is a diagram for explaining an input impedance boosting device according to an embodiment.

Referring to FIG. 1, the input impedance boosting device 100 according to one embodiment can reduce the influence of parasitic capacitance components without additional calibration or trimming processes.

Additionally, the input impedance boosting device 100 can boost the input impedance while minimizing the increase in cost due to power consumption and circuit area.

Additionally, the input impedance boosting device 100 can achieve improved impedance boosting performance compared to existing technology using a trimming process.

To this end, the input impedance boosting device 100 may include an analog-to-digital conversion circuit (ADC), an input capacitor (C _IN ), a feedback capacitor (C' _IN ), and an impedance boosting unit.

For example, the analog-to-digital conversion circuit (ADC) may be an analog-to-digital conversion circuit with a gain value of '2' or '-2' or a continuous time delta-sigma modulator (CTDSM). .

Specifically, the input capacitor C _IN according to one embodiment is connected to the input terminal and the ground line of the analog-to-digital conversion circuit (ADC), and a first shielding metal 110 may be formed at the bottom.

Additionally, the feedback capacitor C' _IN according to one embodiment may be connected to a positive feedback loop of the delta sigma conversion circuit, and a second shielding metal 120 may be formed below.

For example, the first shielding metal 110 and the second shielding metal 120 may be respectively connected to a ground line and may be formed below the corresponding capacitor to be spaced apart by a gap of a preset size.

Additionally, the input capacitor (C _IN ) and the feedback capacitor (C' _IN ) may be metal-oxide-metal (MOM) capacitors.

The impedance boosting unit according to one embodiment is connected to both ends of the feedback capacitor (C' _IN ), and the first parasitic component 110-1 and the feedback formed between the input capacitor (C _IN ) and the first shielding metal 110. The input impedance may be boosted based on the second parasitic component 120-1 formed between the capacitor C' _IN and the second shielding metal 120.

According to one side, the impedance boosting units 130 and 140 may boost the input impedance by copying the first parasitic component 110-1 and the second parasitic component 120-1 and adding them to a positive feedback loop.

According to one side, the impedance boosting units 130 and 140 are formed on a first metal 140 connected to the first terminal of the feedback capacitor C' _IN , and a lower part of the first metal 140 and the feedback capacitor C' _IN ) may include a third shielding metal 130 connected to the second terminal.

For example, the third shielding metal 130 may be formed below the first metal 140 to be spaced apart by a gap of a preset size.

The input impedance boosting device 100 may further include a chopper switch connected to the input terminal of an analog-to-digital conversion circuit (ADC). In other words, the chopper switch may be provided between the input terminal of the analog-to-digital conversion circuit (ADC) and the node to which the input voltage (V _IN ) is applied.

According to one side, the impedance boosting unit may further include a dummy switch connected to both ends of the feedback capacitor (C' _IN ).

Specifically, the impedance boosting unit may boost the input impedance by copying the third parasitic component formed by the chopper switch through a dummy switch and adding it to the positive feedback loop. For example, the dummy switch may be formed to the same size as the chopper switch.

Meanwhile, the analog-to-digital conversion circuit (ADC) includes a linear integrator with a linear transconductance cell (linear Gm cell), a body-driven oscillator (VCO), and a quantizer with a frequency to digital converter (FDC). It may be a continuous-time delta sigma analog-to-digital conversion device.

Specifically, the linear integrator may generate a first output signal corresponding to the input voltage (V _IN ) based on the operation of a linear transconductance cell that receives a preset input voltage (V _IN ).

Additionally, the quantizer generates a second output signal corresponding to the first output signal based on the operation of the body driving oscillator receiving the first output signal, and generates a second output signal based on the operation of the FDC receiving the second output signal. A digital output code (D _OUT ) corresponding to the signal can be generated.

More specifically, the analog-to-digital conversion circuit (ADC) is a first-order CTDSM consisting of a linear integrator 110 with low-noise characteristics and high linearity characteristics and a quantizer based on a body driven oscillator, and a first-order loop (1 ^st It has high stability characteristics due to the characteristics of the order loop, and at the same time, it can achieve low quantization noise characteristics within the signal bandwidth due to the unique noise characteristics of the VCO-based quantizer.

In other words, the analog-to-digital conversion circuit (ADC) can improve the noise-power efficiency and linearity of the integrator and VCO-based quantizer to maximize key performances such as noise performance, linearity, and bandwidth of the entire system.

According to one side, the analog-to-digital conversion circuit (ADC) may further include a 4-tap FIR filter provided on a delta-sigma feedback loop connecting the input terminal of the linear integrator and the output terminal of the quantizer. You can.

For example, a delta-sigma feedback loop may be a positive feedback loop.

Specifically, the input impedance of the analog-to-digital conversion circuit (ADC) is determined by the input capacitor (C _IN ) provided between the input terminal of the linear integrator 210 and the ground line, and the chopping frequency at the node connected to the input terminal of the linear integrator. ; f _CH ), and in the case of existing devices, the chopping frequency is equal to the frequency fs or is used as fs/2 to prevent aliasing of quantization noise due to chopping (where fs is the sampling frequency).

However, in this case, there is a problem of having a low input impedance of less than 1MΩ due to the high sampling frequency. To solve this, the analog-to-digital conversion circuit (ADC) connects a 4-tap FIR filter on the feedback loop to reduce quantization noise. A notch can be created in .

More specifically, the analog-to-digital conversion circuit (ADC) can prevent aliasing of the quantization noise that appears as chopping by filtering the quantization noise in the frequency band where aliasing occurs through a 4-tap FIR filter.

Additionally, the analog-to-digital conversion circuit (ADC) can increase the input impedance by four times compared to existing devices by using the notch frequency of fs/8 generated through a 4-tap FIR filter as a chopping frequency.

2A to 2C are diagrams for explaining in more detail an input impedance boosting device according to an embodiment.

Referring to FIGS. 2A to 2C, reference numeral 210 illustrates parasitic capacitance components to be considered in the input impedance boosting device, and reference numerals 220 and 230 illustrate the input impedance boosting device according to an embodiment in more detail.

According to reference numeral 210, the input impedance boosting device according to one embodiment uses a method of copying (imitating) the parasitic capacitance component without trimming and adding it to the positive feedback loop in order to minimize the influence of the parasitic capacitance component. To this end, the input impedance The boosting device uses 'C _{P_CH} ', a parasitic capacitor component generated from the chopper switch, and 'C _{P_M-GND} ', a parasitic capacitor component generated from the input capacitor (C _IN ) and the feedback capacitor (C' _IN ), as the main parasitic capacitance. can be considered.

Specifically, the input impedance boosting device can implement infinite impedance when the system gain is '-2' and the feedback capacitor (C' _IN ) satisfies the conditions of Equation 2 below.

[Formula 2]

According to reference numerals 220 and 230, the input impedance boosting device according to one embodiment may use a parasitic replication technique to copy the parasitic capacitance component described above through reference numeral 210.

The input impedance boosting device can form a shielding metal at the bottom of the MOM (metal-oxide-metal) type capacitor (C _IN /C' _IN ) to copy the parasitic capacitance caused by the MOM (metal-oxide-metal) type capacitor (C IN /C' IN). In this case, the parasitic capacitance component 'C _{P_M- GND} ' is defined by the overlap area between the shielding metal and the metal layer of the MOM capacitor and can be easily copied.

In addition, the input impedance boosting device can copy the parasitic capacitance component 'C _{P_CH} ' by using a dummy switch of the same size as the chopper switch. Using the above-described method, the effect of the parasitic capacitor is minimized and the impedance is 70 times that of the existing one. Increased effectiveness can be achieved.

Specifically, the input impedance boosting device includes a chopper switch, an analog-to-digital conversion circuit (ADC) connected to the chopper switch, an input capacitor (C _IN ) on which the first shielding metal 221 is formed, and a positive It may include a feedback capacitor ( _C'IN ) located on the feedback loop and having a second shielding metal 222 formed at the bottom.

In addition, the input impedance boosting device is connected to both ends of the feedback capacitor (C' _IN ), and the first parasitic component 221-1 formed between the input capacitor (C _IN ) and the first shielding metal 221 and the feedback capacitor It may further include an impedance boosting unit that boosts the input impedance based on the second parasitic component 222-1 formed between (C' _IN ) and the second shielding metal 222. To this end, the impedance boosting unit may include a feedback capacitor. It may include a first metal connected to the first terminal of ( _C'IN ) and a third shielding metal 223 formed below the first metal and connected to the second terminal of the feedback capacitor ( _C'IN ).

According to one side, the impedance boosting unit may boost the input impedance by copying the first parasitic component 221-1 and the second parasitic component 222-1 and adding them to the positive feedback loop.

More specifically, the input impedance boosting device includes a first shielding metal 221 and a second shielding metal 222 connected to a ground line at the bottom of each of the MOM capacitors, the input capacitor (C _IN ) and the feedback capacitor (C' _IN ). The parasitic capacitance components 221-1 and 222-1 can be controlled by respectively arranging them.

Here, the parasitic capacitance components (221-1, 222-1), that is, the parasitic capacitance components C _{P_GND1} and C _{P_M- GND2} , may be overlap capacitances generated by each metal layer of the MOM capacitor and each shielding metal. there is.

In other words, the input impedance boosting device can add a metal ground parasitic capacitance component around the feedback capacitor (C' _IN ) to remove (offset) the parasitic effect caused by the parasitic capacitance components (C _{P_ GND1} , C _{P_M- GND2} ). .

In other words, the input impedance boosting device includes a first metal connected to the first terminal of the feedback capacitor (C' _IN ) and a third shielding formed under the first metal and connected to the second terminal of the feedback capacitor (C' _IN ). Parasitic capacitance components (C _{P_ GND1} , C _{P_M- GND2} ) are copied (i.e., C' _{P_ GND )} using an impedance boosting unit containing metal 223. = C' _{P _ GND1} + C' _{P _ GND2} ) and reflecting it in the positive feedback loop, the influence of parasitic capacitance components (C _{P_ GND1} , C _{P_M- GND2} ) can be minimized.

Meanwhile, the impedance boosting unit may further include a dummy switch connected to both ends of the feedback capacitor (C' _IN ) and formed in the same size as the chopper switch, and the third parasitic component formed by the chopper switch (i.e. , C _{P_CH} = C _GS + C _J + C _GD + C _J ) is copied (i.e., C' _{P _CH} ) and reflected in the positive feedback loop, thereby minimizing the influence of the parasitic capacitance component (C _{P_CH} ).

Figure 3 is a diagram for explaining the linear integrator according to one embodiment in more detail.

Referring to FIG. 3, the linear integrator 300 according to an embodiment is the first entity to which the input of the analog-to-digital conversion circuit (ADC) according to an embodiment is applied and plays a major role in determining system noise and linearity. Therefore, it can be designed to have low noise and high linearity.

The linear integrator 300 according to one embodiment _is based on the operation of the linear transconductance cell 310 that receives _the preset input voltages (V _{INN ,} V _INP ) _. First output signals (I _OUTN , I _OUTP ) can be generated.

The linear transconductance cell 310 may include a plurality of operational amplifiers 311 and a plurality of resistors (R _D ) connected to the input terminals of each of the plurality of operational amplifiers (311), and a plurality of resistors (R _D ) Each may be connected to each of the plurality of operational amplifiers 311 through one side end and connected to the power supply voltage (V _DD ) line through the other side end.

Additionally, the linear integrator 300 may further include a DC current source 320 connected to the output terminal of the linear transconductance cell 310.

Meanwhile, the linear integrator 300 may design each of the plurality of operational amplifiers 311 as current reuse operational amplifiers to improve noise power efficiency.

Among the plurality of transistors constituting the plurality of operational amplifiers 311, the input voltage V _INP can be received through the gate terminals of transistors M2 and M4, and the input voltage V _INN can be received through the gate terminals of transistors M1 and M3, Here, transistors M1 to M4 may operate as a transconductance amplifier based on the input voltages V _INN and V _INP .

According to one side, the linear integrator 300 stores input voltages (V _{INN ,} V _INP ) at both ends of a plurality of resistors (R _D ) by unit gain feedback in the linear transconductance cell 310. A current that is copied and changes linearly is generated, and a first output signal corresponding to the change in the generated current can be generated.

Specifically, the linear integrator 300 can generate output currents (I _OUTN , I _OUTP ) by copying the linear current change generated by the linear transconductance cell 310 to the output terminal by the NMOS transistor, Linearity can be maintained because the generated output currents (I _OUTN , I _OUTP ) flow into the load capacitor of the linear integrator 300, where the output currents (I _OUTN , I _OUTP ) are controlled by the load capacitor. It may be converted to a corresponding voltage (i.e., first output signal).

Figure 4 is a diagram for explaining in more detail a body driven oscillator according to an embodiment.

Referring to FIG. 4, the quantizer provided in the analog-to-digital conversion circuit (ADC) generates a second output signal corresponding to the first output signal based on the operation of the body driving oscillator 400 that receives the first output signal output from the linear integrator. A digital output code (D _OUT ) corresponding to the second output signal may be generated based on the operation of the FDC that generates the second output signal and receives the second output signal.

Specifically, in a conventional gate driving oscillator, changes in output frequency occur due to changes in the delay of each inverter delay-cell, and these delay changes are generated by changes in the current of the PMOS transistor.

At this time, the input voltage (V _C ) of the gate driving oscillator is applied to the gate terminal of the PMOS transistor, and the G _m characteristics of the PMOS transistor greatly affect the linearity characteristics of the gate driving oscillator. In other words, since G _m of the PMOS transistor has non-linear characteristics, the change in output frequency with respect to the input voltage of the gate driving oscillator has non-linear characteristics.

On the other hand, the body driving oscillator 400 according to one embodiment, unlike the existing gate driving oscillator, input voltage (V _C+ , V _C- ) is applied to the body terminal of the inverter delay-cell, and accordingly, the inverter delay -The delay change of the cell is caused by the change in the body voltage and the inverter delay-appears by the change in the threshold voltage of each of the PMOS transistors and NMOS transistors that make up the cell.

That is, the change in output frequency compared to the input voltage of the body driving oscillator 400 according to one embodiment is G _mb of each transistor. It is expressed by characteristics, and since G _mb has linear characteristics compared to G _m , the body driven oscillator according to one embodiment can secure more linear characteristics than the existing gate driven oscillator.

FIGS. 5A and 5B are diagrams for explaining performance simulation results of an input impedance boosting device according to an embodiment.

Referring to FIGS. 5A and 5B , reference numerals 510 and 520 illustrate measurement results of the input impedance (Z _IN ) of the input impedance boosting device according to one embodiment.

Specifically, the input impedance boosting device according to one embodiment arranges a first shielding metal and a second shielding metal connected to a ground line below each of the input capacitor and the feedback capacitor, which are MOM capacitors, and the first terminal of the feedback capacitor and By arranging the connected first metal and arranging the third shielding metal formed under the first metal and connected to the second terminal of the feedback capacitor (C' _IN ), the parasitic capacitance component due to the input capacitor and the feedback capacitor is controlled. can do.

Additionally, the input impedance boosting device according to one embodiment can control the parasitic capacitance component formed by the chopper switch by disposing a dummy switch connected to both ends of the feedback capacitor and formed to the same size as the chopper switch.

According to reference numerals 510 and 520, the input impedance boosting device according to one embodiment was found to obtain a boosting effect of more than 70 times compared to the theoretical value (unboosted Z _IN ).

In addition, as a result of measurement on 10 multi-chips, the input impedance boosting device according to one embodiment achieved an input impedance of at least 421MΩ@DC and 147MΩ@1kHz, and the parasitic replication technique according to one embodiment was used. It was found that only 7% of the area of the entire system was consumed for application.

Ultimately, using the present invention, the influence of parasitic capacitance components can be reduced without additional calibration or trimming processes.

Additionally, using the present invention, the input impedance can be boosted while minimizing the increase in cost due to power consumption and circuit area.

Additionally, by using the present invention, improved impedance boosting performance can be achieved compared to existing techniques using a trimming process.

Although the embodiments have been described with limited drawings as described above, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

100: Input impedance boosting device ADC: Analog-digital conversion circuit
C _IN : Input capacitor C'IN: Feedback capacitor
110: first shielding metal 110-1: first parasitic component
120: second shielding metal 120-1: second parasitic component
130: third shielding metal 140: first metal

Claims (10)

analog-digital conversion circuit;
an input capacitor connected to the input terminal and a ground line of the analog-to-digital conversion circuit and having a first shielding metal formed at the bottom;
A feedback capacitor connected to the positive feedback loop of the analog-to-digital conversion circuit and having a second shielding metal formed at the bottom, and
It is connected to both ends of the feedback capacitor, and the input impedance is based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal. Impedance boosting unit that boosts
An input impedance boosting device comprising: According to paragraph 1,
The impedance boosting unit,
Boosting the input impedance by copying the first parasitic component and the second parasitic component and adding them to the positive feedback loop.
Input impedance boosting device. According to paragraph 1,
The impedance boosting unit,
Comprising a first metal connected to the first terminal of the feedback capacitor, and a third shielding metal formed below the first metal and connected to the second terminal of the feedback capacitor.
Input impedance boosting device. According to paragraph 1,
The first shielding metal and the second shielding metal are
Each connected to the ground line
Input impedance boosting device. According to paragraph 1,
Further comprising a chopper switch connected to the input terminal of the analog-to-digital conversion circuit.
Input impedance boosting device. According to clause 5,
The impedance boosting unit,
Further comprising a dummy switch connected to both ends of the feedback capacitor.
Input impedance boosting device. According to clause 6,
The impedance boosting unit,
Boosting the input impedance by copying the third parasitic component formed by the chopper switch through the dummy switch and adding it to the positive feedback loop.
Input impedance boosting device. According to clause 6,
The dummy switch is,
Formed in the same size as the chopper switch
Input impedance boosting device. According to paragraph 1,
The feedback capacitor and the input capacitor are,
MOM (metal-oxide-metal) capacitor
Input impedance boosting device. According to paragraph 1,
The analog-to-digital conversion circuit is,
Continuous-time delta sigma analog-to-digital conversion circuit including a linear integrator with a linear transconductance cell (linear Gm cell), a quantizer with a body-driven oscillator (VCO), and a frequency to digital converter (FDC). person
Input impedance boosting device.