CN116614136A - Continuous-time delta-sigma analog-to-digital conversion device and operation method thereof - Google Patents

Continuous-time delta-sigma analog-to-digital conversion device and operation method thereof Download PDF

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Publication number
CN116614136A
CN116614136A CN202310125728.6A CN202310125728A CN116614136A CN 116614136 A CN116614136 A CN 116614136A CN 202310125728 A CN202310125728 A CN 202310125728A CN 116614136 A CN116614136 A CN 116614136A
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China
Prior art keywords
output signal
continuous
digital conversion
linear
conversion apparatus
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Chinese (zh)
Inventor
李政协
崔智雄
李世焕
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Daegu Gyeongbuk Institute of Science and Technology
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Daegu Gyeongbuk Institute of Science and Technology
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Priority claimed from KR1020220176611A external-priority patent/KR20230122973A/en
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Publication of CN116614136A publication Critical patent/CN116614136A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/32—Delta-sigma modulation with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step

Abstract

The invention relates to a continuous-time delta-sigma analog-to-digital conversion device and an operation method thereof, wherein the continuous-time delta-sigma analog-to-digital conversion device of an embodiment of the invention comprises: a linear integrator for generating a first output signal corresponding to an input voltage based on an operation of a linear transconductance circuit (linear Gm circuit) that receives a preset input voltage; and a quantizer that generates a second output signal corresponding to the first output signal based on an operation of a body-driven oscillator (body-driven VCO) that receives the first output signal, and generates a digital output code corresponding to the second output signal based on an operation of a frequency-to-digital converter (FDC: frequency to digital converter) that receives the second output signal.

Description

Continuous-time delta-sigma analog-to-digital conversion device and operation method thereof
Technical Field
The present invention relates to a continuous-time ΔΣ (Delta-Sigma) analog-to-digital conversion device, and more particularly, to a technical idea of improving performance of a continuous-time ΔΣ analog-to-digital conversion device by optimally designing an integrator and a quantizer.
Background
Is provided with G m The C integrator (integrator) and the continuous time Delta-Sigma conversion device (CTDSM) based on VCO quantizer (quantizer) are mainly used to realize high resolution analog-to-digital conversion device (ADC).
The continuous-time Delta-Sigma analog-to-digital conversion device utilizes an integrator and a VCO-based quantizer to convert an input voltage into a digital output code, wherein the digital output code is fed back as an input of the integrator to form a Delta-Sigma loop (Delta-Sigma loop).
Specifically, the continuous-time ΔΣ analog-to-digital conversion apparatus can realize high resolution in a signal band by suppressing the shaped quantization noise (shaped quantization noise) by an integrator by providing inherent first-order noise (noise 1st order) based on a VCO quantizer.
Such a conventional continuous-time ΔΣ analog-to-digital conversion apparatus uses a VCO quantizer, and has a characteristic advantageous for low-power operation, but has a problem that an input voltage is relatively lower than a supply voltage (supply voltage) due to a linearity (linearity) problem of each module.
Specifically, the conventional continuous-time ΔΣ analog-to-digital conversion apparatus can reduce linearity due to quantization noise largely representing the input voltage swing of the integrator even if a negative feedback loop (negative feedback loop) is formed, and has a problem that the system linearity is largely reduced by the nonlinear KVCO based on the VCO quantizer.
Prior art literature
Patent literature
U.S. patent No. 9,397,692, "VOLTAGE-CONTROLLED OSCILLATOR (VCO) AS FIRST STAGE IN AN ANALOG-TO-DIGITAL CONVERTER (ADC) IN COMBINATION WITH ADIGITAL FILTER FOR SECOND OR HIGHER-ORDER NOISE SHAPING";
U.S. publication No. 2007-0152865, "SIGNAL PROCESSING SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER USING DELTA-SIGMA MODULATION HAVING AN INTERNAL STABILIZER LOOP".
Non-patent literature
“28.4A 400mVpp 92.3dB-SNDR 1kHz-BW 2nd-Order VCO-Based ExG-to-Digital Front-End Using a Multiphase Gated-Inverted Ring-Oscillator Quantizer”，C.Pochet，et al，ISSCC Dig.Tech.Papers，pp.392–394，Feb.2021
Disclosure of Invention
The present invention provides a continuous-time delta-sigma analog-to-digital converter and an operation method thereof, which can improve the noise power consumption efficiency and linearity of an integrator and a VCO quantizer to the maximum extent, thereby improving the noise performance, linearity, bandwidth and other main performances of the whole system.
Further, it is another object of the present invention to provide a continuous-time ΔΣ analog-to-digital conversion apparatus and an operation method thereof that can prevent aliasing of quantization noise and raise input impedance by providing a Finite Impulse Response (FIR) filter on a Delta-Sigma feedback loop.
The continuous-time delta-sigma analog-to-digital conversion device according to an embodiment of the present invention may include: a linear integrator that generates a first output signal corresponding to an input voltage based on an operation of a linear transconductance circuit (linear Gm circuit) that receives a preset input voltage; and a quantizer that generates a second output signal corresponding to the first output signal based on an operation of a body-driven oscillator (body-driven VCO) that receives the first output signal, and generates a digital output code corresponding to the second output signal based on an operation of a frequency-to-digital converter (FDC: frequency to digital converter) that receives the second output signal.
According to an embodiment of the present invention, a linear transconductance circuit may include: a plurality of operational amplifiers (OPAMP: operational amplifier); and a plurality of resistors connected to respective input terminals of the plurality of operational amplifiers.
According to an embodiment of the present invention, the plurality of resistors are respectively connected to the plurality of operational amplifiers through one side terminal, and are respectively connected to the power supply voltage VDD line through the other side terminal.
According to an embodiment of the present invention, the plurality of operational amplifiers may be current-multiplexing op amps (current-multiplexing op amps).
According to one embodiment of the invention, the linear integrator generates a current that linearly varies due to the input voltage being copied across the plurality of resistors by means of a unity gain feedback (unit gain feedback) in the linear transconductance circuit, and generates a first output signal corresponding to the variation of the generated current.
According to an embodiment of the present invention, the linear integrator may further include a direct current source (DC-current source) connected to the output terminal of the linear transconductance circuit.
According to one embodiment of the invention, the body-driven oscillator includes a plurality of inverting delay units (inverter delay cell) through each of the body terminals of which the first output signal is receivable.
According to an embodiment of the present invention, a plurality of inverting delay units respectively include: a PMOS transistor connected to a power supply voltage line; and an NMOS transistor connected to the PMOS transistor and the ground line, wherein the plurality of inverting delay units can receive the first output signal through respective body terminals of the PMOS transistor and the NMOS transistor, respectively.
According to an embodiment of the present invention, the continuous-time ΔΣ analog-to-digital conversion apparatus may further include a 4-tap FIR filter (4-tap FIR filter) disposed in a Delta-Sigma feedback loop connecting an input terminal of the linear integrator with an output terminal of the quantizer.
The operation method of the continuous-time delta-sigma analog-to-digital conversion device according to an embodiment of the present invention may comprise the following steps: in the linear integrator, generating a first output signal corresponding to an input voltage based on an operation of a linear transconductance circuit (linear Gmcircuit) that receives a preset input voltage; in the quantizer, generating a second output signal corresponding to the first output signal based on an operation of a body-driven oscillator (body-driven VCO) that receives the first output signal; and generating, in the quantizer, a digital output code corresponding to the second output signal based on operation of a frequency-to-digital converter (FDC, frequency to digital converter) that receives the second output signal.
According to an embodiment of the invention, the noise performance, linearity, bandwidth and other main performances of the whole system can be improved to the greatest extent by improving the noise power consumption efficiency and linearity of the integrator and the VCO quantizer.
According to an embodiment of the invention, aliasing of quantization noise can be prevented and the input impedance raised by placing a finite impulse response filter on the Delta Sigma feedback loop.
Drawings
Fig. 1 is a diagram for explaining a continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
Fig. 2 is a diagram for further details of a continuous-time delta-sigma analog-to-digital conversion device according to an embodiment of the present invention.
Fig. 3 is a diagram of a linear integrator for further elaborating an embodiment of the present invention.
Fig. 4a to 4d are diagrams for further describing the linear transconductance circuit according to an embodiment of the present invention.
Fig. 5a and 5b are diagrams for further explaining a body-driven oscillator according to an embodiment of the present invention in detail.
Fig. 6a and 6b are graphs for illustrating the performance simulation results of the linear integrator according to an embodiment of the present invention.
Fig. 7a and 7b are graphs for explaining the results of performance simulation of the bulk driving oscillator according to an embodiment of the present invention.
Fig. 8a to 8c are graphs for explaining the performance simulation results of the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
Fig. 9 is a diagram for explaining an operation method of the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
Description of the reference numerals
100: continuous time delta sigma analog-to-digital conversion device
110: linear integrator
120: quantizer
Detailed Description
Various embodiments of the present specification are described below with reference to the accompanying drawings.
The examples and the terms used therein are not limited to the techniques described in this specification in terms of specific embodiments, but are to be understood to include various modifications, equivalents and/or alternatives to the respective examples.
In the following, in describing the various embodiments, when it is determined that a detailed description of known functions or configurations may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted.
Also, the following terms, which are terms defined in consideration of functions in the various embodiments, may vary depending on the intention or convention of a user, an operator, or the like. Therefore, it should be defined based on the entire contents of the present specification.
In describing the drawings, like reference numerals have been used for like structural elements.
The expression singular may include the plural unless the context clearly indicates otherwise.
In this specification, the expression "a or B" or "at least one of a and/or B" or the like may include all combinations of items listed together.
The expressions "first", "second", "first" or "second", etc. may modify the corresponding structural elements regardless of the order of sequence or importance, and are only used to distinguish one structural element from other structural elements, and are not limited to the corresponding structural elements.
When a component (e.g., a first component) is "connected" or "coupled" to another component (e.g., a second component), it means that the component is directly connected to the other component, or may be connected via another component (e.g., a third component).
In the present specification, "configured to" is used interchangeably with "applicable to", "having" a function "," changing to "," making to "," playing to "a function" or "designing to" an exchange "in terms of hardware or software, as the case may be.
In certain cases, the expression "a device configured to function" means that the device "functions" together with other devices or components.
For example, a "processor configured (or designed) to perform A, B and C" refers to a general-purpose processor (e.g., a Central Processing Unit (CPU) or an application processor (application processor)) that can perform respective operations by running a dedicated processor (e.g., an embedded processor) or one or more software programs stored on a storage device for performing the respective operations.
Also, the term "or" refers to "exclusive or" rather than "exclusive or".
That is, unless otherwise indicated or explicitly indicated in the text, the expression "x employs a or b" refers to one of the natural inclusive permutations (natural inclusive permutations).
In the following embodiments, the structural elements included in the present invention may be expressed in singular or plural number according to the disclosed embodiments.
However, the expression in the singular or plural is appropriately selected depending on the disclosure in consideration of the convenience in the description, and the following embodiments are not limited to the singular or plural components, and the components expressed in the plural may be constituted by the singular components or the components expressed in the singular may be constituted by the plural components.
On the other hand, although the present specification describes specific embodiments, various modifications can be made without departing from the technical ideas included in the embodiments.
Accordingly, the scope of the present invention should not be limited to the embodiments described below, but should be defined based on the scope of the invention as claimed and their equivalents.
Fig. 1 is a diagram for explaining a continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
Referring to fig. 1, a continuous-time ΔΣ analog-to-digital conversion apparatus 100 according to an embodiment of the present invention can improve the noise performance, linearity, bandwidth, and other main performances of the overall system to the greatest extent by improving the noise power consumption efficiency and linearity of the integrator and VCO-based quantizer.
Also, the analog-to-digital conversion apparatus 100 is provided with a finite impulse response filter on the feedback loop, and thus, can prevent aliasing of quantization noise and raise input impedance.
To this end, the analog-to-digital conversion apparatus 100 may include a linear integrator 110 and a quantizer 120, and may further include a 4-tap FIR filter (4-tap FIR filter) disposed on a Delta-Sigma feedback loop connecting an input of the linear integrator to an output of the quantizer.
The analog-digital conversion apparatus 100 may further include a voltage generation unit that generates a voltage (e.g., a power supply voltage V DD Bias voltage V BIAS Input voltage V IN Etc.) to supply corresponding ones of the generated voltages to respective entities constituting peripheral circuits connected to the analog-digital conversion apparatus 100.
The linear integrator 110 according to an embodiment of the present invention can be based on receiving a predetermined input voltage V IN Is operated by a linear transconductance circuit (linear Gm circuit) to generate an input voltage V IN A corresponding first output signal.
Also, the quantizer 120 of an embodiment of the present invention may generate a second output signal corresponding to the first output signal based on an operation of a body-driven oscillator (body-driven VCO) receiving the first output signal, and generate a digital output code D corresponding to the second output signal based on an operation of a frequency-to-digital converter (FDC: frequency to digital converter) receiving the second output signal OUT 。
Specifically, the analog-to-digital conversion apparatus 100 is a 1-order Continuous Time Delta Sigma Modulator (CTDSM) composed of a linear integrator 110 having low noise characteristics and high linearity characteristics and a quantizer 120 based on a body-driven oscillator, and not only can have high stability and specificity due to 1-order loop (1 st order loop) characteristics, but also can realize low quantization noise characteristics within a signal bandwidth by based on inherent noise characteristics of a VCO quantizer.
The following describes the analog-to-digital conversion apparatus 100 according to an embodiment of the present invention in further detail with reference to fig. 2.
Fig. 2 is a diagram for further details of a continuous-time delta-sigma analog-to-digital conversion device according to an embodiment of the present invention.
Referring to fig. 2, a continuous-time ΔΣ analog-to-digital conversion apparatus 200 according to an embodiment of the present invention may include a linear integrator 210 and a quantizer 220, wherein the quantizer 220 may further include: a body-driven oscillator 221 connected to the linear integrator 210; and a frequency digitizer 222 connected to the body driven oscillator 221.
The linear integrator 210 according to an embodiment of the present invention can be based on receiving a predetermined input voltage V IN Is operated by a linear transconductance circuit (linear Gm circuit) to generate an input voltage V IN A corresponding first output signal.
According to an embodiment of the present invention, a linear transconductance circuit may include: a plurality of operational amplifiers (OPAMP: operational amplifier); and a plurality of resistors connected to respective input terminals of a plurality of operational amplifiers, wherein the plurality of operational amplifiers may be current-multiplexing op amps.
For example, a plurality of resistors are connected to each operational amplifier through one end and can be connected to the power supply voltage V through the other end DD The wires are connected.
Also, the linear integrator 210 may further include a direct current Source (DC-current Source) connected to the output of the linear transconductance circuit.
According to one embodiment of the invention, the linear integrator 210 generates a first output signal corresponding to a change in the generated current by generating a current that varies linearly as a result of the input voltage being copied across (i.e., modeled by) a plurality of resistors through a unity gain feedback (unit gain feedback) in a linear transconductance circuit.
The body driving oscillator 221 of an embodiment of the present invention may receive the first output signal to generate a second output signal corresponding to the first output signal.
According to an embodiment of the present invention, the body-driven oscillator 221 includes a plurality of inverting delay units (inverter delay cell) through each of the body terminals of which the first output signal can be received.
Specifically, the plurality of inverting delay units respectively include: a PMOS transistor connected to a power supply voltage line; and an NMOS transistor connected to the PMOS transistor and the ground line, for receiving the first output signal via respective body terminals of the PMOS transistor and the NMOS transistor.
The frequency-to-digital converter of an embodiment of the invention can receive the second output signal to generate a digital output code D corresponding to the second output signal OUT 。
According to an embodiment of the present invention, the analog-to-digital conversion apparatus 200 may further include a chopper switch (chopper) disposed at an input terminal of the linear integrator 210.
On the other hand, the analog-to-digital conversion apparatus 200 may further include a 4-order finite impulse response filter 230 disposed in a Delta-Sigma feedback loop connecting the input of the linear integrator 210 with the output of the frequency-to-digital converter 222 in order to boost the input impedance.
Specifically, the input impedance of the analog-to-digital conversion apparatus 200 depends on an input capacitor C provided between the input terminal of the linear integrator 210 and the ground line IN (input capacitor) chopping frequency f at the node connected to the input of linear integrator 210 CH (choopping frequency) the prior art devices use a chopping frequency equal to fs or fs/2 (where f s Is the sampling frequency).
However, in this case, there is a problem in that the input impedance is reduced to 1mΩ or less due to the high sampling frequency, and in order to solve this problem, the analog-digital conversion apparatus 200 may connect a 4 th order finite impulse response filter on the feedback loop to vector the noise generation notch (notch).
In particular, the analog-to-digital conversion apparatus 200 may prevent the generation of aliasing of quantization noise, which appears as chop, by filtering the quantization noise in a frequency band where aliasing occurs through the 4 th-order finite impulse response filter 230.
And, compared with the existing deviceThe analog-to-digital conversion apparatus 200 may generate f through the 4 th order finite impulse response filter 230 s The notch frequency (notch frequency) is used as a chopping frequency to increase the input impedance by a factor of 4.
Fig. 3 is a diagram of a linear integrator for further elaborating an embodiment of the present invention.
Referring to fig. 3, the linear integrator 300 according to an embodiment of the present invention, which is a first entity receiving the input of the analog-to-digital conversion apparatus, can be designed to have low noise and high linearity since it plays a major role in determining the system noise and linearity level.
The linear integrator 300 according to an embodiment of the present invention can be based on receiving a predetermined input voltage V INN 、V INP Is operated by a linear transconductance circuit to generate and input voltage V INN 、V INP Corresponding first output signal I OUTN 、I OUTP 。
The linear transconductance circuit may include: a plurality of operational amplifiers; a plurality of resistors R D A plurality of resistors R connected to respective input terminals of the plurality of operational amplifiers D Are respectively connected with each operational amplifier through one side end, and can be connected with a power supply voltage V through the other side end DD The wires are connected.
Furthermore, the linear integrator 300 may further include a dc current source connected to the output of the linear transconductance circuit.
On the other hand, the linear integrator 300 may design a plurality of operational amplifiers as current multiplexing operational amplifiers, respectively, in order to improve noise power consumption efficiency.
Among a plurality of transistors constituting a plurality of operational amplifiers, the pass transistor M 2 And the gate terminal of transistor M4 receives the input voltage V INP Can pass through transistor M 1 Transistor M 3 Receives an input voltage V at a gate terminal of (2) INN Wherein the transistor M 1 To transistor M 4 Can be based on input voltage V INN Input voltage V INP Operates as a transconductance amplifier (transconductance amplifier).
According to one embodiment of the inventionEmbodiment, the linear integrator 300 generates the input voltage V by unity gain feedback (unit gain feedback) in a linear transconductance circuit INN 、V INP Copy to multiple resistors R D A first output signal corresponding to a change in the generated current may be generated.
In particular, the linear integrator 300 may generate an output current I as the linear circuit variations due to the linear transconductance circuit are replicated to the output through NMOS transistors OUTN 、I OUTP Due to the generated output current I OUTN 、I OUTP Into a load capacitor (load capacitor) of the linear integrator 300, and thus, linearity can be maintained, in which the output current I OUTN 、I OUTP May be converted to a voltage corresponding to the load capacitor (i.e., the first output signal).
Fig. 4a to 4d are diagrams for further describing the linear transconductance circuit according to an embodiment of the present invention.
Referring to fig. 4a to 4d, reference numeral 410 denotes a conventional transconductance circuit (G m -cell), reference numeral 420 denotes the linearity of the existing transconductance circuit.
And reference numeral 430 denotes a linear transconductance circuit (linear G) according to an embodiment of the present invention m -cell), reference numeral 440 denotes the linear characteristics of a linear transconductance circuit according to an embodiment of the present invention.
In reference numerals 410 and 420, an input transistor of a conventional transconductance circuit is used as a transconductance amplifier, and generates a specific gain G when an input voltage is applied m In a differential structure, G m Is defined as the following equation 1, and exhibits a nonlinear (nonlinear) characteristic.
1 (1)
In contrast, in reference numerals 430 and 440, the linear transconductance circuit according to an embodiment of the present invention is different from the conventional transconductance circuit, and does not depend only onG of input transistor m The input voltage is copied to the resistor R due to the unity gain feedback D Changes DeltaR of the input voltage duplicated in this way D The current Δi having the following formula 2 linearly varying can be generated based on the resistance characteristics D 。
2, 2
Wherein at the input voltage V IN For input voltage V INN 、V INP In the case of (1) a linearly varying current I D Can be formed by (V) INP －V INN )/(2×R D ) To represent.
Thus, the current variation of the input voltage is defined as 1/R D Thus, the linear transconductance circuit of an embodiment of the present invention may achieve a linear characteristic.
Fig. 5a and 5b are diagrams for further explaining a body-driven oscillator according to an embodiment of the present invention in detail.
Referring to fig. 5a and 5b, reference numeral 510 denotes a conventional gate-driven oscillator (gate-driven VCO), and reference numeral 520 denotes a body-driven oscillator (body-driven VCO).
Specifically, in the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention, the quantizer may generate the second output signal corresponding to the first output signal based on the operation of the body-driven oscillator that receives the first output signal output from the linear integrator, and generate the digital output code DOUT corresponding to the second output signal based on the operation of the frequency-to-digital converter that receives the second output signal.
Specifically, in reference numeral 510, the output frequency variation of the existing gate driving oscillator is embodied by a delay variation of each inverter delay-cell (delay), which is generated by a current variation of the PMOS transistor.
In this case, the input voltage V of the gate-driven oscillator C Applied to the gate terminal of a PMOS transistorG of tube m The characteristics greatly affect the linearity characteristics of the gate-driven oscillator. Namely due to G of PMOS transistor m Has a nonlinear characteristic, and thus, the variation of the output frequency has a nonlinear characteristic with respect to the input voltage of the gate driving oscillator.
In contrast, in reference numeral 520, the bulk-driven oscillator of an embodiment of the present invention is different from the conventional gate-driven oscillator in that the input voltage V C+ 、V C- Since the delay variation of the inverting delay unit is applied to the body (body) terminal of the inverting delay unit, the respective threshold voltages (threshold voltage) of the PMOS transistor and the NMOS transistor constituting the inverting delay unit are changed by the change of the body voltage.
That is, the variation of the input voltage versus the output frequency of the bulk-driven oscillator according to an embodiment of the present invention is determined by the G of each transistor mb Characteristic embodiment, compared with G m Due to G mb The body-driven oscillator according to an embodiment of the present invention has a linear characteristic, and thus can effectively secure the linear characteristic as compared with the conventional gate-driven oscillator.
Fig. 6a and 6b are graphs for illustrating the performance simulation results of the linear integrator according to an embodiment of the present invention.
Referring to fig. 6 a-6 b, reference numeral 610 illustrates the input voltage being copied to the resistor R in a linear transconductance circuit included in a linear integrator of an embodiment of the present invention D Frequency response characteristics at both ends reference numeral 620 shows frequency response characteristics of an input voltage to an output voltage in a linear integrator according to an embodiment of the present invention.
In reference numeral 610, it can be appreciated that a linear transconductance circuit in accordance with an embodiment of the present invention allows an efficient replica of an input voltage across a resistor. In other words, it can be confirmed that the linear transconductance circuit accurately replicates the input voltage within a bandwidth that the loop gain (loop gain) of the unity gain feedback is well maintained.
In reference numeral 620, it can be confirmed that the linear integrator of an embodiment of the present invention exhibits a 3dB corner frequency (3 dB-burner frequency) within a bandwidth of about 200Hz by the load capacitor.
Fig. 7a and 7b are graphs for explaining the results of performance simulation of the bulk driving oscillator according to an embodiment of the present invention.
In fig. 7a and 7b, reference numeral 710 shows a simulation result of a frequency change of an oscillator due to a single tone (single tone) input, and reference numeral 720 shows a simulation result of a power spectral density (PSD: power spectrum density) of a quantizer using a body-driven oscillator according to an embodiment of the present invention.
In reference numerals 710 and 720, the nonlinear prior art oscillator generates harmonics of the single-tone input, as shown in reference numeral 720, which is about 72dB less than the single tone, which means about 20dB improvement over the prior art gate-driven oscillator, as can be seen in the bulk-driven oscillator of an embodiment of the present invention.
Fig. 8a to 8c are graphs for explaining the performance simulation results of the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
Referring to fig. 8a to 8c, reference numeral 810 shows a simulation result of a power spectral density (PSD: power spectrum density) of a continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention, reference numeral 820 shows a signal ratio and noise-distortion ratio sum (SNDR, signal-to-noise plus distortion ratio) simulation result of a continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention, and reference numeral 830 shows a noise simulation result of a continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
In reference numerals 810 to 830, when the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention applies an input of 560mVpp at a supply voltage of 0.7V, 85.1dB of signal ratio-to-noise-and-distortion ratio sum and spurious-free dynamic range (SFDR) performance of 97dB are measured within a 10kHz bandwidth, and in the signal ratio-to-noise-and-distortion ratio sum measurement result, it is confirmed that the 85.1dB of signal ratio-to-noise-and-distortion ratio sum peak (peak SNDR) corresponds to a Dynamic Range (DR) of 87.3 dB.
Further, in the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention, the result of confirming the noise performance shows that the noise performance is measured at 200Hz at 1.4 μvrms and at 10kHz at 8.5 μvrms.
On the other hand, the comparison between the main performance of the continuous-time ΔΣ analog-to-digital conversion apparatus (this work) and the conventional CTDSM based systems (ISSCC '18, ISSCC '19 and ISSCC ' 21) is shown in the following table 1, and the continuous-time ΔΣ analog-to-digital conversion apparatus according to the embodiment of the present invention achieves the performance of 85.1dB of SNDR, 178.1dB of FOMSNDR, 17fJ/step of FOMW, and thus can exhibit the highest performance compared to the conventional systems.
Fig. 9 is a diagram for explaining an operation method of the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention.
In other words, fig. 9 is a diagram for explaining the operation method of the continuous-time ΔΣ analog-to-digital conversion apparatus according to an embodiment of the present invention explained through fig. 1 to 8c, and hereinafter, in the process explained with reference to fig. 9, the repetitive matters explained with reference to fig. 1 to 8c will be omitted.
Referring to fig. 9, in step 910 of the operating method, a Linear integrator may be used to determine the output voltage based on a Linear transconductance circuit (Linear G) that receives a predetermined input voltage m circuit) generates a first output signal corresponding to the input voltage.
For example, the linear transconductance circuit may include: a plurality of operational amplifiers (OPAMP: operational amplifier); and a plurality of resistors connected to respective input terminals of the plurality of operational amplifiers.
The plurality of resistors are connected to the operational amplifiers through one end and connected to the power supply voltage VDD line through the other end.
Also, the plurality of operational amplifiers may be current-multiplexing op amps (current-multiplexing op amps).
The linear integrator may also include a direct Current Source (DC-Current Source) coupled to the output of the linear transconductance circuit.
In accordance with one embodiment of the present invention, in step 910 of the method of operation, the linear integrator generates a current that varies linearly due to the input voltage being copied across the plurality of resistors by means of a unity gain feedback (unit gain feedback) in the linear transconductance circuit, and may generate a first output signal corresponding to the variation of the generated current.
Next, in step 920 of the operation method, a second output signal corresponding to the first output signal may be generated by a quantizer based on an operation of a body-driven oscillator (body-driven VCO) that receives the first output signal.
For example, the body driven oscillator includes a plurality of inverting delay units (inverter delay cell) through each of the body terminals of which the first output signal is receivable.
Specifically, the plurality of inverting delay units respectively include: a PMOS transistor connected to a power supply voltage line; and an NMOS transistor connected to the PMOS transistor and the ground line, for receiving the first output signal via respective body terminals of the PMOS transistor and the NMOS transistor.
Subsequently, in step 930 of the method of operation, a digital output code corresponding to the second output signal may be generated by the quantizer based on operation of a frequency-to-digital converter (FDC, frequency to digital converter) that receives the second output signal.
On the other hand, in step 930 of the method of operation, the digital output code may be fed back as an input to the linear integrator by a Delta Sigma feedback loop connecting the input of the linear integrator with the output of the quantizer, wherein a 4 th order finite impulse response filter may be provided on the Delta Sigma feedback loop.
In step 940 of the method of operation, the chopping frequency of the continuous-time delta-sigma analog-to-digital conversion device of an embodiment of the present invention may be controlled based on the digital output code by a 4-th order finite impulse response filter.
Finally, under the condition of utilizing the invention, the noise performance, linearity, bandwidth and other main performances of the whole system can be improved to the greatest extent by improving the noise power consumption efficiency and linearity of the integrator and the VCO quantizer.
Also, in the case of using the present invention, a finite impulse response filter may be provided on the feedback loop to prevent aliasing of quantization noise and to raise the input impedance.
Although the embodiments have been described above with reference to the limited drawings, various modifications and variations can be made by those skilled in the art to which the present invention pertains. For example, even if the described techniques are performed in a different order than the described methods and/or structural elements of the described systems, structures, devices, circuits, etc. are combined or combined in a different embodiment from the described methods, or even if replaced or substituted with other structural elements or equivalent technical solutions, appropriate results may be achieved.
Accordingly, other embodiments, other examples, and equivalents to the scope of the invention are also within the scope of the invention as claimed.

Claims (10)

1. A continuous-time delta-sigma analog-to-digital conversion apparatus, comprising:
a linear integrator for generating a first output signal corresponding to a preset input voltage based on an operation of a linear transconductance circuit receiving the input voltage; and
and a quantizer that generates a second output signal corresponding to the first output signal based on an operation of a body-driven oscillator that receives the first output signal, and generates a digital output code corresponding to the second output signal based on an operation of a frequency-to-digital converter that receives the second output signal.
2. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 1, wherein,
the linear transconductance circuit includes:
a plurality of operational amplifiers; and
and a plurality of resistors connected to the input terminals of the plurality of operational amplifiers, respectively.
3. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 2, wherein,
each of the plurality of resistors is connected to the plurality of operational amplifiers through one side terminal and to a power supply voltage line through the other side terminal.
4. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 2, wherein,
the plurality of operational amplifiers are current multiplexing operational amplifiers.
5. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 2, wherein,
the linear integrator generates a current linearly varying by the input voltage being copied to both ends of the plurality of resistors by means of a unity gain feedback in the linear transconductance circuit, and generates the first output signal corresponding to the generated current variation.
6. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 1, wherein,
the linear integrator further includes:
and the direct current source is connected with the output end of the linear transconductance circuit.
7. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 1, wherein,
the body-driven oscillator includes a plurality of inverting delay units, and the first output signal is received through a body terminal of each of the plurality of inverting delay units.
8. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 7, wherein,
each of the plurality of inverting delay units includes:
a PMOS transistor connected to a power supply voltage line; and
an NMOS transistor connected to the PMOS transistor and the ground line,
wherein the plurality of inverting delay units receive the first output signal through respective body terminals of the PMOS transistor and the NMOS transistor.
9. The continuous-time delta-sigma analog-to-digital conversion apparatus of claim 1, further comprising:
a 4-order finite impulse response filter, disposed in a delta-sigma feedback loop connecting the input of the linear integrator and the output of the quantizer.
10. A method of operating a continuous-time delta-sigma analog-to-digital conversion device, comprising the steps of:
generating, in a linear integrator, a first output signal corresponding to a preset input voltage based on an operation of a linear transconductance circuit that receives the input voltage;
in a quantizer, generating a second output signal corresponding to the first output signal based on an operation of a body-driven oscillator that receives the first output signal; and
in the quantizer, a digital output code corresponding to the second output signal is generated based on an operation of a frequency-to-digital converter that receives the second output signal.
CN202310125728.6A 2022-02-15 2023-02-15 Continuous-time delta-sigma analog-to-digital conversion device and operation method thereof Pending CN116614136A (en)

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