KR102662942B1 - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided. This semiconductor device includes a substrate including a first region and a second region; a buffer layer on the substrate; a semiconductor layer on the buffer layer; A barrier layer on the semiconductor layer; a first source electrode, a first drain electrode, and a first gate electrode disposed on the barrier layer in the first area; a second source electrode, a second drain electrode, and a second gate electrode disposed on the barrier layer in the second area; and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.

Description

Semiconductor device and method of fabricating the same}

The present invention relates to semiconductor devices and methods for manufacturing the same.

High Electron Mobility Transistor (HEMT) is a 2DEG (2Dimensional Electron) generated by polarization and band discontinuity at the heterojunction interface of semiconductor materials with different energy bandgaps. The gas layer is used as a channel layer (a path through which electrons move from source to drain) of semiconductor devices. These HEMT devices are used in high-power-high-frequency systems due to the high electron mobility in the 2DEG layer.

The problem to be solved by the present invention is to provide a flexible semiconductor device that can be used in a high-output-high-frequency system.

Another problem that the present invention aims to solve is to provide a method for manufacturing semiconductor devices that can reduce defects and reduce manufacturing costs.

A semiconductor device according to the concept of the present invention for achieving the above object includes a substrate including a first region and a second region; a buffer layer on the substrate; a semiconductor layer on the buffer layer; a barrier layer on the semiconductor layer; a first source electrode, a first drain electrode, and a first gate electrode disposed on the barrier layer in the first area; a second source electrode, a second drain electrode, and a second gate electrode disposed on the barrier layer in the second area; and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.

The substrate may be flexible.

The semiconductor device may further include an adhesive layer interposed between the substrate and the buffer layer.

The semiconductor device may further include a hexagonal boron nitride layer interposed between the substrate and the buffer layer.

The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may extend into the semiconductor layer through the barrier layer.

The ferroelectric patterns may be provided in plural numbers and arranged in a row along a first direction, and the first gate electrode may extend in the first direction to cover side surfaces and top surfaces of the ferroelectric patterns.

The first gate electrode, the first source electrode, and the first drain electrode constitute a first transistor, and the second gate electrode, the second source electrode, and the second drain electrode constitute a second transistor, The first transistor may have a positive threshold voltage, and the second transistor may have a negative threshold voltage.

The semiconductor device may further include a 2-Dimensional Electron Gas (2DEG) layer located within the semiconductor layer.

The semiconductor device further includes a recess region formed on one side of the first gate electrode and an upper portion of the barrier layer and the semiconductor layer, wherein a sidewall of the ferroelectric is exposed at an inner wall of the recess region, and the first The gate electrode may cover the inner wall and bottom surface of the recess area.

The semiconductor device may further include a third insulating pattern interposed between the first gate electrode and the semiconductor layer, between the first gate electrode and the sidewall of the barrier layer, and between the first gate electrode and the sidewall of the ferroelectric. You can.

The semiconductor device includes a first insulating pattern interposed between the barrier layer and the ferroelectric pattern; a second insulating pattern interposed between the ferroelectric pattern and the first gate electrode; And it may further include a protective film in contact with the top surface and side surface of the first gate electrode, the side surface of the first insulating pattern, the side surface of the ferroelectric pattern, and the side surface of the second insulating pattern.

The second gate electrode may be in contact with the barrier layer.

A method of manufacturing a semiconductor device according to the concept of the present invention for achieving the above other problems includes sequentially stacking a separation layer, a buffer layer, a semiconductor layer, and a barrier layer on a first sacrificial substrate including a first region and a second region. step; forming a first source electrode and a first drain electrode on the barrier layer in the first area, and forming a second source electrode and a second drain electrode on the barrier layer in the second area; forming a ferroelectric pattern on the barrier layer between the first source electrode and the first drain electrode; forming a first gate electrode on the ferroelectric pattern and forming a second gate electrode on the barrier layer between the second source electrode and the second drain electrode; and removing the first sacrificial substrate.

The separation layer includes a hexagonal boron nitride layer.

The method includes forming a first adhesive layer on the first gate electrode and the second gate electrode before removing the first sacrificial substrate; And it may further include forming a second sacrificial substrate on the first adhesive layer.

The method may further include, before forming the first adhesive layer, forming a protective film covering the entire surface of the first sacrificial substrate on which the first gate electrode and the second gate electrode are formed.

The method may further include forming a flexible substrate under the separation layer after removing the first sacrificial substrate.

The method includes forming a second adhesive layer under the separation layer after removing the first sacrificial substrate; And it may further include the step of adhering a flexible substrate to the second adhesive layer.

The method includes forming a recess region by etching a portion of the barrier layer and the semiconductor layer next to the ferroelectric pattern before forming the first gate electrode and the second gate electrode; and forming a third insulating pattern covering the inner wall and bottom surface of the recess area.

Forming the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may include forming metal patterns spaced apart from each other on the barrier layer; and performing a heat treatment process to diffuse the metal in the metal pattern into parts of the barrier layer and the semiconductor layer.

In the semiconductor device according to embodiments of the present invention, since the first transistor includes a ferroelectric pattern and uses a fin gate structure, a decrease in fin width and drain current can be minimized and a positive threshold voltage can be achieved. As a result, it is possible to implement a HEMT device with a positive threshold voltage without deterioration in output and frequency characteristics. This can provide a flexible semiconductor device that can be used in high-power-high-frequency systems.

Additionally, in the method of manufacturing a semiconductor device according to embodiments of the present invention, a buffer layer can be well formed by using a hexagonal boron nitride layer as a separation layer, and the first sacrificial substrate can be easily separated. This makes it possible to manufacture semiconductor devices that are defect-free, flexible, and have improved reliability. In addition, the first sacrificial substrate can be recycled, thereby reducing manufacturing costs.

1 is a plan view of a semiconductor device according to embodiments of the present invention.
FIG. 2 is a cross-sectional view of FIG. 1 taken along line A-A'.
Figure 3 is a cross-sectional view taken along line B-B' of Figure 1.
Figure 4 shows the polarization phenomenon of the ferroelectric pattern when voltage is applied to the semiconductor device of the present invention.
FIGS. 5 to 10 and FIGS. 11A to 13A are cross-sectional views sequentially showing the process of manufacturing a semiconductor device having the cross-section of FIG. 2 according to embodiments of the present invention.
FIGS. 11B to 13B are cross-sectional views sequentially showing the process of manufacturing a semiconductor device having the cross-section of FIG. 3 according to embodiments of the present invention.

The above objects, other objects, features and advantages of the present invention will be easily understood through the following preferred embodiments related to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure will be thorough and complete and so that the spirit of the invention can be sufficiently conveyed to those skilled in the art.

In this specification, when an element is referred to as being on another element, it means that it may be formed directly on the other element or that a third element may be interposed between them. Additionally, in the drawings, the thickness of components is exaggerated for effective explanation of technical content.

Embodiments described herein will be explained with reference to cross-sectional views and/or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, the form of the illustration may be modified depending on manufacturing technology and/or tolerance. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include changes in form produced according to the manufacturing process. For example, an etch area shown at a right angle may be rounded or have a shape with a predetermined curvature. Accordingly, the regions illustrated in the drawings have properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of the region of the device and are not intended to limit the scope of the invention. In various embodiments of the present specification, terms such as first and second are used to describe various components, but these components should not be limited by these terms. These terms are merely used to distinguish one component from another. Embodiments described and illustrated herein also include complementary embodiments thereof.

The terminology used herein is for describing embodiments and is not intended to limit the invention. As used herein, singular forms also include plural forms, unless specifically stated otherwise in the context. As used in the specification, 'comprise' and/or 'comprising' do not exclude the presence or addition of one or more other elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a plan view of a semiconductor device according to embodiments of the present invention. FIG. 2 is a cross-sectional view of FIG. 1 taken along line A-A'. Figure 3 is a cross-sectional view taken along line B-B' of Figure 1.

1 to 3, the semiconductor device 1000 according to this example includes a substrate 601. The substrate 601 may include a first region (R1) and a second region (R2). The first region R1 may be a transistor region having a positive threshold voltage. The second region R2 may be a transistor region having a negative threshold voltage. A substrate adhesive layer 501, a separation layer 101, a buffer layer 102, a semiconductor layer 103, and a barrier layer 104 are sequentially stacked on the substrate 601. The substrate 601 may be flexible. Preferably, the substrate 601 may include polyethylene terephthalate (PET) or polyimide. The substrate adhesive layer 501 may include either BCB (Benzocyclobutene) resin or wax. The separation layer 101 may include a hexagonal boron nitride layer. The semiconductor layer 103 may be a group III-V semiconductor compound. The semiconductor layer 103 may preferably include at least one selected from AlN, InN, GaN, AlGaN, InGaN, AlInN, AlGaInN, and GaAs. The semiconductor layer 103 may or may not be doped with impurities. The buffer layer 102 may be made of a material with a lattice constant different from that of the semiconductor layer 103. The buffer layer 102 may have a wider energy band gap than the semiconductor layer 103. The buffer layer 102 may be, for example, GaN or AlN.

The barrier layer 104 may form a heterojunction with the semiconductor layer 103. The barrier layer 104 may include at least one selected from Al, Ga, In, and B, or a nitride thereof. The barrier layer 104 may or may not be doped with impurities. The barrier layer 104 may be made of a material with a lattice constant different from that of the semiconductor layer 103. The barrier layer 104 may have a wider energy band gap than the semiconductor layer 103. A 2DEG layer may be formed by polarization and band discontinuity at the heterojunction interface between the semiconductor layer 103 and the barrier layer 104. The 2DEG layer may be located within the semiconductor layer 103. The 2DEG layer can be used as a channel layer through which electrons move in a HEMT device.

A first source electrode 201sa and a first drain electrode 201da may be disposed on the barrier layer 104 in the first region R1. A second source electrode 201sb and a second drain electrode 201db may be disposed on the barrier layer 104 in the second region R2. The first source electrode 201sa, first drain electrode 201da, second source electrode 201sb, and second drain electrode 201db penetrate the barrier layer 104 into the semiconductor layer 103. It may be extended. The first source electrode (201sa), first drain electrode (201da), second source electrode (201sb), and second drain electrode (201db) are selected from among Ti, Al, Ni, Au, Pd, Cu, Co, and Pt. It may include a material in which at least one selected metal is combined with a semiconductor material constituting the barrier layer 104 and the semiconductor layer 103, or an alloy of the metal and the semiconductor material. The first source electrode 201sa, first drain electrode 201da, second source electrode 201sb, and second drain electrode 201db may each protrude onto the barrier layer 104.

Wiring patterns 203 may be disposed on the first source electrode 201sa, first drain electrode 201da, second source electrode 201sb, and second drain electrode 201db, respectively. The first source electrode 201sa, first drain electrode 201da, second source electrode 201sb, and second drain electrode 201db may each contact the 2DEG layer. The first source electrode 201sa may not be connected to the first drain electrode 201da by the 2DEG layer. However, the second source electrode 201sb may be connected to the second drain electrode 201db through the 2DEG layer.

Although not shown, the first source electrode 201sa may be electrically connected to the second source electrode 201sb through one of the wiring patterns 203. The first drain electrode 201da may be electrically connected to the second drain electrode 201db through another one of the wiring patterns 203. The wiring patterns 203 may include at least one metal selected from Ti, Al, Ni, Au, Pd, Cu, Co, and Pt. The first source electrode 201sa, the first drain electrode 201da, the second source electrode 201sb, and the second drain electrode 201db may be spaced apart from each other in a first direction (X1), and the first direction It may extend in a second direction (X2) intersecting (X1).

A ferroelectric pattern 401p may be provided between the first source electrode 201sa and the first drain electrode 201da. The ferroelectric pattern 401p may include HfO2 doped with silicon (Si), aluminum (Al), or zirconium (Zr). Alternatively, the ferroelectric pattern 401p may be made of ferroelectric materials such as Lead Zirconate Titanate (PZT), Lanthanum-modified Lead Zirconate Titanate (PLZT), Bismuth Lanthanum Titanate (BLT), Barium Strontium Titanate (BST), and Strontium Bismuth Tantalate (SBT). It may include, but is not limited to, those selected from the group consisting of a combination of. For example, the PZT is 0.2<x<0.8 as [Pb(ZrxTi1-x)O3], and the PLZT is 0.2<x<0.8 and 0.01<y as [(Pb1-yLay)(ZrxTi1-x)O3]. <0.2, the BLT is 0.l<x<2 with [Bi4-xLaxTi3O12], the BST is 0.5<x<1 with [(BaxSr1-x)TiO3], and the SBT is 0.5< with [SrxBiyTa2O9]. It may be x<1.5 and 1.5<y<3, but is not limited thereto.

The ferroelectric pattern 401p may be provided in plural numbers on the semiconductor layer 103. In FIG. 1, three ferroelectric patterns 401p are shown as examples, but the number may be two or four or more. The ferroelectric patterns 401p may be arranged in one row in the second direction (X2). A first insulating pattern 400p may be interposed between the ferroelectric pattern 401p and the barrier layer 104. A second insulating pattern 402p may be provided on the ferroelectric pattern 401p. The first insulating pattern 400p and the second insulating pattern 402p each have at least one single-layer or multi-layer structure selected from SiO, SiN, SiON, or oxide films such as Al2O3, HfOx, LaOx, and ZrOx. You can.

Referring to FIGS. 1 and 3 , a recess region RC1 may be formed in the barrier layer 104 and the semiconductor layer 103 between the ferroelectric patterns 401p. The sidewalls of the barrier layer 104, the first insulating pattern 400p, the ferroelectric pattern 401p, and the second insulating pattern 402p may be exposed on the inner wall of the recess region RC1. The inner wall and bottom surface of the recess region RC1 may be covered with a third insulating pattern 301. The third insulating pattern 301 may have a single-layer or multi-layer structure selected from SiO, SiN, SiON, or an oxide film such as Al2O3, HfOx, LaOx, or ZrOx. The recess area RC1 may extend in the first direction X1 in FIG. 1 . A portion of the semiconductor layer 103 may have a fin structure due to the recess region RC1.

A first gate electrode 204a may be located on the second insulating pattern 402p. A second gate electrode 204b may be positioned on the barrier layer 104 between the second source electrode 201sb and the second drain electrode 201db. The first gate electrode 204a and the second gate electrode 204b may each include at least one metal selected from Ti, Al, Ni, Au, Pd, Cu, Co, and Pt. The first gate electrode 204a may extend in the second direction (X2) to cover the top and side surfaces of the ferroelectric patterns 401p. The first gate electrode 204a may contact the third insulating pattern 301.

The second gate electrode 204b may extend in the second direction (X2). The second gate electrode 204b may be in direct contact with the barrier layer 104. The second gate electrode 204b may form a Schottky junction with the barrier layer 104. Therefore, since the energy band gap between the second gate electrode 204b and the barrier layer 104 is large, a gate insulating film is not required. Additionally, when the second gate electrode 204b is in direct contact with the barrier layer 104, frequency characteristics may be more advantageous.

The first gate electrode 204a is located at the midpoint between the first source electrode 201sa and the first drain electrode 201da, or is located closer to the first source electrode (201da) than the first drain electrode 201da. It can be located closer to 201sa). The second gate electrode 204b is located at the midpoint between the second source electrode 201sb and the second drain electrode 201db, or is located closer to the second source electrode (201db) than the second drain electrode 201db. It can be located closer to 201sb).

The first gate electrode 204a, the second gate electrode 204b, the wiring patterns 203, and the barrier layer 104 may be covered with a protective film 302. The protective film 302 may include an oxide film such as SiO, SiN, SiON, Al2O3, HfOx, LaOx, or ZrOx, or polyimide.

In the first region R1, the first gate electrode 204a, the first source electrode 201sa, and the first drain electrode 201da may form a first transistor TR1. In the second region R2, the second gate electrode 204b, the second source electrode 201sb, and the second drain electrode 201db may form a second transistor TR2. The first transistor TR1 may have a positive threshold voltage. The second transistor TR2 may have a negative threshold voltage. The semiconductor device 1000 including the first transistor TR1 and the second transistor TR2 may be a HEMT device.

Figure 4 shows the polarization phenomenon of the ferroelectric pattern when voltage is applied to the semiconductor device of the present invention.

Referring to FIG. 4, the semiconductor device 1000 according to this example can be bent by the flexible substrate 601. When a negative voltage (in the form of a pulse) is applied to the first gate electrode 204a, polarization may be formed in the ferroelectric pattern 401p as shown in FIG. 4. As a result, electrons present in the 2DEG layer are repelled (or depleted) by a repulsive force, and as a result, the first transistor TR1 can have a positive threshold voltage.

In order to manufacture a flexible integrated circuit using a HEMT device, a semiconductor device with a negative (-) threshold voltage and a device with a positive (+) threshold voltage must be manufactured simultaneously on one substrate. Additionally, after the integrated circuit is manufactured, the integrated circuit must be separated from the substrate and bonded to the flexible substrate. However, HEMT devices generally have a threshold voltage of only negative (-) values due to the high concentration of 2DEG. Various efforts are made to obtain a HEMT device with a positive threshold voltage, but it is very difficult to obtain the performance required for a high-output-high-frequency device due to processing difficulties or a decrease in drain current. However, in the present invention, since the first transistor TR1 includes a ferroelectric pattern 401p and uses a fin gate structure, the reduction in fin width and drain current can be minimized and a positive threshold voltage can be obtained. As a result, it is possible to implement a HEMT device with a positive threshold voltage without deterioration in output and frequency characteristics.

FIGS. 5 to 10 and FIGS. 11A to 13A are cross-sectional views sequentially showing the process of manufacturing a semiconductor device having the cross-section of FIG. 2 according to embodiments of the present invention. FIGS. 11B to 13B are cross-sectional views sequentially showing the process of manufacturing a semiconductor device having the cross-section of FIG. 3 according to embodiments of the present invention.

Referring to FIG. 5 , a first sacrificial substrate 100 including a first region (R1) and a second region (R2) is provided. The first sacrificial substrate 100 may be, for example, sapphire, silicon (Si), or silicon carbide (SiC). A separation layer 101, a buffer layer 102, a semiconductor layer 103, and a barrier layer 104 are sequentially stacked on the first sacrificial substrate 100. The separation layer 101 may be a hexagonal boron nitride layer. Hexagonal boron nitride is a 2D (2-dimensional) material, and each layer can be bonded by weak Van der Waals force. The separation layer 101 is formed in contact with the first sacrificial substrate 100 and can be used as a layer to separate the first sacrificial substrate 100 in a subsequent process. The buffer layer 102 may be a layer to alleviate differences in thermal expansion coefficient and lattice constant between the first sacrificial substrate 100 and the semiconductor layer 103. Materials of the buffer layer 102, semiconductor layer 103, and barrier layer 104 may be the same/similar to those described above. The separation layer 101, buffer layer 102, semiconductor layer 103, and barrier layer 104 are each formed by a deposition process such as CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), or SEG (Selective Epitaxial Growth). can be formed. When the separation layer 101 is hexagonal boron nitride and the buffer layer 102 includes gallium nitride, it is easy to grow gallium nitride on hexagonal boron nitride because they are the same nitride-based semiconductor material. As a result, the buffer layer 102, which is a high-quality gallium nitride epitaxial layer, can be formed.

Referring to FIG. 6, metal patterns 200 may be formed on the barrier layer 104. The metal patterns 200 may include at least one selected from Ti, Al, Ni, Au, Pd, Cu, Co, and Pt. The metal patterns 200 may define the positions of the subsequent first source electrode 201sa, first drain electrode 201da, second source electrode 201sb, and second drain electrode 201db. The metal patterns 200 may be formed through a deposition process, lift-off, and/or etching process. The metal patterns 200 may have a thickness of several nanometers to several micrometers.

Referring to FIG. 7, a rapid thermal annealing (RTA) process is performed to activate the metal patterns 200 to form a first source electrode 201sa, a first drain electrode 201da, and a second source electrode. (201sb) and a second drain electrode (201db). Through the rapid heat treatment process, metals included in the metal patterns 200 may diffuse into the barrier layer 104 and the semiconductor layer 103. This makes the above metals. An alloy is formed with the materials constituting the barrier layer 104 and the semiconductor layer 103 to form the first source electrode 201sa, the first drain electrode 201da, the second source electrode 201sb, and the second drain. An electrode 201db may be formed. The temperature of the rapid heat treatment process may be about 1000°C or less.

Referring to FIG. 8, a capping layer 300 is conformally formed on the entire surface of the barrier layer 104. For example, the capping layer 300 may have a single-layer or multi-layer structure selected from SiO, SiN, SiON, or an oxide layer such as Al2O3, HfOx, LaOx, or ZrOx. An etching process or a CMP (Chemical Mechanical Polishing) process is performed to remove a portion of the capping layer 300 to form the first source electrode 201sa, the first drain electrode 201da, the second source electrode 201sb, and the first source electrode 201sa. 2 The upper surfaces of the drain electrode 201db may be exposed.

Referring to FIG. 9, wiring patterns 203 are formed on upper surfaces of the first source electrode 201sa, the first drain electrode 201da, the second source electrode 201sb, and the second drain electrode 201db. can be formed respectively. A deposition process, lift-off and/or etching process may be performed to form the wiring patterns 203. Some of the wiring patterns 203 are also formed on the capping layer 300 to form the first source electrode 201sa, the first drain electrode 201da, the second source electrode 201sb, and the second drain electrode 201db. ) can be connected to each other.

Referring to FIG. 10, the barrier layer 104 may be exposed by patterning the capping layer 300 between the first source electrode 201sa and the first drain electrode 201da. A first insulating film 400, a ferroelectric film 401, and a second insulating film 402 may be sequentially formed on the capping layer 300. Additionally, a rapid heat treatment process can be performed to improve the polarization characteristics of the ferroelectric film 401. At this time, the rapid heat treatment process may be several hundred degrees Celsius or less.

Referring to FIGS. 11A and 11B, the second insulating film 402, the ferroelectric film 401, and the first insulating film 400 are sequentially etched to form second insulating patterns 402p and ferroelectric patterns 401p. ) and form first insulating patterns 400p. The capping layer 300 below the first insulating film 400 is removed. Then, portions of the barrier layer 104 and the semiconductor layer 103 may be etched to form recess regions R1.

Referring to FIGS. 12A and 12B, a third insulating film (not shown) is conformally stacked on the front surface of the first sacrificial substrate 100 and then etched to form the inner wall and bottom surface of the recess region RC1. A third insulating pattern 301 covering is formed. A gate film (not shown) is conformally stacked and patterned on the front surface of the first sacrificial substrate 100 to form a first gate electrode (not shown) on the second insulating pattern 402p and the third insulating pattern 301. 204a), and a second gate electrode 204b is formed on the barrier layer 104 in the second region R2. A protective film 302 is conformally stacked on the entire surface of the first sacrificial substrate 100. The protective film 302 not only protects the surface of the device, but also increases the concentration of 2DEG by reducing dangling bonds existing on the surface of the barrier layer 104, and improves the current collapse phenomenon due to drain voltage to improve high frequency characteristics. It can be raised. In addition, it also serves to increase the breakdown voltage by weakening the electric field caused by the drain voltage.

Although not shown in the drawing, rapid heat treatment may be performed to improve the interface characteristics between the barrier layer 104 and the protective film 302 after forming the protective film 302, but at a temperature that does not affect the polarization characteristics of the ferroelectric pattern 401p. It is carried out in In addition, although not shown in the drawing, a contact pad area that is part of the wiring pattern 203 may be opened to apply an external bias after forming the protective film 302. The contact pad area can be opened by etching the protective film 302 using wet, dry, or a combination of these etching methods.

A sacrificial adhesive film 500 and a second sacrificial substrate 600 may be sequentially stacked on the protective film 302. The sacrificial adhesive film 500 may be made of BCB (Benzocyclobutene) resin, wax, or the like. The second sacrificial substrate 600 may be sapphire, silicon (Si), or silicon carbide (SiC).

Referring to FIGS. 12A and 12B and 13A and 13B, the first sacrificial substrate 100 is separated from the separation layer 101. 12A and 12B, for example, when immersed in an etchant (e.g., aluminum etchant or hydrofluoric acid), the separation layer 101 made of a hexagonal boron nitride layer and the first sacrificial substrate ( As the etchant penetrates between 100, the first sacrificial substrate 100 may be separated from the separation layer 101. At this time, hexagonal boron nitride is a 2D (2-dimensional) material, and each layer is bonded by weak Van der Waals force (even though the first sacrificial substrate 100 has a large area). Separation of the first sacrificial substrate 100 can be easily performed. After separating the first sacrificial substrate 100, the substrate 601 may be bonded via the substrate adhesive layer 501.

Referring again to FIGS. 1 to 3 , the second sacrificial substrate 600 may be separated and the sacrificial adhesive film 500 may be removed to expose the protective film 302 . In this way, the semiconductor device 1000 of FIGS. 1 to 3 can be manufactured.

In the method of manufacturing a semiconductor device according to embodiments of the present invention, by using a hexagonal boron nitride layer as the separation layer 101, the buffer layer 102 can be well formed, and the first sacrificial substrate 100 can be easily formed. It can be separated. This makes it possible to manufacture semiconductor devices that are defect-free, flexible, and have improved reliability. In addition, the first sacrificial substrate 100 can be recycled, thereby reducing manufacturing costs.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims (20)

A substrate including a first region and a second region;
a buffer layer on the substrate;
a semiconductor layer on the buffer layer;
a barrier layer on the semiconductor layer;
a first source electrode, a first drain electrode, and a first gate electrode disposed on the barrier layer in the first area;
a second source electrode, a second drain electrode, and a second gate electrode disposed on the barrier layer in the second area; and
It includes a ferroelectric pattern interposed between the first gate electrode and the barrier layer,
It further includes a recess area formed on one side of the first gate electrode and on top of the barrier layer and the semiconductor layer,
A side wall of the ferroelectric is exposed at the inner wall of the recess area,
The first gate electrode covers the inner wall and bottom surface of the recess area,
A semiconductor device further comprising a third insulating pattern interposed between the first gate electrode and the semiconductor layer, between the first gate electrode and the sidewall of the barrier layer, and between the first gate electrode and the sidewall of the ferroelectric. According to claim 1,
The substrate is a flexible semiconductor device. According to claim 1,
A semiconductor device further comprising an adhesive layer interposed between the substrate and the buffer layer. According to claim 1,
A semiconductor device further comprising a hexagonal boron nitride layer interposed between the substrate and the buffer layer. According to claim 1,
The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode penetrate the barrier layer and extend into the semiconductor layer. According to claim 1,
The ferroelectric pattern is provided in plural numbers and arranged in a row along a first direction,
The first gate electrode extends in the first direction to cover side surfaces and top surfaces of the ferroelectric patterns. According to claim 1,
The first gate electrode, the first source electrode, and the first drain electrode constitute a first transistor,
The second gate electrode, the second source electrode, and the second drain electrode constitute a second transistor,
The first transistor has a positive threshold voltage,
The second transistor is a semiconductor device having a negative threshold voltage. According to claim 1,
A semiconductor device further comprising a 2-Dimensional Electron Gas (2DEG) layer located within the semiconductor layer. delete delete According to claim 1,
a first insulating pattern interposed between the barrier layer and the ferroelectric pattern;
a second insulating pattern interposed between the ferroelectric pattern and the first gate electrode; and
A semiconductor device further comprising a protective film in contact with a top surface and a side surface of the first gate electrode, a side surface of the first insulating pattern, a side surface of the ferroelectric pattern, and a side surface of the second insulating pattern. According to claim 1,
The second gate electrode is a semiconductor device in contact with the barrier layer. sequentially stacking a separation layer, a buffer layer, a semiconductor layer, and a barrier layer on a first sacrificial substrate including a first region and a second region;
forming a first source electrode and a first drain electrode on the barrier layer in the first area, and forming a second source electrode and a second drain electrode on the barrier layer in the second area;
forming a ferroelectric pattern on the barrier layer between the first source electrode and the first drain electrode;
forming a recess area by etching a portion of the barrier layer and the semiconductor layer next to the ferroelectric pattern;
forming a third insulating pattern covering the inner wall and bottom of the recess area;
forming a first gate electrode on the ferroelectric pattern and forming a second gate electrode on the barrier layer between the second source electrode and the second drain electrode; and
A method of manufacturing a semiconductor device comprising removing the first sacrificial substrate. According to claim 13,
The separation layer is a method of manufacturing a semiconductor device including a hexagonal boron nitride layer. According to claim 13,
Before removing the first sacrificial substrate,
forming a first adhesive layer on the first gate electrode and the second gate electrode; and
A method of manufacturing a semiconductor device further comprising forming a second sacrificial substrate on the first adhesive layer. According to claim 15,
Before forming the first adhesive layer,
A method of manufacturing a semiconductor device further comprising forming a protective film covering the entire surface of the first sacrificial substrate on which the first gate electrode and the second gate electrode are formed. According to claim 13,
After removing the first sacrificial substrate,
A method of manufacturing a semiconductor device further comprising forming a flexible substrate under the separation layer. According to claim 13,
After removing the first sacrificial substrate,
forming a second adhesive layer below the separation layer; and
A method of manufacturing a semiconductor device further comprising adhering a flexible substrate to the second adhesive layer. delete According to claim 13,
Forming the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode includes:
forming metal patterns spaced apart from each other on the barrier layer; and
A method of manufacturing a semiconductor device comprising performing a heat treatment process to diffuse the metal in the metal pattern to a portion of the barrier layer and the semiconductor layer.

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