KR102658792B1 - Nonvolatile memory devices and methods of operating nonvolatile memory devices - Google Patents

Abstract

A non-volatile memory device includes a memory cell array, page buffer circuit, and control circuit. The memory cell array includes a plurality of pages, and each of the pages includes a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. The page buffer circuit senses selected memory cells among the plurality of memory cells through a plurality of bit lines, and performs a first read operation and a second read operation including two sequential sensings to identify one data state. and a plurality of page buffers each having a latch for performing and storing the result of the first read operation. The control circuit controls the page buffers to store the results of the first read operation and controls the page buffers to perform the second read operation based on the valley searched according to the result of the first read operation. .

Description

Non-volatile memory device and method of operating the non-volatile memory device {NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING NONVOLATILE MEMORY DEVICES}

The present invention relates to semiconductor memory devices, and more particularly, to non-volatile memory devices and methods of operating non-volatile memory devices.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phospide (InP). am. Semiconductor memory devices are largely divided into volatile memory devices and nonvolatile memory devices.

A volatile memory device is a memory device in which the stored data is lost when the power supply is cut off. A non-volatile memory device is a memory device that retains stored data even when the power supply is cut off.

Flash memory has advantages such as low noise, low power, and fast operation speed, so it is used in various fields. For example, mobile systems such as smartphones and tablet PCs use large-capacity flash memory as a storage medium. To increase the capacity of flash memory, multi-level cells (MLC), which store at least 2-bit data in one memory cell, are being used. Since at least 2-bits of data are stored in one memory cell, the read margin of memory cells decreases, and as a result, a large number of error bits are included in the read data.

In addition, as semiconductor processes become more refined, error bits are included in data read from memory cells due to physical factors such as program disturbance and read disturbance by adjacent memory cells.

One object of the present invention is to provide a non-volatile memory device that can improve performance and data reliability.

One purpose of the present invention is to provide a method of operating a non-volatile memory device that can improve performance and data reliability.

Non-volatile memory devices according to embodiments of the present invention include a memory cell array, a page buffer circuit, and a control circuit. The memory cell array includes a plurality of pages, and each of the pages includes a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. The page buffer circuit senses selected memory cells among the plurality of memory cells through a plurality of bit lines, and performs a first read operation and a second read operation including two sequential sensings to identify one data state. and a plurality of page buffers each having a latch for sequentially storing the results of the two sensing operations. The control circuit controls the page buffers to store the result of the first read operation, initializes the latch after completion of the first read operation, and based on the valley searched according to the result of the first read operation. The page buffers are controlled to perform the second read operation.

A memory cell array comprising a plurality of pages according to embodiments of the present invention, wherein each of the plurality of pages includes a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. In a method of operating a non-volatile memory device, a first read operation is performed including two sensing to identify the data state of one of the memory cells selected from the plurality of memory cells through a plurality of bit lines, and the first read operation is performed. A second read operation is performed to identify the one data state based on the valley searched according to the result of the operation. The results of the two sensing operations are sequentially stored in one latch of each page buffer connected to each of the plurality of bit lines.

A memory cell array comprising a plurality of pages according to embodiments of the present invention, wherein each of the plurality of pages includes a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. In a method of operating a non-volatile memory device, a read setting of the non-volatile memory device is determined in response to a command and an address from a memory controller controlling the non-volatile memory device, and when the read setting indicates a normal read operation, Data bits stored in selected memory cells among the plurality of memory cells are detected according to normal read conditions, and when the read setting indicates a valley search read operation, an on-chip valley search read operation is performed on the selected memory cells. The on-chip valley search read operation searches for a valley of the threshold voltage distributions and detects data bits stored in the selected memory cells based on the searched valley.

According to embodiments of the present invention, in an on-chip valley search read operation, sensing nodes are sequentially connected during a bitline development period having different start points in the first group of page buffers and the second group of page buffers. senses twice, searches for a valley by counting the number of on-cells according to the sensing result, and performs a read operation based on the discovered valley, thereby reducing read errors and improving performance by the on-chip itself. there is.

1 is a block diagram showing the configuration of a memory system according to embodiments of the present invention.
FIG. 2 is a block diagram showing the configuration of a memory controller in the memory system of FIG. 1 according to embodiments of the present invention.
FIG. 3 is a block diagram illustrating a non-volatile memory device in the memory system of FIG. 1 according to embodiments of the present invention.
FIG. 4 is a block diagram showing an example of a memory cell array in the non-volatile memory device of FIG. 3.
FIG. 5 is a circuit diagram showing one (BLKi) of the memory blocks (BLK1 to BLKz) of FIG. 4.
Figure 6 is a block diagram showing a non-volatile memory device according to embodiments of the present invention.
FIG. 7 is a circuit diagram showing one of a plurality of page buffers included in the page buffer circuit of FIG. 3.
FIG. 8 is a block diagram showing the configuration of a control circuit in the non-volatile memory device of FIG. 3 according to embodiments of the present invention.
FIG. 9 is a block diagram showing the configuration of a read control circuit in the control circuit of FIG. 8 according to embodiments of the present invention.
FIG. 10 is a block diagram showing the configuration of a voltage generator in the non-volatile memory device of FIG. 3 according to embodiments of the present invention.
FIG. 11 shows the configuration of a page buffer circuit in the non-volatile memory device of FIG. 3 according to embodiments of the present invention.
FIGS. 12 and 13 are diagrams for explaining a plurality of threshold voltage distributions of one page of the memory cell array of FIG. 3 .
Figure 14 is a flowchart showing a method of operating a non-volatile memory device according to embodiments of the present invention.
FIG. 15 is a flowchart showing the on-chip valley search read operation in FIG. 14.
FIG. 16 is a diagram for explaining FIGS. 14 and 15.
Figure 17 is a timing diagram showing an example of an on-chip search read operation according to embodiments of the present invention.
Figures 18 and 19 are timing diagrams showing examples of on-chip search read operations according to embodiments of the present invention.
Figure 20 shows the status of latches in the second group of page buffers.
Figure 21 shows the status of latches in the first group of page buffers.
Figures 22A to 22C show results according to the first read operation of the on-chip valley search read.
Figure 23 is a diagram showing a general reading method of a memory cell.
Figure 24 is a timing diagram illustrating an example of an on-chip valley search read operation applied to an MSB page according to embodiments of the present invention.
Figure 25 is a flowchart showing a method of operating a non-volatile memory device according to embodiments of the present invention.
Figure 26 is a block diagram showing a solid state disk (SSD) or solid state drive (SSD) according to embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

1 is a block diagram showing the configuration of a memory system according to embodiments of the present invention.

Referring to FIG. 1 , a memory system (or storage device) 10 may include a memory controller 100 and at least one non-volatile memory device 200.

In an embodiment, each of the memory controller 100 and the non-volatile memory device 200 may be provided as one chip, one package, one module, etc. Alternatively, the memory controller 100 and the non-volatile memory device 200 may be mounted based on various packages and provided as a storage device such as a memory card.

The non-volatile memory device 200 may perform erase, write, or read operations under the control of the memory controller 100. To this end, the non-volatile memory device 200 receives commands (CMD), addresses (ADDR), and data (DATA) through input/output lines. Additionally, the non-volatile memory device 200 may receive a control signal (CTRL) through a control line. Additionally, the non-volatile memory device 200 may receive power (PWR) from the memory controller 100.

Memory cells included in the non-volatile memory device 200 have physical characteristics in which threshold voltage distribution changes due to factors such as program elapsed time, temperature, program disturbance, and read disturbance. That is, errors may occur in data stored in the non-volatile memory device 200 due to the above-mentioned factors. The memory controller 100 may use various error correction techniques to correct these errors. For example, the memory controller 100 may include an error correction code (ECC) engine 120 and a read management module 131.

During a read operation on the non-volatile memory device 200, the memory controller 100 may read data stored in the first page of the non-volatile memory device 200 based on a default read voltage set. . Illustratively, the basic read voltage set refers to predetermined read voltages. The ECC engine 120 can detect and correct errors included in data read from the non-volatile memory device 200. By way of example, the ECC engine 120 may be provided in hardware form.

For example, error bits that exceed the error correction capability of the ECC engine 120 may be included in the data due to the factors described above or other external factors. In this case, the ECC engine 120 will not be able to correct errors contained in the data. These errors are called ‘UECC (Uncorrectable Error Correction Code) errors’.

For example, if data read based on the basic read voltage set includes a UECC error, the read management module 131 may adjust the read voltage set of the non-volatile memory device 200. The memory controller 100 may transmit an address (ADDR), a command (CMD), and a control signal (CTRL) so that the non-volatile memory device 200 performs a read operation based on the adjusted read voltage set. For example, information about the adjusted read voltage set may be included in the control signal (CTRL) or command (CMD). The ECC engine 120 can detect and correct errors in read data by using an adjusted read voltage set.

For example, the read management module 131 may adjust the read voltage set a predetermined number of times, and the ECC engine 120 may detect and correct errors in the read data based on the adjusted read voltage set. That is, the memory controller 100 may adjust the read voltage set, read data based on the adjusted read voltage set, and repeatedly perform error correction of the read data a predetermined number of times.

For example, when an error in data read during the above-described repetitive operation is corrected, the memory controller 100 may output the corrected data to an external host. For example, while a read operation is repeatedly performed by the read management module 131, read data or specific page data of the read data may be stored in the buffer 130 of FIG. 2. The buffer 130 may be SRAM.

During a read operation on the selected first page of the memory cell array, the non-volatile memory device 200 searches for a valley by performing a first read operation including two sensings, and performs a second read operation based on the searched valley. By performing a read operation, the read voltage level can be independently adjusted according to changes in the threshold voltage distribution without the intervention of the memory controller 100.

FIG. 2 is a block diagram showing the configuration of a memory controller in the memory system of FIG. 1 according to embodiments of the present invention.

Referring to FIGS. 1 and 2 , the memory controller 100 includes a processor 110, an ECC engine 120, a buffer 130, a read management module 131, and a randomizer 140 that are connected to each other through a bus 105. ), a host interface 150, a ROM 160, and a non-volatile memory interface 170.

Since the ECC engine 120, buffer 130, and read management module 131 have been described with reference to FIG. 1, detailed description thereof will be omitted.

The processor 110 controls overall operations of the memory controller 100. For example, the read management module 131 is provided in software form and may be stored in the buffer 130. The read management module 131 stored in the buffer 130 may be driven by the processor 110. The ROM 160 may store various information required for the memory controller 100 to operate in the form of firmware.

The randomizer 140 may randomize data to be stored in the non-volatile memory device 200. For example, the randomizer 140 may randomize data to be stored in the non-volatile memory device 200 on a word line basis.

For example, data randomizing refers to processing data so that memory cells connected to one word line have the same ratio of program states. For example, when the memory cells connected to one word line are multi-level cells (MLC; Multi Level Cell) that each store 2-bit data, each of the memory cells is in an erase state and first to third program states. It will have one of the following states:

At this time, the randomizer 140 determines the number of memory cells in an erase state among the memory cells connected to one word line, the number of memory cells in the first program state, the number of memory cells in the second program state, and Data may be randomized so that the number of memory cells having the third program state is the same. That is, memory cells storing randomized data will have substantially the same number of program states. By way of example, the randomizer 140 may derandomize data read from the non-volatile memory device 200.

For example, the randomizer 140 may randomize page data. By way of example, the configuration of the ideal randomizer 140 has been described for concise explanation. However, the technical idea of the present invention is not limited to this, and the randomizer 140 actually includes the number of memory cells in an erase state among the memory cells connected to one word line, the number of memory cells in the first program state, Data may be randomized so that the number of memory cells having the second program state and the number of memory cells having the third program state are substantially close to the same value. That is, memory cells storing actual randomized data may have a substantially similar number of program states.

The memory controller 100 may communicate with the host through the host interface 150. For example, the host interface 150 may be provided as at least one of various interfaces such as Universal Serial Bus (USB), Nonvolatile Memory-express (NVMe), and Universal Flash Storage Interface (UFS). The memory controller 100 may communicate with the non-volatile memory device 200 through the non-volatile memory interface 170.

FIG. 3 is a block diagram illustrating a non-volatile memory device in the memory system of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 3, the non-volatile memory device 200 includes a memory cell array 300, an address decoder 405, a page buffer circuit 410, a data input/output circuit 480, a cell counter 490, and a control circuit ( 500) and a voltage generator 700.

The memory cell array 300 may be connected to the address decoder 405 through a string select line (SSL), a plurality of word lines (WLs), and a ground select line (GSL). Additionally, the memory cell array 300 may be connected to the page buffer circuit 410 through a plurality of bit lines (BL1 to BL2n). The memory cell array 300 may include a plurality of memory cells connected to a plurality of word lines (WLs) and a plurality of bit lines (BLs).

In an embodiment, the memory cell array 300 may be a three-dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array 300 may include vertical memory cell strings including a plurality of memory cells that are formed by stacking each other.

FIG. 4 is a block diagram showing an example of a memory cell array in the non-volatile memory device of FIG. 3.

Referring to FIG. 4, the memory cell array 300 includes a plurality of memory blocks BLK1 to BLKz. In an embodiment, memory blocks (BLK1 to BLKz, z is a natural number of 3 or more) are selected by the address decoder 405 shown in FIG. 3. For example, the address decoder 405 may select a memory block (BLK) corresponding to a block address among the memory blocks (BLK1 to BLKz).

FIG. 5 is a circuit diagram showing one (BLKi) of the memory blocks (BLK1 to BLKz) of FIG. 4.

The memory block BLKi shown in FIG. 5 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 5 , the memory block BLKi may include a plurality of memory cell strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL.

Each of the plurality of memory cell strings (NS11 to NS33) may include a string selection transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground selection transistor (GST). The string select transistor (SST) may be connected to the corresponding string select line (SSL1, SSL2, SSL3). A plurality of memory cells (MC1, MC2, ..., MC8) may each be connected to corresponding word lines (WL1, WL2, ..., WL8). The ground select transistor (GST) may be connected to the corresponding ground select line (GSL1, GSL2, GSL3). The string select transistor (SST) may be connected to the corresponding bit lines (BL1, BL2, BL3), and the ground select transistor (GST) may be connected to the common source line (CSL). Word lines (eg, WL1) of the same height may be connected in common, and ground selection lines (GSL1, GSL2, GSL3) and string selection lines (SSL1, SSL2, SSL3) may be separated from each other.

Referring again to FIG. 3, the control circuit 500 receives a command signal (CMD) and an address signal (ADDR) from the memory controller 100, and generates a non-volatile signal based on the command signal (CMD) and the address signal (ADDR). The erase loop, program loop, and read operations of the memory device 200 can be controlled. Here, the program loop may include a program operation and a program verify operation, and the erase loop may include an erase operation and an erase verify operation.

For example, the control circuit 500 may include control signals (CTLs) for controlling the voltage generator 700 and a page buffer control signal (PCTL) for controlling the page buffer circuit 410 based on the command signal (CMD). ) can be generated, and a row address (R_ADDR) and a column address (C_ADDR) can be generated based on the address signal (ADDR). The control circuit 500 may provide a row address (R_ADDR) to the address decoder 405 and a column address (C_ADDR) to the data input/output circuit 420.

The address decoder 405 may be connected to the memory cell array 300 through a string select line (SSL), a plurality of word lines (WLs), and a ground select line (GSL). During a program operation or a read operation, the address decoder 405 determines one of the plurality of word lines (WLs) as the selected word line based on the row address (R_ADDR) provided from the control circuit 500, and selects a plurality of words. Among the lines WLs, the remaining word lines excluding the selected word line may be determined as non-selected word lines.

The voltage generator 700 may generate word line voltages VWLs necessary for operation of the non-volatile memory device 200 based on control signals CTLs provided from the control circuit 500. Word line voltages VWLs generated from the voltage generator 700 may be applied to a plurality of word lines WLs through the address decoder 430.

For example, during an erase operation, the voltage generator 700 may apply an erase voltage to a well of a memory block and a ground voltage to all word lines of the memory block. During an erase verification operation, the voltage generator 700 may apply an erase verification voltage to all word lines of one memory block or may apply an erase verification voltage on a word line basis. For example, during a program operation, the voltage generator 700 may apply a program voltage to selected word lines and a program pass voltage to unselected word lines. Additionally, during a program verification operation, the voltage generator 700 may apply a program verification voltage to selected word lines and a verification pass voltage to unselected word lines. Additionally, during a read operation, the voltage generator 700 may apply a basic read voltage to selected word lines and a read pass voltage to unselected word lines.

The page buffer circuit 410 may be connected to the memory cell array 300 through a plurality of bit lines (BLs). The page buffer circuit 410 may include a plurality of page buffers. In an embodiment, the page buffers may be divided into a first group of page buffers connected to a first group of bit lines and a second group of page buffers connected to a second group of bit lines. The page buffer circuit 410 may temporarily store data to be programmed in a page selected during a program operation, and may temporarily store data read from the selected page during a read operation.

The first group of page buffers and the second group of page buffers may each include at least one latch, and a first read operation and a second read operation including two sensing to identify the data state of the selected memory cells. The action can be performed. The page buffers of the first group and the page buffers of the second group simultaneously perform sequential first and second sensing in a development section starting at different development start points, and the results of the second sensing are stored in a cell counter. It can be provided at (490).

The cell counter 490 is a control circuit that counts the results of sensing provided from each of the first group of page buffers and the second group of page buffers and determines the number (nC) of memory cells having a threshold voltage in a specific threshold voltage range. It can be provided at (500). The control circuit 500 compares the number (nC) of memory cells provided by the cell counter 490, searches for a valley of the threshold voltage distribution based on the comparison result, and performs a second read operation based on the searched valley. The page buffer circuit 410 can be controlled to perform.

The data input/output circuit 420 may be connected to the page buffer circuit 410. During a program operation, the data input/output circuit 420 receives program data (DATA) from the memory controller 100 and stores the program data (DATA) in the page buffer based on the column address (C_ADDR) provided from the control circuit 500. It can be provided to the circuit 410. During a read operation, the data input/output circuit 420 provides read data (DATA) stored in the page buffer circuit 410 to the memory controller 100 based on the column address (C_ADDR) provided from the control circuit 500. You can.

Figure 6 is a block diagram showing a non-volatile memory device according to embodiments of the present invention.

While FIG. 3 is a block diagram simultaneously showing several components connected to the non-volatile memory device 200, FIG. 6 shows a plurality of planes constituting the memory cell array 300 of FIG. 3 and the page buffer circuit 410. and a block diagram showing the connection relationship of the control circuit 500. Descriptions overlapping with FIG. 3 are omitted.

Referring to FIGS. 3 and 6 , the memory cell array 300 may include a plurality of planes (PLN1 to PLN16). The page buffer circuit 410 may include a plurality of sub-page buffer groups (SPBG1 to SPBG16) corresponding to the planes (PLN1 to PLN16). The page buffers included in the sub-page buffer groups (SPBG9 to SPBG16) may constitute the first group of page buffers (PBG1), and the page buffers included in the sub-page buffer groups (SPBG1 to SPBG8) may form the second group of page buffers (PBG1). You can configure group page buffers (PBG2). The control circuit 500 applies a first bit line set-up signal (BLSTP1) to the first group of page buffers (PBG1) and a second bit line set-up signal to the second group of page buffers (PBG2). By applying the signal BLSTP2, the first group of page buffers PBG1 starts bit line development at a first time point, and the second group of page buffers PBG2 starts bit line development at a second time point later than the second time point. You can start bitline development from .

FIG. 7 is a circuit diagram showing one of a plurality of page buffers included in the page buffer circuit of FIG. 3.

Referring to FIG. 7 , the page buffer (PB) may include a precharge circuit 430, a switch circuit 435, and a sensing and latch circuit 440.

The precharge circuit 430, switch circuit 435, and detection and latch circuit 440 of the page buffer (PB) operate in response to the control signal (PBC) of the control circuit 500. The control signal (PBC) is the load signal (LOAD), bitline set-up signal (BLSTP1), bitline voltage control signal (BLSHF), bitline select signal (BLSLT), shield signal (SHLD), and refresh signal (RFR). Includes etc.

The precharge circuit 430 supplies the precharge voltage (Vdd) to the sensing node (SO). The precharge circuit 430 includes a first PMOS transistor 431 and a second PMOS transistor 432 connected in series between the precharge voltage (Vdd) and the sensing node (SO). The first PMOS transistor 431 may be turned on/off in response to the load signal LOAD, and the second PMOS transistor 432 may be turned on/off in response to the bit line set-up signal BLSTP1.

The switch circuit 435 may include transistors M1, M2, and M3. The transistor M1 precharges the bit line BL to a predetermined voltage level in response to the bit line voltage control signal BLSHF. The transistor M2 selects the bit line BL in response to the bit line selection signal BLSLT. The transistor M3 discharges the bit line BL in response to the shield signal SHLD.

The sensing and latch circuit 440 detects the voltage level of the sensing node SO. Data is latched according to the detected voltage level of the sensing node (SO). The sensing and latch circuit 440 may include a latch 441 and NMOS transistors MT1 to MT4.

The latch 441 may include inverters INV1 and INV2. The NMOS transistors MT1 and MT3 are connected between the first node N11 and the ground voltage, and the NMOS transistors MT2 and MT4 are connected between the second node N12 and the ground voltage. A set signal (SET) is applied to the gate of the NMOS transistor (MT1), a reset signal (RST) is applied to the gate of the NMOS transistor (MT2), and a refresh signal (RFR) is applied to the gate of the NMOS transistor (MT3). is applied, and the gate of the transistor MT4 may be connected to the sensing node SO. The sensing and latch circuit 440 operates in response to the control signals SET, RST, and RFR included in the control signal PBC.

FIG. 8 is a block diagram showing the configuration of a control circuit in the non-volatile memory device of FIG. 3 according to embodiments of the present invention.

Referring to FIG. 8 , the control circuit 500 may include a command decoder 510, an address buffer 520, a control signal generator 530, and a read control circuit 540.

The command decoder 510 may decode the command signal (CMD) and provide the decoded command (D_CMD) to the control signal generator 530, and when the decoded command (D_CMD) is a read command, the decoded command (D_CMD) ) can be provided to the read control circuit 540.

The address buffer 520 receives the address signal (ADDR), and among the address signals (ADDR), the row address (R_ADDR) is provided to the address decoder 430, and the column address (C_ADDR) is provided to the data input/output circuit 420. You can.

The read control circuit 540 receives the number (nC) of memory cells in a specific threshold voltage region from the cell counter 490, and receives a first number of memory cells in the first region and a second number of memory cells in the second region. may be compared, and a decision signal DS according to the result of the comparison may be provided to the control signal generator 530.

The control signal generator 530 receives the decoded command (D_CMD) and the decision signal (DS), and generates control signals (CTLs) based on the operation indicated by the decoded command (D_CMD) to generate the voltage generator 600. can be provided. The control signal generator 530 may also provide the page buffer control signal PCTL to the page buffer circuit 410 according to the comparison result indicated by the decision signal DS.

FIG. 9 is a block diagram showing the configuration of a read control circuit in the control circuit of FIG. 8 according to embodiments of the present invention.

Referring to FIG. 9 , the read control circuit 540 may include a decision logic 541 and a register 542.

The decision logic 541 determines a first number (nC1) of memory cells according to the second sensing result of the first group of page buffers and a second number (nC1) of memory cells according to the second sensing result of the second group of page buffers. ) is received, the first number (nC1) and the second number (nC2) are compared, the result of the comparison is compared with at least one reference value (REF), and a decision signal (DS) is sent to the control signal generator 530. can be provided. The register 543 may store at least one reference value (REF).

For example, when the difference between the first number (nC1) and the second number (nC2) is within the reference value (REF), the decision logic 541 sends a decision signal (DS) indicating this to the control signal generator 530. to provide. When the difference between the first number (nC1) and the second number (nC2) is greater than the reference value (REF), and the first number (nC1) is greater than the second number (nC2), the decision logic 541 generates a decision signal indicating this. (DS) is provided to the control signal generator 530. When the difference between the first number (nC1) and the second number (nC2) is greater than the reference value (REF) and the first number (nC1) is smaller than the second number (nC2), the decision logic 541 generates a decision signal indicating this. (DS) is provided to the control signal generator 530. The decision signal DS may include a plurality of bits to represent the above-described cases.

FIG. 10 is a block diagram showing the configuration of a voltage generator in the non-volatile memory device of FIG. 3 according to embodiments of the present invention.

Referring to FIG. 10 , the voltage generator 700 may include a high voltage generator 710 and a low voltage generator 730. In an embodiment, the voltage generator 700 may further include a negative voltage generator 750.

The high voltage generator 710 responds to the first control signal (CTL1) and generates a program voltage (VPGM), a program pass voltage (VPPASS), a verification pass voltage (VVPASS), and a read pass voltage ( VRPASS) and erase voltage (VRES) can be generated.

The program voltage (VPGM) is applied to the selected word lines, the program pass voltage (VPPASS), program verify pass voltage (VVPASS), and read pass voltage (VRPASS) are applied to the unselected word lines, and the erase voltage (VRES) is applied to the selected word lines. It can be applied to a well of a memory block. The first control signal CTL1 may include a plurality of bits and indicate an operation indicated by the decoded command D_CMD.

The low-voltage generator 730 generates a program verification voltage (VPV), a basic read voltage (VRD), and an erase verification voltage (VEV) according to the operation indicated by the command (CMD) in response to the second control signal (CTL2). You can. Program verification voltage (VPV), basic read voltage (VRD), and erase verification voltage (VEV) may be applied to the selected word line depending on the operation. The second control signal CTL2 may include a plurality of bits and indicate an operation indicated by the decoded command D_CMD.

The negative voltage generator 750 generates a program verification voltage (VPV'), a read voltage (VRD'), and an erase verification having negative levels according to the operation indicated by the command (CMD) in response to the third control signal (CTL3). A voltage (VEV') can be generated. The third control signal CTL3 may include a plurality of bits and indicate an operation indicated by the decoded command D_CMD.

FIG. 11 shows the configuration of a page buffer circuit in the non-volatile memory device of FIG. 3 according to embodiments of the present invention.

Referring to FIG. 11 , the page buffer circuit 410 may include a plurality of page buffers 411 to 42n connected to the memory cell array 300 through bit lines BL1 to BL2n. Each of the plurality of page buffers 411 to 412n may include a sense latch (SL), data latches (DL1 to DL3), and a cache latch (CL). Among the page buffers 411 to 42n, the page buffers 411 to 41n may form the second group of page buffers PBG2, and the page buffers 41(n+1) to 42n may form the first group of page buffers PBG2. Group page buffers (PBG1) can be configured. The page buffers 411 to 412n may use only the detection latch SL in the first read operation and the second read operation.

FIGS. 12 and 13 are diagrams for explaining a plurality of threshold voltage distributions of one page of the memory cell array of FIG. 3 .

For concise explanation, the memory cells included in the non-volatile memory device 200 are triple level cells (TLC) that store 3 bits, and the read voltage set for determining the program state of the memory cells is 7. It is assumed to include read voltages.

Referring to FIG. 12 , memory cells included in the non-volatile memory device 200 may have one of an erase state (E) and first to seventh program states (P1 to P7). The non-volatile memory device 200 may determine program states of memory cells based on basic read voltage sets (VRD1 to VRD7) under the control of the memory controller 100 and output read data. By way of example, the voltage levels of the basic read voltage sets VRD1 to VRD7 may be predetermined voltage levels considering the characteristics of memory cells. For example, the voltage levels of the basic read voltage sets VRD1 to VRD7 may be levels determined in consideration of the threshold voltage distribution immediately after the memory cells are programmed.

Next, referring to FIG. 13 , the threshold voltage distribution of memory cells may change as time passes after the memory cells are programmed due to physical characteristics of the memory cells or external factors, as shown in FIG. 13 . If a read operation is performed based on the basic read voltage set (VRD1 to VRD7), the read data will contain errors.

In order to reduce errors included in such read data, the non-volatile memory device 200 provides a development system in which the first group of page buffers (PBG1) and the second group of page buffers (PBG2) have different development points. A first read operation including first sensing and second sensing may be performed simultaneously from the lop section, and a second read operation may be performed on-chip based on the valley found as a result of the first read operation.

FIG. 14 is a flowchart showing a method of operating a non-volatile memory device according to embodiments of the present invention, FIG. 15 is a flowchart showing an on-chip valley search read operation in FIG. 14, and FIG. 16 shows FIGS. 14 and 15. This is a drawing for explanation.

FIG. 16 shows threshold voltage distributions ST1 and ST2 that are adjacent to each other and partially overlap among the plurality of threshold voltage distributions in FIG. 13 .

2 to 16, a memory cell array 300 includes a plurality of pages, each of the pages having a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. ) In the method of operating the non-volatile memory device 200, the control circuit 500 performs a requested read operation based on the command (CMD) and address (ADDR) received from the memory controller 100. Check the settings (S110). The control circuit 500 checks whether the mode of the read operation is normal read or on-chip valley search read (S120).

If the requested read operation is a normal read (No in S120), the control circuit 500 provides a read voltage to identify one state according to the normal read condition, and uses the voltage generator 700 and the voltage generator 700 to perform one-time sensing. The page buffer circuit 410 is controlled (S130). The page buffer circuit 410 latches the sensed data (S140).

If the requested read operation is an on-chip valley search read (Yes in S120), the control circuit 500 provides a read voltage to identify one state, and the first group of page buffers PBG1 and the second group The page buffers (PBG2) of the group perform a first read operation including first sensing and second sensing simultaneously from development sections starting at different points in time, and read data in the valley discovered as a result of the first read operation. Based on this, the voltage generator 700 and the page buffer circuit 410 are controlled to perform the second read operation (S200). That is, the control circuit 500 controls the voltage generator 700 and the page buffer circuit 410 to perform an on-chip valley search read operation.

The control circuit 500 determines whether the read operation has been completed (S150). When the read operation is completed (Yes in S150), the sensed data is output to the memory controller 100 (S160). If the read operation is not completed (No in S150), the process returns to step S120.

14 to 16, in order to perform on-chip valley search read (S200), the control circuit 500 controls the voltage generator 700 and the address decoder 405 to select where the selected memory cells are connected. A basic read voltage (first read voltage, VRDD) is applied to the word line. The control circuit 500 develops the bit lines of the first group from a first point in time by applying the first bit line set-up signal (SPT1) to the page buffers (PBG1) of the first group, and develops at least the first group of bit lines. In the lob section, the first sensing and the second sensing are sequentially performed to sense the data states of the first memory cells belonging to the region RG3 (S220).

The control circuit 500 applies the second bit line set-up signal (SPT2) to the page buffers (PBG2) of the second group to develop the bit lines of the second group from a second time point later than the first time point. , the data states of memory cells belonging to the region RG2 are sensed by sequentially performing the third sensing and the fourth sensing in a second development section that is at least smaller than the first development section (S230). The first sensing and the third sensing can be performed simultaneously, and the second sensing and the fourth sensing can be performed simultaneously. The regions RG3 and RG4 may belong to the threshold voltage distribution ST2, and the regions RG1 and RG2 may belong to the threshold voltage distribution ST1.

The cell counter 490 counts a first number (nC1) and a second number (nC2) of memory cells belonging to the regions (RG3, RG2) based on the data states of the memory cells in the regions (RG3, RG2). Thus, the first number (nC1) and the second number (nC2) of cells are provided to the control circuit 500 (S240). The control circuit 500 searches for a valley based on a comparison of the first number (nC1) and the second number (nC2) and performs a second read operation based on the searched valley.

By the first sensing, memory cells belonging to the regions RG3 and RG4 are sensed as off cells, and by the second sensing, only memory cells belonging to the region RG3 are sensed as off cells. Additionally, memory cells belonging to the regions R2, RG3, and RG4 are sensed as off cells by the third sensing, and only memory cells belonging to the region RG2 are sensed as off cells by the fourth sensing.

Figure 17 is a timing diagram showing an example of an on-chip search read operation according to embodiments of the present invention.

Referring to FIG. 17, an on-chip valley search read operation can be performed by sequentially latching sensing nodes at the same time points during different development sections and storing the sensing results.

A precharge operation is performed from time T0 to time T1. For precharge, the bit lines (BL1 to BL2n) and sensing nodes (SO) connected to the page buffers (PB1 to PB2n) are charged. When the control signals (SHLD, BLST), load signal (LOAD), and bit line set-up signals (BLSTP1, BLSTP2) are activated, the sensing node (SO) and bit lines (BL1 to BL2n) are freed to a specific level. It is occupied.

When the load signal LOAD and the first bit line set-up signal BLST1 are deactivated at a high level at time T1, the PMOS transistors of the precharge circuit of each of the page buffers PBG1 of the first group are turned off, Current supply from the power supply voltage (Vdd) to the sensing node (SO) is blocked. In addition, when the second bit line set-up signal BLST2 is deactivated at a high level at time T2 after time T1, the PMOS transistors of the precharge circuit of each of the page buffers PBG2 of the second group are turned off, Current supply from the power supply voltage (Vdd) to the sensing node (SO) is blocked.

From this point on, the level of each sensing node (SO) of the first group of page buffers (PBG1) and the level of each of the sensing nodes (SO) of the second group of page buffers (PBG2) determine whether the memory cell is on/off. It changes depending on the size of the current flowing through the bit line (BL). When the selected memory cell is an on cell, the current flowing through the bit line is relatively large. Accordingly, the level of the sensing node (SO) decreases relatively quickly. On the other hand, when the selected memory cell is an off-cell, the level of the sensing node (SO) will maintain an almost constant level.

However, memory cells distributed around the valley are memory cells located at the boundary between on-cell and off-cell. Accordingly, identification of on-cell or off-cell for these cells may vary depending on the development time. That is, even if the development time is slightly reduced, the memory cells distributed around the scatter valley may be identified as off-cells. On the other hand, even if the development time is slightly increased, the memory cells distributed around the scatter valley can be identified as on-cells.

In other words, reducing the development time for memory cells with a threshold voltage similar to the read voltage provided to the word line can provide a sensing effect by lowering the read voltage. In other words, simultaneously sensing the sensing node (SO) in development sections with different development times by varying the development start timing has the same effect as precharging and sensing the bit line by varying the word line voltage.

Figures 18 and 19 are timing diagrams showing examples of on-chip search read operations according to embodiments of the present invention.

FIG. 18 shows the operation of the first group of page buffers, and FIG. 19 shows the operation of the second group of page buffers.

Referring to FIGS. 18 and 19, the first group of page buffers PBG1 precharges the sensing node SO from T0 to T1, and develops the first group of bit lines from T1 to T4. I order it. In the second group of page buffers (PBG2), the sensing node (SO) is precharged from time T0 to T1, and the bit lines of the first group are developed from time T2 to T4, which is later than time T1.

The first group of page buffers PBG1 performs first sensing at time T3 and second sensing at time T5. The second group of page buffers (PBG2) performs third sensing at time T3 and fourth sensing at time T5. Accordingly, the trip level TL1 of the sensing node SO of the first group of page buffers PBG1 corresponds to the first voltage V11, and the trip level of the sensing node SO of the page buffers PBG2 of the second group corresponds to the first voltage V11. The trip level (TL1) of ) corresponds to the second voltage (V12). The first voltage (V11) is smaller than the second voltage (V12).

The first group of page buffers (PBG1) and the second group of page buffers (PBG2) precharge the sensing node (SO) again at time T6 and T7, and the bit line of the first group from time T7 to T8 and developing the second group of bit lines, a refresh signal (RFR) is applied to the transistor (TM3) of the latch and detection circuit 440 between time points T7 and T8, and a reset signal (RFR) is applied to the transistor (TM2) RST) is applied to reset the latch 441. The first group of page buffers PBG1 and the second group of page buffers PBG2 may detect the sensing node SO between time points T8 and T9 and output data.

18 and 19, VSO represents the voltage level of the sensing node (SO), and reference numbers 611 to 614 correspond to bit lines respectively connected to memory cells belonging to the regions RG1 to RG4 in FIG. 16. Indicates the voltage of the connected sensing node (SO). 18 and 19, from time point T0 to time point T6 may correspond to the first read operation, and from time point T6 to time T9 may correspond to the second read operation.

FIG. 20 shows the state of latches in the second group of page buffers, and FIG. 21 shows the state of the latch in the first group of page buffers.

20 and 21, the latch 441 of each page buffer is set to high level.

Referring to FIG. 20, when third sensing is performed by activating the reset signal (RST) in the page buffers (PBG2) of the second group, the latch connected to the on cells maintains a high level, and the latch connected to the off cells The latch is flipped to low level. When the fourth sensing is performed by activating the set signal SET in the page buffers PBG2 of the second group, the latch connected to the on cells belonging to the region RG2 is maintained at a low level, and the latch connected to the off cells is maintained at a low level. The latch flips to high level. Accordingly, the second number (nC2) can be calculated by counting the number of cells in which the latch value is at the low level as a result of the fourth sensing.

Referring to FIG. 21, when the first sensing is performed by activating the reset signal (RST) in the page buffers (PBG1) of the first group, the latch connected to the on cells maintains a high level, and the latch connected to the off cells The latch is flipped to low level. When the second sensing is performed by activating the set signal SET in the first group of page buffers PBG1, the latch connected to the on cells belonging to the region RG3 is maintained at a low level, and the latch connected to the off cells is maintained at a low level. The latch flips to high level. Accordingly, the first number (nC1) can be calculated by counting the number of cells in which the latch value is at the low level as a result of the second sensing.

Figures 22A to 22C show results according to the first read operation of the on-chip valley search read.

Referring to Figure 22a, as a result of the second and fourth sensing, the difference between the first number (nC1) and the second number (nC2) is greater than the reference value (REF), and the first number (nC1) is greater than the second number (nC1). nC2), this means that the valley is smaller than the threshold voltage corresponding to the basic read voltage (VRDD), so the control circuit 500 applies a second read voltage greater than the basic read voltage (VRDD) to the selected word line. By applying the second read operation, the second read operation is performed.

Referring to FIG. 22b, as a result of the second sensing and the fourth sensing, if the difference between the first number (nC1) and the second number (nC2) is less than or equal to the reference value (REF), this means that the valley corresponds to the basic read voltage (VRDD). Since this means that it is located near the threshold voltage, the control circuit 500 applies the basic read voltage VRDD to the selected word line to perform the second read operation.

Referring to Figure 22c, as a result of the second sensing and the fourth sensing, the difference between the first number (nC1) and the second number (nC2) is greater than the reference value (REF), and the first number (nC1) is larger than the second number (nC1). nC2), this means that the valley is greater than the threshold voltage corresponding to the basic read voltage (VRDD), so the control circuit 500 applies a second read voltage smaller than the basic read voltage (VRDD) to the selected word line. Thus, the second read operation is performed.

Figure 23 is a diagram showing a general reading method of a memory cell.

Referring to FIG. 23, a page-by-page read method of a triple level cell (TLC) capable of storing 3 bits of data per cell is shown.

To read the least significant bit (LSB) page, a read voltage (VRD1) is provided to the word lines of the selected memory cells. The on/off status of the read voltage VRD1 is sensed and stored in one of a plurality of latches. Logic '1' will be latched as a result of sensing a memory cell (on-cell) with a threshold voltage lower than the read voltage (VRD1). Logic '0' will be latched as a result of sensing a memory cell (on-cell) with a threshold voltage equal to or higher than the read voltage VRD1.

Subsequently, a read voltage VRD5 will be provided to the word lines of the selected memory cells. And the previously latched logic '0' is maintained for the memory cell sensed as an on-cell for the read voltage RD5. For memory cells sensed as off-cells for the read voltage VRD5, previously latched logic '0' is toggled to logic '1'. And after this processing is completed, the read result of the least significant bit (LSB) page can be output.

To read a middle bit (CSB) page, a read voltage (VRD2) is provided to the word lines of selected memory cells. With respect to the read voltage VRD2, logic '1' is latched in the page buffer of memory cells sensed as on-cells, and logic '0' is latched in the page buffers of memory cells sensed as off-cells. And with respect to the read voltage VRD4, the page buffer of memory cells sensed as on-cells maintains the previously sensed logic value, and logic '1' is latched in the page buffers of memory cells sensed as off-cells. Afterwards, with respect to the read voltage VRD6, the page buffers of memory cells sensed as on-cells will maintain the previously sensed logic value, and the page buffers of memory cells sensed as off-cells will be toggled to logic '0'.

To read the most significant bit (MSB) page, a read voltage (VRD3) is provided to the word lines of selected memory cells. The on/off status of the read voltage VRD3 is sensed and stored in one of a plurality of latches. Logic '1' is latched in the page buffer of memory cells sensed as on-cell with respect to the read voltage VRD3, and logic '0' is latched in the page buffer of memory cells sensed as off-cell with respect to the read voltage VRD3. .

Subsequently, a read voltage VRD7 will be provided to the word lines of the selected memory cells. And the logic value of the page buffer of the memory cell sensed as an on-cell for the read voltage VRD7 is maintained at the previous logic value. The page buffer of the memory cell sensed as an off-cell for the read voltage VRD7 toggles the previously latched logic '0' to logic '1'. And after this processing is completed, the read result of the most significant bit (MSB) page can be output.

In the above, a general read operation was explained using a triple level cell (TLC) as an example. During such a general read operation, a read failure may occur due to deterioration of the memory cell. The non-volatile memory device 200 of the present invention can perform an on-chip belly search (OCVS) read to provide high reliability according to external requests or internal judgment, and provide the results to the outside.

Figure 24 is a timing diagram illustrating an example of an on-chip valley search read operation applied to an MSB page according to embodiments of the present invention.

Referring to FIG. 24, a read operation in on-chip valley search (OCVS) mode using the read voltage VRD7 may be performed to read the most significant bit (MSB) page. Subsequently, a normal read operation for the read voltage VRD3 may be performed, and a count and comparison operation of cells may be performed in the precharge section of the normal read operation. After the normal read operation for the read voltage VRD3 is performed, a read recovery operation may be performed.

Figure 25 is a flowchart showing a method of operating a non-volatile memory device according to embodiments of the present invention.

Referring to FIG. 25, in response to a program command, randomized data is programmed into the first page so that a plurality of memory cells of the selected first page of the memory cell array 300 have a plurality of threshold voltage distributions evenly ( S410).

A read command and address are received from the memory controller 100 (S420). When the received read command indicates an on-chip valley search read mode for the first page, the valley is searched by performing the above-described on-chip valley search read operation, and a read operation is performed based on the searched valley. Output data by performing (S430).

Figure 26 is a block diagram showing a solid state disk (SSD) or solid state drive (SSD) according to embodiments of the present invention.

Referring to FIG. 26, the SSD 1000 includes a plurality of non-volatile memory devices 1100 and an SSD controller 1200.

Non-volatile memory devices 1100 may optionally be implemented to receive an external high voltage (VPP). Non-volatile memory devices 1100 may be implemented as the non-volatile memory device 30 of FIG. 3 described above. Accordingly, the non-volatile memory devices 1100 can each perform an on-chip valley search operation to search for a valley and perform a read operation based on the searched valley to reduce read errors.

The SSD controller 1200 is connected to the non-volatile memory devices 1100 through a plurality of channels CH1 to CH4. The SSD controller 1200 includes at least one processor 1210, a buffer memory 1220, an error correction circuit 1230, a host interface 1250, and a non-volatile memory interface 1260.

The buffer memory 1220 can temporarily store data necessary for driving the memory controller 1200. Additionally, the buffer memory 1220 may buffer data to be used for program operations when a write request is made. The error correction circuit 1230 calculates an error correction code value of data to be programmed in a write operation, corrects errors in the read data based on the error correction code value in a read operation, and uses the non-volatile memory device 1100 in a data recovery operation. ) can correct errors in data recovered from.

According to embodiments of the present invention, in an on-chip valley search read operation, sensing nodes are sequentially connected during a bitline development period having different start points in the first group of page buffers and the second group of page buffers. senses twice, searches for a valley by counting the number of on-cells according to the sensing result, and performs a read operation based on the discovered valley, thereby reducing read errors and improving performance by the on-chip itself. there is.

A memory device or storage device according to an embodiment of the present invention may be mounted using various types of packages.

As described above, the present invention has been described with reference to preferred embodiments, but those skilled in the art can vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be modified and changed.

Claims (20)

A memory cell array comprising a plurality of pages, each of the pages having a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions;
Sensing selected memory cells among the plurality of memory cells through a plurality of bit lines, performing a first read operation and a second read operation including two sequential sensings to identify one data state, and the two A page buffer circuit including a plurality of page buffers each having one latch for sequentially storing the results of multiple sensings; and
Control the page buffers to store the result of the first read operation, reset the latch after completion of the first read operation, and perform the second read based on the valley searched according to the result of the first read operation. comprising a control circuit that controls the page buffers to perform operations,
The page buffer circuit includes a first group of page buffers connected to the first group of bit lines among the plurality of bit lines and a second group of page buffers connected to the second group of bit lines among the plurality of bit lines. Contains page buffers of,
The first group of page buffers and the second group of page buffers perform at least the first read operation in a first development period and a second development period having different start points of the selected memory cells, respectively. Non-volatile memory device. delete According to paragraph 1,
While the first read operation is in progress, a first read voltage of the same level is applied to the word lines of the selected memory cells, and the page buffers of the first group are applied to the bit lines of the first group among the plurality of bit lines. The first sensing and the second sensing are sequentially performed on the bit lines of the second group, and the page buffers of the second group sequentially perform the third sensing and the fourth sensing on the bit lines of the second group among the plurality of bit lines. A non-volatile memory device that performs as. According to paragraph 3,
The page buffers of the first group perform the first read operation on at least the selected memory cells in the first development period starting at a first point in time,
A non-volatile memory device wherein the page buffers of the second group perform the first read operation on at least the selected memory cells in the second development period starting at a second time point later than the first time point. According to paragraph 3,
The control circuit configures the first group of page buffers and the second group of page buffers to simultaneously perform the first sensing and the third sensing, and simultaneously perform the second sensing and the fourth sensing. A non-volatile memory device that controls one group of page buffers and the second group of page buffers. According to clause 5,
The control circuit determines a first number of on cells stored in a latch of each of the page buffers of the first group according to the result of the second sensing and each of the page buffers of the second group according to the result of the fourth sensing. Counting a second number of on cells stored in,
A non-volatile memory device that determines the location of the valley by comparing the first number and the second number. According to clause 6,
When the difference between the first number and the second number is less than or equal to a reference value, the control circuit controls the page buffers to perform the second read operation based on the first read voltage. According to clause 6,
When the difference between the first number and the second number is greater than the reference value, and the first number is less than the second number. The control circuit initializes values stored in the latches of the page buffers and controls the page buffers to perform the second read operation based on a second read voltage that is greater than the first read voltage. According to clause 6,
When the difference between the first number and the second number is greater than a reference value, and the first number is greater than the second number, the control circuit initializes the value stored in the latch of the page buffers, and the first number is greater than the reference value. A non-volatile memory device that controls the page buffers to perform the second read operation based on a second read voltage that is smaller than the read voltage. The method of claim 1, wherein each of the plurality of page buffers
A precharge circuit including a first PMOS transistor and a second PMOS transistor connected in series between the power supply voltage and the sensing node;
a switch circuit connected between a corresponding bit line among the plurality of bit lines and the sensing node; and
comprising a sensing and latch circuit connected between the sensing node and a ground voltage,
The control circuit applies a load signal to the gate of the first PMOS transistor and a bit line set-up signal to the gate of the second PMOS transistor,
The sensing and latch circuit is
the latch;
A first NMOS transistor and a second NMOS transistor connected in series between the first node of the latch and the ground voltage; and
Comprising a third NMOS transistor and a fourth NMOS transistor connected in series between the second node of the latch and the ground voltage,
The gate of the fourth NMOS transistor is connected to the sensing node,
The control circuit applies a reset signal to the third NMOS transistor to perform first sensing of the first read operation, and applies a set signal to the first NMOS transistor to perform second sensing of the first read operation. A non-volatile memory device that performs. 11. The method of claim 10, wherein after precharging the bit lines, the control circuit:
The first bit line set-up signal is deactivated to a logic high level in the second PMOS transistor of each of the page buffers of the first group among the page buffers at a first point in time, thereby performing first sensing and first sensing for the sensing node. 2 Sensing is performed sequentially,
The second PMOS transistor of each of the page buffers of the second group among the page buffers deactivates the second bit line set-up signal to a logic high level at a second time point later than the first time point to the sensing node. A non-volatile memory device that sequentially performs third and fourth sensing. According to clause 11,
The control circuit configures the first group of page buffers and the second group of page buffers to simultaneously perform the first sensing and the third sensing, and simultaneously perform the second sensing and the fourth sensing. A non-volatile memory device that controls one group of page buffers and the second group of page buffers. According to clause 11,
The control circuit determines a first number of on cells stored in latches of each of the page buffers of the first group according to the results of the first sensing and the second sensing and the results of the third sensing and the fourth sensing. Accordingly, counting a second number of on cells stored in each of the page buffers of the second group,
Determine the valley by comparing the first number and the second number,
A non-volatile memory device that initializes the value stored in the latch by applying a refresh signal to the gate of the third NMOS transistor after determining the valley. The method of claim 1, wherein the memory cell array is
first memory cells corresponding to the selected memory cells connected to a first word line; and
A non-volatile memory device connected to a second word line and including second memory cells stacked on the first memory cells. A method of operating a non-volatile memory device including a memory cell array having a plurality of pages, each of the pages having a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. ,
In a page buffer circuit, performing a first read operation including two times of sensing to identify a data state of one of the memory cells selected from among the plurality of memory cells through a plurality of bit lines; and
Comprising a step of performing a second read operation to identify the one data state based on the valley searched according to the result of the first read operation,
The results of the two sensing operations are sequentially stored in one latch of each page buffer connected to each of the plurality of bit lines,
The page buffer circuit includes a first group of page buffers connected to the first group of bit lines among the plurality of bit lines and a second group of page buffers connected to the second group of bit lines among the plurality of bit lines. Contains page buffers of,
The first read operation is performed in a first development period and a second development period having different start points of the selected memory cells by the first group of page buffers and the second group of page buffers, respectively. A method of operating a non-volatile memory device. According to clause 15,
The step of performing the first read operation is
At least during the first development period starting at a first point in time, first sensing and second sensing for a sensing node connected to each of the bit lines of the first group are sequentially performed in each of the page buffers of the first group. Steps performed as; and
At least during the second development period starting at a second time point later than the first time point, third sensing for a sensing node connected to each of the bit lines of the second group in each of the page buffers of the second group A method of operating a non-volatile memory device including sequentially performing a fourth sensing operation. According to clause 16,
The first sensing and the third sensing are performed simultaneously,
A method of operating a non-volatile memory device in which the second sensing and the fourth sensing are performed simultaneously. According to clause 16,
Counting a first number of on cells stored in a latch of each of the page buffers of the first group according to a result of the second sensing;
counting a second number of on-cells stored in latches of each of the page buffers of the second group according to a result of the fourth sensing; and
A method of operating a non-volatile memory device comprising comparing the first number and the second number to determine the location of the valley. A method of operating a non-volatile memory device including a memory cell array having a plurality of pages, each of the pages having a plurality of memory cells capable of storing a plurality of data bits using a plurality of threshold voltage distributions. ,
determining read settings of the non-volatile memory device in response to commands and addresses from a memory controller that controls the non-volatile memory device;
When the read setting indicates a normal read operation, data bits stored in selected memory cells among the plurality of memory cells are read according to normal read conditions through a plurality of page buffers connected to the memory cell array through a plurality of bit lines. detecting; and
When the read setting indicates a valley search read operation, performing an on-chip valley search read operation on the selected memory cells through the plurality of page buffers, wherein the on-chip valley search read operation is performed. searches for valleys of the threshold voltage distributions and detects data bits stored in the selected memory cells based on the searched valleys,
The step of performing the on-chip valley search operation is:
Performing a first read operation including two sensing to identify one data state of the selected memory cells,
The plurality of page buffers include a first group of page buffers connected to a first group of bit lines among the plurality of bit lines, and a second group of page buffers connected to a second group of bit lines among the plurality of bit lines. Contains the group's page buffers,
The first read operation is performed in a first development period and a second development period having different start points of the selected memory cells by the first group of page buffers and the second group of page buffers, respectively. A method of operating a non-volatile memory device. The method of claim 19, wherein performing the on-chip valley search read operation comprises:
Further comprising performing a second read operation to identify the one data state based on a valley searched according to a result of the first read operation,
A method of operating a non-volatile memory device in which the results of the two sensing operations are sequentially stored in one of a plurality of latches in each of the plurality of page buffers respectively connected to the plurality of bit lines.

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