KR102656764B1 - one-bit full adder - Google Patents

Abstract

A 1-bit full adder is initiated. The disclosed 1-bit full adder includes a first input unit configured to receive a carry-in signal, a first operation unit including a first XNOR (exclusive NOR) operation unit connected in series to the first input unit, and the carry input. It may include a second input unit configured to receive an inverted signal of a signal, and a second calculation unit including a second XNOR operation unit connected in series to the second input unit. Here, the first arithmetic unit and the second arithmetic unit are connected in parallel through a first bit line through which the addition output signal of the 1-bit full adder is provided, and each of the first XNOR arithmetic unit and the second XNOR arithmetic unit includes two FeFETs. It may be configured to include a (Ferroelectric Field Effect Transistor) element.

Description

1-bit full adder

The disclosure below relates to a full adder.

With the development of artificial intelligence, high-density integration of devices, improved system performance, and low power consumption are emerging as issues. In the existing von Neumann structure, no matter how much the performance of the device improves, speed delays and power consumption inevitably occur due to data reception and transmission between the memory and the computing device. In artificial intelligence, issues related to speed delay and power consumption are receiving more and more attention as data is transmitted and received more actively between memory and computing devices. Accordingly, much research is being conducted on structures that efficiently process calculations in the memory area. Recently, attempts have been made to increase the processing speed of memory by using devices using ferroelectric materials.

The problem to be solved by the present disclosure is to provide a full adder that can be implemented with a small number of elements.

The problems to be solved by the present disclosure are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to one feature of the present disclosure, a 1-bit full adder is provided. This 1-bit full adder includes a first input unit configured to receive a carry-in signal, a first operation unit including a first XNOR (exclusive NOR) operation unit connected in series to the first input unit, and the carry input. It may include a second input unit configured to receive an inverted signal of a signal, and a second calculation unit including a second XNOR operation unit connected in series to the second input unit. The first arithmetic unit and the second arithmetic unit are connected in parallel through a first bit line through which the addition output signal of the 1-bit full adder is provided, and each of the first XNOR arithmetic unit and the second XNOR arithmetic unit includes two FeFETs ( It may be configured to include a Ferroelectric Field Effect Transistor) element.

In one embodiment, the 1-bit full adder includes a third input unit configured to receive the carry input signal, a third operation unit including an OR operation unit serially connected to the third input unit, and an inverted signal of the carry input signal. It further includes a fourth input unit configured to receive input, and a fourth operator including an AND operator connected in series to the fourth input unit. The third operation unit and the fourth operation unit are connected in parallel through a second bit line through which a carry-out signal of the 1-bit full adder is provided, and each of the OR operation unit and the AND operation unit is connected to one FeFET. It is composed of elements.

In one embodiment, the first input unit includes a first Complementary Metal Oxide Semiconductor (CMOS) transistor, the first CMOS transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode receives the carry input signal. It is an electrode for receiving input, and the drain electrode is connected to the first bit line.

In one embodiment, the first Having an electrode, a source electrode, and a drain electrode, the first FeFET transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode of the second CMOS transistor receives the first input signal to the 1-bit full adder. an electrode for, the drain electrode of the second CMOS transistor is connected to the source electrode of the first CMOS transistor, the source electrode of the second CMOS transistor is connected to the drain electrode of the first FeFET transistor, and the first FeFET The gate electrode of the transistor is an electrode for receiving a logic 0 signal, the source electrode of the first FeFET transistor is connected to a ground line, and the first FeFET transistor is in a state corresponding to the second input signal to the 1-bit full adder. It is a transistor that is programmed with .

In one embodiment, the third CMOS transistor has a gate electrode, a source electrode, and a drain electrode, the second FeFET transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode of the third CMOS transistor is the first electrode. 1 is an electrode for receiving an inverted signal of an input signal, the drain electrode of the third CMOS transistor is connected to the source electrode of the first CMOS transistor, and the source electrode of the third CMOS transistor is connected to the drain of the second FeFET transistor. It is connected to an electrode, the gate electrode of the second FeFET transistor is an electrode for receiving a logic 0 signal, the source electrode of the second FeFET transistor is connected to the ground line, and the second FeFET transistor is an electrode for receiving the logic 0 signal. It is a transistor that is programmed into a state corresponding to an inverting signal.

In one embodiment, the second input unit includes a fourth CMOS transistor, the fourth CMOS transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode is used to receive an inverted signal of the carry input signal. electrode, and the drain electrode is connected to the first bit line.

In one embodiment, the second The third FeFET transistor has a gate electrode, a source electrode and a drain electrode, and the gate electrode of the fifth CMOS transistor is an inverted signal of the first input signal to the 1-bit full adder. is an electrode for receiving an input, the drain electrode of the fifth CMOS transistor is connected to the source electrode of the fourth CMOS transistor, the source electrode of the fifth CMOS transistor is connected to the drain electrode of the third FeFET transistor, The gate electrode of the third FeFET transistor is an electrode for receiving a logic 0 signal, the source electrode of the third FeFET transistor is connected to the ground line, and the third FeFET transistor is connected to the second input signal to the 1-bit full adder. It is a transistor that is programmed into the corresponding state.

In one embodiment, the sixth CMOS transistor has a gate electrode, a source electrode, and a drain electrode, the fourth FeFET transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode of the sixth CMOS transistor is the first electrode. 1 An electrode for receiving an input signal, the drain electrode of the sixth CMOS transistor is connected to the source electrode of the fourth CMOS transistor, and the source electrode of the sixth CMOS transistor is connected to the drain electrode of the fourth FeFET transistor. The gate electrode of the fourth FeFET transistor is an electrode for receiving a logic 0 signal, the source electrode of the fourth FeFET transistor is connected to the ground line, and the fourth FeFET transistor receives the inversion signal of the second input signal. It is a transistor that is programmed into a state corresponding to .

In one embodiment, the third input unit includes a seventh CMOS transistor, the seventh CMOS transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode is an electrode for receiving the carry input signal, The drain electrode is connected to the second bit line.

In one embodiment, the OR operator includes a fifth FeFET transistor, the fifth FeFET transistor includes a gate electrode, a source electrode, and a drain electrode, and the gate electrode of the fifth FeFET transistor is the 1-bit full adder. is an electrode for receiving the first input signal, the drain electrode of the fifth FeFET transistor is connected to the source electrode of the seventh CMOS transistor, the source electrode of the fifth FeFET transistor is connected to the ground line, and the fifth FeFET transistor is connected to the source electrode of the seventh CMOS transistor. The FeFET transistor is a transistor that is programmed to a state corresponding to the second input signal to the 1-bit full adder.

In one embodiment, the fourth input unit includes an eighth CMOS transistor, the eighth CMOS transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode is used to receive an inverted signal of the carry input signal. electrode, and the drain electrode is connected to the second bit line.

In one embodiment, the AND operation unit includes a ninth CMOS transistor and a sixth FeFET transistor connected in series to the ninth CMOS transistor, and the ninth CMOS transistor includes a gate electrode, a source electrode, and a drain electrode, The sixth FeFET transistor includes a gate electrode, a source electrode, and a drain electrode, the gate electrode of the ninth CMOS transistor is an electrode for receiving the first input signal to the 1-bit full adder, and the gate electrode of the ninth CMOS transistor is an electrode for receiving the first input signal to the 1-bit full adder. The drain electrode is connected to the source electrode of the eighth CMOS transistor, the gate electrode of the sixth FeFET transistor is an electrode for receiving a logic 0 signal, and the drain electrode of the sixth FeFET transistor is the source electrode of the ninth CMOS transistor. electrode, the source electrode of the sixth FeFET transistor is connected to a ground line, and the sixth FeFET transistor is a transistor programmed to a state corresponding to a second input signal to the 1-bit full adder.

In one embodiment, the first FeFET transistor is programmable to be in either a first state or a second state, and when the second input signal is a logic 0 signal, the first FeFET transistor is programmable to the first state. And, when the second input signal is a logic 1 signal, the first FeFET transistor is programmed to the second state.

In one embodiment, the second FeFET transistor is programmable to be in either a first state or a second state, and when the second input signal is a logic 0 signal, the second FeFET transistor is programmable to the second state. And, when the second input signal is a logic 1 signal, the second FeFET transistor is programmed to the first state.

In one embodiment, the third FeFET transistor is programmable to be in either a first state or a second state, and when the second input signal is a logic 0 signal, the third FeFET transistor is programmable to the first state. And, when the second input signal is a logic 1 signal, the third FeFET transistor is programmed to the second state.

In one embodiment, the fourth FeFET transistor is programmable to be in either a first state or a second state, and when the second input signal is a logic 0 signal, the fourth FeFET transistor is programmable to the second state. And, when the second input signal is a logic 1 signal, the fourth FeFET transistor is programmed to the first state.

In one embodiment, the fifth FeFET transistor is programmable to be in either a first state or a second state, and when the second input signal is a logic 0 signal, the fifth FeFET transistor is programmable to the first state. And, when the second input signal is a logic 1 signal, the fifth FeFET transistor is programmed to the second state.

In one embodiment, the sixth FeFET transistor is programmable to be in one of a first state and a second state, and when the second input signal is a logic 0 signal, the sixth FeFET transistor is programmable to the first state. And, when the second input signal is a logic 1 signal, the sixth FeFET transistor is programmed to the second state.

According to the disclosed embodiments, there is a technical effect of being able to implement a full adder with a small number of elements.

FIG. 1A is a diagram illustrating the structure of an embodiment of a Ferroelectric Field Effect Transistor (FeFET) transistor.
Figure 1b is a diagram showing the equivalent circuit of a FeFET transistor.
Figure 1c is a diagram showing an example of the IV characteristic curve of a FeFET transistor.
Figure 1d is a diagram showing a truth table for explaining the operation of a FeFET transistor.
Figure 2 is a diagram showing a circuit diagram of one embodiment of a one-bit full adder constructed using FeFET transistors.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be changed and implemented in various forms. Accordingly, the actual implementation form is not limited to the specific disclosed embodiments, and the scope of the present disclosure includes changes, equivalents, or substitutes included in the technical idea described in the embodiments.

Although terms such as “first” or “second” may be used to describe various components, these terms should be interpreted only for the purpose of distinguishing one component from another component. For example, a “first component” may be named a “second component” and similarly, a “second component” may also be named a “first component”.

When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected or connected to the other component, but that other components may exist in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In the present disclosure, terms such as "comprise" or "have" are intended to designate the presence of the described features, numbers, steps, operations, components, parts, or combinations thereof, and are intended to indicate the presence of one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the present disclosure. No.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the accompanying drawings, identical components will be assigned the same reference numerals regardless of the reference numerals, and overlapping descriptions thereof will be omitted.

1A, 1B, 1C, and 1D respectively illustrate the structure of an embodiment of a Ferroelectric Field Effect Transistor (FeFET) transistor, an equivalent circuit of an FeFET transistor, an embodiment of an I-V characteristic curve of a FeFET transistor, and an operation of the FeFET transistor. These are drawings showing the truth table for:

Referring first to Figure 1A, the structure of one embodiment of a FeFET transistor is shown. The FeFET transistor 100 may include a P-type well region 110. The P-type well region 110 may be created by implanting P-type ions from the top of a substrate (not shown). The FeFET transistor 100 may further include a gate insulating film 120 formed on the P-type well region 110. In one embodiment, the gate insulating film 120 may be formed of an oxide film, a nitride film, an oxynitride film, a metal oxide film, or a multi-layered film thereof. The FeFET transistor 100 may further include a metal layer 130, a ferroelectric (FE) layer 140, and a gate electrode 150 formed on the gate insulating film 120. The FE layer 140 may be formed of a ferroelectric material that functions as capacitance. In one embodiment, the FE layer 140 may include a hafnium oxide layer, a zirconium oxide layer, a hafnium titanate layer, or a haftium zirconium oxide layer. In one embodiment, FE layer 140 may be formed from a composite layer of two or more of the above layers. The FeFET transistor 100 can have hysteresis current voltage (IV) characteristics due to the FE layer 140. The gate electrode 150 may be formed of a material such as polysilicon or metal. The gate electrode 150 may have a doping type opposite to that of the well. In the illustrated embodiment, since the doping type of the well region 110 is P, the gate electrode 150 may be doped with N-type ions. The FeFET transistor 100 may further include doped regions 160 and 170 formed below the gate insulating film 120 and on the left and right sides of the gate insulating film 120 to be spaced apart from each other. The doped regions 160 and 170 may be formed in the P-type well region 110 by implanting ions of the same type as the doping type of the gate electrode 150. Therefore, like the gate electrode 150, the doped regions 160 and 170 may have a doping type opposite to that of the well region 110. In the illustrated embodiment, the gate electrode 150 is doped with N-type ions, so the doped regions 160 and 170 may be formed by implantation of N-type ions. The doped region 160 may form the drain of the FeFET transistor 100, and the doped region 170 may form the source of the FeFET transistor 100. In one embodiment, the FeFET transistor 100 is a FeFET based on a multi-nanosheet complementary metal oxide semiconductor (CMOS). Referring to Figure 1b, the equivalent circuit of a FeFET transistor is shown. As shown, the FeFET transistor 100 has a capacitance component representing a CMOS transistor and a ferroelectric ( ) can be expressed as a series-connected circuit. In the above description, the structure of the FeFET transistor was explained using the N-type FeFET transistor as an example, but it should be noted that the P-type FeFET transistor may also have a similar structure except for the difference in conductivity type.

Figure 1c is a diagram showing an example of the I-V characteristic curve of a FeFET transistor.

As shown, the FeFET transistor 100 has hysteresis current voltage (IV) characteristics. Voltage between the gate electrode and source electrode of the FeFET transistor 100 ( When ) is above the threshold voltage, the FeFET transistor 100 is turned on, as shown by the upward arrow in FIG. 1C, and a current ( ) flows. However, the voltage between the gate electrode and the source electrode ( Even if ) falls below the threshold voltage, the FeFET transistor 100 does not turn off immediately. As indicated by the downward arrow in Figure 1c, the voltage ( ) even if it falls to around 0 V, the current ( ) does not fall sharply but tends to fall gently. That is, when the FeFET transistor 100 is turned on, the voltage ( Even if ) falls, the FeFET transistor 100 maintains its previous state. The FeFET transistor 100 has a current ( ) and the first state and current (turn-off state) in which less current flows (turn-off state). ) may be in one of the second states in which a lot of voltage flows (turn-on state), and the newly input voltage ( ) The state changes according to ) are summarized in a truth table as shown in Figure 1d. As shown in FIG. 1D, the FeFET transistor 100 is currently in the first state and the newly input voltage ( ) is logic 0, the FeFET transistor 100 maintains the first state. The FeFET transistor 100 is currently in the first state and the newly input voltage ( ) is logic 1, the FeFET transistor 100 transitions to the second state. The FeFET transistor 100 is currently in the second state and the newly input voltage ( ) is logic 0, the FeFET transistor 100 maintains the second state. The FeFET transistor 100 is currently in the second state and the newly input voltage ( ) is logic 1, the FeFET transistor 100 maintains the second state. In summary, when the FeFET transistor 100 is currently in the first state, the newly input voltage ( ) is determined depending on what the state is, and when the FeFET transistor 100 is currently in the second state, the voltage ( ), the second state remains the same regardless of what it is. It is possible to economically construct a logic circuit using the characteristics of the FeFET transistor 100.

Figure 2 is a diagram showing a circuit diagram of one embodiment of a one-bit full adder constructed using FeFET transistors.

One embodiment of the 1-bit full adder shown in FIG. 2 uses Equation 1, which is a logical expression for the addition output signal (S), and the carry output signal ( ) can be designed to implement Equation 2, which is the logical expression for ).

Here, S represents the addition output signal output from the 1-bit full adder 200, X and Y represent the first and second input signals respectively input to the 1-bit full adder 200, represents a carry-in signal input to the 1-bit full adder 200.

here represents the carry output signal output from the 1-bit full adder 200.

As shown in FIG. 2, the 1-bit full adder 200 may include a first operation unit and a second operation unit to provide an addition output signal (S). The first operation unit carries a carry-in signal ( ) may include a first input unit configured to receive input, and a first XNOR (exclusive NOR) operation unit connected in series to the first input unit. The first input unit includes a first CMOS transistor 221, and the first CMOS transistor 221 has a gate electrode, a source electrode, and a drain electrode, where the gate electrode is a carry input signal ( ), and its drain electrode can be connected to the first bit line BL1 to which the addition output signal (S) of the 1-bit full adder 200 is provided. The first . The second CMOS transistor 222 may have a gate electrode, a source electrode, and a drain electrode. The first FeFET transistor 241 may have a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second CMOS transistor 222 is an electrode for receiving the first input signal to the 1-bit full adder 200, and the drain electrode of the second CMOS transistor 222 is the source electrode of the first CMOS transistor 221. It can be connected to an electrode. The source electrode of the second CMOS transistor 222 may be connected to the drain electrode of the first FeFET transistor 241. The gate electrode of the first FeFET transistor 241 is an electrode for receiving a logic 0 signal, and the source electrode of the first FeFET transistor 241 may be connected to the ground line (GND). The first FeFET transistor 241 is programmable to be in either a first state or a second state. The first FeFET transistor 241 may be programmed to a state corresponding to the second input signal to the 1-bit full adder 200. When the second input signal is a logic 0 signal, the first FeFET transistor 241 can be programmed to the first state, and when the second input signal is a logic 1 signal, the first FeFET transistor 241 can be programmed to the second state. there is.

The third CMOS transistor 223 may have a gate electrode, a source electrode, and a drain electrode. The second FeFET transistor 242 may have a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third CMOS transistor 223 is an electrode for receiving the inversion signal of the first input signal, and the drain electrode of the third CMOS transistor 223 may be connected to the source electrode of the first CMOS transistor 221. there is. The source electrode of the third CMOS transistor 223 may be connected to the drain electrode of the second FeFET transistor 242. The gate electrode of the second FeFET transistor 242 is an electrode for receiving a logic 0 signal, and the source electrode of the second FeFET transistor 242 may be connected to the ground line (GND). The second FeFET transistor 242 is programmable to be in either the first state or the second state. The second FeFET transistor 242 may be programmed to a state corresponding to the inverted signal of the second input signal. When the second input signal is a logic 0 signal, the second FeFET transistor 242 can be programmed to the second state, and when the second input signal is a logic 1 signal, the second FeFET transistor 242 can be programmed to the first state. there is.

The second operation unit carries a carry input signal ( ) may include a second input unit configured to receive an inverted signal, and a second XNOR operation unit connected in series to the second input unit. The second calculation unit may be connected in parallel with the first calculation unit through the first bit line BL1 to which the addition output signal S of the 1-bit full adder 200 is provided. The second input unit includes a fourth CMOS transistor 224, and the fourth CMOS transistor 224 has a gate electrode, a source electrode, and a drain electrode, where the gate electrode is a carry input signal ( ) is an electrode for receiving an inverted signal, and its drain electrode can be connected to the first bit line BL1. The second . The fifth CMOS transistor 225 may have a gate electrode, a source electrode, and a drain electrode. The third FeFET transistor 243 may have a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth CMOS transistor 225 may be an electrode for receiving an inverted signal of the first input signal to the 1-bit full adder 200. The drain electrode of the fifth CMOS transistor 225 may be connected to the source electrode of the fourth CMOS transistor 224. The source electrode of the fifth CMOS transistor 225 may be connected to the drain electrode of the third FeFET transistor 243. The gate electrode of the third FeFET transistor 243 may be an electrode for receiving a logic 0 signal. The source electrode of the third FeFET transistor 243 may be connected to the ground line (GND). The third FeFET transistor 243 is programmable to be in either the first state or the second state. The third FeFET transistor 243 may be programmed to a state corresponding to the second input signal to the 1-bit full adder 200. When the second input signal is a logic 0 signal, the third FeFET transistor 243 can be programmed to the first state, and when the second input signal is a logic 1 signal, the third FeFET transistor 243 can be programmed to the second state. there is.

The sixth CMOS transistor 226 may have a gate electrode, a source electrode, and a drain electrode. The fourth FeFET transistor 244 may have a gate electrode, a source electrode, and a drain electrode. The gate electrode of the sixth CMOS transistor 226 is an electrode for receiving the first input signal, and the drain electrode of the sixth CMOS transistor 226 may be connected to the source electrode of the fourth CMOS transistor 224. The source electrode of the sixth CMOS transistor 226 may be connected to the drain electrode of the fourth FeFET transistor 244. The gate electrode of the fourth FeFET transistor 244 is an electrode for receiving a logic 0 signal, and the source electrode of the fourth FeFET transistor 244 may be connected to the ground line (GND). The fourth FeFET transistor 244 is programmable to be in either the first state or the second state. The fourth FeFET transistor 244 may be programmed to a state corresponding to the inverted signal of the second input signal. When the second input signal is a logic 0 signal, the fourth FeFET transistor 244 can be programmed to the second state, and when the second input signal is a logic 1 signal, the fourth FeFET transistor 244 can be programmed to the first state. there is.

The 1-bit full adder 200 produces a carry output signal ( ) may further include a third operation unit and a fourth operation unit for providing. The third operation unit carries a carry input signal ( ) may include a third input unit configured to receive input, and an OR operator connected in series to the third input unit. The third input unit includes a seventh CMOS transistor 227, and the seventh CMOS transistor 227 has a gate electrode, a source electrode, and a drain electrode, where the gate electrode is a carry input signal ( ), and the drain electrode is the carry-out signal (carry-out signal) of the 1-bit full adder 200. ) may be connected to the second bit line BL2 provided. The OR operation unit may include a fifth FeFET transistor 245. The fifth FeFET transistor 245 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth FeFET transistor 245 may be an electrode for receiving the first input signal to the 1-bit full adder 200. The drain electrode of the fifth FeFET transistor 245 may be connected to the source electrode of the seventh CMOS transistor 227, and the source electrode of the fifth FeFET transistor 245 may be connected to the ground line (GND). The fifth FeFET transistor 245 is programmable to be in either the first state or the second state. The fifth FeFET transistor 245 may be programmed to a state corresponding to the second input signal to the 1-bit full adder 200. When the second input signal is a logic 0 signal, the fifth FeFET transistor 245 can be programmed to the first state, and when the second input signal is a logic 1 signal, the fifth FeFET transistor 245 can be programmed to the second state. there is.

The fourth operation unit carries a carry input signal ( ) may include a fourth input unit configured to receive an inverted signal, and an AND operation unit connected in series to the fourth input unit. The fourth operation unit is the carry output signal of the 1-bit full adder 200 ( ) can be connected in parallel with the third operation unit through the second bit line BL2 provided. The fourth input unit includes an eighth CMOS transistor 228, and the eighth CMOS transistor 228 has a gate electrode, a source electrode, and a drain electrode, where the gate electrode is a carry input signal ( ) is an electrode for receiving an inverted signal, and its drain electrode may be connected to the second bit line BL2. The AND operation unit may include a ninth CMOS transistor 229 and a sixth FeFET transistor 246 connected in series to the ninth CMOS transistor 229. The ninth CMOS transistor 229 may include a gate electrode, a source electrode, and a drain electrode. The sixth FeFET transistor 246 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the 9th CMOS transistor 229 is an electrode for receiving the first input signal to the 1-bit full adder 200, and the drain electrode of the 9th CMOS transistor 229 is the source of the 8th CMOS transistor 228. It can be connected to an electrode. The gate electrode of the sixth FeFET transistor 246 is an electrode for receiving a logic 0 signal, the drain electrode of the sixth FeFET transistor 246 is connected to the source electrode of the ninth CMOS transistor 229, and the sixth FeFET transistor 246 is connected to the source electrode of the ninth CMOS transistor 229. The source electrode of 246 may be connected to the ground line (GND). The sixth FeFET transistor 246 is programmable to be in either the first state or the second state. The sixth FeFET transistor 246 can be programmed to a state corresponding to the second input signal to the 1-bit full adder 200. When the second input signal is a logic 0 signal, the sixth FeFET transistor 246 can be programmed to the first state, and when the second input signal is a logic 1 signal, the sixth FeFET transistor 246 can be programmed to the second state. there is.

The 1-bit full adder 200 according to the embodiments disclosed above can be implemented using a small number of devices by adopting FeFETs using ferroelectric materials. Additionally, since the 1-bit adder 200 according to the embodiments disclosed above is implemented using a small number of elements, it has the advantage of being able to perform the same addition function while consuming less power. According to the 1-bit full adder 200 according to the disclosed embodiments, the number of elements can be dramatically reduced compared to the existing CMOS full adder that requires 28 CMOS elements, so not only can performance be improved through high-density design. Operation at high speed and low power is possible. In addition, the 1-bit full adder 200 according to the disclosed embodiments has a parallel structure, so that the addition output signal (S) and the carry output signal ( ) individual control becomes possible.

In the above description, the meaning of a description that a component is connected or combined with another component not only means that the component is directly connected or combined with the other component, but also one or more other components interposed between them. It should be understood to include the meaning that it can be connected or combined through elements. In addition, terms used to describe relationships between components (e.g., ‘on’, ‘above’, ‘above’, ‘between’, ‘between’, etc.) should be interpreted with a similar meaning.

In the embodiments disclosed herein, the arrangement of the components shown may vary depending on the environment or requirements in which the technology is implemented. For example, some components may be omitted or some components may be integrated and implemented as one. Additionally, the arrangement order and connection of some components may change.

As described above, although the embodiments have been described with limited drawings, those skilled in the art can apply various technical modifications and variations based on this. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

100: FeFET transistor
110: Month area
120: Gate insulating film
130: metal layer
140: FE layer
150: gate electrode
160, 170: doping area
221, 222, 223, 224, 225, 226, 227, 228, 229: CMOS transistors
241, 242, 243, 244, 245, 246: FeFET transistor

Claims (18)

As a 1-bit full adder,
A first operation unit including a first input unit configured to receive a carry-in signal and a first XNOR (exclusive NOR) operation unit connected in series to the first input unit, and
A second input unit configured to receive an inverted signal of the carry input signal, and a second operation unit including a second XNOR operation unit connected in series to the second input unit,
The first operation unit and the second operation unit are connected in parallel through a first bit line through which an addition output signal of the 1-bit full adder is provided,
A 1-bit full adder, wherein each of the first XNOR operation unit and the second XNOR operation unit includes two FeFET (Ferroelectric Field Effect Transistor) elements. According to paragraph 1,
A third operation unit including a third input unit configured to receive the carry input signal and an OR operation unit connected in series to the third input unit, and
It further includes a fourth input unit configured to receive an inverted signal of the carry input signal, and a fourth operation unit including an AND operation unit connected in series to the fourth input unit,
The third operation unit and the fourth operation unit are connected in parallel through a second bit line through which a carry-out signal of the 1-bit full adder is provided,
A 1-bit full adder, wherein each of the OR operation unit and the AND operation unit includes one FeFET element. According to paragraph 1,
The first input unit includes a first CMOS (Complementary Metal Oxide Semiconductor) transistor, the first CMOS transistor has a gate electrode, a source electrode, and a drain electrode, and the gate electrode is an electrode for receiving the carry input signal. , the drain electrode is connected to the first bit line, a 1-bit full adder. According to paragraph 3,
The first
The second CMOS transistor has a gate electrode, a source electrode, and a drain electrode,
The first FeFET transistor has a gate electrode, a source electrode, and a drain electrode,
The gate electrode of the second CMOS transistor is an electrode for receiving the first input signal to the 1-bit full adder,
The drain electrode of the second CMOS transistor is connected to the source electrode of the first CMOS transistor,
The source electrode of the second CMOS transistor is connected to the drain electrode of the first FeFET transistor,
The gate electrode of the first FeFET transistor is an electrode for receiving a logic 0 signal,
The source electrode of the first FeFET transistor is connected to a ground line,
A 1-bit full adder, wherein the first FeFET transistor is a transistor programmed to a state corresponding to a second input signal to the 1-bit full adder. According to paragraph 4,
The third CMOS transistor has a gate electrode, a source electrode, and a drain electrode,
The second FeFET transistor has a gate electrode, a source electrode, and a drain electrode,
The gate electrode of the third CMOS transistor is an electrode for receiving an inverted signal of the first input signal,
The drain electrode of the third CMOS transistor is connected to the source electrode of the first CMOS transistor,
The source electrode of the third CMOS transistor is connected to the drain electrode of the second FeFET transistor,
The gate electrode of the second FeFET transistor is an electrode for receiving a logic 0 signal,
The source electrode of the second FeFET transistor is connected to a ground line,
A 1-bit full adder, wherein the second FeFET transistor is a transistor programmed to a state corresponding to an inverted signal of the second input signal. According to paragraph 1,
The second input unit includes a fourth CMOS transistor, and the fourth CMOS transistor has a gate electrode, a source electrode, and a drain electrode, the gate electrode is an electrode for receiving an inversion signal of the carry input signal, and the drain electrode is an electrode for receiving an inversion signal of the carry input signal. A 1-bit full adder, wherein the electrode is connected to the first bit line. According to clause 6,
The second
The fifth CMOS transistor has a gate electrode, a source electrode, and a drain electrode,
The third FeFET transistor has a gate electrode, a source electrode, and a drain electrode,
The gate electrode of the fifth CMOS transistor is an electrode for receiving an inverted signal of the first input signal to the 1-bit full adder,
The drain electrode of the fifth CMOS transistor is connected to the source electrode of the fourth CMOS transistor,
The source electrode of the fifth CMOS transistor is connected to the drain electrode of the third FeFET transistor,
The gate electrode of the third FeFET transistor is an electrode for receiving a logic 0 signal,
The source electrode of the third FeFET transistor is connected to a ground line,
A 1-bit full adder, wherein the third FeFET transistor is a transistor programmed to a state corresponding to a second input signal to the 1-bit full adder. In clause 7,
The sixth CMOS transistor has a gate electrode, a source electrode, and a drain electrode,
The fourth FeFET transistor has a gate electrode, a source electrode, and a drain electrode,
The gate electrode of the sixth CMOS transistor is an electrode for receiving the first input signal,
The drain electrode of the sixth CMOS transistor is connected to the source electrode of the fourth CMOS transistor,
The source electrode of the sixth CMOS transistor is connected to the drain electrode of the fourth FeFET transistor,
The gate electrode of the fourth FeFET transistor is an electrode for receiving a logic 0 signal,
The source electrode of the fourth FeFET transistor is connected to the ground line,
The fourth FeFET transistor is a 1-bit full adder, wherein the fourth FeFET transistor is a transistor programmed to a state corresponding to an inverted signal of the second input signal. According to paragraph 2,
The third input unit includes a seventh CMOS transistor, the seventh CMOS transistor has a gate electrode, a source electrode, and a drain electrode, the gate electrode is an electrode for receiving the carry input signal, and the drain electrode is an electrode for receiving the carry input signal. A 1-bit full adder, connected to the second bit line. According to clause 9,
The OR operation unit includes a fifth FeFET transistor,
The fifth FeFET transistor includes a gate electrode, a source electrode, and a drain electrode,
The gate electrode of the fifth FeFET transistor is an electrode for receiving the first input signal to the 1-bit full adder,
The drain electrode of the fifth FeFET transistor is connected to the source electrode of the seventh CMOS transistor,
The source electrode of the fifth FeFET transistor is connected to a ground line,
A 1-bit full adder, wherein the fifth FeFET transistor is a transistor programmed to a state corresponding to a second input signal to the 1-bit full adder. According to paragraph 2,
The fourth input unit includes an eighth CMOS transistor, the eighth CMOS transistor has a gate electrode, a source electrode, and a drain electrode, the gate electrode is an electrode for receiving an inversion signal of the carry input signal, and the drain electrode is an electrode for receiving an inversion signal of the carry input signal. A 1-bit full adder, wherein the electrode is connected to the second bit line. According to clause 11,
The AND operation unit includes a ninth CMOS transistor and a sixth FeFET transistor connected in series to the ninth CMOS transistor,
The ninth CMOS transistor includes a gate electrode, a source electrode, and a drain electrode,
The sixth FeFET transistor includes a gate electrode, a source electrode, and a drain electrode,
The gate electrode of the ninth CMOS transistor is an electrode for receiving the first input signal to the 1-bit full adder,
The drain electrode of the ninth CMOS transistor is connected to the source electrode of the eighth CMOS transistor,
The gate electrode of the sixth FeFET transistor is an electrode for receiving a logic 0 signal,
The drain electrode of the sixth FeFET transistor is connected to the source electrode of the ninth CMOS transistor,
The source electrode of the sixth FeFET transistor is connected to a ground line,
A 1-bit full adder, wherein the sixth FeFET transistor is a transistor programmed to a state corresponding to a second input signal to the 1-bit full adder. According to paragraph 4,
The first FeFET transistor is programmable to be in either a first state or a second state,
When the second input signal is a logic 0 signal, the first FeFET transistor is programmed to a first state, and when the second input signal is a logic 1 signal, the first FeFET transistor is programmed to a second state, 1 bit Full adder. According to clause 5,
The second FeFET transistor is programmable to be in either a first state or a second state,
When the second input signal is a logic 0 signal, the second FeFET transistor is programmed to a second state, and when the second input signal is a logic 1 signal, the second FeFET transistor is programmed to a first state, 1 bit Full adder. In clause 7,
The third FeFET transistor is programmable to be in either a first state or a second state,
When the second input signal is a logic 0 signal, the third FeFET transistor is programmed to a first state, and when the second input signal is a logic 1 signal, the third FeFET transistor is programmed to a second state, 1 bit Full adder. According to clause 8,
The fourth FeFET transistor is programmable to be in either a first state or a second state,
When the second input signal is a logic 0 signal, the fourth FeFET transistor is programmed to the second state, and when the second input signal is a logic 1 signal, the fourth FeFET transistor is programmed to the first state, 1 bit Full adder. According to clause 10,
The fifth FeFET transistor is programmable to be in either a first state or a second state,
When the second input signal is a logic 0 signal, the fifth FeFET transistor is programmed to a first state, and when the second input signal is a logic 1 signal, the fifth FeFET transistor is programmed to a second state, 1 bit Full adder. According to clause 12,
The sixth FeFET transistor is programmable to be in either a first state or a second state,
When the second input signal is a logic 0 signal, the sixth FeFET transistor is programmed to a first state, and when the second input signal is a logic 1 signal, the sixth FeFET transistor is programmed to a second state, 1 bit Full adder.