KR102656127B1 - Organic light emitting display device - Google Patents

Abstract

An organic light emitting display device according to the present invention includes a substrate having a thin film transistor region on which a thin film transistor is disposed and an auxiliary electrode region on which an auxiliary structure is disposed; and an organic light emitting diode disposed on the substrate and having an anode electrically connected to the thin film transistor, a cathode facing the anode, and an organic compound layer interposed between the anode and the cathode, and the auxiliary structure includes: , first insulating pattern; a second insulating pattern located on the first insulating pattern; a first auxiliary electrode located on the second insulating pattern and having an end that protrudes outward from an end of the second insulating pattern; and a stacked first insulating pattern, a second insulating pattern, and a second auxiliary electrode formed along an outer surface of the first auxiliary electrode, wherein the organic compound layer is separated from the auxiliary electrode region, 2 A portion of the auxiliary electrode is exposed, and the cathode is in direct contact with the exposed second auxiliary electrode.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display device.

Organic light emitting display devices are self-luminous displays that excite organic compounds to emit light. They do not require the backlight used in LCDs, so they are lightweight and thin, and have the advantage of simplifying the process. In addition, organic electroluminescent display devices are widely used because they can be manufactured at low temperatures, have a high-speed response speed of 1 ms or less, and have characteristics such as low power consumption, wide viewing angle, and high contrast. there is.

Organic light emitting display devices include organic light emitting diodes (Organic Light Emitting Diodes) that convert electrical energy into light energy. In an organic light emitting display device, holes and electrons injected from an anode and a cathode combine inside the light emitting layer to form excitons, and the formed excitons change from the excited state to the ground state. As it falls, it emits light and displays an image.

In the case of a large-area organic light emitting display device, uniform luminance cannot be maintained over the entire active area where the input image is displayed, and luminance deviation occurs depending on the location. More specifically, the cathode constituting the organic light emitting diode is formed widely to cover most of the active area, but a problem occurs in which the power voltage applied to the cathode does not have a uniform voltage value across the entire surface. For example, as the difference between the voltage value at the inlet where the power supply voltage is applied due to the resistance of the cathode and the voltage value at a position away from the inlet increases, the luminance deviation depending on the position increases.

This problem is even more problematic in top emission display devices. That is, in a top-emitting display device, it is necessary to secure the transmittance of the cathode located on the upper layer of the organic light-emitting diode, so the cathode is made of a transparent conductive material such as ITO (Indium Tin Oxide) or a very thin, opaque material. It is formed from a conductive material. In this case, since the sheet resistance increases, the luminance difference depending on the position also significantly increases correspondingly.

To solve this problem, a method of forming an Evss auxiliary electrode containing a low-resistance material and connecting it to the cathode to prevent voltage drop depending on location has been proposed. However, in the conventional structure, it was difficult to secure a sufficient contact area between the Evss auxiliary electrode and the cathode, so it was difficult to improve the luminance deviation depending on the location as contact defects occurred. In addition, when the contact area between the Evss auxiliary electrode and the cathode is narrow, heat is generated as the current density rapidly increases in that area, causing a problem of deteriorating the organic light emitting diode.

The object of the present invention is to provide an organic light emitting display device that can secure a sufficient contact area between the Evss auxiliary electrode and the cathode.

An organic light emitting display device according to the present invention includes a substrate having a thin film transistor region on which a thin film transistor is disposed and an auxiliary electrode region on which an auxiliary structure is disposed; and an organic light emitting diode disposed on the substrate and having an anode electrically connected to the thin film transistor, a cathode facing the anode, and an organic compound layer interposed between the anode and the cathode, and the auxiliary structure includes: , first insulating pattern; a second insulating pattern located on the first insulating pattern; a first auxiliary electrode located on the second insulating pattern and having an end that protrudes outward from an end of the second insulating pattern; and a stacked first insulating pattern, a second insulating pattern, and a second auxiliary electrode formed along an outer surface of the first auxiliary electrode, wherein the organic compound layer is separated from the auxiliary electrode region, 2 A portion of the auxiliary electrode is exposed, and the cathode is in direct contact with the exposed second auxiliary electrode.

The substrate includes an Evss wire that receives a power voltage from a power generator, and the first auxiliary electrode is connected to the Evss wire to receive the power voltage.

The first auxiliary electrode may be a part branched from the Evss wiring.

The area of the first auxiliary electrode may be larger than the area of the second insulating pattern.

An end of the second auxiliary electrode may be in direct contact with the substrate.

The organic compound layer may include a first part located on the upper surface of the auxiliary structure and a second part located on the periphery of the auxiliary structure.

The cathode may be in direct contact with the second auxiliary electrode in a space spaced between the first part and the second part.

The substrate includes a light blocking layer disposed in the thin film transistor area; a buffer layer covering the light blocking layer; a semiconductor layer disposed on the buffer layer and overlapping the light blocking layer; an interlayer insulating film covering the semiconductor layer; a source electrode and a drain electrode disposed on the interlayer insulating film and connected to one side and the other side of the semiconductor layer, respectively, through contact holes penetrating the interlayer insulating film; A passivation film and a planarization film are sequentially stacked on the source electrode and the drain electrode and have a pixel contact hole that exposes the source electrode and connects the source electrode and the anode, wherein the first auxiliary electrode is connected to the source electrode. and may be formed of the same material as the drain electrode.

The second auxiliary electrode may be made of ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

The auxiliary structure includes a third auxiliary electrode interposed between the substrate and the first insulating pattern, the first insulating pattern includes a first auxiliary hole exposing the third auxiliary electrode, and the second insulator The pattern includes a second auxiliary hole exposing the third auxiliary electrode and the first auxiliary hole, and the first auxiliary electrode is connected to the third auxiliary electrode through the first auxiliary hole and the second auxiliary hole. You can.

The substrate includes an Evss wire that receives a power voltage from a power generator, and the third auxiliary electrode is connected to the Evss wire to receive the power voltage.

The third auxiliary electrode may be a part branched from the Evss wiring.

The second auxiliary electrode may be in direct contact with the third auxiliary electrode.

The substrate includes a light blocking layer disposed in the thin film transistor area; a buffer layer covering the light blocking layer; a semiconductor layer disposed on the buffer layer and overlapping the light blocking layer; an interlayer insulating film covering the semiconductor layer; a source electrode and a drain electrode disposed on the interlayer insulating film and connected to one side and the other side of the semiconductor layer, respectively, through contact holes penetrating the interlayer insulating film; A passivation film and a planarization film are sequentially stacked on the source electrode and the drain electrode and have a pixel contact hole that exposes the source electrode and connects the source electrode and the anode, wherein the first auxiliary electrode is connected to the source electrode. and the drain electrode and the third auxiliary electrode may be formed of the same material as the light blocking layer.

The organic light emitting display device according to the present invention can secure a sufficient contact area between the Evss auxiliary electrode and the cathode. Accordingly, the preferred embodiment of the present invention has the advantage of effectively improving the luminance deviation depending on the position because it can prevent poor contact between the Evss auxiliary electrode and the cathode.

In addition, the preferred embodiment of the present invention has the advantage of securing a sufficient contact area between the Evss auxiliary electrode and the cathode, thereby preventing a heating phenomenon due to an increase in current density that may occur when the contact area is narrow. .

1 is a block diagram schematically showing an organic light emitting display device.
FIG. 2 is a schematic configuration diagram of the pixel shown in FIG. 1.
Figure 3 is a cross-sectional view showing an organic light emitting display device according to a preferred embodiment of the present invention.
Figure 4 is a diagram schematically showing the auxiliary electrode area of the organic light emitting display device according to the first embodiment of the present invention.
5 to 16 are diagrams for explaining an example of a method of manufacturing an organic light emitting display device according to a first embodiment of the present invention.
Figure 17 is a diagram schematically showing the auxiliary electrode area of the organic light emitting display device according to the second embodiment of the present invention.
18 to 29 are diagrams for explaining an example of a method of manufacturing an organic light emitting display device according to a second embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. In describing various embodiments, the same components may be representatively described at the beginning and omitted in other embodiments.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

1 is a block diagram schematically showing an organic light emitting display device. FIG. 2 is a schematic configuration diagram of the pixel shown in FIG. 1.

Referring to FIG. 1, the organic light emitting display device 10 according to the present invention includes a display driving circuit and a display panel (DIS).

The display driving circuit includes a data driving circuit 12, a gate driving circuit 14, and a timing controller 16, and writes the video data voltage of the input image to the pixels of the display panel DIS. The data driving circuit 12 converts digital video data (RGB) input from the timing controller 16 into an analog gamma compensation voltage and generates a data voltage. The data voltage output from the data driving circuit 12 is supplied to the data wires D1 to Dm. The gate driving circuit 14 sequentially supplies a gate signal synchronized with the data voltage to the gate wires G1 to Gn to select pixels of the display panel DIS to which the data voltage is written.

The timing controller 16 inputs timing signals such as the vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), data enable signal (Data Enable, DE), and main clock (MCLK) input from the host system 19. The operation timing of the data driving circuit 12 and the gate driving circuit 14 is synchronized. The data timing control signal for controlling the data driving circuit 12 includes a source sampling clock (Source Sampling Clock, SSC), a source output enable signal (Source Output Enable, SOE), etc. Gate timing control signals for controlling the gate driving circuit 14 include gate start pulse (Gate Start Pulse, GSP), gate shift clock (GSC), gate output enable signal (GOE), etc. Includes.

The host system 19 may be implemented as any one of a television system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), home theater system, and phone system. The host system 19 includes a system on chip (SoC) with a built-in scaler and converts digital video data (RGB) of the input image into a format suitable for display on a display panel (DIS). The host system 19 transmits timing signals (Vsync, Hsync, DE, MCLK) along with digital video data to the timing controller 16.

The display panel (DIS) includes a pixel array. The pixel array includes pixels defined by data lines (D1 to Dm, m is a positive integer) and gate lines (G1 to Gn, n is a positive integer). Each pixel includes an organic light emitting diode (Organic Light Emitting Diode), which is a self-luminous device.

Referring further to FIG. 2, a plurality of data wires (D) and a plurality of gate wires (G) intersect in the display panel (DIS), and pixels are arranged in a matrix form in each intersection area. Each pixel includes an organic light emitting diode, a driving thin film transistor (TFT) (DT) that controls the amount of current flowing through the organic light emitting diode, and a programming unit (SC) for setting the gate-source voltage of the driving thin film transistor (DT). ) includes.

The programming unit SC may include at least one switch thin film transistor and at least one storage capacitor. The switch thin film transistor is turned on in response to a gate signal from the gate wire (G), thereby applying the data voltage from the data wire (D) to one electrode of the storage capacitor. The driving thin-film transistor (DT) controls the amount of light emitted from the organic light-emitting diode by controlling the amount of current supplied to the organic light-emitting diode according to the magnitude of the voltage charged in the storage capacitor. The amount of light emitted from the organic light emitting diode is proportional to the amount of current supplied from the driving thin film transistor (DT). These pixels are connected to a high-potential voltage source (Evdd) and a low-potential voltage source (Evss), and receive high-potential power supply voltage and low-potential power supply voltage, respectively, from a power generator (not shown). Thin film transistors constituting a pixel may be implemented as p-type or n-type. Additionally, the semiconductor layer of the thin film transistors constituting the pixel may include amorphous silicon, polysilicon, or oxide. Hereinafter, the case where the semiconductor layer contains oxide will be described as an example. The organic light emitting diode includes an anode (ANO), a cathode (CAT), and an organic compound layer interposed between the anode (ANO) and the cathode (CAT). The anode (ANO) is connected to the driving thin film transistor (DT).

Figure 3 is a cross-sectional view showing an organic light emitting display device according to a preferred embodiment of the present invention.

Referring to FIG. 3, an organic light emitting diode display device according to a preferred embodiment of the present invention includes a display panel including a first substrate (SUB1) and a second substrate (SUB2) facing each other. The display panel may further include a filler layer FL interposed between the first substrate SUB1 and the second substrate SUB2. The filler layer FL may include multiple fillers. The filler layer FL may be provided to maintain a cell gap between the first substrate SUB1 and the second substrate SUB2.

The first substrate SUB1 may be a thin film transistor array substrate having pixels on which a thin film transistor T and an organic light emitting diode OLE are arranged. The second substrate SUB2 may be a color filter substrate on which a color filter is formed. The second substrate SUB2 may function as an encapsulation substrate. The first substrate SUB1 and the second substrate SUB2 may be bonded together using a sealant SL. The sealant SL may be disposed at the edges of the first and second substrates SUB1 and SUB2 to maintain a predetermined bonding gap.

The first substrate SUB1 may be made of glass or plastic. For example, the first substrate SUB1 may be made of a plastic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC), and may have flexible characteristics.

On the first substrate SUB1, a thin film transistor T and an organic light emitting diode OLE connected to the thin film transistor T are formed. A light blocking layer (LS) and a buffer layer (BUF) may be formed between the first substrate (SUB1) and the thin film transistor (T). The light blocking layer (LS) is arranged to overlap the semiconductor layer of the thin film transistor (T), especially the channel, and serves to protect the oxide semiconductor device from external light. The buffer layer (BUF) serves to block ions or impurities diffusing from the first substrate (SUB1) and to block external moisture from penetrating.

The thin film transistor (T) includes a semiconductor layer (ACT), a gate electrode (GE), and source/drain electrodes (SE, DE).

A gate insulating film (GI) and a gate electrode (GE) are disposed on the semiconductor layer (ACT). The gate insulating film (GI) insulates the gate electrode (GE) and may be made of a silicon oxide film (SiOx), but is not limited thereto. The gate electrode GE is arranged to overlap the semiconductor layer ACT with the gate insulating film GI interposed therebetween. The gate electrode (GE) is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). and tungsten (W), or an alloy thereof. The gate insulating layer GI and the gate electrode GE may be patterned using the same mask. In this case, the gate insulating layer GI and the gate electrode GE may have the same area. Although not shown, the gate insulating layer GI may be formed to cover the entire surface of the first substrate SUB1.

An interlayer insulating film (IN) is disposed on the gate electrode (GE). The interlayer insulating film (IN) insulates the gate electrode (GE) and the source/drain electrodes (SE, DE) from each other and may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is limited thereto. That is not the case.

Source/drain electrodes (SE, DE) are disposed on the interlayer insulating film (IN). The source electrode (SE) and the drain electrode (DE) are arranged to be spaced apart from each other by a predetermined distance. The source electrode SE contacts one side of the semiconductor layer ACT through a source contact hole penetrating the interlayer insulating film IN. The drain electrode (DE) contacts the other side of the semiconductor layer (ACT) through a drain contact hole penetrating the interlayer insulating film (IN).

The source electrode (SE) and drain electrode (DE) can be made of a single layer or multiple layers. In the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), It may be made of any one selected from the group consisting of nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source electrode (SE) and drain electrode (DE) are multilayered, they are a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, titanium/aluminum, or copper/molytitanium, or molybdenum/aluminum-neodymium/molybdenum, molybdenum. It may be made of a triple layer of /aluminum/molybdenum, titanium/aluminum/titanium, or molytitanium/copper/molytitanium.

As shown, the storage capacitor Cst may be formed in a triple structure in which first to third capacitor electrodes overlap, and may be implemented with a plurality of various layers as needed.

A passivation film (PAS) is located on the thin film transistor (T). The passivation film (PAS) protects the thin film transistor (T) and may be made of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

A planarization film (OC) is located on the passivation film (PAS). The planarization film (OC) is used to flatten the lower step and can be made of organic materials such as photo acryl, polyimide, benzocyclobutene resin, and acrylate. there is. If necessary, either the passivation film (PAS) or the planarization film (OC) may be omitted.

An organic light emitting diode (OLE) is located on the planarization film (OC). An organic light emitting diode (OLE) includes an anode (ANO), an organic compound layer (OL), and a cathode (CAT).

In more detail, an anode (ANO) is located on the planarization film (OC). The anode (ANO) may be divided to correspond to each pixel and assigned one to each pixel. The anode (ANO) is connected to the source electrode (SE) of the thin film transistor (T) through a contact hole penetrating the passivation film (PAS) and the planarization film (OC). The anode (ANO) may include a reflective layer and function as a reflective electrode. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), molybdenum (Mo), titanium (Ti), or an alloy thereof, and is preferably made of APC (silver/palladium/copper). alloy). The anode (ANO) may be made of multiple layers including a reflective layer. As an example, the anode (ANO) may be formed of a triple layer made of ITO/APC/ITO.

A bank layer (BN) dividing pixels is located on the first substrate (SUB1) on which the anode (ANO) is formed. The bank layer (BN) may be made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. The center of the anode (ANO) exposed by the bank layer (BN) may be defined as a light emitting area.

The bank layer BN includes an opening exposing at least a portion of the anode ANO. The bank layer (BN) may be arranged to expose most of the center of the anode (ANO) but cover the side edges of the anode (ANO). The area of the exposed anode (ANO) is preferably designed to the maximum possible value to ensure a sufficient aperture ratio.

The organic compound layer OL is located on the first substrate SUB1 on which the bank layer BN is formed. The organic compound layer OL is widely formed on the entire surface of the first substrate SUB1 and covers the bank layer BN. The organic compound layer (OL) is a layer that emits light by combining electrons and holes, and includes an emission layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), and an electron layer (HTL). It may further include one or more of an electron transport layer (ETL) and an electron injection layer (EIL). The organic light emitting layer (OL) can generate white light and can implement a specific color by combining it with a color filter.

The organic compound layer (OL) that emits white light may have a multi-stack structure such as an n (n is an integer equal to or greater than 1) stack structure. As an example, a two-stack structure includes a charge generation layer (CGL) disposed between an anode (ANO) and a cathode (CAT), and a charge generation layer (CGL) disposed below and above the charge generation layer with the charge generation layer in between. It may include a first stack and a second stack. The first stack and the second stack each include an emission layer and may further include at least one of common layers. The light emitting layer of the first stack and the light emitting layer of the second stack may include light emitting materials of different colors.

A cathode (CAT) is located on the organic compound layer (OL). The cathode (CAT) is formed widely on the entire surface of the first substrate (SUB1) and covers the organic compound layer (OL). The cathode (CAT) may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), and may be made of magnesium (Mg) or calcium (Ca) that is thin enough to allow light to pass through. , aluminum (Al), silver (Ag), or alloys thereof.

Although not shown, a capping layer and a blocking layer may be sequentially disposed on the second electrode E2. The capping layer may be a layer for compensating the color viewing angle. The blocking layer may be a layer to block moisture and foreign substances from entering the organic light emitting diode (OLE). The blocking layer may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). The capping layer and the blocking layer may be formed widely over the entire surface of the substrate to cover a plurality of subpixels.

The organic light emitting display device according to a preferred embodiment of the present invention further includes a connecting member LM bonded to at least one side of the first substrate SUB1. The connection member (LM) may be COF (Chip On Film), but is not limited thereto. The connection member LM is electrically connected to a printed circuit board (PCB), etc., and can receive signals for driving subpixels and transmit them to the display panel. For example, the connection member LM may receive a low-potential power supply voltage (Evss (FIG. 2)) and provide it to the display panel.

For example, the first substrate SUB1 may include an Evss pad portion EVP1 (or a low-potential power pad portion). The Evss pad portion (EVP1) may be disposed outside the sealant (SL) and electrically connected to the connection member (LM). The Evss pad part (EVP1) receives the low-potential power voltage generated from the power generator (not shown) through the connection member (LM) and transmits it to the subpixels inside the sealant (SL). That is, the low-potential power voltage input through the connection member LM may be supplied to the cathode CAT inside the sealant SL.

More specifically, the Evss pad portion (EVP1) includes at least one pad electrode. When there are a plurality of pad electrodes, the pad electrodes may be arranged in different layers with at least one insulating film interposed therebetween, and may be electrically connected through a pad contact hole penetrating the at least one insulating film. For example, as shown in the drawing, the Evss pad portion (EVP1) may include a first pad electrode (PE1) and a second pad electrode (PE2) disposed in different layers with a passivation film (PAS) interposed therebetween. The first pad electrode PE1 and the second pad electrode PE2 may be connected to each other through the first pad contact hole PH1 penetrating the passivation film PAS.

The first pad electrode PE1 is exposed to the outside of the sealant SL. The exposed first pad electrode PE1 may be bonded to the connection member LM. The connection member LM and the first pad electrode PE1 may be bonded to each other through an Anisotropic Conductive Film (ACF) layer interposed therebetween.

The second pad electrode (PE2) may be electrically connected to the Evss line (EVL) located inside the sealant (SL). The Evss line (EVL) may branch from the second pad electrode (PE2). That is, the Evss line (EVL) may be formed integrally with the second pad electrode (PE2). However, it is not limited to this. For example, the Evss line (EVL) and the second pad electrode (PE2) may be disposed on different layers with at least one insulating layer interposed therebetween, and a contact hole penetrating the at least one insulating layer may be formed. can be interconnected through

The Evss wiring (EVL) can be electrically connected to the cathode (CAT) in a preset area. The Evss line (EVL) is connected to the cathode (CAT) in a preset area, so that a low-potential power supply voltage can be supplied to the cathode (CAT). Accordingly, the low-potential power supply voltage applied to the Evss pad portion (EVP1) can be supplied to the cathode (CAT) through the Evss line (EVL). Although not shown, the EVS line (EVL) may be disposed on at least one edge of the display panel and may be connected to the cathode (CAT) at the outer edge of the display panel. Additionally, the Evss line (EVL) may be disposed at at least one edge of the display panel, branch from thereto into a plurality of lines, and extend to be positioned between subpixels located in a preset area. In this case, a plurality of branched wires may be connected to the cathode (CAT) in the preset area. The plurality of branched wires may be electrically connected to the auxiliary electrode (AE), which will be described later, and supply a low-potential power supply voltage to the auxiliary electrode (AE).

On the second substrate SUB2, a black matrix BM and a color filter CF are formed. On the second substrate SUB2, the stacking order of the black matrix BM and the color filter CF may be changed. That is, the color filter (CF) may be formed after the black matrix (BM) is formed, and the black matrix (BM) may be formed after the color filter (CF) is formed. The black matrix (BM) can prevent color mixing defects from occurring between neighboring subpixels. The black matrix BM may be disposed in a non-emission area so as to expose at least the emission area.

The color filter (CF) may include red (R), blue (B), and green (G) color filters (CF). A pixel may include subpixels that emit red (R), blue (B), and green (G) light, and a color filter (CF) may be assigned to each of the corresponding subpixels. Red (R), blue (B), and green (G) color filters (CF) may be partitioned by a black matrix (BM).

In the organic light emitting display device according to the present invention, the white (W) light emitted from the organic compound layer (OL) is divided into red ( By passing through the color filters (CF) of R), green (G), and blue (B), red (R), green (G), and blue (B) can be realized. If necessary, the pixel may further include white (W) subpixels.

The organic light emitting display device according to a preferred embodiment of the present invention may be implemented as a transparent display device. For example, a pixel may include an emissive area (EA) and a transmissive area (TA). The emission area (EA) can be defined as an area where light to implement an input image is emitted. A plurality of subpixels may be arranged in the emission area EA. The transmission area (TA) can be defined as an area through which external light is transmitted so that the user can recognize objects located on the back of the display device. The transmission area (TA) may be defined as an area outside the emission area (EA).

When a bank layer (BN) and a planarization film (OC) are disposed in such a transmission area (TA), the light passing through that part may have a yellowish color, which may cause visual discomfort to the user. . The display device according to a preferred embodiment of the present invention can further improve transmittance by removing the bank layer (BN) and planarization film (OC) from the transmission area (TA).

<First embodiment>

Figure 4 is a diagram schematically showing the auxiliary electrode area of the organic light emitting display device according to the first embodiment of the present invention.

The first substrate (SUB1) according to the first embodiment of the present invention is defined by being divided into a thin film transistor area (TRA) where the thin film transistor (T) is disposed and an auxiliary electrode area (AEA) where the auxiliary electrode (AE) is provided. It can be. The auxiliary electrode area (AEA) may be an area where the auxiliary electrode (AE) and the cathode (CAT) are in contact.

Referring to FIG. 4 along with FIG. 3 , the auxiliary electrode area (AEA) may include an auxiliary structure (AS) electrically connected to the cathode (CAT). The auxiliary structure AS may have a combined structure of the first auxiliary electrode AE1, the second auxiliary electrode AE2, and the third auxiliary electrode AE3.

The first auxiliary electrode AE1 may be located on the auxiliary electrode area AEA of the first substrate SUB1. The first auxiliary electrode (AE1) may receive a low-potential power supply voltage from the Evss line (EVL). The first auxiliary electrode (AE1) may be a part branched from the Evss line (EVL). The first auxiliary electrode AE1 may be formed of the same material E1 on the same layer as the light blocking layer LS.

On the first auxiliary electrode AE1, a first insulating pattern I1 and a second insulating pattern I2 formed by patterning the buffer layer BUF and the interlayer insulating film IN may be sequentially positioned. The first insulating pattern I1 and the second insulating pattern I2 may expose the side surface of the first auxiliary electrode AE1. The first insulating pattern I1 and the second insulating pattern I2 may expose at least a portion of the upper surface adjacent to the side surface of the first auxiliary electrode AE1.

The first insulating pattern I1 may include a first auxiliary hole AH1 exposing at least a portion of the upper surface of the first auxiliary electrode AE1. The second insulating pattern I2 may include a second auxiliary hole AH2 exposing at least a portion of the upper surface of the first auxiliary electrode AE1. The second auxiliary hole (AH2) may expose the first auxiliary hole (AH1).

The second auxiliary electrode AE2 may be located on the second insulating pattern I2. The second auxiliary electrode AE2 may have a larger area than the second insulating pattern I2. For example, the second auxiliary electrode AE2 may be formed on the second insulating pattern I2 to protrude outward from the second insulating pattern I2. Accordingly, the end of the second auxiliary electrode AE2 may have a shape that protrudes outward from the second insulating pattern I2.

The second auxiliary electrode AE2 may be connected to the first auxiliary electrode AE1 through the first auxiliary hole AH1 and the second auxiliary hole AH2. The second auxiliary electrode (AE2) is electrically connected to the Evss line (EVL) through the first auxiliary electrode (AE1) and can receive a low-potential power supply voltage. The second auxiliary electrode (AE2) may be formed of the same material (E2) on the same layer as the source electrode (SE) and drain electrode (DE) of the transistor (T).

The third auxiliary electrode (AE3) may be formed along the outer surfaces of the stacked first auxiliary electrode (AE1), first insulating pattern (I1), second insulating pattern (I2), and second auxiliary electrode (AE2). there is. An end of the third auxiliary electrode AE3 may directly contact the first substrate SUB1. The third auxiliary electrode AE3 may maintain continuity without being separated by a step between the second auxiliary electrode AE2 and the second insulating pattern I2.

The third auxiliary electrode (AE3) is formed to surround the outer surfaces of the stacked first auxiliary electrode (AE1), first insulating pattern (I1), second insulating pattern (I2), and second auxiliary electrode (AE2). , may be connected to the first auxiliary electrode (AE1) and the second auxiliary electrode (AE2). That is, the third auxiliary electrode AE3 may be in direct contact with the side surface and the upper surface of the first auxiliary electrode AE1 at the lower end of the auxiliary structure AS, and the second auxiliary electrode may be in direct contact with the upper surface of the auxiliary structure AS. It may be in direct contact with the top surface, side surface, and bottom surface of (AE2). The third auxiliary electrode (AE3) is electrically connected to the Evss line (EVL) through the first auxiliary electrode (AE1) and the second auxiliary electrode (AE2) and can receive a low-potential power supply voltage.

The third auxiliary electrode (AE3) is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum ( It may be made of a single layer or multiple layers of any one selected from the group consisting of Ta) and tungsten (W) or an alloy thereof. Alternatively, the third auxiliary electrode AE3 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). It may be desirable for the third auxiliary electrode AE3 to be formed of a transparent conductive material with good step coverage.

A portion of the organic compound layer OL may remain on the auxiliary structure AS. The organic compound layer OL may be physically separated by a step between the second auxiliary electrode AE2 and the second insulating pattern I2. Part (R1) (or first part) of the separated organic compound layer (OL) remains on top of the auxiliary structure (AS), and the other part (R2) (or second part) remains in the auxiliary structure (AS). It may remain in the periphery. The other part (R2) may be an extension of the organic compound layer (OL) located in the thin film transistor region (TRA). The organic compound layer OL is separated to expose a portion of the third auxiliary electrode AE3.

The cathode (CAT) may be formed along the outer surface of the stacked third auxiliary electrode (AE3) and the organic compound layer (OL). The cathode CAT may maintain continuity without being separated by a step between the second auxiliary electrode AE2 and the second insulating pattern I2.

The cathode CAT may be formed to surround the outer surface of the stacked third auxiliary electrode AE3 and the organic compound layer OL, and may be connected to the third auxiliary electrode AE3. The cathode (CAT) may be in direct contact with the third auxiliary electrode (AE3) in the area where the organic compound layer (OL) does not remain. That is, the cathode CAT may directly contact the third auxiliary electrode AE3 in the space between the separated first part R1 and the second part R2. The cathode (CAT) is electrically connected to the Evss line (EVL) through the third auxiliary electrode (AE3) and can receive a low-potential power supply voltage.

In the first embodiment of the present invention, the surface area of the third auxiliary electrode AE3, which directly contacts the cathode CAT and transmits a low-potential power supply voltage to the cathode CAT, can be secured sufficiently large, and accordingly, A sufficient contact area between the cathode (CAT) and the third auxiliary electrode (AE3) can be secured. Therefore, since the organic light emitting display device according to the first embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE), luminance deviation due to the sheet resistance of the cathode (CAT) has the advantage of being able to improve effectively. In addition, since the organic light emitting display device according to the first embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE), the current density that can occur when the contact area is narrow increases. It has the advantage of preventing heat generation caused by .

5 to 16 are diagrams for explaining an example of a method of manufacturing an organic light emitting display device according to a first embodiment of the present invention.

The first substrate (SUB1) according to the first embodiment of the present invention is defined by being divided into a thin film transistor area (TRA) where the thin film transistor (T) is disposed and an auxiliary electrode area (AEA) where the auxiliary electrode (AE) is provided. It can be. The auxiliary electrode area (AEA) may be an area where the auxiliary electrode (AE) and the cathode (CAT) are in contact.

Referring to FIGS. 5A and 5B , a light blocking layer LS and a first auxiliary electrode AE1 are formed on the first substrate SUB1. The light blocking layer LS and the first auxiliary electrode AE1 may be formed of the same material E1 on the same layer. That is, the metal material E1 can be applied on the first substrate SUB1 and patterned through a mask process to form the light blocking layer LS and the first auxiliary electrode AE1. The light blocking layer (LS) is located in the thin film transistor region (TRA). The first auxiliary electrode AE1 is located within the auxiliary electrode area AEA.

A buffer layer (BUF) may be formed on the first substrate (SUB1) on which the light blocking layer (LS) and the first auxiliary electrode (AE1) are formed. The buffer layer BUF may be formed widely on the first substrate SUB1 to cover the light blocking layer LS and the first auxiliary electrode AE1.

Referring to FIGS. 6A and 6B , the semiconductor layer ACT is formed on the first substrate SUB1 on which the buffer layer BUF is formed. That is, a semiconductor material can be applied on the buffer layer (BUF) and patterned through a mask process to form the semiconductor layer (ACT). The semiconductor layer (ACT) is located in the thin film transistor region (TRA). The semiconductor layer (ACT) may be formed to overlap the light blocking layer (LS). The semiconductor layer (ACT) does not remain in the auxiliary electrode area (AEA).

Referring to FIGS. 7A and 7B , a gate insulating film GI and a gate electrode GE are formed on the first substrate SUB1 on which the semiconductor layer ACT is formed. That is, the inorganic insulating material and the metal material can be sequentially applied and patterned through a mask process to form the gate insulating film (GI) and the gate electrode (GE). The gate electrode GE may be located in the thin film transistor region TRA. The gate electrode GE may overlap the channel region of the semiconductor layer ACT. The gate electrode (GE) does not remain in the auxiliary electrode area (AEA).

Referring to FIGS. 8A and 8B, on the first substrate (SUB1) on which the gate electrode (GE) is formed, an interlayer insulating film ( IN) is formed. That is, an inorganic insulating material is applied and patterned through a mask process to form an interlayer insulating film (IN) having a source contact hole (SH), a drain contact hole (DH), and a second auxiliary hole (AH2). . The interlayer insulating film (IN) may be formed widely throughout the thin film transistor area (TRA) and the auxiliary electrode area (AEA).

The source contact hole (SH) and the drain contact hole (DH) are formed in the thin film transistor region (TRA) and may penetrate the interlayer insulating film (IN) to expose one side and the other side of the semiconductor layer (ACT), respectively. At this time, an auxiliary hole (AH) may be formed that penetrates the buffer layer (BUF) and the interlayer insulating film (IN) and exposes a portion of the first auxiliary electrode (AE1). The auxiliary hole AH may include a first auxiliary hole AH1 penetrating the buffer layer BUF and a second auxiliary hole AH2 penetrating the interlayer insulating film IN.

Referring to FIGS. 9A and 9B , a source electrode (SE), a drain electrode (DE), and a second auxiliary electrode (AE2) are formed on the first substrate (SUB1) on which the interlayer insulating film (IN) is formed. The source electrode (SE), drain electrode (DE), and second auxiliary electrode (AE2) may be formed of the same material (E2). That is, the metal material E2 is applied and patterned through a mask process to form the source electrode SE, the drain electrode DE, and the second auxiliary electrode AE2.

The source electrode SE is formed in the thin film transistor area TRA and may be connected to one side of the semiconductor layer ACT through the source contact hole SH. The drain electrode DE is formed in the thin film transistor area TRA and may be connected to the other side of the semiconductor layer ACT through the drain contact hole DH. The source electrode (SE) and drain electrode (DE) do not remain in the auxiliary electrode area (AEA). The second auxiliary electrode AE2 is formed in the auxiliary electrode area AEA and may be connected to the first auxiliary electrode AE1 through the first auxiliary hole AH1. The second auxiliary electrode AE2 does not remain in the thin film transistor area TRA.

Referring to FIGS. 10A and 10B , the buffer layer BUF and the interlayer insulating film IN are patterned to form a first insulating pattern I1 and a second insulating pattern I2. That is, in the auxiliary electrode area AEA, the buffer layer BUF and the interlayer insulating film IN may be patterned through a mask process to form the first insulating pattern I1 and the second insulating pattern I2.

In this mask process, a mask MK having an opening OP exposing the auxiliary electrode area AEA may be used. More specifically, although not shown, the photosensitive film may be applied on the first substrate (SUB1) on which the interlayer insulating film (IN) is formed. A portion of the photosensitive film located in the area corresponding to the opening OP may be removed through an exposure process and a development process. Thereafter, as the etching process progresses, the interlayer insulating film IN and the buffer layer BUF may be removed from the area corresponding to the opening OP. However, a portion of the interlayer insulating film IN and a portion of the buffer layer BUF located below the second auxiliary electrode AE2 may remain as the second auxiliary electrode AE2 functions as a barrier.

Thereafter, in the first embodiment of the present invention, an over etch process may be performed. When the over-etching process proceeds, the interlayer insulating film IN and the buffer layer BUF may be further removed from below the second auxiliary electrode AE2. At this time, the remaining interlayer insulating film IN and buffer layer BUF may be referred to as the first insulating pattern I1 and the second insulating pattern I2, respectively. Accordingly, the end of the second auxiliary electrode AE2 may have a shape that protrudes outward compared to the ends of the first and second insulating patterns I1 and I2. That is, a step may be formed between the end of the second auxiliary electrode AE2 and the end of the second insulating pattern I2.

The first insulating pattern (I1) includes a first auxiliary hole (AH1) exposing the first auxiliary electrode (AE1), and the second insulating pattern (I2) includes a second auxiliary hole (AH1) exposing the first auxiliary electrode (AE1). Includes hole (AH2).

Referring to FIGS. 11A and 11B , a third auxiliary electrode AE3 is formed on the first substrate SUB1 on which the first insulating pattern I1 and the second insulating pattern I2 are formed. That is, the third auxiliary electrode AE3 can be formed by applying the metal material E3 and patterning it through a mask process. For example, the film forming process of the metal material E3 to form the third auxiliary electrode AE3 may be performed through a sputtering method. Accordingly, the metal material E3 is formed to have continuity along the outer surfaces of the stacked first auxiliary electrode AE1, first insulating pattern I1, second insulating pattern I2, and second auxiliary electrode AE2. It can be.

Metal materials for forming the third auxiliary electrode (AE3) include copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be made of a single layer or multiple layers of any one selected from the group consisting of neodymium (Nd), tantalum (Ta), and tungsten (W), or an alloy thereof. Alternatively, it may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The metal material used to form the third auxiliary electrode AE3 may preferably be a transparent conductive material with good step coverage.

The third auxiliary electrode AE3 is formed in the auxiliary electrode area AEA, and includes the stacked first auxiliary electrode AE1, first insulating pattern I1, second insulating pattern I2, and second auxiliary electrode ( It is formed along the outer surface of AE2). The third auxiliary electrode AE3 may maintain continuity without being separated by a step between the second auxiliary electrode AE2 and the second insulating pattern I2. The third auxiliary electrode AE3 may be in direct contact with the first auxiliary electrode AE1 and the second auxiliary electrode AE2. The third auxiliary electrode AE3 does not remain in the thin film transistor area TRA.

Referring to FIGS. 12A and 12B , a passivation film (PAS) and a planarization film (OC) are formed on the first substrate (SUB1) on which the third auxiliary electrode (AE3) is formed. That is, an inorganic insulating material and an organic insulating material are sequentially applied and patterned through a mask process to form a passivation layer (PAS) and a planarization layer (OC) having a pixel contact hole (PH). The passivation film (PAS) may be formed throughout the thin film transistor area (TRA) and the auxiliary electrode area (AEA). The planarization film (OC) is formed in the thin film transistor area (TRA) and does not remain in the auxiliary electrode area (AEA).

For example, the sequentially applied inorganic insulating material and organic insulating material are patterned through a mask process to remove the organic insulating material from the auxiliary electrode area (AEA) and to remove the source electrode (SE) from the thin film transistor area (TRA). An exposed pixel contact hole (PH) can be formed. The pixel contact hole (PH) may be formed by penetrating an inorganic insulating material and an organic insulating material. The process of forming the pixel contact hole (PH) may be divided into a process of patterning an organic insulating material and a process of patterning an inorganic insulating material.

Referring to FIGS. 13A and 13B , an anode (ANO) is formed on the first substrate (SUB1) on which the passivation film (PAS) and the planarization film (OC) are formed. That is, the anode (ANO) can be formed by applying a metal material (E4) and patterning it through a mask process.

The anode (ANO) is formed in the thin film transistor region (TRA) and may be connected to the source electrode (SE) through the pixel contact hole (PH). The anode (ANO) does not remain in the auxiliary electrode area (AEA). The metal material E4 may be removed from the auxiliary electrode area AEA through an etching process. At this time, since the passivation film (PAS) remains below the metal material (E4), it is possible to prevent the third auxiliary electrode (AE3) from being damaged during the etching process.

Thereafter, the passivation film (PAS) may be removed from the auxiliary electrode area (AEA) through an additional mask process. That is, as the passivation film PAS of the auxiliary electrode area AEA is removed through an additional mask process, the third auxiliary electrode AE3 may be exposed.

Referring to FIGS. 14A and 14B , a bank layer BN is formed on the first substrate SUB1 on which the anode ANO is formed. That is, the bank layer (BN) can be formed by applying an organic insulating material and patterning it through a mask process.

The bank layer (BN) is formed in the thin film transistor region (TRA) and may have an opening that exposes most of the anode (ANO). The bank layer (BN) does not remain in the auxiliary electrode area (AEA).

Referring to FIGS. 15A and 15B , an organic compound layer OL is formed on the first substrate SUB1 on which the bank layer BN is formed. The organic compound layer OL may be formed throughout the thin film transistor area TRA and the auxiliary electrode area AEA.

The organic compound layer OL may be physically separated by a step between the second auxiliary electrode AE2 and the second insulating pattern I2 in the auxiliary electrode area AEA. A portion (R1) of the separated organic compound layer (OL) may remain on the upper surface of the second auxiliary electrode (AE2), and the other portion (R2) may remain in the periphery of the auxiliary electrode area (AEA). The organic compound layer OL is separated to expose a portion of the third auxiliary electrode AE3.

Referring to FIGS. 16A and 16B , a cathode (CAT) is formed on the first substrate (SUB1) on which the organic compound layer (OL) is formed. The cathode (CAT) may be formed throughout the thin film transistor area (TRA) and the auxiliary electrode area (AEA).

The cathode CAT may maintain continuity without being separated by a step between the second auxiliary electrode AE2 and the second insulating pattern I2. The film forming process of a conductive material to form a cathode (CAT) may be performed through a sputtering method. Accordingly, the conductive material may be formed to have continuity along the outer surfaces of the stacked third auxiliary electrode AE3 and the organic compound layer OL.

In the first embodiment of the present invention, the surface area of the third auxiliary electrode AE3, which directly contacts the cathode CAT and transmits a low-potential power supply voltage to the cathode CAT, can be secured sufficiently large, and accordingly, A sufficient contact area between the cathode (CAT) and the third auxiliary electrode (AE3) can be secured. Therefore, since the organic light emitting display device according to the first embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE), luminance deviation due to the sheet resistance of the cathode (CAT) has the advantage of being able to improve effectively. In addition, since the organic light emitting display device according to the first embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE), the current density that can occur when the contact area is narrow increases. It has the advantage of preventing heat generation caused by .

<Second Embodiment>

Figure 17 is a diagram schematically showing the auxiliary electrode area of the organic light emitting display device according to the second embodiment of the present invention.

The first substrate (SUB1) according to the second embodiment of the present invention is divided into a thin film transistor area (TRA) where the thin film transistor (T) is disposed and an auxiliary electrode area (AEA) where the auxiliary electrode (AE') is provided. can be defined. The auxiliary electrode area (AEA) may be an area where the auxiliary electrode (AE') and the cathode (CAT) are in contact.

Referring to FIG. 17 along with FIG. 3 , the auxiliary electrode area (AEA) may include an auxiliary structure (AS) electrically connected to the cathode (CAT). The auxiliary structure AS may have a combined structure of a first auxiliary electrode AE1' and a second auxiliary electrode AE2'.

On the first substrate SUB1, a first insulating pattern I1 and a second insulating pattern I2 formed by patterning the buffer layer BUF and the interlayer insulating film IN may be sequentially positioned.

The first auxiliary electrode AE2' may be located on the second insulating pattern I2. The first auxiliary electrode AE1' may have a larger area than the second insulating pattern I2. For example, the first auxiliary electrode AE1' may be formed on the second insulating pattern I2 to protrude outward from the second insulating pattern I2. Accordingly, the end of the first auxiliary electrode AE1' may have a shape that protrudes outward from the second insulating pattern I2 in at least one area.

The first auxiliary electrode (AE1') may receive a low-potential power supply voltage from the Evss line (EVL). The first auxiliary electrode (AE1') may be a part branched from the Evss line (EVL). The first auxiliary electrode (AE1') may be formed of the same material (E1') on the same layer as the source electrode (SE) and drain electrode (DE) of the thin film transistor (T).

The second auxiliary electrode AE2' may be formed along the outer surfaces of the stacked first insulating pattern I1, second insulating pattern I2, and first auxiliary electrode AE1'. An end of the second auxiliary electrode AE2' may directly contact the first substrate SUB1. The second auxiliary electrode AE2' may maintain continuity without being separated by a step between the first auxiliary electrode AE1' and the second insulating pattern I2.

The second auxiliary electrode (AE2') is formed to surround the outer surfaces of the stacked first insulating pattern (I1), second insulating pattern (I2), and first auxiliary electrode (AE1'), and the first auxiliary electrode ( AE1') can be connected. That is, the second auxiliary electrode AE2' may directly contact the top surface, side surface, and bottom surface of the first auxiliary electrode AE1' at the upper end of the auxiliary structure AS. The second auxiliary electrode (AE2') is electrically connected to the Evss line (EVL) through the first auxiliary electrode (AE1') and can receive a low-potential power supply voltage.

The second auxiliary electrode (AE2') is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum. It may be made of a single layer or multiple layers of any one selected from the group consisting of (Ta) and tungsten (W) or an alloy thereof. Alternatively, the second auxiliary electrode AE2' may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second auxiliary electrode AE2' may preferably be formed of a transparent conductive material with good step coverage.

A portion of the organic compound layer OL may remain on the auxiliary structure AS. The organic compound layer OL may be physically separated on the auxiliary structure AS by a step between the first auxiliary electrode AE1' and the second insulating pattern I2. Part (R1) (or first part) of the separated organic compound layer (OL) remains on top of the auxiliary structure (AS), and the other part (R2) (or second part) remains in the auxiliary structure (AS). It may remain in the periphery. The other part (R2) may be an extension of the organic compound layer (OL) located in the thin film transistor region (TRA). The organic compound layer OL is separated to expose a portion of the second auxiliary electrode AE2'.

The cathode (CAT) may be formed along the outer surface of the stacked second auxiliary electrode (AE2') and the organic compound layer (OL). The cathode CAT may maintain continuity without being separated by a step between the first auxiliary electrode AE1' and the second insulating pattern I2.

The cathode CAT may be formed to surround the outer surface of the stacked second auxiliary electrode AE2' and the organic compound layer OL, and may be connected to the second auxiliary electrode AE2'. The cathode CAT may be in direct contact with the second auxiliary electrode AE2' in an area where the organic compound layer OL does not remain. That is, the cathode CAT may be in direct contact with the second auxiliary electrode AE2' between the separated first and second parts R1 and R2. The cathode (CAT) is electrically connected to the Evss line (EVL) through the second auxiliary electrode (AE2') and can receive a low-potential power supply voltage.

The second embodiment of the present invention can secure a sufficiently large surface area of the second auxiliary electrode (AE2'), which directly contacts the cathode (CAT) and transmits a low-potential power supply voltage to the cathode (CAT), corresponding to this. Thus, a sufficient contact area between the cathode (CAT) and the second auxiliary electrode (AE2') can be secured. Therefore, since the organic light emitting display device according to the second embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE'), the luminance due to the sheet resistance of the cathode (CAT) It has the advantage of effectively improving deviations. In addition, since the organic light emitting display device according to the second embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE'), the current density that can occur when the contact area is small It has the advantage of preventing heat generation due to increase.

18 to 29 are diagrams for explaining an example of a method of manufacturing an organic light emitting display device according to a second embodiment of the present invention.

The first substrate (SUB1) according to the second embodiment of the present invention is divided into a thin film transistor area (TRA) where the thin film transistor (T) is disposed and an auxiliary electrode area (AEA) where the auxiliary electrode (AE') is provided. can be defined. The auxiliary electrode area (AEA) may be an area where the auxiliary electrode (AE') and the cathode (CAT) are in contact.

Referring to FIGS. 18A and 18B , a light blocking layer LS is formed on the first substrate SUB1. The light blocking layer (LS) is located in the thin film transistor region (TRA).

A buffer layer BUF may be formed on the first substrate SUB1 on which the light blocking layer LS and the first auxiliary electrode AE1' are formed. The buffer layer (BUF) may be formed widely over the thin film transistor area (TRA) and the auxiliary electrode area (AEA).

Referring to FIGS. 19A and 19B , a semiconductor layer (ACT) is formed on the first substrate (SUB1) on which the buffer layer (BUF) is formed. The semiconductor layer (ACT) is located in the thin film transistor region (TRA). The semiconductor layer (ACT) may be formed to overlap the light blocking layer (LS).

Referring to FIGS. 20A and 20B , a gate insulating film GI and a gate electrode GE are formed on the first substrate SUB1 on which the semiconductor layer ACT is formed. The gate electrode GE may be located in the thin film transistor region TRA. The gate electrode GE may overlap the channel region of the semiconductor layer ACT.

Referring to FIGS. 21A and 21B , an interlayer insulating film IN having a source contact hole SH and a drain contact hole DH is formed on the first substrate SUB1 on which the gate electrode GE is formed. That is, an inorganic insulating material is applied and patterned through a mask process to form an interlayer insulating film (IN) having a source contact hole (SH) and a drain contact hole (DH). The interlayer insulating film (IN) may be formed widely throughout the thin film transistor area (TRA) and the auxiliary electrode area (AEA).

The source contact hole (SH) and the drain contact hole (DH) are formed in the thin film transistor region (TRA) and may penetrate the interlayer insulating film (IN) to expose one side and the other side of the semiconductor layer (ACT), respectively.

Referring to FIGS. 22A and 22B , a source electrode (SE), a drain electrode (DE), and a first auxiliary electrode (AE1') are formed on the first substrate (SUB1) on which the interlayer insulating film (IN) is formed. The source electrode (SE), the drain electrode (DE), and the first auxiliary electrode (AE1') may be formed of the same material (E1'). That is, the metal material E1' may be applied and patterned through a mask process to form the source electrode SE, the drain electrode DE, and the first auxiliary electrode AE1'.

The source electrode SE is formed in the thin film transistor area TRA and may be connected to one side of the semiconductor layer ACT through the source contact hole SH. The drain electrode DE is formed in the thin film transistor area TRA and may be connected to the other side of the semiconductor layer ACT through the drain contact hole DH. The first auxiliary electrode AE1' is formed in the auxiliary electrode area AEA.

Referring to FIGS. 23A and 23B , the buffer layer (BUF) and the interlayer insulating film (IN) are patterned to form a first insulating pattern (I1) and a second insulating pattern (I2). That is, in the auxiliary electrode area AEA, the buffer layer BUF and the interlayer insulating film IN may be patterned through a mask process to form the first insulating pattern I1 and the second insulating pattern I2.

In this mask process, a mask MK having an opening OP exposing the auxiliary electrode area AEA may be used. More specifically, although not shown, the photosensitive film may be applied on the first substrate (SUB1) on which the interlayer insulating film (IN) is formed. A portion of the photosensitive film located in the area corresponding to the opening OP may be removed through an exposure process and a development process. Thereafter, as the etching process progresses, the interlayer insulating film IN and the buffer layer BUF may be removed from the area corresponding to the opening OP. However, a portion of the interlayer insulating film IN and a portion of the buffer layer BUF located below the first auxiliary electrode AE1' may remain as the first auxiliary electrode AE1' functions as a barrier.

Thereafter, in the second embodiment of the present invention, an over etch process may be performed. When the over-etching process proceeds, the interlayer insulating film IN and the buffer layer BUF may be further removed from below the first auxiliary electrode AE1'. At this time, the remaining interlayer insulating film IN and buffer layer BUF may be referred to as the first insulating pattern I1 and the second insulating pattern I2, respectively. Accordingly, the end of the first auxiliary electrode AE1' may have a shape that protrudes outward compared to the ends of the first and second insulating patterns I1 and I2. That is, a step may be formed between the end of the first auxiliary electrode AE1' and the end of the second insulating pattern I2.

Referring to FIGS. 24A and 24B , a second auxiliary electrode AE2' is formed on the first substrate SUB1 on which the first insulating pattern I1 and the second insulating pattern I2 are formed. That is, the second auxiliary electrode AE2' can be formed by applying the metal material E2' and patterning it through a mask process. For example, the film forming process of the metal material E2' to form the second auxiliary electrode AE2' may be performed through a sputtering method. Accordingly, the metal material E2' may be formed to have continuity along the outer surfaces of the stacked first insulating pattern I1, second insulating pattern I2, and first auxiliary electrode AE1'.

Metal materials for forming the second auxiliary electrode (AE2') include copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), and nickel (Ni). , neodymium (Nd), tantalum (Ta), and tungsten (W). It may be made of a single layer or multiple layers of any one selected from the group consisting of, or an alloy thereof. Alternatively, it may be formed of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The metal material used to form the second auxiliary electrode AE2' may preferably be a transparent conductive material with good step coverage.

The second auxiliary electrode (AE2') is formed in the auxiliary electrode area (AEA) and forms the outer surface of the stacked first insulating pattern (I1), second insulating pattern (I2), and first auxiliary electrode (AE1'). It is formed according to The second auxiliary electrode AE2' may maintain continuity without being separated by a step between the first auxiliary electrode AE1' and the second insulating pattern I2. The second auxiliary electrode AE2' may be in direct contact with the first auxiliary electrode AE1'.

Referring to FIGS. 25A and 25B , a passivation film (PAS) and a planarization film (OC) are formed on the first substrate (SUB1) on which the second auxiliary electrode (AE2') is formed. That is, an inorganic insulating material and an organic insulating material are sequentially applied and patterned through a mask process to form a passivation layer (PAS) and a planarization layer (OC) having a pixel contact hole (PH). The passivation film (PAS) may be formed throughout the thin film transistor area (TRA) and the auxiliary electrode area (AEA). The planarization film (OC) is formed in the thin film transistor area (TRA) and does not remain in the auxiliary electrode area (AEA).

For example, the sequentially applied inorganic insulating material and organic insulating material are patterned through a mask process to remove the organic insulating material from the auxiliary electrode area (AEA) and to remove the source electrode (SE) from the thin film transistor area (TRA). An exposed pixel contact hole (PH) can be formed. The pixel contact hole (PH) may be formed by penetrating an inorganic insulating material and an organic insulating material. The process of forming a pixel contact hole (PH) can be divided into a process of patterning an organic insulating material and a process of patterning an inorganic insulating material.

Referring to FIGS. 26A and 26B , an anode (ANO) is formed on the first substrate (SUB1) on which the passivation film (PAS) and the planarization film (OC) are formed. That is, the anode (ANO) can be formed by applying a metal material (E3') and patterning it through a mask process.

The anode (ANO) is formed in the thin film transistor region (TRA) and may be connected to the source electrode (SE) through the pixel contact hole (PH). The anode (ANO) does not remain in the auxiliary electrode area (AEA). The metal material E3' may be removed from the auxiliary electrode area AEA through an etching process. At this time, since the passivation film (PAS) remains below the metal material (E3'), it is possible to prevent the second auxiliary electrode (AE2') from being damaged during the etching process.

Thereafter, the passivation film (PAS) may be removed from the auxiliary electrode area (AEA) through an additional mask process. That is, as the passivation film PAS of the auxiliary electrode area AEA is removed through an additional mask process, the second auxiliary electrode AE2' may be exposed.

Referring to FIGS. 27A and 27B , a bank layer (BN) is formed on the first substrate (SUB1) on which the anode (ANO) is formed. That is, the bank layer (BN) can be formed by applying an organic insulating material and patterning it through a mask process.

The bank layer (BN) is formed in the thin film transistor region (TRA) and may have an opening that exposes most of the anode (ANO). The bank layer (BN) does not remain in the auxiliary electrode area (AEA).

Referring to FIGS. 28A and 28B , an organic compound layer OL is formed on the first substrate SUB1 on which the bank layer BN is formed. The organic compound layer OL may be formed throughout the thin film transistor area TRA and the auxiliary electrode area AEA.

The organic compound layer OL may be physically separated by a step between the first auxiliary electrode AE1' and the second insulating pattern I2 in the auxiliary electrode area AEA. A portion (R1) of the separated organic compound layer (OL) may remain on the upper surface of the first auxiliary electrode (AE1'), and the other portion (R2) may remain in the periphery of the auxiliary electrode area (AEA). The organic compound layer OL is separated to expose a portion of the second auxiliary electrode AE2'.

Referring to FIGS. 29A and 29B , a cathode (CAT) is formed on the first substrate (SUB1) on which the organic compound layer (OL) is formed. The cathode (CAT) may be formed throughout the thin film transistor area (TRA) and the auxiliary electrode area (AEA).

The cathode CAT may maintain continuity without being separated by a step between the first auxiliary electrode AE1' and the second insulating pattern I2. The film forming process of a conductive material to form a cathode (CAT) may be performed through a sputtering method. Accordingly, the conductive material may be formed to have continuity along the outer surfaces of the stacked second auxiliary electrode AE2' and the organic compound layer OL.

The second embodiment of the present invention can secure a sufficiently large surface area of the second auxiliary electrode (AE2'), which directly contacts the cathode (CAT) and transmits a low-potential power supply voltage to the cathode (CAT), corresponding to this. Thus, a sufficient contact area between the cathode (CAT) and the second auxiliary electrode (AE2') can be secured. Therefore, since the organic light emitting display device according to the second embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE'), the luminance due to the sheet resistance of the cathode (CAT) It has the advantage of effectively improving deviations. In addition, since the organic light emitting display device according to the second embodiment of the present invention can secure a sufficient contact area between the cathode (CAT) and the auxiliary electrode (AE'), the current density that can occur when the contact area is small It has the advantage of preventing heat generation due to increase.

Through the above-described content, those skilled in the art will be able to make various changes and modifications without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be determined by the scope of the patent claims.

SUB1: 1st substrate SUB2: 2nd substrate
TRA: thin film transistor area AEA: auxiliary electrode area
T: Thin film transistor OLE: Organic light emitting diode
OL: Organic compound layer BN: Bank layer
CAT: Cathode EVL: Evss wiring
AS: Auxiliary structure
AE, AE1, AE2, AE3, AE1', AE2': Auxiliary electrode
I1: First insulating pattern I2: Second insulating pattern

Claims (20)

A substrate having a thin film transistor region on which a thin film transistor is disposed and an auxiliary electrode region on which an auxiliary structure is disposed; and
An organic light emitting diode disposed on the substrate and having an anode electrically connected to the thin film transistor, a cathode facing the anode, and an organic compound layer interposed between the anode and the cathode,
The auxiliary structure is,
first insulating pattern;
a second insulating pattern located on the first insulating pattern;
a first auxiliary electrode located on the second insulating pattern and having an end that protrudes outward from an end of the second insulating pattern; and
Comprising a stacked first insulating pattern, a second insulating pattern, and a second auxiliary electrode formed along an outer surface of the first auxiliary electrode,
The organic compound layer is,
separated from the auxiliary electrode area to expose a portion of the second auxiliary electrode,
The cathode is,
It is directly contacted to the exposed second auxiliary electrode,
The end of the second auxiliary electrode is,
An organic light emitting display device in direct contact with the substrate on which the stacked first and second insulating patterns are not located.
According to claim 1,
The substrate is,
Includes Evss wiring that receives the power voltage from the power generator,
The first auxiliary electrode is,
An organic light emitting display device connected to the Evss wiring and receiving the power voltage.
According to claim 2,
The first auxiliary electrode is,
An organic light emitting display device, which is a part branched from the Evss wiring.
According to claim 1,
The area of the first auxiliary electrode is,
An organic light emitting display device that is larger than the area of the second insulating pattern.
delete According to claim 1,
The organic compound layer is,
An organic light emitting display device comprising a first part located on an upper surface of the auxiliary structure, and a second part located in a periphery of the auxiliary structure.
According to claim 6,
The cathode is,
An organic light emitting display device in direct contact with the second auxiliary electrode in a space spaced between the first part and the second part.
According to claim 1,
The substrate is,
A light blocking layer disposed in the thin film transistor area;
a buffer layer covering the light blocking layer;
a semiconductor layer disposed on the buffer layer and overlapping the light blocking layer;
an interlayer insulating film covering the semiconductor layer;
a source electrode and a drain electrode disposed on the interlayer insulating film and connected to one side and the other side of the semiconductor layer, respectively, through contact holes penetrating the interlayer insulating film;
A passivation film and a planarization film are sequentially stacked on the source electrode and the drain electrode and have a pixel contact hole that exposes the source electrode and connects the source electrode and the anode,
The first auxiliary electrode is,
An organic light emitting display device formed of the same material as the source electrode and the drain electrode.
According to claim 1,
The second auxiliary electrode is,
An organic light emitting display device made of ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).
According to claim 1,
The auxiliary structure is,
It includes a third auxiliary electrode interposed between the substrate and the first insulating pattern,
The first insulating pattern is,
It includes a first auxiliary hole exposing the third auxiliary electrode,
The second insulating pattern is,
It includes a second auxiliary hole exposing the third auxiliary electrode and the first auxiliary hole,
The first auxiliary electrode is,
An organic light emitting display device connected to the third auxiliary electrode through the first auxiliary hole and the second auxiliary hole.
According to claim 10,
The substrate is,
Includes Evss wiring that receives the power voltage from the power generator,
The third auxiliary electrode is,
An organic light emitting display device connected to the Evss wiring and receiving the power voltage.
According to claim 11,
The third auxiliary electrode is,
An organic light emitting display device, which is a part branched from the Evss wiring.
According to claim 10,
The second auxiliary electrode is,
An organic light emitting display device that is in direct contact with the third auxiliary electrode.
According to claim 10,
The substrate is,
A light blocking layer disposed in the thin film transistor area;
a buffer layer covering the light blocking layer;
a semiconductor layer disposed on the buffer layer and overlapping the light blocking layer;
an interlayer insulating film covering the semiconductor layer;
a source electrode and a drain electrode disposed on the interlayer insulating film and connected to one side and the other side of the semiconductor layer, respectively, through contact holes penetrating the interlayer insulating film;
A passivation film and a planarization film are sequentially stacked on the source electrode and the drain electrode and have a pixel contact hole that exposes the source electrode and connects the source electrode and the anode,
The first auxiliary electrode is,
Formed from the same material as the source electrode and the drain electrode,
The third auxiliary electrode is,
An organic light emitting display device formed of the same material as the light blocking layer. According to claim 10,
The first insulating pattern and the second insulating pattern are,
An organic light emitting display device exposing a portion of an upper surface adjacent to a side surface of the third auxiliary electrode.
According to claim 10,
The area of the first auxiliary electrode is,
An organic light emitting display device that is larger than the area of the second insulating pattern.
According to claim 10,
The end of the first auxiliary electrode is,
An organic light emitting display device having a shape protruding outside of the second insulating pattern.
According to claim 13,
The second auxiliary electrode is,
An organic light emitting display device in direct contact with a side surface and a top surface of the third auxiliary electrode, and in direct contact with a top surface, a side surface, and a bottom surface of the first auxiliary electrode.
According to claim 10,
The organic compound layer is,
Separated by a step between the first auxiliary electrode and the second insulating pattern,
An organic light emitting display device comprising a first part located on an upper surface of the auxiliary structure, and a second part located in a periphery of the auxiliary structure.
According to claim 19,
The cathode is,
Not separated by a step between the first auxiliary electrode and the second insulating pattern,
An organic light emitting display device in direct contact with the second auxiliary electrode in a space spaced between the first part and the second part.

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