KR102655045B1 - Gate driving circuit and display device including the same - Google Patents

Abstract

A gate driving circuit that can prevent deterioration of a transistor by reducing the holding time of an output node of a dummy stage in a gate driving circuit of a gate-in-panel structure and a display device including the same are provided. In the gate driving circuit, the level shifter sequentially outputs the first and second reset signals, and some of the multiple dummy stages are simultaneously reset in priority according to the first reset signal, and the rest are reset in subordinate priority according to the second reset signal. reset at the same time.

Description

Gate driving circuit and display device including the same}

The present invention relates to a gate driving circuit, and in particular to a gate driving circuit capable of preventing deterioration of a transistor in the dummy stage of a gate driving circuit composed of a gate in panel (GIP) structure, and a display device including the same. will be.

A liquid crystal display device is a display panel including a plurality of pixels equipped with thin film transistors connected to gate lines and data lines, a gate driving circuit for sequentially providing gate signals to the gate lines, and a device for providing data signals to the data lines. Includes a data driving circuit.

Typically, the gate driving circuit and the data driving circuit are implemented as integrated circuits, and they are mounted on a flexible film such as a tape carrier package or chip on film and attached to the display panel. In addition, liquid crystal displays with a Gate In Panel (GIP) structure have recently been developed, in which part of the gate driving circuit is embedded within the display panel to reduce manufacturing costs and reduce the bezel area.

Figure 1 is a diagram schematically showing a gate driving circuit built into a display panel in a conventional GIP structure liquid crystal display device.

As shown in FIG. 1, the conventional gate driving circuit 10 includes N stages (S1 to Sn) that are driven dependently according to a plurality of externally provided gate clock signals (GCLK) and start signals (VST). do. In addition, a plurality of dummy stages (d1 to d6) are formed at the rear of the N-th stage (Sn). Each of the N stages (S1 to Sn) and the multiple dummy stages (d1 to d6) is composed of multiple transistors.

The start signal (VST) is provided to the first stage (S1). And, except for the first stage (S1), the remaining stages, that is, the second stage (not shown) to the N-th stage (Sn) and a plurality of dummy stages (d1 to d6), each use the output of the previous stage as a start signal. It is provided and operated sequentially.

In addition, each of the N stages (S1 to SN), excluding a plurality of dummy stages (d1 to d6), is sequentially reset by receiving the output of the subsequent stage as a reset signal. Each of the multiple dummy stages (d1 to d6) is simultaneously reset according to an externally provided reset signal (RST).

Figure 2 is a timing diagram showing the operation of a conventional gate driving circuit.

Referring to Figures 1 and 2, the first stage (S1) among the N stages (S1 to SN) of the gate driving circuit 10 outputs the first gate signal (Gout_1) according to the start signal (VST). In addition, the second to Nth stages (Sn), excluding the first stage (S1), receive the output of the previous stage as a start signal and output gate signals, respectively.

Additionally, the first stage (S1) is reset by receiving the output of a subsequent stage, for example, the sixth stage (not shown) as a reset signal. The second to Nth stages (Sn) are also reset by receiving the output of the subsequent stage as a reset signal.

The first dummy stage (d1) receives the N-th gate signal (Gout_n) of the N-th stage (Sn) as a start signal and outputs the first dummy signal (d_1). The first dummy signal (d_1) is provided as a reset signal of the (N-5)th stage (not shown) among the N stages (S1 to SN).

The second dummy stage (not shown) receives the first dummy signal (d_1) of the first dummy stage (d1) as a start signal and outputs the second dummy signal (d_2). The second dummy signal (d_2) is provided as a reset signal of the (N-4)th stage (not shown) among the N stages (S1 to SN).

Likewise, the sixth dummy stage (d6) receives the fifth dummy signal (not shown) of the fifth dummy stage (not shown) as a start signal and outputs the sixth dummy signal (d_6). The sixth dummy signal (d_6) is provided as a reset signal of the Nth stage (Sn) among the N stages (S1 to SN).

The first dummy stage d1 to the sixth dummy stage d6 are simultaneously reset by a reset signal RST provided from the outside. At this time, the reset signal (RST) is provided to the gate driving circuit 10 after the sixth dummy signal (d_6) is output from the sixth dummy stage (d6).

Because of this, the conventional gate driving circuit 10 increases the hold period of the output node in each of the multiple dummy stages d1 to d6. In particular, the first dummy stage (d1) must hold the output node for a holding time (T1) of approximately 6H or more, that is, until the sixth dummy signal (d_6) is output from the sixth dummy stage (d6).

This increase in the hold period of the output node deteriorates the transistors provided in each of the multiple dummy stages (d1 to d6). In addition, deterioration of the transistors causes malfunction of the multiple dummy stages (d1 to d6) and the gate driving circuit 10 including them, thereby lowering the operational reliability of the liquid crystal display device.

The object of the present invention is to provide a gate driving circuit that can prevent deterioration of a dummy stage transistor and a display device including the same.

The gate driving circuit of the present invention for achieving the above object includes a level shift and a shift register.

The level shift generates a plurality of gate clock signals, a start signal, a first reset signal, and a second reset signal in response to the gate control signal.

The shift register consists of multiple gate stages and multiple dummy stages. Some of the plurality of dummy stages are simultaneously reset in priority order in response to the first reset signal. The remainder of the plurality of dummy stages are simultaneously reset to lower priority in response to the second reset signal.

The display device of the present invention for achieving the above object includes a display panel, a timing control unit, and a gate driving circuit.

The gate driving circuit includes a level shifter and a shift register. The shift register is placed in a GIP structure inside the display panel, and the level shifter is placed on a printed circuit board connected to the display panel.

In the gate driving circuit according to the present invention, a plurality of dummy stages of the shift register can be reset by the first reset signal and the second reset signal sequentially output from the level shifter. At this time, some of the plurality of dummy stages may be simultaneously reset in priority according to the first reset signal, and others may be simultaneously reset in subordinate priority according to the second reset signal.

Accordingly, the gate driving circuit can reduce the output node holding time of the first dummy stage among the plurality of dummy stages, thereby preventing deterioration of the plurality of transistors inside the dummy stage.

Additionally, by preventing deterioration of the transistor of the dummy stage, malfunction of the gate driving circuit does not occur, which can improve the operational reliability of the display device.

Figure 1 is a diagram schematically showing a gate driving circuit built into a display panel in a conventional GIP structure liquid crystal display device.
Figure 2 is a timing diagram showing the operation of a conventional gate driving circuit.
Figure 3 is a diagram showing a display device according to an embodiment of the present invention.
FIG. 4 is a diagram showing the level shifter of the gate driving circuit shown in FIG. 3.
FIG. 5 is a diagram showing the shift register of the gate driving circuit shown in FIG. 3.
Figure 6 is a timing diagram showing the operation of a display device according to an embodiment of the present invention.

Hereinafter, a display device according to the present invention will be described in detail with reference to the attached drawings. For convenience of explanation, the display device of this embodiment is an example of a liquid crystal display device, but the present invention is not limited thereto. The display device of the present invention may be one of various flat panel displays, such as a plasma display panel, a field emission display device, and an organic light emitting display device, in addition to a liquid crystal display device.

Figure 3 is a diagram showing a display device according to an embodiment of the present invention.

Referring to FIG. 3, the display device 100 of this embodiment may include a display panel 110 and driving circuits for driving the display panel 110. The driving circuits may include a gate driving circuit 120, a data driving circuit 150, and a timing control unit 160.

The display panel 110 may be a liquid crystal panel including an array substrate (not shown), a color filter substrate (not shown), and a liquid crystal layer (not shown) sandwiched between the two substrates, but is not limited thereto. The display panel 110 may include a display area (A/A) and a non-display area (N/A).

In the display area (A/A) of the display panel 110, a plurality of gate lines (GL) and a plurality of data lines (DL) are arranged to intersect each other, and a thin film transistor (T) and a liquid crystal cell are formed in the intersection area of each line. A pixel (P) including (LC) may be configured.

The thin film transistor (T) of each pixel (P) has a gate electrode connected to the gate line (GL), a source electrode connected to the data line (DL), and a drain electrode connected to one end of the liquid crystal cell (LC). One end of the liquid crystal cell (LC) is connected to the drain electrode of the thin film transistor (T), and a common voltage (VCOM) is applied to the other end.

The thin film transistor (T) is turned on by a gate signal applied through the gate line (GL), and transmits the pixel voltage applied through the data line (DL) to the liquid crystal cell (LC). The liquid crystal cell (LC) charges the pixel voltage transmitted from the thin film transistor (T) and maintains the charged pixel voltage until the next frame of the display panel 101. In addition, the liquid crystal cell (LC) displays an image by adjusting the light transmittance by changing the arrangement of the liquid crystal according to the electric field formed by the charged pixel voltage and the common voltage applied to the other end.

The gate driving circuit 120 may include a level shifter 130 and a shift register 140. The level shifter 130 may be disposed outside the display panel 110, for example, on a printed circuit board (not shown) connected to the display panel 110 through a flexible film (not shown). The shift register 140 may be arranged in a gate in panel (GIP) structure in the non-display area (N/A) of the display panel 110.

The gate driving circuit 120 may generate a plurality of gate signals in response to the gate control signal (GCS) provided from the timing control unit 160. The gate driving circuit 120 may sequentially output multiple gate signals to multiple gate lines GL of the display panel 110 .

To explain further, the level shifter 130 responds to the gate control signal (GCS) provided from the timing control unit 160 and sends a plurality of signals, for example, a plurality of gate clock signals (GCLK), a start signal (VST), a first A reset signal (RST1) and a second reset signal (RST2) can be generated. The level shifter 130 can output multiple generated signals to the shift register 140.

The shift register 140 may generate a plurality of gate signals in response to a start signal (VST) output from the level shifter 130 and a plurality of gate clock signals (GCLK). The shift register 140 may include multiple gate stages (not shown) and multiple dummy stages (not shown). Each stage may be composed of multiple transistors.

Each of the plurality of gate stages and the plurality of dummy stages can be operated dependently according to the start signal (VST) and the gate signal of the previous stage to output the gate signal and the dummy signal.

Additionally, each of the multiple gate stages can be reset according to the output of the subsequent stage. Each of the plurality of dummy stages may be reset in response to the first reset signal (RST1) and the second reset signal (RST2) output from the level shifter 130. At this time, some of the multiple dummy stages may be simultaneously reset in priority order according to the first reset signal (RST1), and the remainder may be simultaneously reset as subordinate priority according to the second reset signal (RST2).

Accordingly, the gate driving circuit 120 of this embodiment can reduce the output node holding period of multiple dummy stages. Due to this, the gate driving circuit 120 can prevent malfunction of the gate driving circuit 120 by preventing deterioration of transistors provided inside a plurality of dummy stages. The specific configuration of this gate driving circuit 120 will be described in more detail later with reference to the drawings.

The data driving circuit 150 may generate a data signal from the image data (DATA) in response to the data control signal (DCS) provided from the timing control unit 160. Data signals may be output to each pixel (P) of the display area (A/A) through a plurality of data lines (DL) of the display panel 110.

The timing control unit 160 may generate a gate control signal (GCS) and a data control signal (DCS) from a timing signal (TS) provided from an external system (not shown). The gate control signal (GCS) may be output to the gate driving circuit 120, and the data control signal (DCS) may be output to the data driving circuit 150.

Additionally, the timing control unit 160 may generate image data (DATA) by sorting image signals (RGB) input from an external system according to the resolution of the display panel 110. Image data (DATA) may be output to the data driving circuit 150 together with the data control signal (DCS).

FIG. 4 is a diagram showing the level shifter of the gate driving circuit shown in FIG. 3.

Referring to FIGS. 3 and 4, the level shifter 130 of this embodiment includes a switching signal generator 131, a first switch 132, a second switch 133, a switch control unit 134, and a selection unit 135. ) and a plurality of signal generators (136, 137, 138). The plurality of signal generators 136, 137, and 138 may include a first reset signal generator 136, a second reset signal generator 137, and a start signal generator 138.

The switching signal generator 131 may generate the first switching signal S1 and the second switching signal S2 according to the gate control signal GCS provided from the timing control unit 160. The gate control signal (GCS) may include a gate start signal (GST), a first clock signal (CLK_on), and a second clock signal (CLK_off). The switching signal generator 131 may generate a first switching signal (S1) and a second switching signal (S2) by combining the above-described gate control signal (GCS).

To this end, the switching signal generator 131 may be composed of multiple logic elements. The switching signal generator 131 may include three AND gate elements (AND1 to AND3), one OR gate element (OR), and one inverter element (NOT).

The first AND gate element (AND1) outputs the logical product of the gate start signal (GST) and the first clock signal (CLK_on). The OR gate element (OR) outputs the logical sum of the output of the first AND gate element (AND1) and the output of the inverter element (NOT). The inverter element (NOT) inverts the second clock signal (CLK_off) and outputs it. The second AND gate element (AND2) logically multiplies the output of the gate start signal (GST) and the OR gate element (OR) and outputs the first switching signal (S1). The third AND gate element AND3 outputs a second switching signal S2 by logically multiplying the gate start signal GST and the second clock signal CLK_off. The first switching signal S1 and the second switching signal S2 may be output at one of a first level, for example, a high level, and a second level, for example, a low level.

The first switch 132 may perform a switching operation to provide the first switching signal S1 to the selection unit 135. The second switch 133 may perform a switching operation to provide the second switching signal S2 to the selection unit 135.

The switch control unit 134 can control the switching operations of the first switch 132 and the second switch 133. The switch control unit 134 can turn on both the first switch 132 and the second switch 133 to connect the switching signal generator 131 and the selection unit 135. Accordingly, the first switching signal (S1) and the second switching signal (S2) output from the switching signal generating unit 131 may be transmitted to the selecting unit 135.

In addition, the switch control unit 134 determines the A node (A) level between the selection unit 135 and the start signal generation unit 138, and switches both the first switch 132 and the second switch 133 accordingly. It can be turned off. The switch control unit 134 can turn off both the first switch 132 and the second switch 133 when the A node (A) is at the first level. Accordingly, the connection between the switching signal generator 131 and the selection unit 135 may be blocked.

The selection unit 135 selects a plurality of signal generators 136 according to the level of the first switching signal (S1) and the second switching signal (S2) provided from the first switch 132 and the second switch 133, respectively. , 137, 138) operations can be controlled.

For example, if both the first switching signal (S1) and the second switching signal (S2) are at the first level, the selection unit 135 selects the first reset signal generator ( 136) can be controlled to operate. In addition, if the first switching signal (S1) is at the second level and the second switching signal (S2) is at the first level, the selection unit 135 selects the second reset among the plurality of signal generators (136, 137, and 138). The signal generator 137 can be controlled to operate. If the first switching signal (S1) is at the first level and the second switching signal (S2) is at the second level, the selection unit 135 selects the start signal generator ( 138) can be controlled to operate.

Additionally, when the connection between the switching signal generator 131 and the selection unit 135 is blocked by the switch control unit 134, the selection unit 135 can maintain its previous state. In other words, the switch control unit 134 turns off both the first switch 132 and the second switch 133 when the node A is at the first level. Node A (A) is a node between the selection unit 135 and the start signal generation unit 138, and may be at the first level when the start signal generation unit 138 is operated by the selection unit 135. Therefore, even if the connection between the switching signal generation unit 131 and the selection unit 135 is blocked by the switch control unit 134, the selection unit 135 can maintain operation control of the start signal generation unit 138. At this time, the selection unit 135 may output the gate start signal (GST) provided from the timing control unit 160 as the start signal (VST).

The first reset signal generator 136 may generate and output the first reset signal RST1 under the control of the selector 135. The first reset signal generator 136 may include a first clock counter 136_a and a first output terminal.

The first clock counter 136_a may count the second clock signal CLK_off provided from the timing control unit 160. The first clock counter 136_a can count the second clock signal CLK_off for 4H.

The first output terminal may output the first reset signal RST1 at the first level during the count operation of the first clock counter 136_a. The first output stage may be composed of two transistors (T1 and T2) disposed between the gate high voltage (VGH) and the gate low voltage (VGL).

The second reset signal generator 137 may generate and output the second reset signal RST2 under the control of the selector 135. The second reset signal generator 137 may include a second clock counter 137_a and a second output terminal.

The second clock counter 137_a may count the second clock signal CLK_off provided from the timing control unit 160. The second clock counter 137_a can count the second clock signal CLK_off for 4H.

The second output terminal may output the second reset signal (RST2) at the first level during the count operation of the second clock counter (137_a). The second output stage may be composed of two transistors (T3 and T4) disposed between the gate high voltage (VGH) and the gate low voltage (VGL).

The start signal generator 138 may generate and output the start signal VST under the control of the selector 135. The start signal generator 138 may include a third output stage consisting of two transistors T5 and T6 disposed between the gate high voltage (VGH) and the gate low voltage (VGL).

The first reset signal generator 136, the second reset signal generator 137, and the start signal generator 138 may be operated under the control of the selection unit 135. At this time, the first reset signal generator 136, the second reset signal generator 137, and the start signal generator 138 do not operate simultaneously. That is, while the first reset signal generator 136 is operating, the second reset signal generator 137 and the start signal generator 138 are not operated. Likewise, the first reset signal generator 136 and the start signal generator 138 are not operated during the operation of the second reset signal generator 137, and the first reset signal is not operated during the operation of the start signal generator 138. The generator 136 and the second reset signal generator 137 do not operate.

As described above, the level shifter 130 of the present embodiment responds to the gate control signal (GCS) provided from the timing control unit 160 to generate the first reset signal (RST1), the second reset signal (RST2), and the start signal (VST). ) can be output respectively. And, as described above, the first reset signal (RST1) is output to some of the plurality of dummy stages of the shift register 140 in priority to reset them, and the second reset signal (RST2) is output to the remaining dummy stages of the shift register 140. You can reset them by outputting them in lower priority.

Accordingly, in the gate driving circuit 120 of this embodiment, the holding time of the output nodes of multiple dummy stages can be reduced. As a result, it is possible to prevent malfunction of the gate driving circuit 120 by preventing deterioration of a plurality of transistors provided inside the dummy stage.

FIG. 5 is a diagram showing the shift register of the gate driving circuit shown in FIG. 3.

Referring to Figures 3 and 5, the shift register 140 of this embodiment may include a plurality of gate stages (ST1 to STn) and a plurality of dummy stages (DST1 to DST3). Multiple gate stages (ST1 to STn) and multiple dummy stages (DST1 to DST3) may be connected in a dependent manner. A plurality of dummy stages (DST1 to DST3) may be disposed at the rear of the last gate stage (STn) among the plurality of gate stages (ST1 to STn), for example, the Nth gate stage (STn). Here, N is a natural number greater than 1.

The plurality of gate stages (ST1 to STn) each generate a pair of gate signals and sequentially output them to the plurality of gate lines (GL) of the display panel 110. (STn) may be included. A plurality of gate stages (ST1 to STn) may be selectively connected to a plurality of clock signal lines that supply the first gate clock signal (GCLK1) to the fourth gate clock signal (GCLK4).

The first to third dummy stages (DST1) to the third dummy stages (DST3) each generate a pair of dummy signals and sequentially output them to the plurality of gate stages (ST1 to STn). ) may include. The multiple dummy signals D1 to D6 output from the multiple dummy stages DST1 to DST3 may be signals that reset the multiple gate stages ST1 to STn. A plurality of dummy stages (DST1 to DST3) may be selectively connected to a plurality of clock signal lines that supply the first gate clock signal (GCLK1) to the fourth gate clock signal (GCLK4).

The plurality of gate stages (ST1 to STn) and the plurality of dummy stages (DST1 to DST3), except for the first gate stage (ST1), may be operated dependently in response to the output of the previous stage.

Specifically, the first gate stage (ST1) may output a first gate signal (G1) and a second gate signal (G2) in response to the start signal (VST) provided from the level shifter 130. The first gate signal G1 and the second gate signal G2 may be sequentially output to the first gate line and the second gate line of the display panel 110. At the same time, the first gate signal (G1) and the second gate signal (G2) may be provided as start signals of the second gate stage (not shown). Accordingly, the second gate stage may output a third gate signal (not shown) and a fourth gate signal (not shown) in response to the first gate signal (G1) and the second gate signal (G2), respectively.

Likewise, the Nth gate stage (STn) receives the gate signal output from the (N-1)th gate stage (not shown) as a start signal and receives the (N-1)th gate signal (G(n-1)) and The Nth gate signal (Gn) can be output. In addition, the first dummy stage (DST1) generates the first dummy stage in response to the (N-1)th gate signal (G(n-1)) and the Nth gate signal (Gn) output from the Nth gate stage (STn). A signal D1 and a second dummy signal D2 can be output, respectively. The third dummy stage (DST3) generates a fifth dummy signal (D5) and a sixth dummy signal (D6) in response to the third dummy signal (D3) and the fourth dummy signal (D4) output from the second dummy stage (DST2). ) can be output respectively.

Additionally, multiple gate stages (ST1 to STn) may be reset dependently in response to the output of the subsequent stage.

Specifically, the first gate stage ST1 may be reset in response to the seventh gate signal (not shown) and the eighth gate signal (not shown) output from a subsequent stage, for example, the fourth gate stage (not shown). . Additionally, the N-th gate stage STn may be reset in response to the fifth dummy signal D5 and the sixth dummy signal D6 output from the third dummy stage DST3.

Meanwhile, the plurality of dummy stages DST1 to DST3 may be reset in response to the first reset signal RST1 and the second reset signal RST2 output from the level shifter 130.

Specifically, a portion of the first dummy stage (DST1) and the second dummy stage (DST2), for example, a circuit unit (not shown) that outputs the third dummy signal (D3) from the second dummy stage (DST2), is a level shifter ( It may be reset simultaneously in response to the first reset signal (RST1) output from 130). In addition, the remainder of the second dummy stage DST2, for example, a circuit unit (not shown) that outputs the fourth dummy signal D4 from the second dummy stage DST2 and the third dummy stage DST3, is a level shifter 130. ) can be reset simultaneously in response to the second reset signal (RST2) output from ).

Here, the level shifter 130 may output the second reset signal (RST2) after outputting the first reset signal (RST1). Accordingly, part of the first dummy stage (DST1) and the second dummy stage (DST2) are reset in priority according to the first reset signal (RST1), and the remainder of the second dummy stage (DST2) and the third dummy stage (DST3) ) may be reset to a lower priority according to the second reset signal (RST2).

As described above, the shift register 140 of this embodiment operates a plurality of dummy stages (DST1 to DST3) in response to the first reset signal (RST1) and the second reset signal (RST2) output from the level shifter 130. It can be reset. At this time, the front dummy stage, that is, part of the first dummy stage (DST1) and the second dummy stage (DST2), is reset in priority by the first reset signal (RST1), and the rear stage is reset by the second reset signal (RST2). The remainder of the second dummy stage (DST2) and the third dummy stage (DST3) may be reset to lower priority. Accordingly, in the gate driving circuit 120 of this embodiment, the time for which the output node is held in the first dummy stage (DST1) among the plurality of dummy stages (DST1 to DST3) can be reduced. As a result, deterioration of the plurality of transistors inside the first dummy stage DST1 is prevented, thereby improving malfunction of the gate driving circuit 120.

Figure 6 is a timing diagram showing the operation of a display device according to an embodiment of the present invention.

Referring to FIGS. 3 to 6 , the timing control unit 160 may output a gate control signal (GCS) to the gate driving circuit 120. The gate control signal (GCS) may include a gate start signal (GST), a first clock signal (CLK_on), and a second clock signal (CLK_off). The gate control signal (GCS) may be provided to the level shifter 130 of the gate driving circuit 120.

Here, the gate start signal (GST) output from the timing control unit 160 may include a first gate start signal (GST1) and a second gate start signal (GST2). The first gate start signal (GST1) may include a 1-1 gate start signal (GST1-1) and a 1-2 gate start signal (GST1-2). The first gate start signal (GST1) may mean the end of the frame operation of the display panel 110, and the second gate start signal (GST2) may mean the start of the frame operation of the display panel 110. That is, the timing control unit 160 can output the gate start signal (GST) at least three times during one frame of operation of the display panel 110.

The level shifter 130 may generate a plurality of gate clock signals (GCLK) in response to the gate control signal (GCS) and output them to the shift register 140. In addition, the level shifter 130 generates one of the first reset signal (RST1), the second reset signal (RST2), and the start signal (VST) in response to the gate control signal (GCS), and uses the shift register 140 to generate one of the first reset signal (RST1), the second reset signal (RST2), and the start signal (VST). It can be output as .

To explain this further, the 1-1 gate start signal (GST1-1), the first clock signal (CLK_on), and the second clock signal (CLK_off) input to the level shifter 130 are all at the first level, for example, high. If the level, the switching signal generator 131 of the level shifter 130 may output a first switching signal (S1) and a second switching signal (S2) of the first level.

Accordingly, the first reset signal generator 136 of the level shifter 130 may output the first reset signal RST1 under the control of the selector 135. The first reset signal (RST1) may be output at the first level during the 4H period of the second clock signal (CLK_off).

The shift register 140 operates on the first dummy stage (DST1) and the second dummy stage (DST2) among the plurality of dummy stages (DST1 to DST3) in response to the first reset signal (RST1) output from the level shifter 130. Some, for example, the circuit units of the second dummy stage DST2 that outputs the third dummy signal D3 can be reset at the same time.

Therefore, the first dummy stage (DST1) of the shift register 140 holds the output node for a holding time (T2) that is relatively shorter than the holding time (T1 in FIG. 2) of the conventional shift register, so that the first dummy stage (DST1) DST1) Deterioration of multiple transistors inside can be prevented.

In addition, the 1-2 gate start signal (GST1-2) input to the level shifter 130 is the first level, the first clock signal (CLK_on) is the second level, for example, a low level, and the second clock signal ( When CLK_off) is at the first level, the switching signal generator 131 may output a first switching signal (S1) of the second level and a second switching signal (S2) of the first level.

Accordingly, the second reset signal generator 137 of the level shifter 130 can output the second reset signal RST2 under the control of the selector 135. The second reset signal RST2 may be output at the first level during the 4H period of the second clock signal CLK_off.

The shift register 140 responds to the second reset signal RST2 output from the level shifter 130 and selects a stage that has not been reset by the first reset signal RST1 among the plurality of dummy stages DST1 to DST3, for example, the first reset signal RST2. 4The circuit unit of the second dummy stage (DST2) and the third dummy stage (DST3) that output the dummy signal (D4) can be reset at the same time.

Therefore, the second dummy stage (DST2) of the shift register 140 holds the output node for a holding time (T3) that is relatively shorter than the holding time (T1 in FIG. 2) of the conventional shift register, thereby forming the second dummy stage ( DST2) Deterioration of multiple internal transistors can be prevented. Here, the holding time (T2) of the first dummy stage (DST1) and the holding time (T3) of the second dummy stage (DST2) may be the same.

Subsequently, if the second gate start signal (GST2) input to the level shifter 130 is at the first level, and the first clock signal (CLK_on) and the second clock signal (CLK_off) are both at the second level, a switching signal is generated. The unit 131 may output a first switching signal (S1) of the first level and a second switching signal (S2) of the second level.

Accordingly, the start signal generator 138 of the level shifter 130 can output the start signal VST under the control of the selector 135. Here, the start signal (VST) may be the same as the second gate start signal (GST2).

In addition, the level shifter 130 blocks the connection between the switching signal generator 131 and the selection unit 135 because the level of the A node (A) is the first level, and the selection unit 135 is in the previous state, That is, the state in which the start signal (VST) is output can be maintained.

Accordingly, the first gate stage (ST1) of the shift register 140 receives the first gate signal (G1) and the first gate signal (G1) from the plurality of gate clock signals (GCLK) in response to the start signal (VST) output from the level shifter 130. 2 Gate signal (G2) can be generated and output. In addition, except for the first gate stage (ST1), the remaining gate stages and a plurality of dummy stages (DST1 to DST3) may sequentially output gate signals and dummy signals in response to the output of the previous stage.

Although many details are described in detail in the foregoing description, this should be interpreted as an example of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be determined by the described embodiments, but by the scope of the patent claims and their equivalents.

100: display device 110: display panel
120: Gate driving circuit 130: Level shifter
131: switching signal generator 134: switch control unit
135: selection unit 136: first reset signal generation unit
137: second reset signal generator 138: start signal generator
140: shift register 150: data driving circuit
160: Timing control unit

Claims (10)

A level shifter that generates a plurality of gate clock signals, a start signal, a first reset signal, and a second reset signal in response to the gate control signal; and
It is composed of a plurality of gate stages and a plurality of dummy stages to sequentially output gate signals. Among the plurality of dummy stages, some dummy stages are reset in priority in response to the first reset signal, and the remaining dummy stages are reset to the second reset signal. Includes a shift register that is reset to a lower priority in response to a reset signal,
The level shifter is,
A plurality of signal generators including a start signal generator that generates the start signal, a first reset signal generator that generates the first reset signal, and a second reset signal generator that generates the second reset signal;
a switching signal generator that generates a first switching signal and a second switching signal according to the gate control signal; and
A gate driving circuit including a selection unit that controls one of the plurality of signal generators to operate according to the levels of each of the first switching signal and the second switching signal. According to paragraph 1,
The level shifter is a gate driving circuit that generates one of the start signal, the first reset signal, and the second reset signal in response to the gate control signal and outputs it to the shift register. delete According to paragraph 1,
The gate control signal includes a gate start signal, a first clock signal, and a second clock signal,
The switching signal generator,
If the gate start signal, first clock signal, and second clock signal are all at the first level, generate a first switching signal of the first level and a second switching signal of the first level, respectively,
When each of the gate start signal and the second clock signal is at a first level, and the first clock signal is at a second level, a first switching signal at a second level and a second switching signal at the first level are generated, respectively. ,
When the gate start signal is at a first level and each of the first clock signal and the second clock signal is at a second level, generating a first switching signal at the first level and a second switching signal at the second level, respectively. Gate driving circuit. The method of claim 1, wherein the selection unit,
If each of the first switching signal and the second switching signal is at the first level, the first reset signal generator is controlled to operate,
When the first switching signal is at the second level and the second switching signal is at the first level, the second reset signal generator is controlled to operate,
A gate driving circuit that controls the start signal generator to operate when the first switching signal is at a first level and the second switching signal is at a second level. According to paragraph 1,
a first switch and a second switch disposed between the switching signal generator and the selection unit and providing the first switching signal and the second switching signal to the selection unit through a switching operation, respectively; and
It further includes a switch control unit that turns off both the first switch and the second switch according to the node level between the selection unit and the start signal generator to block the connection between the switching signal generator and the selection unit,
A gate driving circuit in which the selection unit maintains its previous state when the connection with the switching signal generator is cut off. According to paragraph 1,
The first reset signal generator and the second reset signal generator each include a clock counter,
A gate driving circuit wherein the first reset signal generator and the second reset signal generator output the first reset signal and the second reset signal during a count operation of the clock counter under the control of the selector. A display panel equipped with a plurality of gate lines;
A timing control unit that outputs a gate control signal; and
and a gate driving circuit that sequentially outputs a plurality of gate signals to the plurality of gate lines of the display panel in response to the gate control signal,
The gate driving circuit is,
A level shifter that generates a plurality of gate clock signals, a start signal, a first reset signal, and a second reset signal in response to the gate control signal; and
It is composed of a plurality of gate stages and a plurality of dummy stages to sequentially output gate signals. Among the plurality of dummy stages, some dummy stages are reset in priority in response to the first reset signal, and the remaining dummy stages are reset to the second reset signal. Includes a shift register that is reset to a lower priority in response to a reset signal,
The level shifter is,
A plurality of signal generators including a start signal generator that generates the start signal, a first reset signal generator that generates the first reset signal, and a second reset signal generator that generates the second reset signal;
a switching signal generator that generates a first switching signal and a second switching signal according to the gate control signal; and
A display device comprising a selection unit that controls one of the plurality of signal generators to operate according to the levels of each of the first switching signal and the second switching signal. According to clause 8,
A display device wherein the shift register is arranged in a GIP structure inside the display panel, and the level shifter is arranged on a printed circuit board connected to the display panel. According to clause 8,
The gate control signal includes a gate start signal,
A display device wherein the timing control unit outputs the gate start signal at least three times during one frame of operation of the display panel.