KR102646177B1 - Content addressable memory device and operating method thereof - Google Patents

Abstract

An addressable memory device according to an embodiment of the present disclosure includes a memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET), and a match connected to the plurality of memory cells through a plurality of match lines. It includes an amplifier, and the FeTFET has a first doped region having a first conductivity type, a second doped region having a second conductivity type different from the first conductivity type, and a channel region formed between the first doped region and the second doped region. , and a gate formed on the channel region and including a ferroelectric layer.

Description

Content addressable memory device and operating method thereof {CONTENT ADDRESSABLE MEMORY DEVICE AND OPERATING METHOD THEREOF}

The present disclosure relates to a content-addressable memory device and a method of operating the same, and more specifically, to a content-addressable memory device including a CAM memory cell based on an FeTFET element and a method of operating the same.

Existing random access memory (RAM), such as SRAM and DRAM, stores data during the write cycle and reads the stored memory during the read cycle. At this time, random access memory devices must specify a specific memory location called an address, so sequential memory operations are inevitable.

RAM's sequential memory operation is not suitable for high-speed, large-capacity data retrieval, which has recently become a hot topic in the big data and artificial intelligence fields. Research is actively underway to increase bandwidth to overcome this, but a fundamental solution is far away. .

In contrast, content addressable memory (CAM) does not perform sequential memory operations based on addresses, but rather compares all data stored in the memory with the data to be retrieved based on content. At the same time, because it is processed in parallel, it is expected that its usefulness will increase as data capacity increases and demand for high-speed operation increases. However, although the technical demand for CAM is increasing day by day, it is difficult to implement high capacity memory and high power consumption, so it is not actively used for various purposes.

In the case of binary CAM (BCAM), about 10 MOSFETs are used, and in the case of ternary CAM (TCAM), about 16 MOSFETs are used. This makes it difficult to implement high-capacity CAM, and as the data capacity increases, the power required for memory operation decreases. Because consumption and operation time increase, CAM generally has the limitation of being implemented with a much smaller capacity than RAM.

Korean Patent Publication No. 10-2015-0093245 relates to a static NAND cell for ternary content addressable memory (TCAM), which is a first pool. - a key cell coupled to the pull-down transistor and the first pull-up transistor, and a mask cell coupled to the second pull-down transistor and the second pull-up transistor. (mask cell), the first pull-down transistor and the second pull-down transistor are connected in parallel, the first pull-up transistor and the second pull-up transistor are connected in series, and the first pull-up transistor is connected in series. comprising a match line output coupled to the pull-down transistor and the second pull-down transistor and additionally coupled to the first pull-up transistor and the second pull-up transistor. It is characterized by

In addition, Korean Patent Publication No. 2001-0107136 provides a content addressable memory (CAM) cell, including a latch means for latching first and second data complementary to the first node and the second node, a first bit line, and A first transistor having a current path formed between the first nodes and a gate connected to the word line, a second transistor having a current path formed between a second bit line and the second node and a gate connected to the word line, A third transistor having a current path formed between the first bit line and the third node and a gate connected to the second node, a current path formed between the third node and the second bit line and the first node, and a fourth transistor having a gate connected to it, a current path formed between a match line and a ground voltage, a fifth transistor having a gate connected to the third node, a current path formed between a power supply voltage and the match line, and a precharge signal; It includes a precharge transistor having a connected gate, wherein the third and fourth transistors are each configured as a PMOS transistor.

1, Korean Patent Publication No. 10-2015-0093245 (2015.08.17) 2. Korean Patent Publication No. 10-2001-0107136 (December 7, 2001)

An embodiment of the present disclosure implements a multi-bit CAM based on a Ferroelectric tunnel FET (FeTFET), thereby performing a multi-bit CAM operation using a single transistor and simultaneously implementing content addressability up to a degree of mismatch. The object is to provide a memory device and a method of operating the same.

An addressable memory device according to an embodiment of the present disclosure includes a memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET), and a match connected to the plurality of memory cells through a plurality of match lines. It includes an amplifier, and the FeTFET has a first doped region having a first conductivity type, a second doped region having a second conductivity type different from the first conductivity type, and a channel region formed between the first doped region and the second doped region. , and a gate formed on the channel region and including a ferroelectric layer.

A content addressable memory including a memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET) according to an embodiment of the present disclosure, and a match amplifier connected to the plurality of memory cells through a match line. The operation method of the device is to precharge the match line by applying a power voltage to the match line, inputting a codeword into a memory cell connected to the match line, and comparing the codeword with the data stored in the memory cell connected to the match line to obtain data. A step of determining whether there is a match/mismatch; If it is determined that the codeword and the stored data match, the match line is not discharged; If it is determined that the codeword and the stored data do not match, the match line is discharged; Match and generating, by an amplifier, an output signal based on the discharge rate of the match line.

A memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET) according to an embodiment of the present disclosure, a match amplifier connected to the plurality of memory cells through a match line, and supplying current to the match line. The operating method of the addressable memory device includes the steps of applying a ground voltage to the match line to precharge the match line, inputting a codeword into a memory cell connected to the match line, and entering a codeword into a memory cell connected to the match line. A step of comparing the stored data and the codeword to determine whether the data matches/mismatches. If it is determined that the codeword and the stored data match, the match line is charged. If it is determined that the codeword and the stored data do not match, The match line includes the steps of not charging and, by the match amplifier, generating an output signal.

Among embodiments, a content addressable memory device according to an embodiment of the present disclosure includes a plurality of CAM memory cells connected in parallel based on a match line, disposed at one end of the match line, and detecting the discharge rate of the match line. In a content-addressable memory device including a sense amplifier, one CAM memory cell includes a P+ region and an N+ region formed on a semiconductor substrate at a predetermined distance apart, a channel region formed between the P+ region and the N+ region, and the channel It is characterized by including one FeTFET (Ferroelectric Tunnel FET) device consisting of a gate formed on the region.

It further includes a search line (SL) for inputting search data, and the search line is connected to the gate of the CAM memory cell.

It further includes a pre-charge unit connected to the match line and pre-charging the match line with a power supply voltage (VDD) (or high voltage).

It further includes a current source that precharges the match line (ML) to a low voltage (GND) and then supplies charging current (IML) to the match line.

The gate includes a stacked structure of an insulating layer, a ferroelectric layer, and a gate electrode layer, and the ferroelectric layer is PZT(Pb(Zr,Ti)O ₃ ), SBT(SrBi ₂ Ta ₂ O ₉ ), SBTN(SrBi ₂ (Ta , _{Nb )} O ₉ ) _, BLT((Bix _{, La1- 2} /Si), aluminum-added hafnium oxide (HfO ₂ /Al), zirconium-added hafnium oxide (HfO ₂ /Zr), or a combination thereof.

The sense amplifier determines match/mismatch of data based on the voltage level of the match line depending on whether it is discharged or charged during a search operation, and outputs an address where the data matches. It is characterized by

A method of operating a content addressable memory device according to an embodiment of the present disclosure includes a plurality of CAM memory cells connected in parallel based on a match line and including one FeTFET (Ferroelectric Tunnel FET) element, and the match line ( ML), comprising: precharging the match line by applying a VDD voltage to the match line; and providing search data to the CAM memory cell. Inputting, comparing input search data with data stored in the CAM memory cell to determine whether the data matches/mismatches, and maintaining the voltage of the match line when the search data matches the stored data. It is characterized in that it includes the step of discharging the match line when there is a mismatch, and the step of detecting the discharge rate of the match line in the sense amplifier and generating an output signal.

The step of inputting the search data is performed by inputting the search data into one search line connected to the CAM memory cell.

When the search data matches the stored data, the VDD voltage precharged at the match line is maintained, and the voltage at the output terminal of the sense amplifier is maintained.

When there is a mismatch between the search data and the stored data, a discharge current path occurs in the CAM memory cell, the match line is discharged, and a voltage drop occurs at the output terminal of the sense amplifier.

The number of mismatch bits is determined based on the speed at which the match line is discharged and the time difference at which the voltage drop at the output terminal of the sense amplifier occurs. It is determined that the number of mismatch bits increases as the speed at which the match line is discharged increases, and the number of mismatch bits is determined to increase as the speed at which the match line is discharged increases. It is determined that the faster the voltage drop occurs, the more the number of mismatched bits increases.

In addition, a method of operating a content addressable memory device according to an embodiment of the present disclosure includes a plurality of CAM memory cells connected in parallel based on a match line and including one FeTFET (Ferroelectric Tunnel FET) element, and the match A content-addressable memory device including a sense amplifier (SA) output terminal disposed at one end of a line (ML) and a current source supplying a charging current (IML) to a match line, wherein a GND is connected to the match line. Precharging the match line to GND by applying a voltage, inputting search data into the CAM memory cell, and comparing the input search data with data stored in the CAM memory cell to determine whether the data matches or does not match. determining that the GND voltage of the match line is maintained if the search data and the stored data do not match, and charging the match line to a high voltage if they match; and charging speed of the match line in the sense amplifier. It includes a step of detecting and generating an output signal.

The step of inputting the search data is performed by inputting the search data into one search line connected to the CAM memory cell.

When there is a mismatch between the search data and the stored data, a discharge current path is generated in the CAM memory cell to offset the current supplied from the current source to the match line, so that the GND voltage precharged on the match line is maintained. And the voltage at the output terminal of the sense amplifier is maintained.

When the search data and stored data match, the match line is charged with high voltage, and a voltage rise occurs at the output terminal of the sense amplifier.

The number of mismatch bits is determined based on the speed at which the match line is charged and the time difference in which the voltage at the output terminal of the sense amplifier occurs. It is determined that the number of mismatch bits increases as the speed at which the match line is charged decreases, and the number of mismatch bits is determined to increase as the speed at which the match line is charged decreases. It is characterized in that it is determined that the number of mismatch bits increases as the voltage rise occurs within a slow time.

The disclosed technology can have the following effects. However, since it does not mean that a specific embodiment must include all of the following effects or only the following effects, the scope of rights of the disclosed technology should not be understood as being limited thereby.

The content addressable memory device and its operating method according to an embodiment of the present disclosure implement a multi-bit CAM based on a Ferroelectric tunnel FET (FeTFET), thereby performing a multi-bit CAM operation using one transistor and at the same time reducing the degree of mismatch ( You can achieve the effect of implementing up to a degree of mismatch.

1 is a block diagram showing a content addressable memory device according to an embodiment of the present disclosure.
Figure 2a is a diagram showing an example of a MOSFET-based content addressable memory device.
FIG. 2B is a graph for explaining MOSFET device characteristics of the content addressable memory device of FIG. 2A.
FIG. 3 is a block diagram showing an example of a portion of the CAM device of FIG. 1.
FIG. 4 is a diagram showing an example of the first ferroelectric tunnel field effect transistor device of FIG. 3.
FIG. 5 is a graph showing the operating characteristics of the first FeTFET device of FIG. 4.
FIG. 6 is a flowchart showing an example of a method of operating the CAM device of FIG. 1 including the first memory cell group of FIG. 3.
FIGS. 7A to 7D are diagrams for explaining an operation of searching data stored in the first memory cell group of FIG. 3 .
FIG. 8 is a block diagram showing an example of a portion of the CAM device of FIG. 1.
FIG. 9 is a flowchart showing an example of a method of operating the CAM device of FIG. 1 including the first memory cell group of FIG. 8.
FIGS. 10A to 10D are diagrams for explaining the operation of the first memory cell of FIGS. 3 and 8.
FIG. 11 is a diagram showing an example of the first ferroelectric tunnel field effect transistor device of FIGS. 3 and 8.
FIG. 12 is a diagram illustrating an example of the first ferroelectric tunnel field effect transistor device of FIGS. 3 and 8.
FIG. 13 is a graph for explaining the characteristics of the first FeTFET device of FIGS. 3 and 8.
FIG. 14 is a graph for explaining a 2-bit implementation operation using the switching characteristics of the first FeTFET device of FIGS. 3 and 8.
Figure 15 is an operation prediction graph for determining the degree of inconsistency of a content addressable memory device according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail so that a person skilled in the art can easily practice the present disclosure.

1 is a block diagram showing a content addressable memory device according to an embodiment of the present disclosure. Referring to FIG. 1, a content addressable memory (CAM) 1000 (hereinafter referred to as a CAM device) includes a driver 1100, a memory cell array 1200, an amplifier 1300, and It may include a ranking encoder 1400. The memory cell array 1200 may include first to fourth memory cell groups 1200_1 to 1200_4. The amplifier 1300 may include first to fourth match amplifiers 1300_1 to 1300_4. In one embodiment, the CAM device 100 may further include a bias circuit (not shown). In FIG. 1, the numbers of the first to fourth memory cell groups 1200_1 to 1200_4 and the first to fourth match amplifiers 1300_1 to 1300_4 are merely examples, and the present disclosure is not limited thereto. No.

The driver 1100 provides a codeword (or search data, input data) to the memory cell array 1200 through the first to fourth search lines SL1 to SL4. A codeword is data to be searched among data stored in the memory cell array 1200. Hereinafter, codewords are used in the same sense as search data and input data. For example, the codeword may be provided from an external processor (not shown).

The first memory cell group 1200_1 may include first to fourth memory cells C11 to C14. The second memory cell group 1200_2 may include fifth to eighth memory cells C21 to C24. The third memory cell group 1200_3 may include ninth to twelfth memory cells C31 to C34. The fourth memory cell group 1200_4 may include 13th to 16th memory cells C41 to C44. Here, the number of memory cells shown is merely an example, and the number of memory cells may be determined according to the size of various codewords, such as 32 bits to 256 bits. Additionally, the number of search lines shown may change depending on the size of the codeword.

Each of the first to sixteenth memory cells C11 to C44 may include a transistor. For example, each of the first to sixteenth memory cells C11 to C44 may include a ferroelectric tunnel field effect transistor (FeTFET).

In one embodiment, each of the first to sixteenth memory cells C11 to C44 may store 1 bit or 2 bits. However, the scope of the present disclosure is not limited thereto, and the number of bits stored in a memory cell may increase or decrease depending on implementation. For convenience of explanation, it is assumed below that each of the first to sixteenth memory cells C11 to C44 stores 2 bits.

For example, each of the first to sixteenth memory cells C11 to C44 may store logic '11', '10', '01', and '00'. Or, each of the first to sixteenth memory cells (C11 to C44) has logic '11', '10', '01', '00', and Don't Care (D.C.) bits (i.e., 'XX' ) can be saved. When searching data (or cell data) stored in a memory cell, regardless of the codeword, the memory cell in which the Don Care (D.C.) bit is stored can output a matched result. That is, the CAM device 1000 may be a TCAM (Ternary content addressable memory) device. Hereinafter, it is assumed that the CAM device 1000 is a TCAM device.

The priority encoder 1400 outputs the address of the memory cell array having data matching the codeword as a match address (ML_add), based on the voltage (or signal) provided from the amplifier output lines (OA1 to OA4). . For example, when there are multiple matching memory cell arrays, the priority encoder 1400 may output the address of one memory cell array according to a priority algorithm.

For example, the codeword is '11 10 01 00', the first memory cell (C11) stores '11', the second memory cell (C12) stores '10', and the third memory cell ( C13) stores '01', the fourth memory cell (C14) stores '00', the fifth memory cell (C21) stores '11', and the sixth memory cell (C22) stores '10'. ', the seventh memory cell C23 stores '01', the eighth memory cell C24 stores '11', the ninth memory cell C31 stores '00', The 10th memory cell C32 stores '01', the 11th memory cell C33 stores '10', the 12th memory cell C34 stores '11', and the 13th memory cell ( C41) stores 'XX', the 14th memory cell (C42) stores 'XX', the 15th memory cell (C43) stores '01', and the 16th memory cell (C44) stores '00'. ' is assumed to be stored.

Each of the match amplifiers 1300_1 to 1300_4 of the amplifier 1300 can detect the voltage of the corresponding match line and output the match result (or comparison result) of the codeword and the stored data to the priority encoder 1400. . For example, each of the match amplifiers 1300_1 to 1300_4 may output a power supply voltage (VDD) when the corresponding match line is matched. Each of the match amplifiers 1300_1 to 1300_4 may output a ground voltage (GND) when the corresponding match line is mismatched. However, the scope of the present disclosure is not limited thereto.

In one embodiment, each of the match amplifiers 1300_1 to 1300_4 determines the number of mismatch (or mismatch) bits of the codeword and stored data based on the discharge rate or charge rate of the corresponding match line, and determines the number of mismatch bits. Can be printed.

In one embodiment, the CAM device 1000 may further include a mismatch ratio output circuit (not shown). A mismatch rate output circuit may be placed between amplifier 1300 and priority encoder 1400. The mismatch ratio output circuit generates mismatch through the time difference between the voltage drops (or voltage increases, depending on the implementation of the match amplifier) of each of the amplifier output lines (OA1 to OA4) output from each of the match amplifiers (1300_1 to 1300_4). The number of bits can be determined.

In one embodiment, each of the match amplifiers 1300_1 to 1300_4 may determine that the number of mismatch bits increases as the discharge rate (or charge rate) of the corresponding match line increases. The mismatch ratio output circuit may determine that the faster the voltage drop (or voltage rise) of the amplifier output line occurs, the more the number of mismatch bits increases.

For example, the codeword is “11 10 01 00”, the data stored in the first memory cell group (1200_1) is “11 10 01 00”, and the data stored in the second memory cell group (1200_2) is “11 10”. 01 11”, the data stored in the third memory cell group 1200_3 is “00 01 10 11”, and the data stored in the fourth memory cell group 1200_4 is “XX XX 01 00”.

The driver 1100 may provide a voltage corresponding to the first code '11' of the codeword to the first search line SL1. Similarly, the driver 1100 provides a voltage corresponding to the second code '10' of the codeword to the second search line (SL2), and provides a voltage corresponding to the third code '01' to the third search line (SL2). SL3), and the voltage corresponding to the fourth code '00' may be provided to the fourth search line (SL4).

The first, fifth, ninth, and thirteenth memory cells C11, C21, C31, and C41 may each receive the first code '11' of the codeword through the first search line SL1. The second, sixth, tenth, and fourteenth memory cells C12, C22, C32, and C42 may each receive a second code '10' through the second search line SL2. The third, seventh, eleventh, and fifteenth memory cells C13, C23, C33, and C43 may each receive the third code '01' through the third search line SL3. The fourth, eighth, twelfth, and sixteenth memory cells C14, C24, C34, and C44 may each receive the fourth code '00' through the fourth search line SL4.

The first to sixteenth memory cells C11 to C44 can each determine whether the stored data matches the provided code. In one embodiment, after a previous data search operation and before a recent search operation, the match lines ML1, ML2, ML3, and ML4 may each be precharged with the power supply voltage VDD (or a high voltage).

The first memory cell group 1200_1 can compare the stored data '11 10 01 00' with the codeword. Since the bits of the stored data '11 10 01 00' each match the bits of the codeword '11 10 01 00', the first memory cell group 1200_1 discharges (or discharge) may not occur. Since the data '11 10 01 11' stored in the second memory cell group 1200_2 does not match the codeword '11 10 01 00', the second memory cell group 1200_2 connects the second match line ML2 to the ground voltage. It can be discharged to (GND). Since the data '00 01 10 11' stored in the third memory cell group 1200_3 does not match the codeword '11 10 01 00', the third memory cell group 1200_3 cannot discharge the third match line ML3. You can. Since the data 'XX XX 01 00' stored in the fourth memory cell group 1200_4 matches the codeword '11 10 01 00', the fourth memory cell group 1200_4 does not discharge the fourth match line ML4. It may not be possible.

The first and fourth match amplifiers (1300_1, 1300_4) receive undischarged power supply voltage (VDD) (or high voltage) from the match lines (ML1, ML4), respectively, and send the match results to the amplifier output lines (OA1, OA4). Print out. Additionally, the second and third match amplifiers 1300_2 and 1300_3 receive the discharged ground voltage (GND) from the match lines ML2 and ML3, respectively, and output the match results to the amplifier output lines OA2 and OA3.

For example, according to the priority algorithm, the priority encoder 1400 may set the priority of the memory cell group in which fewer Don Care (D.C.) bits are stored to be higher. In this case, the priority encoder 1400 determines the address of the first memory cell group 1200_1 with fewer don care (D.C.) bits among the first and fourth memory cell groups 1200_1 and 1200_4 with matched data. It can be output as a match address (ML_add). However, the present disclosure is not limited to the above-described algorithm.

As described above, the memory cell of the CAM device 1000 according to an embodiment of the present disclosure may include a FeTFET, and the match result and the number of mismatch bits may be determined and output. Accordingly, an improved CAM device 1000 is provided.

Figure 2a is a diagram showing an example of a MOSFET-based content addressable memory device. Briefly, a match line (ML) is provided, and two MOSFET elements (TR1 and TR2) connected to the match line are arranged in parallel. Additionally, a search line (SL) and a complementary search line (or search line bar) (/SL) are connected to the two MOSFET elements, respectively. In addition, it further includes a precharge unit (PRE) that applies the VDD voltage to the match line and an output stage (OA) that outputs a signal detected from a sense amplifier.

Hereinafter, for convenience of explanation, terms such as “sense amplifier” and “match amplifier” are used interchangeably. These terms may have the same meaning or different meanings depending on the context of the embodiments, and the meaning of each term will be understood according to the context of the embodiments to be described.

FIG. 2B is a graph for explaining MOSFET device characteristics of the content addressable memory device of FIG. 2A. Graph (i) of FIG. 2B shows the drain current (ID) against the gate voltage (VSL) applied through the search line, and graph (ii) of FIG. 2B shows the drain current (ID) against the gate voltage (VSL) applied through the search line. This shows the voltage (VOA) at the output stage of the sense amplifier.

Referring to FIG. 2b, it can be seen that the two transistors have opposing voltages in sections excluding a specific voltage section (the section between Va and Vb). In this way, the MOSFET device has two types as shown in Figure 2a to implement a high-pass filter or low-pass filter that allows or blocks current according to the gate voltage being higher or lower than the threshold voltage. A configuration that combines MOSFET elements in parallel is essential.

FIG. 3 is a block diagram showing an example of a portion of the CAM device of FIG. 1. For convenience of explanation and brevity of drawings, only the first memory cell group 1200_1 is shown in FIG. 3 . The remaining memory cell groups 1200_2 to 1200_4 may be the same or similar to the first memory cell group 1200_1. Referring to Figure 3, the precharge-high scheme is explained.

Referring to FIGS. 1 and 3 , each of the first to fourth memory cells C11 to C14 may include a ferroelectric tunnel field effect transistor (FeTFET). For example, the first memory cell C11 includes a first FeTFET (FT11), the second memory cell C12 includes a second FeTFET (FT12), and the third memory cell C13 includes a third FeTFET (FT11). It includes a FeTFET (FT13), and the fourth memory cell (C14) may include a fourth FeTFET (FT14). The gate of the first FeTFET (FT11) is connected to the first search line (SL1), the gate of the second FeTFET (FT12) is connected to the second search line (SL2), and the gate of the third FeTFET (FT13) is connected to the first search line (SL1). 3 may be connected to the search line (SL3), and the gate of the fourth FeTFET (FT14) may be connected to the fourth search line (SL4).

The first FeTFET (FT11) is connected between the first match line (ML1) and the ground voltage (GND) (or a specific voltage, for example, VSS), and the second FeTFET (FT12) is connected to the first match line (ML1) and the ground voltage (GND), the third FeTFET (FT13) is connected between the first match line (ML1) and the ground voltage (GND), and the fourth FeTFET (FT14) is connected to the first match line (ML1) and a ground voltage (GND).

The CAM device 1000 may further include a first precharge transistor PT1. The first precharge transistor PT1 is connected between the power supply voltage VDD and the first match line ML1, and may operate in response to the complementary precharge signal /PRE. The first precharge transistor PT1 may precharge the first match line ML1 with the power supply voltage VDD in response to the complementary precharge signal /PRE. For example, the first precharge transistor PT1 may be a PMOS transistor. The first match amplifier 1300_1 may be connected between the first match line ML1 and the amplifier output line OA1.

In one embodiment, after the previous data search operation and before the latest search operation, the first match line ML1 may be precharged with the power supply voltage VDD in response to the complementary precharge signal /PRE. The first to fourth memory cells C11 to C14 are turned on or turned off in response to the corresponding search lines, thereby creating or blocking a discharge path to the first match line ML1. An action can be performed.

When the codeword to be searched matches (or matches) data stored in the first memory cell group 1200_1, the first match line ML1 may maintain the precharged voltage. Alternatively, when searching for data of a cell in which data of the don care (D.C.) bit is stored, the first match line ML1 may maintain the precharged voltage, regardless of the codeword. Additionally, if the codeword mismatches (or does not match) the stored data, the first match line ML1 may be discharged.

In one embodiment, the first match amplifier 1300_1 may determine whether there is a match/mismatch between the codeword and the data stored in the first memory cell group 1200_1 based on the voltage level of the first match line ML1. there is. For example, when the first match amplifier 1300_1 determines that the first match line ML1 maintains the power supply voltage VDD, it determines that the data stored in the first memory cell group 1200_1 matches the codeword. can do. When the first match amplifier 1300_1 determines that the first match line ML1 is discharged, it may determine that the data stored in the first memory cell group 1200_1 and the codeword do not match.

As described above, before the search operation, the first match line ML1 of the first memory cell group 1200_1 is precharged (or charged) with the power supply voltage VDD (or high voltage), and the stored data and the search data are Depending on the match/mismatch, the precharged voltage of the first match line ML1 may be maintained or discharged.

FIG. 4 is a diagram showing an example of the first ferroelectric tunnel field effect transistor device of FIG. 3. Each of the first to fourth FeTFETs (FT11 to FT14) is configured substantially the same as each other and operates substantially the same. Therefore, for convenience of explanation, the first FeTFET (FT11) is used as an example, and since the remaining cells (FT12 to FT14) are the same or similar to the first FeTFET (FT11), detailed description thereof is omitted.

Referring to Figures 3 and 4, the first FeTFET (FT11) device includes a first doped region 410 and a second doped region 420 formed at a certain distance apart from the semiconductor substrate 400, and the first doped region It may be composed of a channel region 430 formed between 410 and the second doped region 420, and a gate 440 formed on the channel region 430. That is, the first FeTFET (FT11) may include a first doped region 410, a second doped region 420, and a channel region 430 formed on the semiconductor substrate 400. The first FeTFET (FT11) may further include a gate 440, a first electrode 450, and a second electrode 460.

For example, the semiconductor substrate 400 may be any suitable semiconductor substrate, such as a semiconductor wafer, a silicon-on-insulator substrate, a semiconductor layer formed on a semiconductor substrate, etc. Although the semiconductor substrate 400 may be a silicon substrate, the scope of the present disclosure is not limited thereto, and other semiconductor materials may be used as the semiconductor substrate 400.

In one embodiment, the semiconductor substrate 400 may be doped with P-type impurities more lightly than the first doped region 410 (P- region) or may be formed as an undoped intrinsic region. Alternatively, the semiconductor substrate 400 may be doped with N-type impurities more lightly than the second doped region 420 (N- region) or may be formed as an undoped intrinsic region. That is, the semiconductor substrate 400 may be an intrinsic (i-type) silicon substrate.

In one embodiment, the first doped region 410 may have a first conductivity type. For example, the first doped region 410 may have a P+ type. The first doped region 410 may have a first doping concentration. The first doped region 410 may be a source region. The second doped region 420 may have a second conductivity type. For example, the second doped region 420 may have an N+ type. The second doped region 420 may have a second doping concentration. The second doped region 420 may be a drain region.

The first doped region 410 and the second doped region 420 may be spaced apart from each other along the first direction D1. The first doped region 410 and the second doped region 420 may extend along a direction opposite to the second direction D2 perpendicular to the first direction D1.

In one embodiment, to improve turn-on operation and bipolar (or ambipolar) operation, the doping concentration of the first doped region 410 is adjusted (or adjusted, changed) or the doping concentration of the second doped region 410 ( The doping concentration of 420) can be adjusted. The first doped region 410 may have a third doping concentration that is higher than the first doping concentration. Alternatively, the second doped region 420 may have a fourth doping concentration that is higher than the second doping concentration.

The channel region 430 may be doped with P-type impurities more lightly than the first doped region 410 (P- region) or may be formed as an undoped intrinsic region. Alternatively, the channel region 430 may be doped with N-type impurities more lightly than the second doped region 420 (N- region) or may be formed as an undoped intrinsic region.

The gate 440 may be disposed on the upper surface of the channel region 430. The gate 440 may be formed by sequentially stacking a gate insulating layer 440a, a ferroelectric layer 440b, and a gate electrode layer 440c. That is, the gate 440 may include a gate insulating layer 440a, a ferroelectric layer 440b, and a gate electrode layer 440c that are sequentially stacked. The gate 440 may cover a portion of the top surface of the channel region 430.

At this time, the ferroelectric layer 440b is PZT(Pb(Zr,Ti)O ₃ ), SBT(SrBi ₂ Ta ₂ O ₉ ), SBTN(SrBi ₂ (Ta,Nb)O ₉ ), BLT((Bix,La1- x) ₄ Ti ₃ O ₁₂ ) and BST (BaxSr(1-x)TiO ₃ ), hafnium oxide (Hf0O ₂ ), hafnium oxide with silicon added (HfO ₂ /Si), hafnium oxide with aluminum added (HfO ₂ /Al), zirconium-added hafnium oxide (HfO ₂ /Zr), or a combination thereof.

The first electrode 450 may be disposed on the first doped region 410 . In one embodiment, the first electrode 450 may be a source electrode. The second electrode 460 may be disposed on the second doped region 420 . In one embodiment, the second electrode 460 may be a drain electrode.

In one embodiment, the first FeTFET (FT11) may be a tunnel field-effect transistor (TFET) that uses a band-to-band tunneling phenomenon. That is, the first FeTFET (FT11) may be a ferroelectric tunnel field effect transistor (FeTFET) including a ferroelectric layer. The first FeTFET (FT11) has a first doped region 410 and a second doped region 420 having opposite conductivity types, and current flow can be controlled by a bias applied to the gate 440.

The first FeTFET (FT11) has a p-type source region (i.e., first doped region 410), an n-type drain region (i.e., second doped region 420), and an intrinsic state between them. It may include a channel area 430. In a state where no bias is applied to the source and drain regions and the gate, that is, in a state of thermal equilibrium, the p-type Fermi level of the source region and the n-type Fermi level of the drain region are different, so the valence band and electron The energy level of the band may be higher in the source region than in the drain region. That is, the energy level of the source region may be higher than the energy level of the channel region, and the energy level of the drain region may be lower than the energy level of the channel region.

When a reverse bias is applied between the source and drain regions and a turn-off voltage (for example, 0v) is applied to the gate, that is, in a turn-off state in which no electric field is applied to the channel region. , Since a wide potential barrier exists between the source region and the drain region, tunneling of charges does not occur, and a current flow greater than a critical current may not occur between the source region and the drain region. However, a slight leakage current flow may exist between the source and drain regions.

When a reverse bias is applied between the source region and the drain region and a gate voltage above the threshold voltage is applied to the gate electrode, that is, in the turn-on state in which an electric field is applied to the channel region, the potential barrier between the channel region and the source region As this becomes narrower, a band-to-band tunneling phenomenon may occur in which electrons quantum mechanically tunnel from the valence band of the source region to the conduction band of the channel region. Accordingly, current flow may occur between the source region and the drain region.

Since the first FeTFET (FT11) controls the flow of electrons or holes using an inter-band tunneling method, the change in output current may be large compared to a small change in gate voltage (or driving voltage). That is, the first FeTFET (FT11) may have a subthreshold swing below a small threshold voltage. Accordingly, the first FeTFET (FT11) may be a semiconductor device that can be driven at low voltage or low power.

In one embodiment, the semiconductor substrate 400, the first doped region 410, the second doped region 420, and the channel region 430 may be formed of a semiconductor material. For example, the semiconductor substrate 400, the first doped region 410, the second doped region 420, and the channel region 430 are each made of a semiconductor material such as silicon, a narrow bandgap, ) (e.g., silicon-germanium (SiGe), germanium (Ge), indium gallium arsenide (InGaAs), indium arsenide (InAs)), or a semiconductor material with a direct bandgap It can be formed by at least one of:

In one embodiment, the semiconductor substrate 400, the first doped region 410, the second doped region 420, and the channel region 430 may all be formed of the same material. For example, the semiconductor substrate 400, the first doped region 410, the second doped region 420, and the channel region 430 may all be formed of silicon. In one embodiment, the semiconductor substrate 400, the first doped region 410, the second doped region 420, and the channel region 430 may be formed of different materials. For example, the semiconductor substrate 400, the second doped region 420, and the channel region 430 may be formed of silicon, and the first doped region 410 may be formed of silicon-germanium (SiGe). Alternatively, the semiconductor substrate 400, the first doped region 410, and the channel region 430 may be formed of silicon, and the second doped region 420 may be formed of indium arsenide (InAs). Accordingly, by facilitating band-to-band tunneling of the first FeTFET (FT11) device and reducing the turn-on voltage (V _TH ), the CAM device 1000 performs turn-on operation and Bipolar (or ambipolar) operation can be improved.

FIG. 5 is a graph showing the operating characteristics of the first FeTFET device of FIG. 4. Referring to FIG. 5, the horizontal axis indicates the gate voltage (VSL) applied through the first search line, and the vertical axis indicates the drain current (ID).

It can be seen that, unlike the MOSFET device, the first FeTFET device flows a small current at a certain gate voltage, and a high current flows at a gate voltage beyond this. Through these characteristics of the FeTFET device, the first memory cell C11 of the CAM device according to an embodiment of the present disclosure can determine match/mismatch with only one transistor. Through these characteristics, a configuration in which two or more transistors are arranged can be configured with only one transistor, and the integration of the CAM device can be improved by omitting the complementary search line (/SL).

FIG. 6 is a flowchart showing an example of a method of operating the CAM device of FIG. 1 including the first memory cell group of FIG. 3. Referring to FIGS. 1, 3, and 6, in step S110, the CAM device 1000 may precharge the match line. Hereinafter, for convenience of explanation, description will be made based on the first memory cell group 1200_1. Since the second to fourth memory cell groups 1200_2 to 1200_4 operate the same or similar to the first memory cell group 1200_1, detailed descriptions are omitted. For example, the CAM device 1000 may precharge the first match line ML1 by applying the power supply voltage VDD to the first match line ML1.

In step S120, the CAM device 1000 may input a codeword. For example, the driver 1100 of the CAM device 1000 may provide (or input) a codeword to the first memory cell group 1200_1 through a plurality of search lines SL1 to SL4. The CAM device 1000 may apply a voltage corresponding to a codeword to a plurality of search lines SL1 to SL4.

In step S130, the CAM device 1000 may perform a match line evaluation operation. For example, each of the first to fourth memory cells C11 to C14 may compare stored data and codewords to determine whether there is a data match/mismatch (or match/mismatch). When the codeword is '11 10 01 00', it is assumed that the first memory cell C11 stores '11' and the second memory cell C12 stores '00'. Since the first memory cell C11 stores '11', in response to the voltage corresponding to '11' provided through the first search line SL1, the first FeTFET (FT11) of the first memory cell C11 can be turned off. That is, the first memory cell C11 can be matched. Since the second memory cell C12 stores '00', in response to the voltage corresponding to '10' provided through the second search line SL2, the second FeTFET (FT12) of the second memory cell C12 can be turned on. That is, the second memory cell C12 may mismatch.

In step S140, the CAM device 1000 may determine whether the match line matches/mismatches. For example, the CAM device 1000 may determine whether the first match line ML1 is a match/mismatch. If the match line matches, the CAM device 1000 performs step S150, and if the match line mismatches, the CAM device 1000 performs step S160.

In step S150, the match line may not be discharged. For example, when all memory cells C11 to C14 of the first memory cell group 1200_1 are matched, the first match line ML1 may not be discharged. That is, the first match line ML1 can maintain the precharged voltage (eg, power supply voltage VDD).

In step S160, the match line may be discharged. For example, when at least one of the memory cells C11 to C14 of the first memory cell group 1200_1 mismatches, the first match line ML1 may be discharged. That is, the first match line ML1 may be reduced from the precharged voltage to the ground voltage GND.

In step S170, the CAM device 1000 may generate an output signal based on the discharge rate (or discharge rate). For example, when at least one of the memory cells C11 to C14 of the first memory cell group 1200_1 is mismatched, the first match amplifier 1300_1 operates based on the discharge rate of the first match line ML1. The degree of mismatch (or number of mismatch bits) can be determined. The degree of mismatch indicates the ratio of the total number of memory cells in the first memory cell group and the number of mismatched memory cells. The first match amplifier 1300_1 may generate an output signal including the match result and the degree of mismatch through the first amplifier output line OA1, and transmit the output signal to the priority encoder 1400.

FIGS. 7A to 7D are diagrams for explaining an operation of searching data stored in the first memory cell group of FIG. 3 . 3 and 7A to 7D, the first memory cell C11 stores '11', the second memory cell C12 stores '10', and the third memory cell C13 stores '10'. It is assumed that '01' is stored, and the fourth memory cell C14 stores '00'. To search data, a voltage according to the logic value of the codeword may be applied to the first to fourth search lines SL1 to SL4.

To search data, the CAM device 1000 may perform a search line precharge step, a match line precharge step, and a match line evaluation step. The CAM device 1000 may precharge the search line in the search line precharge step. Thereafter, the CAM device 1000 may precharge the first match line ML1 with the power supply voltage VDD in the match line precharge step. Afterwards, the CAM device 1000 may apply a voltage corresponding to the codeword to the plurality of search lines SL1 to SL4 in the match line evaluation step. When a mismatch occurs in at least one of the plurality of memory cells C11 to C14 of the first memory cell group 1200_1, the first match line ML1 may be discharged to the ground voltage GND. When all memory cells C11 to C14 of the first memory cell group 1200_1 are matched, the first match line ML1 can maintain the precharged voltage.

As in the first case (CASE 1), all cells C11 to C14 of the first memory cell group 1200_1 may be matched. For example, the codeword may be '11 10 01 00'. The first memory cell C11 stores '11', and a voltage corresponding to '11' is provided through the first search line SL1, so the first memory cell C11 can be matched. The second memory cell C12 stores '10', and a voltage corresponding to '10' is provided through the second search line SL2, so the second memory cell C12 can be matched. The third memory cell C13 stores '01', and a voltage corresponding to '01' is provided through the third search line SL3, so the third memory cell C13 can be matched. The fourth memory cell C14 stores '00', and a voltage corresponding to '00' is provided through the fourth search line SL4, so the fourth memory cell C14 can be matched.

FIG. 7B is a graph for explaining the voltage of the first match line ML1 over time in the first case CASE 1 of FIG. 7A. The horizontal axis of the graph in FIG. 7B indicates time, and the vertical axis indicates the voltage (VML) of the first match line (ML1). Referring to FIG. 7B, the voltage VML of the first match line ML1 may maintain the precharged voltage. That is, since all cells C11 to C14 of the first memory cell group 1200_1 match, the voltage VML of the first match line ML1 may not be discharged.

As in the second case (CASE 2), the first memory cell C11 may mismatch, and the second to fourth memory cells C12 to C14 may match. For example, the codeword may be '00 10 01 00'. Since the first memory cell C11 stores '11' and a voltage corresponding to '00' is provided through the first search line SL1, the first memory cell C11 may be mismatched. The second memory cell C12 stores '10', and a voltage corresponding to '10' is provided through the second search line SL2, so the second memory cell C12 can be matched. The third memory cell C13 stores '01', and a voltage corresponding to '01' is provided through the third search line SL3, so the third memory cell C13 can be matched. The fourth memory cell C14 stores '00', and a voltage corresponding to '00' is provided through the fourth search line SL4, so the fourth memory cell C14 can be matched.

FIG. 7C is a graph for explaining the voltage of the first match line ML1 over time in the second case CASE 2 of FIG. 7A. The horizontal axis of the graph in FIG. 7C indicates time, and the vertical axis indicates the voltage (VML) of the first match line (ML1). Referring to FIG. 7C, the voltage VML of the first match line ML1 may be discharged to the ground voltage GND. Since the first memory cell C11 is mismatched, the precharged voltage VML of the first match line ML1 may be discharged to the ground voltage GND. For example, the voltage VML of the first match line ML1 may have the reference voltage VR at the first time point t1.

As in the third case (CASE 3), all cells C11 to C14 of the first memory cell group 1200_1 may mismatch. For example, the codeword may be '00 01 10 11'. Since the first memory cell C11 stores '11' and a voltage corresponding to '00' is provided through the first search line SL1, the first memory cell C11 may be mismatched. Since the second memory cell C12 stores '10' and a voltage corresponding to '01' is provided through the second search line SL2, the second memory cell C12 may be mismatched. Since the third memory cell C13 stores '01' and a voltage corresponding to '10' is provided through the third search line SL3, the third memory cell C13 may be mismatched. Since the fourth memory cell C14 stores '00' and a voltage corresponding to '11' is provided through the fourth search line SL4, the fourth memory cell C14 may be mismatched.

FIG. 7D is a graph for explaining the voltage of the first match line ML1 over time in the third case CASE 3 of FIG. 7A. The horizontal axis of the graph in FIG. 7D indicates time, and the vertical axis indicates the voltage (VML) of the first match line (ML1). Referring to FIG. 7D, the voltage VML of the first match line ML1 may be discharged to the ground voltage GND. Since all cells C11 to C14 of the first memory cell group 1200_1 are mismatched, the precharged voltage VML of the first match line ML1 may be discharged to the ground voltage GND. For example, the voltage VML of the first match line ML1 may have the reference voltage VR at a second time point t2, which is earlier than the first time point t1.

FIG. 8 is a block diagram showing an example of a portion of the CAM device of FIG. 1. For convenience of explanation and brevity of drawings, only the first memory cell group 1200_1 is shown in FIG. 8 . The remaining memory cell groups 1200_2 to 1200_4 may be the same or similar to the first memory cell group 1200_1. With reference to FIG. 8, the Current-race method is explained.

Referring to FIGS. 1 and 8 , each of the first to fourth memory cells C11 to C14 may include a ferroelectric tunnel field effect transistor (FeTFET). For example, the first memory cell C11 includes a first FeTFET (FT11), the second memory cell C12 includes a second FeTFET (FT12), and the third memory cell C13 includes a third FeTFET (FT13). ), and the fourth memory cell C14 may include a fourth FeTFET (FT14). The gate of the first FeTFET (FT11) is connected to the first search line (SL1), the gate of the second FeTFET (FT12) is connected to the second search line (SL2), and the gate of the third FeTFET (FT13) is connected to the first search line (SL1). 3 may be connected to the search line (SL3), and the gate of the fourth FeTFET (FT14) may be connected to the fourth search line (SL4).

The first FeTFET (FT11) is connected between the first match line (ML1) and the ground voltage (GND) (or a specific voltage, for example, VSS), and the second FeTFET (FT12) is connected to the first match line (ML1) and the ground voltage (GND), the third FeTFET (FT13) is connected between the first match line (ML1) and the ground voltage (GND), and the fourth FeTFET (FT14) is connected to the first match line (ML1) and a ground voltage (GND).

The CAM device 1000 may further include a current source (IML) (or current source), a second precharge transistor (PT2), and an activation transistor (ET). The second precharge transistor PT2 is connected between the ground voltage GND and the first match line ML1 and may operate in response to the precharge signal PRE. For example, the second precharge transistor PT2 may be an NMOS transistor. The second precharge transistor PT2 may precharge the first match line ML1 to the ground voltage GND in response to the precharge signal PRE.

The current source (IML) may be connected between the power supply voltage (VDD) and the activation transistor (ET). The activation transistor (ET) is connected between the current source (IML) and the first match line (ML1) and may operate in response to the complementary activation signal (/EN). For example, the activation transistor (ET) may be a PMOS transistor. The first match amplifier 1300_1 may be connected between the first match line ML1 and the amplifier output line OA1.

Unlike FIG. 3 , the first match line ML1 may be precharged with the ground voltage GND (or a specific voltage, for example, VSS). For example, the specific voltage (VSS) may be the same as or at a lower level than the ground voltage (GND). However, the scope of the present disclosure is not limited thereto. The match state of the first memory cell group 1200_1 can be evaluated by charging the first match line ML1 with the current provided by the current source IML.

To search data, the CAM device 1000 may perform a search line/match line precharge step and a match line evaluation step. That is, unlike FIG. 3, instead of performing the match line precharge step after performing the search line precharge step, the search line/match line precharge step can be performed simultaneously. That is, since the first match line ML1 is precharged with the ground voltage GND, the search line precharge step and the match line precharge step can be performed simultaneously.

In the search line/match line precharge step, the CAM device 1000 may precharge the search line and precharge the first match line ML1 to the ground voltage GND. Afterwards, in the match line evaluation step, the CAM device 1000 may apply a voltage corresponding to the codeword to the plurality of search lines SL1 to SL4. The current source (IML) may be connected to the first match line (ML1) in response to the complementary activation signal (/EN). When a mismatch occurs in at least one of the plurality of memory cells C11 to C14 of the first memory cell group 1200_1, the first match line ML1 is connected according to the voltage dividing principle of the series resistance. , as shown in Equation 1, the miss voltage ( ) can be charged. represents the number of mismatched cells in the first memory cell group 1200_1, R _FT represents the resistance of the FeTFET corresponding to the mismatched cell, and R _IML represents the resistance of the current source.

When all memory cells C11 to C14 of the first memory cell group 1200_1 are matched, the capacitance of the first match line ML1 is sufficiently charged and enters a steady-state. When charged, it can reach VDD. Alternatively, if a transient state is used, the difference between the sum of the current of the current source ( I _ML ) and the current of m mismatched FeTFETs ( I _FT ) is the time (t) to charge the capacitance of the match line ( C _ML ). You can use this to determine match/mismatch.

In one embodiment, the first match amplifier 1300_1 may determine whether there is a match/mismatch between the codeword and the data stored in the first memory cell group 1200_1 based on the voltage level of the first match line ML1. there is. For example, when the first match amplifier 1300_1 determines that the first match line ML1 is charged, it may determine that the data stored in the first memory cell group 1200_1 matches the codeword. When the first match amplifier 1300_1 determines that the first match line ML1 maintains a low voltage or ground voltage, it may determine that the data stored in the first memory cell group 1200_1 and the codeword do not match.

As described above, unlike FIG. 3, before the search operation, the first match line ML1 of the first memory cell group 1200_1 is precharged (or charged) with the ground voltage GND (or low voltage), and the stored Depending on the match/mismatch between the data and the search data, the first match line ML1 may be charged at a high voltage or maintained at a low voltage.

FIG. 9 is a flowchart showing an example of a method of operating the CAM device of FIG. 1 including the first memory cell group of FIG. 8. Referring to FIGS. 1, 8, and 9, in step S210, the CAM device 1000 may precharge the match line. Hereinafter, for convenience of explanation, description will be made based on the first memory cell group 1200_1. Since the second to fourth memory cell groups 1200_2 to 1200_4 operate the same or similar to the first memory cell group 1200_1, detailed descriptions are omitted. For example, the CAM device 1000 may precharge the first match line ML1 by applying the ground voltage GND to the first match line ML1.

In step S220, the CAM device 1000 may input a codeword. For example, the driver 1100 of the CAM device 1000 may provide (or input) a codeword to the first memory cell group 1200_1 through a plurality of search lines SL1 to SL4. The CAM device 1000 may apply a voltage corresponding to a codeword to a plurality of search lines SL1 to SL4.

In step S230, the CAM device 1000 may perform a match line evaluation operation. For example, each of the first to fourth memory cells C11 to C14 may compare stored data and codewords to determine whether there is a data match/mismatch (or match/mismatch).

In step S240, the CAM device 1000 may determine whether the match line matches/mismatches. For example, the CAM device 1000 may determine whether the first match line ML1 is a match/mismatch. If the match line matches, the CAM device 1000 performs step S250, and if the match line mismatches, the CAM device 1000 performs step S260.

In step S250, the match line may be charged. For example, when all memory cells C11 to C14 of the first memory cell group 1200_1 are matched, the first match line ML1 may not be discharged. That is, the first match line ML1 can be charged to a high voltage by the current provided by the current source IML. That is, the first match line ML1 may increase from the ground voltage GND to the high voltage or power voltage VDD.

In step S260, the match line may not be charged. For example, when at least one of the memory cells C11 to C14 of the first memory cell group 1200_1 is mismatched, the first match line ML1 may maintain a low voltage or the ground voltage GND. A discharge current path is generated by mismatched memory cells among the memory cells C11 to C14 of the first memory cell group 1200_1, offsetting the current supplied from the current source IML, so that the first match line is free of charge. A charged ground voltage (GND) can be maintained.

In step S270, the CAM device 1000 may generate an output signal. For example, the CAM device 1000 may generate an output signal based on the charging rate. The first match amplifier 1300_1 generates an output signal including the match result and the degree of mismatch (or the number of mismatch bits) through the first amplifier output line OA1, and delivers the output signal to the priority encoder 1400. You can.

FIGS. 10A to 10D are diagrams for explaining the operation of the first memory cell of FIGS. 3 and 8. Each of the first to fourth FeTFETs (FT11 to FT14) is configured substantially the same as each other and operates substantially the same. Therefore, for convenience of explanation, the first FeTFET (FT11) is used as an example, and since the remaining cells (FT12 to FT14) are the same or similar to the first FeTFET (FT11), detailed description thereof is omitted.

Referring to FIGS. 1, 3, 8, and 10A, the first memory cell C11 can store 2 bits. For example, the first memory cell C11 may store logic '11', '01', '00', and '10'. When the CAM device 1000 is a TCAM device, the first memory cell C11 may additionally store 'XX'.

In one embodiment, when the first memory cell C11 stores '11', if the voltage VSL of the first search line SL1 is 0V or more and the first voltage V1 or less, the drain current ID ) may be smaller than the reference current. If the voltage VSL of the first search line SL1 exceeds the first voltage V1, the drain current ID may be greater than the reference current.

When the first memory cell C11 stores '01', if the voltage VSL of the first search line SL1 is greater than the first voltage V1 and less than the second voltage V2, the drain current ID ) may be smaller than the reference current. If the voltage VSL of the first search line SL1 is less than the first voltage V1 or greater than the second voltage V2, the drain current ID may be greater than the reference current.

When the first memory cell C11 stores '00', if the voltage VSL of the first search line SL1 is greater than the second voltage V2 and less than the third voltage V3, the drain current ID ) may be smaller than the reference current. If the voltage VSL of the first search line SL1 is less than the second voltage V2 or greater than the third voltage V3, the drain current ID may be greater than the reference current.

When the first memory cell C11 stores '10', if the voltage VSL of the first search line SL1 is higher than the third voltage V3 and lower than the fourth voltage V4, the drain current ID ) may be smaller than the reference current. If the voltage VSL of the first search line SL1 is less than the third voltage V3 or greater than the fourth voltage V4, the drain current ID may be greater than the reference current.

When the first memory cell (C11) stores 'XX', if the voltage (VSL) of the first search line (SL1) is 0V or more and the fourth voltage (V4) or less, the drain current (ID) is greater than the reference current. It can be small. If the voltage VSL of the first search line SL1 is less than 0V or greater than the fourth voltage V4, the drain current ID may be greater than the reference current.

Referring to FIG. 10B, a method of programming (or storing) '11' or '01' in the first memory cell C11 will be described. In one embodiment, a positive voltage is applied to the gate electrode layer 440c, and a ground voltage (GND) (or a level equal to or lower than the ground voltage (GND)) is applied to the first electrode 450 and the second electrode 460. By applying a specific voltage (VSS, low voltage), the ferroelectric layer 440b may have a first polarization state. For example, the first polarization state may be a down polarization state. Electrons may accumulate in the upper part of the channel region 430. A first positive voltage is applied to the gate electrode layer 440c, '11' is programmed into the first memory cell C11, and a second positive voltage smaller than the first positive voltage is applied to the gate electrode layer 440c. Thus, '01' can be programmed into the first memory cell C11.

Referring to FIG. 10C, a method of programming '00' or '10' into the first memory cell C11 will be described. In one embodiment, a negative voltage is applied to the gate electrode layer 440c, and a ground voltage (GND) (or a level equal to or lower than the ground voltage (GND)) is applied to the first electrode 450 and the second electrode 460. By applying a specific voltage (VSS), the ferroelectric layer 440b may have a second polarization state. For example, the second polarization state may be an up polarization state. Holes may accumulate in the upper part of the channel region 430. A first negative voltage is applied to the gate electrode layer 440c, so that '00' is programmed into the first memory cell C11, and a second negative voltage is applied to the gate electrode layer 440c, so that the first memory cell (C11) is programmed with '00'. '10' can be programmed in C11). The absolute value of the second negative voltage may be greater than the absolute value of the first negative voltage.

Referring to FIG. 10D, a method of programming 'XX' into the first memory cell C11 will be described. In one embodiment, a third positive voltage is applied to the gate electrode layer 440c, a fourth positive voltage greater than the third positive voltage is applied to the first electrode 450, and a fourth positive voltage is applied to the second electrode 460. By applying the ground voltage (GND) (or a specific voltage (VSS) that is the same or lower level as the ground voltage (GND)), the ferroelectric layer 440b may have a third polarization state. Holes may accumulate in the upper part of the channel region 430 adjacent to the first doped region 410, and electrons may accumulate in the upper part of the channel region 430 adjacent to the second doped region 420.

FIG. 11 is a diagram showing an example of the first ferroelectric tunnel field effect transistor device of FIGS. 3 and 8. Hereinafter, for convenience of explanation and brevity of drawings, detailed descriptions of components that are the same as or similar to the components described above are omitted.

3, 8, and 11, the first FeTFET (FT11) has a first doped region 410, a second doped region 420, a channel region 430, and a first doped region 410 formed on the semiconductor substrate 400. It may include a first delta doped region 470 and a second delta doped region 480. The first FeTFET (FT11) may further include a gate 440, a first electrode 450, and a second electrode 460.

In one embodiment, the first delta doped region 470 may be formed adjacent to the first doped region 410 in the first direction D1. The first delta doped region 470 may be formed between the first doped region 410 and the channel region 430. The first delta doped region 470 may be formed (or disposed, located) below the gate 440 . The first delta doped region 470 may have a conductivity type opposite to that of the first doped region 410. For example, the first delta doped region 470 may have a second conductivity type. The first delta doped region 470 may have a high concentration of N+ type doped. The first delta doped region 470 may be a source pocket region doped at a high concentration with impurities of the same conductivity type as the second doped region 420.

The first delta doping region 470 may have a first delta doping concentration. The doping concentration of the first delta doped region 470 may be higher than that of the channel region 430 or the semiconductor substrate 400. The doping concentration of the first delta doped region 470 may be equal to or higher than the doping concentration of the second doped region 420.

In one embodiment, the second delta doped region 480 may be formed adjacent to the second doped region 420 in the first direction D1. The second delta doped region 480 may be formed between the second doped region 420 and the channel region 430. The second delta doped region 480 may be formed below the gate 440 . The second delta doped region 480 may have a conductivity type opposite to that of the second doped region 420. For example, the second delta doped region 480 may have a first conductivity type. The second delta doped region 480 may have a highly doped P+ type. The second delta doped region 480 may be a drain pocket region doped at a high concentration with impurities of the same conductivity type as the first doped region 410.

The second delta doping region 480 may have a second delta doping concentration. The doping concentration of the second delta doped region 480 may be higher than that of the channel region 430 or the semiconductor substrate 400. The doping concentration of the second delta doped region 480 may be equal to or higher than the doping concentration of the first doped region 410.

The width of the first doped region 410 in the first direction D1 is the first length L1, and the width of the first delta doped region 470 in the first direction D1 is the second length L2. ), the width of the channel region 430 in the first direction (D1) is the third length (L3), and the width of the second delta doped region 480 in the first direction (D1) is the fourth length (L3). L4), and the width of the second doped region 420 in the first direction D1 may be the fifth length L5.

The second length L2 may be smaller than the first length L1 or the third length L3. For example, the ratio of the second length L2 and the third length L3 may be 1:250. The fourth length L4 may be smaller than the third length L3 or the fifth length L5. For example, the ratio of the fourth length L4 and the third length L3 may be 1:250. The second length L2 and the fourth length L4 may be the same or similar. However, the scope of the present disclosure is not limited thereto.

Accordingly, by facilitating band-to-band tunneling of the first FeTFET (FT11) device and reducing the turn-on voltage (V _TH ), the CAM device 1000 performs turn-on operation and Bipolar (or ambipolar) operation can be improved.

FIG. 12 is a diagram illustrating an example of the first ferroelectric tunnel field effect transistor device of FIGS. 3 and 8. Hereinafter, for convenience of explanation and brevity of drawings, detailed descriptions of components that are the same as or similar to the components described above are omitted.

Referring to FIGS. 3, 8, 11, and 12, in one embodiment, the doping concentration of the first delta doped region 470 may be adjusted. For example, the first delta doping region 470 may have a third delta doping concentration that is different from the first delta doping concentration. The doping concentration of the second delta doped region 480 can be adjusted. For example, the second delta doping region 480 may have a fourth delta doping concentration that is different from the second delta doping concentration.

In one embodiment, unlike FIG. 11 , the first delta doped region 470 of FIG. 12 may not extend as deeply into the semiconductor substrate 400 as the first doped region 410 . The second delta doped region 480 of FIG. 12 may not extend as deeply into the semiconductor substrate 400 as the second doped region 420 .

The width of the first doped region 410 in FIG. 11 in the second direction D2 may be equal to the width of the first delta doped region 470 in the second direction D2. The width of the second doped region 420 in FIG. 11 in the second direction D2 may be the same as the width of the second delta doped region 480 in the second direction D2.

On the other hand, the width of the first doped region 410 in FIG. 12 in the second direction D2 may be different from the width of the first delta doped region 470 in the second direction D2. The width of the second doped region 420 in FIG. 12 in the second direction D2 may be different from the width of the second delta doped region 480 in the second direction D2. The width of the first doped region 410 in the second direction D2 is the first width W1, and the width of the second doped region 420 in the second direction D2 is the second width W2. , the width of the first delta doped region 470 in the second direction (D2) is the third width (W3), and the width of the second delta doped region 480 in the second direction (D2) is the fourth width. It may be the width (W4). The third width W3 may be smaller than the first width W1. The fourth width W4 may be smaller than the second width W2. The third width W3 and the fourth width W4 may be the same or similar.

FIG. 13 is a graph for explaining the characteristics of the first FeTFET device of FIG. 3. Referring to FIGS. 1, 3, and 13, graph (i) of FIG. 13 shows the drain current (i.e., the voltage of the first search line (SL1)) versus the gate voltage (VSL) applied through the search line. ID). That is, the horizontal axis of graph (i) indicates the gate voltage (VSL), and the vertical axis of graph (i) indicates the drain current (ID). Graph (ii) shows the voltage (VOA) of the match amplifier output stage (i.e., the voltage of the amplifier output line (OA1)) relative to the gate voltage (VSL) applied through the search line. That is, the horizontal axis of graph (ii) indicates the gate voltage (VSL), and the vertical axis of graph (i) indicates the voltage (VOA) of the match amplifier output stage.

Referring to FIG. 13, it can be seen that the FeTFET device has a very low current in a specific gate voltage range (the section between Va and Vb). However, it has a band rejection characteristic for voltage called ambipolar behavior, in which the current increases rapidly when it exceeds a certain voltage range. In other words, it is turned off within a specific voltage range, and automatically turns on when the voltage is lower or higher than the specific voltage range.

Due to these characteristics, if the MOSFET device of FIG. 2a is replaced with the FeTFET device of FIG. 3, multi-bit CAM can be implemented with only one transistor without the complementary search line (/SL), and the degree of mismatch ) operations can be implemented simultaneously. Additionally, rapid on-off switching characteristics improve multi-bit sensing accuracy, and the degree of mismatch can be accurately determined using low off-current and low on-current characteristics.

FIG. 14 is a graph for explaining a 2-bit implementation operation using the switching characteristics of the first FeTFET device of FIG. 3. Graph (i) of FIG. 14 shows the drain current (ID) against the gate voltage (VSL) applied through the search line, and graph (ii) of FIG. 14 shows the drain current (ID) against the gate voltage (VSL) applied through the search line. This shows the voltage (VOA) at the output stage of the sense amplifier.

Referring to FIG. 14, it can be seen that the difference between the current flowing when search data and stored data match and the current flowing when mismatching is maximized.

The FeTFET device operates under the reverse voltage condition of the gated pin diode structure, so it has a very low off current compared to the MOSFET device. In addition, it shows a low driving voltage due to abrupt on-off switching, and shows a relatively low on-current because it uses tunneling current. This means that match/mismatch accuracy and power consumption can be reduced when implementing large-capacity CAM. In other words, it is possible to implement an accurate low-power content addressable memory device and a content addressable memory device that determines the degree of mismatch by using a very low off current, low driving voltage, and reversely using the low on current.

Figure 15 is an operation prediction graph for determining the degree of inconsistency of a content addressable memory device according to an embodiment of the present disclosure. Graph (i) in FIG. 15 shows the change in voltage (V) of the match line with respect to the gate voltage (VSL) applied through the search line, and graph (ii) in FIG. 15 shows the change in gate voltage (VSL) applied through the search line. It shows the voltage (VSAOUT or VOA) at the output stage of the sense amplifier (or match amplifier) relative to VSL).

Figure 15 shows an operation prediction graph in the precharge-high method. Generally, a high voltage is applied to the match line (ML) during a precharge operation, and the search data (or codeword) matches the stored data. In this case, high voltage on the match line is maintained. Conversely, if the search data and the stored data do not match, the match line is discharged, and a voltage drop occurs at the output terminal (OA) of the sense amplifier (or match amplifier). On the other hand, in the current race method, a low voltage is applied to the match line (ML) during a precharge operation, and if there is a mismatch between search data and stored data, the low voltage of the match line is maintained. Conversely, when the search data matches the stored data, the match line is charged, and a voltage rise occurs at the output terminal (OA) of the sense amplifier (or match amplifier), showing a trend opposite to that shown in FIG. 15.

In the present disclosure, in the case of precharge-high, the number of mismatch bits can be determined through the speed at which the match line is discharged and the resulting time difference in the voltage drop at the output stage of the sense amplifier (or match amplifier), as shown in FIG. 15. On the other hand, in the case of the current race, contrary to Figure 15, the number of mismatch bits can be determined through the speed at which the match line is charged and the resulting time difference in the voltage increase at the output stage of the sense amplifier (or match amplifier).

In the precharge-high method, it can be determined that the number of mismatch bits increases as the speed at which the match line is discharged increases. Additionally, the number of mismatched bits can be determined through the time difference in the voltage drop that occurs at the output stage of the sense amplifier. For example, as the number of mismatched bits increases from 1 bit mismatch to 8 bit mismatch, the voltage of the match line decreases rapidly, and as the number of mismatched bits increases, the voltage drop at the output stage of the sense amplifier occurs in a short period of time. On the other hand, in the current race method, it can be determined that the number of mismatch bits decreases as the speed at which the match line is charged increases. Additionally, the number of mismatched bits can be determined through the time difference in the voltage rise that occurs at the output stage of the sense amplifier. For example, as the number of mismatched bits increases from 1 bit mismatch to 8 bit mismatch, the voltage of the match line rises more slowly, and as the number of mismatched bits increases, the voltage at the output stage of the sense amplifier occurs in a slower time.

The operation of determining the degree of data mismatch requires discharging the voltage precharged in the match line while providing appropriate conductance in the CAM memory cells according to the degree of mismatch. As in the present disclosure, memory cells based on FeTFET devices are used. The addressable memory device has a low on-current, that is, low conductivity, so as the capacity of the CAM increases, it has a very advantageous advantage in determining the degree of mismatch.

The operation of determining the degree of this discrepancy is not simply to judge the relationship between input data (or search data, codewords) and stored data as a dichotomy of match/mismatch, but to determine the degree of discrepancy even in the case of mismatch. , This is a necessary operation in recent artificial intelligence or one-shot/few-shot learning.

As described above, the content addressable memory device according to an embodiment of the present disclosure configures a multi-bit CAM using one transistor and can independently perform the function of determining the degree of mismatch. These content-addressable memory devices can be deployed as leading high-speed, low-power, parallel data processing technologies essential for the implementation of intelligent semiconductors. In addition, it goes beyond applications such as image processing, pattern recognition, and Internet routers to enable high-speed, low-power, high-intensity parallel data processing, making it possible to acquire new growth engines that will dramatically advance the competitiveness of big data and artificial intelligence-related ICT products. It can be applied to one-shot/few-shot learning using MANN (memory-augmented neural network), which has recently been gaining a lot of attention in the field of artificial intelligence.

The above-described contents are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that are simply designed or can be easily changed. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described below.

1000: CAM device
1100: driver
1200: Memory cell array
1300: Amplifier
1400: Priority encoder

Claims (20)

a memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET);
a driver providing a codeword to the memory cell array through a plurality of search lines; and
A match amplifier connected to the plurality of memory cells through a plurality of match lines,
The FeTFET is:
a first doped region having a first conductivity type;
a second doped region having a second conductivity type different from the first conductivity type;
a channel region formed between the first doped region and the second doped region; and
formed on the channel region, comprising a gate including a ferroelectric layer, and
The content addressable memory device wherein the gate is connected to the one search line, and one of the first doped region and the second doped region is connected to one match line of the plurality of match lines. delete According to claim 1,
The FeTFET is a first FeTFET of a first memory cell among the plurality of memory cells,
The one search line is the first search line,
The one match line is the first match line,
A doped region of the first doped region and the second doped region that is not connected to the first match line is connected to a ground voltage,
The first FeTFET is a content addressable memory device in which the first FeTFET is turned on or turned off in response to a voltage corresponding to a codeword applied through the first search line. According to claim 1,
Further comprising a precharge transistor connected between a first match line among the plurality of match lines and a power voltage, and operating in response to a precharge signal,
The precharge transistor precharges the first match line with the power voltage in response to the precharge signal. According to claim 4,
The first match line is not discharged when the codewords of all of the memory cells connected to the first match line match the stored data,
The first match line is discharged when the codeword does not match the data stored in at least one of the memory cells connected to the first match line. According to claim 4,
The match amplifier determines the number of mismatch bits based on the discharge rate of the first match line. According to claim 1,
a precharge transistor connected between a first match line among the plurality of match lines and a ground voltage and operating in response to a precharge signal;
A current source connected between the power supply voltage and the enabling transistor; and
Further comprising the activation transistor connected between the current source and the first match line and operating in response to an activation signal,
The precharge transistor precharges the first match line to the ground voltage in response to the precharge signal in the match line precharge step,
The activation transistor provides current to the first match line in response to the activation signal in a match line evaluation step after the match line precharge step to charge the first match line. According to claim 7,
The first match line is charged when the stored data and codeword of all of the memory cells connected to the first match line match,
The first match line is not charged when at least one of the memory cells connected to the first match line does not match stored data with the codeword. According to claim 1,
The gate includes a gate insulating layer, the ferroelectric layer, and a gate electrode layer,
The ferroelectric layer is PZT(Pb(Zr,Ti)O ₃ ), SBT(SrBi ₂ Ta ₂ O ₉ ), SBTN(SrBi ₂ (Ta,Nb)O ₉ ), BLT((Bix,La1-x) ₄ Ti ₃ O ₁₂ ) and BST (BaxSr(1-x)TiO ₃ ), hafnium oxide (HfO ₂ ), hafnium oxide with silicon added (HfO ₂ /Si), hafnium oxide with aluminum added (HfO ₂ /Al), or zirconium-doped hafnium oxide (HfO ₂ /Zr). According to claim 1,
Further comprising a priority encoder outputting an address of the memory cell array having data matching a codeword,
The match amplifier determines match/mismatch between the codeword and data stored in memory cells connected to the first match line based on the voltage level of the first match line and outputs the match result to the priority encoder. memory device. According to claim 1,
The FeTFET is:
a first delta doped region having the second conductivity type between the first doped region and the channel region; and
A content addressable memory device further comprising a second delta doped region having the first conductivity type between the second doped region and the channel region. According to claim 11,
The width of the first doped region in the first direction is a first length, and the width of the first delta doped region in the first direction is a second length smaller than the first length,
A width of the second doped region in the first direction is a third length, and a width of the second delta doped region in the first direction is a fourth length smaller than the third length. According to claim 12,
A width of the first doped region in a second direction perpendicular to the first direction is equal to a width of the first delta doped region in the second direction,
A content addressable memory device wherein a width of the second doped region in the second direction is equal to a width of the second delta doped region in the second direction. According to claim 12,
The width of the first doped region in the second direction perpendicular to the first direction is a first width, and the width of the first delta doped region in the second direction is a second width smaller than the first width. ,
The width of the second doped region in the second direction is a third width, and the width of the second delta doped region in the second direction is a fourth width smaller than the third width. A memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET), a driver providing a codeword to the memory cell array through a plurality of search lines, and a plurality of memories through a match line. A method of operating a content addressable memory device comprising a match amplifier connected to cells, wherein each of the plurality of memory cells is connected to one of the plurality of search lines,
Precharging the match line by applying a power supply voltage to the match line;
Inputting a codeword into a memory cell connected to the match line;
comparing the codeword with data stored in the memory cell connected to the match line to determine whether the data matches/mismatches;
not discharging the match line when it is determined that the codeword and the stored data match;
discharging the match line when it is determined that the codeword and the stored data do not match; and
generating, by the match amplifier, an output signal based on the discharge rate of the match line, and
An operating method wherein the gate of the FeTFET is connected to the one search line, and the drain region of the FeTFET is connected to the match line. According to claim 15,
The step of inputting the codeword includes applying a voltage corresponding to the codeword to the plurality of search lines. According to claim 15,
The output signal includes the number of mismatch bits and a match result determined based on the discharge rate. A memory cell array including a plurality of memory cells each including a ferroelectric tunnel field effect transistor (FeTFET), a match amplifier connected to the plurality of memory cells through a match line, and a current source supplying current to the match line. In a method of operating a content addressable memory device,
Precharging the match line by applying a ground voltage to the match line;
Inputting a codeword into a memory cell connected to the match line;
comparing the codeword with data stored in the memory cell connected to the match line to determine whether the data matches/mismatches;
If it is determined that the codeword and the stored data match, charging the match line;
If it is determined that the codeword and the stored data do not match, not charging the match line; and
A method of operation comprising generating an output signal by the match amplifier. According to claim 18,
The step of inputting the codeword includes applying a voltage corresponding to the codeword to search lines connected to each of the memory cells connected to the match line. According to claim 18,
The step of charging the match line includes charging the match line to a high voltage by a current provided by the current source,
The step of not charging the match line includes maintaining a low voltage in the match line because a discharge current path is generated by a mismatched memory cell to offset the current provided from the current source.

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