KR102635886B1 - System for transmitting multichannel audio signal - Google Patents

Abstract

The present invention relates to a multi-channel audio signal transmission system implemented to enable multi-channel real-time network audio transmission by applying AVB (audio video bridging), a standardized audio and video transmission standard, and includes a main board and an audio input/output board. and; The main board includes a clock generator that generates a clock signal by a frequency control signal; A frequency control signal is generated and input to the clock generator, a drive control signal is generated according to the clock signal generated by the clock generator, and audio signals are transmitted to the audio input/output board by applying AVB, a standardized audio and video transmission standard. a processor unit that controls real-time network transmission of the channel; and an interface unit that performs an interface with the audio input/output board unit and a network interface according to the driving control signal generated by the processor unit. The audio input/output board has an audio input channel formed of at least two or more multi-channels and an audio output channel formed of at least two or more multi-channels, and inputs and outputs audio signals under the control of the processor unit to perform real-time network transmission. do.

Description

{System for transmitting multichannel audio signal}

The technical field of the present invention relates to a multi-channel audio signal transmission system. In particular, a multi-channel audio signal implemented to enable multi-channel real-time network audio transmission by applying AVB (audio video bridging), a standardized audio and video transmission standard. It's about the transmission system.

Audio devices provide many people with the ability to listen to music at any time in their daily lives. In particular, portable audio playback devices such as mobile phones and MP3 players with music playback functions have made remarkable progress, allowing many people to own a portable audio playback device. After storing dozens or hundreds of songs, you can now enjoy music files while carrying them around. There are several types of digital audio interface formats used for such music files.

Representative digital audio interface formats include I2S (inter-IC sound bus), normal serial audio format, and S/PDIF. In particular, the I2S format is widely used in ADCs (analog to digital converters) used in small portable digital audio devices. This is because audio signals can be transmitted by changing settings such as.

In order to transmit audio signals in this I2S format, three transmission channels are required to transmit left right clock (LRCK), bit clock (BCLK), and serial data (SD). LRCK is, for example, a clock for distinguishing between left and right signals in the case of a 2-channel audio signal. BCLK is a clock for transmitting each bit corresponding to the audio signal. SD is a signal that includes an audio signal and has an MSB (most significant bit) mode in which the most significant bit is transmitted first, and an LSB (least significant bit) mode in which the least significant bit is transmitted first.

The IC (integrated circuit) that receives the audio signal cannot know how many bits the SD contains and how many bits will be transmitted. However, if the size of the word used by the system is larger than the size of the transmitted audio signal, the system adjusts the size of the SD by adding a NULL signal (for example, '0') to the end of the audio signal. Adjust to the size of the word used. By adding a null signal after the audio signal in this way, there is an advantage that the IC receiving the SD does not need to know the size of the SD, but there is a disadvantage that the transmission channel is wasted by adding an unnecessary null signal. Additionally, in order to use an I2S format audio signal on an IC such as an ADC or DAC (digital to analog converter), the ADC or DAC must be controlled. Therefore, because a separate channel is needed to transmit control signals, ICs for transmitting I2S format audio signals have the disadvantage of having to use many pins.

Korean Patent No. 10-1116617 (registered on February 8, 2012) is a method and device for I2S format audio transmission and processing that saves transmission channels and efficiently controls audio signals in I2S format. Disclosed is an apparatus for transmitting an audio signal in a regular serial audio format between a first logic and a second logic, comprising: a converter that converts an additional information signal for an audio signal into an additional information signal in a regular serial audio format; and a transmission unit that uses a channel through which the audio signal is transmitted, inserts and transmits the converted additional information signal in a section where the audio signal is not transmitted, and the additional information signal includes format information of the audio signal, It is characterized by including at least one of time information for synchronized playback. According to the disclosed technology, there is no need to use a separate transmission channel by transmitting the additional information signal together with the channel transmitting the audio signal, and the audio signal can be controlled in sampling units, thereby accurately and efficiently controlling the A/V flow. can do.

Korean Patent No. 10-0172500 (registered on October 24, 1998) connects a digital audio source device and an amplifier through a multichannel audio digital interface (MADI), thereby providing a device that is redundantly built into the source device and amplifier. A multi-channel audio signal transmission system is disclosed that not only reduces the number of decoders, but also allows transmission of multi-channel uncompressed audio signals or high-sampling audio signals. According to the disclosed technology, in a circuit for transmitting multi-channel PCM audio signals, a digital audio source device and a digital amplifier/processor are connected through MADI capable of transmitting multi-channel PCM audio signals; The digital audio source device includes a decoder that multi-channel decodes compressed audio signals read from a predetermined recording medium and converts them into PCM audio signals; a format unit that formats the PCM audio signal received from the decoder and the PCM audio signal read from the recording medium for transmission through MADI; And by including a MADI output unit for outputting the formatted audio signal as MADI, the amplifier has a relatively reduced digital circuit, thereby reducing the negative impact on the analog signal, and also MMCD/SD (multimedia compact disc/super). Multi-channel uncompressed audio signals or high-sampling audio signals supported by density) can also be output using MADI.

In the conventional technology as described above, there is a disadvantage of incompatibility as separate audio transmission standards must be followed depending on the type of system or device used by the user. Two-way network audio transmission capable of multi-channel transmission is not possible, and multi-channel transmission is not possible. During transmission, transmission delays occur depending on the channel, making multi-channel real-time transmission impossible, the quality of transmission data is poor, the installation structure is complex, making the use of surrounding space inefficient, and installation costs also increase.

Korean Patent No. 10-1116617 Korean Patent No. 10-0172500

The problem to be solved by the present invention is to solve the above-mentioned shortcomings, and implements multi-channel real-time network audio transmission by applying AVB (audio video bridging), a standardized audio and video transmission standard. To provide a channel audio signal transmission system.

Means for solving the above-described problem include, according to one feature of the present invention, a main board and an audio input/output board; The main board includes a clock generator that generates a clock signal by a frequency control signal; A frequency control signal is generated and input to the clock generator, a drive control signal is generated according to the clock signal generated by the clock generator, and an audio signal is input and output by applying AVB, a standardized audio and video transmission standard. A processor unit that controls real-time network transmission for multiple channels on the board; and an interface unit that performs an interface with the audio input/output board unit and a network interface according to a driving control signal generated by the processor unit. The audio input/output board has an audio input channel formed of at least two or more multi-channels and an audio output channel formed of at least two multi-channels, and inputs and outputs audio signals under the control of the processor unit to perform real-time network transmission. Provides a multi-channel audio signal transmission system that performs

In one embodiment, the clock generator receives an analog waveform signal and compares the frequency converted to a digital signal with the frequency multiplied by digital logic by the frequency control signal of the processor unit to adjust the desired clock frequency in the system. It is characterized by generating a clock signal using a digital frequency adjustment method that outputs it.

In one embodiment, the clock generator generates a low-jitter clock signal with little waveform distortion in a frequency multiplier PLL IC, and supplies the generated low-jitter 24MHz signal as the main clock of the processor unit. It is characterized by giving.

In one embodiment, the clock generator inputs the reference clock of the PLL IC that supplies the MCLK signal to the ADC and DAC operating at a sampling rate of 48 KHz.

In one embodiment, the processor unit includes a multi-core processor that includes at least two tiles with at least two cores, and performs multitasking of input/output, signal processing, and user program execution.

In one embodiment, the processor unit has eight cores built in for each tile, is designed with an internal memory sharing structure so that each core can access common memory, and maintains a processing speed of 2,000 MIPS, It supports USB or Gigabit Ethernet, and has programming for ADC and DAC control and LED display control operations through the I2C interface of the interface unit for analog audio input and output, and controls the chip designed on the audio input/output board. It is characterized by being in charge.

In one embodiment, the processor unit includes a synchronization check signal generator that generates a synchronization check signal under control and transmits it to each of the multiple channels; a check response signal receiver that receives synchronization check response signals transmitted from each receiver of multiple channels according to control and notifies the synchronization response of each channel; a response time checker that controls the operations of the synchronization check signal generator and the check response signal receiver, receives synchronization responses of each channel from the check response signal receiver, and checks the synchronization response time of each channel; a response difference calculator that checks the latest synchronization response time among the synchronization response times of each channel confirmed by the response time checker and calculates a difference time from the synchronization response time of each channel based on the latest confirmed synchronization response time; and a transmission time setting device that sets network transmission times for the multiple channels to delay audio signals by the synchronization difference times calculated by the response difference calculator and transmit them over the network.

In one embodiment, the synchronization check signal generator is characterized in that it transmits the synchronization check signal directly to each of the multiple channels without going through the transmission time setting device.

In one embodiment, the receiver receives the synchronization check signal transmitted from the synchronization check signal generator, processes the signal, generates a synchronization check response signal as a corresponding synchronization response, and transmits the synchronization check signal to the check response signal receiver. It is characterized by:

In one embodiment, the response time checker is characterized in that it controls the operations of the synchronization check signal generator and the check response signal receiver when performing an initial operation, upon resetting, or at a preset period.

In one embodiment, the processor unit is notified of a channel that has elapsed a preset synchronization error time from the response time checker, and further includes an error notification unit that notifies the operator or manager of the channel in which the synchronization error occurred. .

In one embodiment, the response time checker is notified of the synchronization response of each channel from the check response signal receiver, checks whether there is a channel whose confirmed synchronization response time has elapsed a preset synchronization error time, and determines whether the preset synchronization error time has elapsed. If there is a channel whose error time has elapsed, this is notified to the error notification device.

In one embodiment, the processor unit further includes a transmission time initialization manager that initializes the network transmission time for each channel of the transmission time setter under the control of the response time checker.

In one embodiment, the check response signal receiver receives the first initialization check response signal transmitted from each receiver of multiple channels under the control of the response time checker and sends the first initialization response of each channel at the response time. At the same time as notifying the checker, the second initialization check response signal transmitted from each multi-channel receiver is received and the second initialization response of each channel is notified to the response time checker.

In one embodiment, the receiver receives the first initialization check signal transmitted from the transmission time initialization manager, processes the signal, and then generates a first initialization check response signal as a first initialization response corresponding to the first initialization check signal to perform the check. At the same time as transmitting each to the response signal receiver, each second initialization check signal transmitted from the transmission time initialization manager is received and processed, and a second initialization check response signal is generated as a corresponding second initialization response. It is characterized in that it is transmitted to each of the check response signal receivers.

In one embodiment, the response time checker controls the operation of the transmission time initialization manager when performing an initial operation or upon reset, and receives notification of the first initialization response of each channel from the check response signal receiver to determine the first initialization response of each channel. Confirming the initialization response time and notifying it to the response difference calculator, simultaneously receiving notification of the second initialization response of each channel from the check response signal receiver, confirming the second initialization response time of each channel and reporting it to the response difference calculator It is characterized by doing.

In one embodiment, the response difference calculator calculates the difference time between the first initialization response time and the second initialization response time of each channel notified from the response time checker and reports the difference time to the transmission time initialization manager. It is characterized by

In one embodiment, the transmission time initialization manager generates first and second initialization check signals under the control of the response time checker, and directly transmits the first initialization check signal to the multi-channel without going through the transmission time setting device. At the same time as transmitting to each of the multi-channels, a second initialization check signal is transmitted to each of the multi-channels through the transmission time setting device.

In one embodiment, the transmission time initialization manager is characterized in that it resets the network transmission time for the channel in which the initialization difference time occurs among the initialization difference times notified from the response difference calculator.

In one embodiment, the interface unit is provided with an I2C interface to set the operation mode of the ADC, check over-flow, enter the power-down mode, and set the registers necessary for mute control through the I2C interface, and the main board and an audio interface that interfaces through 26 pins and 18 pins, respectively, in the case of the interface of the audio input/output board; And for physical network interface, an RJ45 jack with a built-in Ethernet PHY chip and magnetic transformer is used. The Ethernet PHY chip supports Ethernet speeds of 10/100/1000Mbps and connects to MAC through RGMII. In the case of the RGMII signal line, it is designed to have an impedance of 50 ohms, and in the case of the signal line connection between the PHY and RJ45 jack, it is designed to have an impedance of 100 ohms. In the case of the Ethernet MAC and PHY, the internal register of the PHY IC is connected through the SMI interface. It is characterized by having a network interface that sets the operating environment for speed, auto-negotiation settings, and low-power operation.

In one embodiment, the audio input/output board is characterized by adding -12Vdc and +12Vdc power necessary for the operation of the op-amp of the +48V dc power ADC input buffer circuit for supplying power to the condenser microphone in the case of the audio input board. Do it as

The effect of the present invention is to provide a multi-channel audio signal transmission system and method that enables multi-channel real-time network audio transmission by applying AVB (audio video bridging), a standardized audio and video transmission standard, thereby enabling AVB. By applying it, it increases compatibility regardless of the type of system or device the user uses, enables two-way network audio transmission capable of multi-channel transmission, and uses AVB's time synchronization technology to enable low-latency real-time transmission of less than 2ms. The quality of transmission data is guaranteed, the installation structure is simple, enabling efficient use of surrounding space, and installation costs can be reduced.

1 is a diagram illustrating a multi-channel audio signal transmission system according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the processor unit in FIG. 1 as a first example.
FIG. 3 is a diagram illustrating the processor unit in FIG. 1 as a second example.
FIG. 4 is a diagram illustrating the processor unit in FIG. 1 as a third example.
FIG. 5 is a diagram illustrating transmission of the first and second initialization check signals of the transmission time initialization manager in FIG. 4.
Figure 6 is a diagram illustrating the operation of a multi-channel audio signal transmission system according to an embodiment of the present invention.

Below, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. However, since the description of the present invention is only an example for structural and functional explanation, the scope of the present invention should not be construed as limited by the examples described in the text. In other words, since the embodiments can be modified in various ways and can take various forms, the scope of rights of the present invention should be understood to include equivalents that can realize the technical idea. In addition, the purpose or effect presented in the present invention does not mean that a specific embodiment must include all or only such effects, so the scope of the present invention should not be understood as limited thereby.

The meaning of terms described in the present invention should be understood as follows.

Terms such as “first” and “second” are used to distinguish one component from another component, and the scope of rights should not be limited by these terms. For example, a first component may be named a second component, and similarly, the second component may also be named a first component. When a component is referred to as being “connected” to another component, it should be understood that it may be directly connected to the other component, but that other components may also exist in between. On the other hand, when a component is referred to as being “directly connected” to another component, it should be understood that there are no other components in between. Meanwhile, other expressions that describe the relationship between components, such as "between" and "immediately between" or "neighboring" and "directly neighboring" should be interpreted similarly.

Singular expressions should be understood to include plural expressions, unless the context clearly indicates otherwise, and terms such as “comprise” or “have” refer to the specified features, numbers, steps, operations, components, parts, or them. It is intended to specify the existence of a combination, and should be understood as not excluding in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

All terms used herein, unless otherwise defined, have the same meaning as commonly understood by a person of ordinary skill in the field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as consistent with the meaning they have in the context of the related technology, and cannot be interpreted as having an ideal or excessively formal meaning unless clearly defined in the present invention.

Now, a multi-channel audio signal transmission system according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram illustrating a multi-channel audio signal transmission system according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the processor unit in FIG. 1 as a first example, and FIG. 3 is a diagram illustrating the processor unit in FIG. 1 as a second example. This is a diagram explaining the example, and FIG. 4 is a diagram explaining the processor unit in FIG. 1 as a third example, and FIG. 5 is a diagram explaining the transmission of the first and second initialization check signals of the transmission time initialization manager in FIG. 4.

1 to 5, the multi-channel audio signal transmission system 10 includes a main board 100 and an audio input/output board 200; The main board 100 includes a clock generator 110, a processor 120, and an interface 130.

The main board 100 may further include a power supply unit.

The power supply unit provides a DC voltage of power (e.g., +3.3V, +2.5V, +1.0V) to be provided to the multi-core processor, serial flash memory, and processor core provided inside the main board 100. It can be supplied as +5Vdc from SMPS and supplied as a step-down output from a switching regulator in PWM mode of 1.5A, 1.5MHz.

In one embodiment, the power supply unit may supply +12 or -12V DC voltage to the operational amplifier (OP Amp.) of the analog part of the audio input/output board 200.

The clock generator 110 generates a clock signal based on the frequency control signal input from the processor unit 120 and transmits it to the processor unit 120.

In one embodiment, the clock generator 110 receives an analog waveform signal and compares the frequency converted to a digital signal with the frequency multiplied by digital logic by the frequency control signal of the processor unit 120 to determine the frequency in the system. A clock signal can be generated using a digital frequency adjustment method that adjusts and outputs the desired clock frequency.

In one embodiment, the clock generator 110 can generate a clock signal necessary for each part of the system, and in the case of a low-jitter clock signal with little waveform deformation, a frequency multiplication PLL (phase lock loop) can be generated by an integrated circuit (IC), and the generated low-jitter 24MHz signal can be supplied as the main clock of the processor unit 120.

In one embodiment, the clock generator 110 includes an analog to digital converter (ADC) and a digital to analog converter (DAC) that operate at a sampling rate of 48 KHz in the case of the generated low-jitter 24 MHz signal. It can be input as the reference clock of another PLL IC (for example, CS2100) that supplies the MCLK (memory clock) signal.

The processor unit 120 generates a frequency control signal and inputs it to the clock generator 110, and generates a drive control signal according to the clock signal transmitted from the clock generator 110 and inputs it to the interface unit 130. It controls real-time network transmission of audio signals to multiple channels of the audio input/output board 200 by applying AVB (audio video bridging), a standardized audio and video transmission standard.

In one embodiment, the processor unit 120 includes a multi-core processor with at least two tiles having at least two cores, and performs various functions such as input/output, signal processing, user program execution, etc. It can perform multitasking and can run a hardware-like real time operating system (RTOS).

In one embodiment, the processor unit 120 has eight cores built in for each tile, and is designed with an internal memory sharing structure so that each core can access common memory, thereby preventing data loss. It can maintain a processing speed of 2,000 MIPS (million instructions per second), supports USB or gigabit ethernet, and also uses the I2C interface of the interface unit 130 for analog audio input and output. Through this, programming for ADC and DAC control and LED display control operations can be provided, and it can be responsible for controlling the chip designed on the audio input/output board 200.

In one embodiment, the processor unit 120 controls the network transmission of audio signals in real time by applying AVB, a standardized audio and video transmission standard, but does not control the status or status of each multi-channel of the audio input/output board 200. Since differences may occur in network transmission speed depending on the network transmission environment such as the status of each receiver, for more effective real-time network transmission synchronization, as shown in FIG. 2, a synchronization check signal generator 121 and a check response signal It may include a receiver 122, a response time checker 123, a response difference calculator 124, and a transmission time setter 125.

The synchronization check signal generator 121 generates a synchronization check signal under the control of the response time checker 123 and transmits it to each of the multiple channels of the audio input/output board 200.

In one embodiment, the synchronization check signal generator 121 can directly transmit the synchronization check signal to each of the multiple channels of the audio input/output board 200 without going through the transmission time setting device 125.

The check response signal receiver 122 receives synchronization check response signals transmitted from each multi-channel receiver under the control of the response time checker 123, and sends the synchronization response of each channel to the response time checker 123. Notify me. Here, each receiver receives the synchronization check signal transmitted from the synchronization check signal generator 121, processes the signal, and then generates a synchronization check response signal as a corresponding synchronization response and sends the synchronization check signal to the check response signal receiver 122. I can send it to you.

The response time checker 123 controls the operation of the synchronization check signal generator 121 and the check response signal receiver 122, and receives synchronization responses for each channel from the check response signal receiver 122 to synchronize each channel. The response time is checked and notified to the response difference calculator (124).

In one embodiment, the response time checker 123 may control the operations of the synchronization check signal generator 121 and the check response signal receiver 122 when performing an initial operation, upon resetting, or at preset intervals.

In one embodiment, the response time checker 123, for example, when there are four multiple channels, the synchronization response time of the first channel is 2 ms, the synchronization response time of the second channel is 1.9 ms, and the synchronization response time of the third channel is 2 ms. It can be seen that the synchronization response time of the channel is 1.8ms, and the synchronization response time of the fourth channel is 1.6ms.

The response difference calculator 124 checks the latest synchronization response time among the synchronization response times of each channel notified by the response time checker 123, and determines the synchronization response time of each channel based on the confirmed latest synchronization response time. The difference time is calculated and notified to the transmission time setting device (125).

In one embodiment, the response difference calculator 124 determines the first channel synchronization response time of 2 ms, the second channel synchronization response time of 1.9 ms, and the third channel synchronization response time of 1.8 ms notified from the response time checker 123. Time, you can check the 4th channel synchronization response time of 1.6ms, and you can also check the 1st channel synchronization response time of 2ms, which is the latest synchronization response time among the confirmed synchronization response times. Based on the synchronization response time, the difference time from the synchronization response time of each channel, which is 0ms, 0.1ms, 0.2ms, and 0.4ms, can be calculated respectively.

The transmission time setter 125 delays each audio signal by the synchronization difference time notified by the response difference calculator 124 and sets the network transmission time for the multiple channels of the audio input/output board 200 to transmit it over the network. .

In one embodiment, the transmission time setter 125 delays the audio signal by the synchronization difference time of 0 ms, 0.1 ms, 0.2 ms, and 0.4 ms notified from the response difference calculator 124, and delays the audio signal for network transmission. You can set each network transmission time.

The processor unit 120 with the above-described configuration is configured to replace the corresponding channel by checking if there is no response from the receiver or the response time is slow due to an error on the channel despite real-time network transmission synchronization, as shown in FIG. 3. As shown, an error notification view 126 may be further included.

In one embodiment, the response time checker 123 is notified of the synchronization response of each channel from the check response signal receiver 122, and the confirmed synchronization response time is equal to the preset synchronization error time (for example, 2.1 ms). It is possible to check whether any channels have elapsed, and if any channels have elapsed the preset synchronization error time, this can be notified to the error notification viewer 126.

The error notification viewer 126 is notified of the channel that has elapsed the preset synchronization error time from the response time checker 123 and notifies the operator or manager of the channel in which the synchronization error occurred, allowing the corresponding channel to be replaced. there is.

The processor unit 120 having the above-described configuration may further include a transmission time initialization manager 127, as shown in FIG. 4, for more accurate real-time network transmission synchronization.

In one embodiment, the check response signal receiver 122 receives the first initialization check response signal transmitted from each receiver of multiple channels under the control of the response time checker 123 and receives the first initialization response signal of each channel. Notifies the response time checker 123, and simultaneously receives the second initialization check response signal transmitted from each multi-channel receiver and reports the second initialization response of each channel to the response time checker 123. I will do it. Here, each receiver receives the first initialization check signal (rc1-1, rc1-2, rc1-3, rc1-4) transmitted from the transmission time initialization manager 127, processes the signal, and then sends the corresponding signal. In response to the first initialization, the first initialization check response signal is generated and transmitted to the check response signal receiver 122, and at the same time, the second initialization check signal (rc2-1, rc2) transmitted from the transmission time initialization manager 127 is generated. -2, rc2-3, rc2-4) are respectively received and signal processed, and then a second initialization check response signal can be generated as a second initialization response corresponding thereto and transmitted to the check response signal receiver 122, respectively. there is.

In one embodiment, the response time checker 123 can control the operation of the transmission time initialization manager 127 when performing the first operation or upon reset, and performs the first initialization of each channel from the check response signal receiver 122. Upon receiving the response, the first initialization response time of each channel is checked and notified to the response difference calculator 124. At the same time, the second initialization response of each channel is notified from the check response signal receiver 122, and the first initialization response time of each channel is confirmed. 2The initialization response time can be checked and notified to the response difference calculator 124.

In one embodiment, the response time checker 123 determines that, for example, when there are four multiple channels, the first initialization response time of the first channel is 2 ms, and the first initialization response time of the second channel is 1.9 ms. , and confirm that the first initialization response time of the third channel is 1.8 ms and the first initialization response time of the fourth channel is 1.8 ms, and the second initialization response time of the first channel is 2 ms, and the second channel It can be seen that the second initialization response time of is 1.9 ms, the second initialization response time of the third channel is 1.8 ms, and the second initialization response time of the fourth channel is 1.6 ms.

In one embodiment, the response difference calculator 124 calculates the difference time between the first initialization response time and the second initialization response time of each channel notified from the response time checker 123 and transmits the transmission time initialization manager 127. ) can be notified.

In one embodiment, the response difference calculator 124 uses the first channel first initialization response time of 2 ms, the second channel first initialization response time of 1.9 ms, and the first initialization response time of 1.8 ms notified from the response time checker 123. Confirming the 3-channel first initialization response time and the 4th channel first initialization response time of 1.8 ms, the first channel 2nd initialization response time of 2 ms and the 1.9 ms first initialization response time notified from the response time checker 123 You can check the 2nd channel 2nd initialization response time, the 3rd channel 2nd initialization response time of 1.8ms, and the 4th channel 2nd initialization response time of 1.6ms, and also the 1st initialization response time and 2nd initialization response of each channel. The difference times between times, 0ms, 0ms, 0ms, and 0.2ms, can be calculated respectively.

The transmission time initialization manager 127 initializes the network transmission time for each channel of the transmission time setting device 125 under the control of the response time checker 123.

In one embodiment, the transmission time initialization manager 127 generates the first and second initialization check signals under the control of the response time checker 123, as shown in FIG. 5, for example, multi-channel In the case of these four, the first initialization check signal (rc1-1, rc1-2, rc1-3, rc1-4) is sent directly to each of the multi-channels of the audio input/output board 200 without going through the transmission time setting device 125. At the same time as transmitting, the second initialization check signal (rc2-1, rc2-2, rc2-3, rc2-4) is transmitted to each of the multi-channels of the audio input/output board 200 through the transmission time setting device 125. I can give it.

In one embodiment, the transmission time initialization manager 127 transmits the initialization difference time to the channel (for example, the fourth channel) where the initialization difference time occurred among the initialization difference times of 0 ms, 0 ms, 0 ms, and 0.2 ms notified from the response difference calculator 124. You can reset the network transmission time for

The interface unit 130 performs an interface with the audio input/output board unit 200 and a network interface according to a driving control signal input from the processor unit 120.

In one embodiment, the interface unit 130 may include an audio interface and a network interface.

The audio interface is equipped with an I2C interface, and register settings required for ADC operation mode setting, over-flow check, power down mode entry, and mute control are performed through the corresponding I2C interface. In addition, in the case of the interface between the main board 100 and the audio input/output board 200, the interface can be performed through 26 pins and 18 pins, respectively.

The network interface can use an Ethernet PHY chip and an RJ45 jack with a built-in magnetic transformer to serve as a physical network interface. The Ethernet PHY chip can support Ethernet speeds of 10/100/1000Mbps. It can be connected to MAC (media access control) through RGMII (reduced gigabit media independent interface). The signal line of RGMII must have an impedance of 50 ohm, and the signal line connection between PHY and RJ45 jack is required. In this case, it can be designed to have an impedance of 100 ohm, and in the case of Ethernet MAC and PHY, the internal register of the PHY IC can be set through the SMI interface to set the speed, auto-negotiation, You can set operating environments such as low power operation.

The audio input/output board 200 has an audio input channel formed of at least two or more multi-channels and an audio output channel formed of at least two or more multi-channels, and inputs and outputs audio signals under the control of the processor unit 120. I will do it.

In one embodiment, the audio input/output board 200 adds -12Vdc and +12Vdc power required for the operation of the op amp of the +48V dc power ADC input buffer circuit for supplying power to the condenser microphone in the case of the audio input board. You can.

The multi-channel audio signal transmission system 100 having the above-described configuration enables multi-channel real-time network audio transmission by applying AVB, a standardized audio and video transmission standard, so that users can use AVB by applying AVB. It increases compatibility regardless of the type of system or device, enables two-way network audio transmission capable of multi-channel transmission, and utilizes AVB's time synchronization technology to enable low-latency real-time transmission of less than 2ms, and Quality is guaranteed, and the simple installation structure allows efficient use of surrounding space and reduces installation costs.

The multi-channel audio signal transmission system 100 having the above-described configuration includes an Ethernet pie interface, a precision timing protocol (PTP) engine, an audio streaming component, and a media clock in the design of the software and protocol of the processor unit 120. AVB endpoint software including a server may be provided.

The Ethernet MAC component allows the AVB terminal to be connected to Ethernet, and can form a GMII interface inside the processor unit 120 to connect to 1Gbps Ethernet, and a timestamp containing time information of the reference clock in the Ethernet frame. (time-stamp) packets can be transmitted and received, and in order to smoothly transmit media signals such as audio and video, priority and transmission bandwidth limitation information specified in the IEEE 802.1Qav technical standard can be included in different transmission channels.

The AVB protocol stack can include an audio packet in a format defined in the IEEE 1722 packet structure in the transmitter MAC component and transmit it to a receiver (eg, Listener).

The PTP protocol component provides accurate reference time information to each system in the network and ensures the timing synchronization necessary for the expression and playback of media signals transmitted through the network. At this time, the time information component is connected to the Ethernet MAC component and allows the receiver to extract time information from data transmitted through the network. It also interprets the PTP packet information transmitted through the MAC component to obtain standard time information. can help you maintain it.

The PTP components of nodes connected on the network become PTP grand-masters or PTP slaves, and the grant-master provides source clock information to the network. Additionally, the side receiving the reference time information can maintain accurate timing information by comparing and correcting the local clock data and the reference time information.

Audio signals transmitted through a network include multiple audio channels in each transmission stream, and are given a unique 64-bit stream ID. At this time, the endpoint can be a transmitter (eg, Talker) or a receiver (eg, listener), and can implement both functions at the same time. Each transport stream includes a unique transmission MAC address and a reception address, and multicast address transmission is also possible, allowing reception by multiple receivers.

Switches on the AVB network store path information between terminals and can secure transmission bandwidth to ensure stream transmission. And each stream is encoded by the 1722 AVB transmission protocol, and all channel data constituting the stream can be synchronized to the same sample clock.

The clock information of the audio signal transmitted to the AVB network can be adjusted to the clock signal input to the port for synchronization with other devices connected to the network, the timing information included in the stream encoded by the 1722 protocol, or the reference PTP clock signal. there is. And all media clock signals are maintained by the clock server component inside the system, and information about changes in the clock signal can be periodically updated to maintain system synchronization.

The media clock server component can ensure that accurate media data is played by extracting timing information included in the input 1722 stream. In addition, the high-quality clock signal with little waveform deformation used in the audio codec, which is a system hardware component, is not generated by the processor unit 120 itself but is generated by an external phase-locked loop (PLL), and is generated by the processor unit 120. ), the frequency can be adjusted by controlling the distribution ratio inside the PLL.

AVB endpoint components can apply a time division multiplexing (TDM) interface to transmit audio signals. The TDM interface can transmit multiple audio channel data on one line, simplifying system design, and TDM is a protocol that can transmit multiple signals multiplexed on one line, and the TDM protocol signal line uses BCLK, a bit clock signal generated by an external oscillator, FYUNC, a transmission data frame synchronization signal line, and DATA, a transmission data line. Includes. The DATA line outputs data from a processor that performs master duties or a codec IC that acts as a slave, depending on the data transmission direction. In addition, the TDM signal includes CHANNELS_PER_FRAME, which is the number of audio channels that can be multiplexed in one frame and transmitted on the data line, FYSNC_OFFSET, which is the number of bits between the transition state of the frame synchronization signal and the data transmitted on the signal line, and the transmission start state of the transmission frame. It can be operated by the program parameter of FYSNC_LENGTH, which is the number of bits of the frame synchronization signal while maintaining the high state.

While the FSYNC signal remains high, transmission begins from the most significant bit (MSB), the highest bit of data, after a delay equal to FSYNC_OFFSET. One channel has 32 bits of data, and transmission starts from channel 0. Transmission takes place as many channels as the number of channels that make up the frame. The speed and number of channels of the TDM interface that can be transmitted through the data line are, in the case of 12.288MHz BLCK frequency, Channel No, Per FRAME is 8, sample frequency is 48000Hz, input (number of channels) is 2 (16), The output (number of channels) is 2 (16), in the case of 6.144MHz BLCK frequency, Channel No, Per FRAME is 4, the sample frequency is 48000Hz, the input (number of channels) is 4 (16), and the output (number of channels) is 4 (16). ) is 4(16).

As an AVB endpoint software component, a program for transmitting multiple audio channel data using the standard AVB protocol using a multi-core processor over Ethernet includes a 10/100/1000Mbps Ethernet MAC, 1722 61883-6 audio transmitter, and Receiver configuration, TDM master interface supporting 32-channel audio input and output with 24bit 48KHz sampling rate, 1722 MAAP protocol capable of receiving information containing multicast MAC addresses and extracting address data, 802.1 Q MRP, MVRP, MSRP protocol, gPTP management It may include components and protocols, such as interfaces for audio clock reproduction and PLL clock generation, and the 1722.1 AVDECC protocol.

The multi-core processor consists of program components that can process tasks such as multi-channel audio interface, AVB protocol, time information processing, Ethernet MAC address filtering, Ethernet packet processing, PHY chip driver, interface and control in parallel.

The TDM master component performs TDM audio interface operations, and the audio buffer manager is called from the TDM master to initialize the audio codec IC and PLL block outside the processor unit 120 and through GPIO tasks. You can initialize the system and clock frequency.

The audio input sample buffer task is an element that manages the audio buffer with a dual storage structure in the memory area shared by the audio buffer manager task and the 1722 transmitter task, and provides information on input and output of audio data, TDM handler, and empty buffer. information is exchanged.

The audio output sample buffer task performs a first in first out (FIFO) operation on audio sample data in the shared memory area. The 1722 transmitter converts the audio data input to the buffer memory into a stream in the 1722 protocol format with a packet structure with display time information and stream ID, and sends the data to the Ethernet MAC so that it can be transmitted through the network. . And, for the 1722 stream packet data received through the Ethernet MAC, audio sample data is extracted from the packet format data by the 1722 receiver, temporarily stored in the audio output FIFO buffer, and media display time information and audio clock frequency are reproduced.

The gPTP and media clock server task maintains the system's standard time information and reproduces the clock signal by synchronizing the frequency and phase of the audio clock to the network audio clock master.

1722.1 MAAP (multicast address allocation protocol) and SRP (stream reservation protocol) tasks are protocol stacks required for AVB endpoint control and transmission bandwidth reservation.

The AVB master task sets up the above-mentioned program execution elements and coordinates communication between each component.

When executing the AVB endpoint program, the multi-channel audio signal transmission system 100 having the above-described configuration creates the avb_conf.h file and sets various parameters required by the AVB endpoint through the #define preprocessor. It is defined and can be reset to suit the configuration hardware environment of the endpoint. The processor of the AVB endpoint has ports responsible for several external interfaces, and these ports are used in the processor unit (processor unit) by creating a main.xc file. 120) can be defined and used on each physical pin, and can be defined and used as a port for other functions as needed. In the main function, the interface and components of each task are set, and each task has defined variables. It can be designed to transmit parameter values required for program execution.

The tasks required for Ethernet MAC operation inside the processor unit 120 set the environment required for MAC operation and are configured to be externally interfaced through the RGMII port, and rgmii_ethernet_mac_config, smitask, and ar8035_phy_driver are one of the tasks inside the processor unit 120. Make it work on the core. ar8035_phy_driver defines the execution conditions required for operation in the user application, and is newly defined and used according to the PHY chip designed in the endpoint system. The first execution function generates a 1000ms pulse signal that resets the Ethernet PHY chip. do. Set the MAC operating environment to have a delay time in nanoseconds for data input and output through the Ethernet PHY interface. This delay time is a value based on the maintenance, modification, and exchange of time information that each node constituting the AVB network defined in the IEEE802.1AS technical standard must have. In addition, the delay time changes depending on the network transmission speed, so parameter values for speed can be provided, and the setting value can be changed depending on the PHY chip used.

The smi_phy_is_powered_down function waits until power is supplied to the PHY chip before performing a data read or write operation on the MDIO (management data input/output) register. When power is supplied, the PHY chip is activated through the register interface of SMI (serial management interface). Set the operating environment. For AVB networking operation, auto-negotiation (auto-negotiation) does not drive the power consumption efficiency state, which is one of the operating states of the PHY chip, and automatically sets the speed and network connection status of the PHY chip by the smi_configuration function. negotiation) Configure parameters. When the network is connected, the speed of the network connection link is periodically checked through a polling operation using the smi_get_link_state function, and the network connection speed is checked by referring to the special register value inside the PHY chip. When there is a change in link speed, the speed change is notified to the AVB protocol stack through MAC.

The interior of the multi-core processor of the processor unit 120 is divided into tile 0 and tile 1, and each tile is composed of a total of 8 cores, so that tasks for executing programs are processed in parallel. Tile 0 runs components responsible for AVB endpoint functions other than Ethernet network operation. The I2C bus is used to configure the audio codec and PLL of the multi-channel audio endpoint system, and the I2C clock and data pins are interfaced using the processor's 4-bit port. Settings for port configuration, bus speed (100Kbps), and clock and data bit positions are initialized by i2c_master_single_port.

The output GPIO function can enable the multi-bit port to operate as ADC, DAC reset, and various other additional functions through the xC interface inside the processor unit 120. The TDM interface, which is a digital audio data transmission method, is initialized from the lib_i2s library, and the master clock signal input from the PLL has the input frequency value divided by 1/2 by the clock generator 110 inside the main board 100 to create the TDM interface. It is set to operate as a motion and audio bit clock. In order to manage the buffering operation of audio signals input and output through the TDM interface, the tdm_master task is interconnected with the buffer_manager_to_tdm task defined in the user application, and the connection of functions required by each program is called from the tdm_master task to the application program. It works. Operations such as ADC and DAC initialization, audio data transmission and reception, etc. are called.

Setting up the hardware environment required for audio transmission for network transmission begins with a function call to initialize the TDM interface. At this time, task settings required for driving the audio hardware and audio data buffering operations are set, as well as setting the audio hardware clock and the codec chip. Set the operating environment through GPIO and I2C interface.

Transmission and reception of audio data through the TDM interface is accomplished by receiving or passing audio sample data from the audio buffer manager task. Data input to the audio buffer is stored in an array structure in the audio_frame_t structure, and when the last audio sample of the transmission frame is input, the channel is exchanged to an unused buffer by the buffer manager task.

All devices on an Ethernet network require a unique Ethernet MAC address for device identification, and AVB endpoints also use the MAC address specified by IEEE by storing it in the board's OTP (one time programming) memory. The saved MAC address can be read through the lib_otpinfo library, and the address can also be set through the set_macaddr interface function. Initialization of the endpoint's AVB protocol stack is performed by the control task of the application program through the AVB API (application programming interface), and is also operated by calling the control callback function through the 1722.1 protocol. Media clock settings required to drive audio hardware are first accomplished by setting the sample rate of 48kHz and the type of INPUT_STREAM_DERIVED. This refers to operating as a slave audio clock synchronized to the audio clock master, and expresses that the clock signal is extracted from the received audio stream data.

On an AVB network, the device that generates audio data is called a transmitter (e.g., Talker), and the device that receives and plays data is called a receiver (e.g., Listener). The transmitter and receiver connected to the network can send and receive a total of four streams. One stream consists of 8 audio channels and is transmitted in 24bit MBLA (multi bit linear audio) format.

Each device (node) in the AVB network has a built-in IEEE 1722.1 protocol that identifies the AVB network and manages and controls connections between devices, so it is connected to the AVB network and performs related operations by interpreting various command parameters sent through the protocol. will be performed. For example, if the transmitted protocol stack includes the SET_CONTROL command code, the application program of the processor unit 120 interprets this command, performs an appropriate operation, and then notifies the application that modification of the required parameter field has been completed. The given action is completed.

Figure 6 is a diagram explaining the operation of a multi-channel audio signal transmission system according to an embodiment of the present invention.

Referring to FIG. 6, first, the power supply unit provided on the main board 100 provides power (e.g., +3.3V) to be provided to the multi-core processor, serial flash memory, and processor core provided inside the main board 100. , +2.5V, +1.0V) DC voltage is supplied as +5Vdc from the manufactured SMPS and step-down at the switching regulator in PWM mode of 1.5A, 1.5MHz. It is supplied as output. Additionally, in the case of +12, -12V DC voltage, the power supply unit supplies it to the operational amplifier (OP Amp.) of the analog part of the audio input/output board 200.

The processor unit 120 generates a frequency control signal and inputs it to the clock generator 110 (S601).

When the frequency control signal is input in step S601 described above, the clock generator 110 generates a clock signal based on the frequency control signal input from the processor unit 120 and transmits it to the processor unit 120 (S602) ).

In transmitting the clock signal in the above-described step S602, the clock generator 110 receives the analog waveform signal and multiplies the frequency converted into a digital signal by digital logic by the frequency control signal of the processor unit 120. A clock signal can be generated using a digital frequency adjustment method that adjusts and outputs the desired clock frequency in the system by comparing it to the specified frequency.

In transmitting the clock signal in the above-described step S602, the clock generator 110 can generate the clock signal necessary for each part of the system and generates a low-jitter clock with almost no waveform deformation. In the case of the signal, it can be generated by a frequency multiplier PLL IC, and in the case of the generated low-jitter 24MHz signal, it can be supplied as the main clock of the processor unit 120.

In transmitting the clock signal in step S602 described above, the clock generator 110 includes an analog to digital converter (ADC) operating at a sampling rate of 48 KHz in the case of the generated low-jitter 24 MHz signal, and It can also be input as the reference clock of another PLL IC (e.g. CS2100) that supplies the MCLK signal to a DAC (digital to analog converter).

When the clock signal is transmitted in step S602 described above, the processor unit 120 generates a drive control signal according to the clock signal transmitted from the clock generator 110 and inputs it to the interface unit 130, and provides a standardized AVB (audio video bridging), an audio and video transmission standard, is applied to control real-time network transmission of audio signals to multiple channels of the audio input/output board 200 (S603).

In performing real-time network transmission control in the above-described step S603, the processor unit 120 having a multi-core processor with at least two tiles containing at least two cores, It can perform multitasking such as input/output, signal processing, and user program execution, and can perform a hardware-like real time operating system (RTOS).

In performing real-time network transmission control in step S603 described above, the processor unit 120 has eight cores built into each tile and is designed with an internal memory sharing structure so that each core can access common memory. Therefore, it can prevent data loss, maintain a processing speed of 2,000 MIPS (million instructions per second), support USB or gigabit ethernet, and provide analog audio input and output. Programming for ADC and DAC control and LED display control operations can be provided through the I2C interface of the interface unit 130, and can be responsible for controlling the chip designed in the audio input/output board 200.

In performing the real-time network transmission control in the above-described step S603, although the audio signal is controlled to be transmitted over the network in real time by applying AVB, a standardized audio and video transmission standard, each of the multi-channels of the audio input/output board 200 Differences in network transmission speed may occur depending on the network transmission environment, such as the state or the state of each receiver, so for more effective real-time network transmission synchronization, the response time checker 123 provided in the processor unit 120 , the operation of the synchronization check signal generator 121 and the check response signal receiver 122 provided in the processor unit 120 is controlled. Accordingly, the synchronization check signal generator 121 generates a synchronization check signal under the control of the response time checker 123 and transmits it to each of the multiple channels of the audio input/output board 200. At this time, the synchronization check signal generator 121 can directly transmit the synchronization check signal to each of the multiple channels of the audio input/output board 200 without going through the transmission time setting device 125.

In performing real-time network transmission control in the above-described step S603, each multi-channel receiver receives the synchronization check signal transmitted from the synchronization check signal generator 121, processes the synchronization check signal, and then checks the synchronization with the corresponding synchronization response. Each response signal can be generated and transmitted to the check response signal receiver 122. Accordingly, the check response signal receiver 122 receives the synchronization check response signal transmitted from each multi-channel receiver under the control of the response time checker 123 and sends the synchronization response of each channel to the response time checker 123. ) will be notified.

In performing real-time network transmission control in the above-described step S603, the response time checker 123 receives synchronization response of each channel from the check response signal receiver 122, checks the synchronization response time of each channel, and checks the synchronization response time of each channel. This is notified to the response difference calculator (124) provided at (120). Accordingly, the response difference calculator 124 checks the latest synchronization response time among the synchronization response times of each channel notified by the response time checker 123, and synchronizes each channel based on the confirmed latest synchronization response time. The difference time from the response time is calculated and notified to the transmission time setting device 125 provided in the processor unit 120. Then, the transmission time setter 125 sets the network transmission times for the multiple channels of the audio input/output board 200 to delay each audio signal by the synchronization difference time notified by the response difference calculator 124 and transmit it over the network. Let me do it.

In performing real-time network transmission control in the above-described step S603, the response time checker 123 uses the synchronization check signal generator 121 and the check response signal receiver 122 when performing the first operation, upon reset, or at each preset period. The operation of can be controlled, and for example, in the case of 4 multiple channels, the synchronization response time of the first channel is 2 ms, the synchronization response time of the second channel is 1.9 ms, and the synchronization response time of the third channel is 1.9 ms. It can be confirmed that this is 1.8ms, and the synchronization response time of the fourth channel is 1.6ms. Accordingly, in the response difference calculator 124, the first channel synchronization response time of 2 ms, the second channel synchronization response time of 1.9 ms, and the third channel synchronization response time of 1.8 ms notified from the response time checker 123, You can check the 4th channel synchronization response time of 1.6ms, and you can also check the 1st channel synchronization response time of 2ms, which is the latest synchronization response time among the confirmed synchronization response times. Based on time, the difference time from the synchronization response time of each channel, which is 0ms, 0.1ms, 0.2ms, and 0.4ms, can be calculated respectively. Then, the transmission time setter 125 delays the audio signal by the synchronization difference time of 0 ms, 0.1 ms, 0.2 ms, and 0.4 ms notified from the response difference calculator 124, and sets the network transmission time for each channel to be transmitted over the network. You can set each.

When performing real-time network transmission control in the above-described step S603, in order to check if there is no response from the receiver or the response time is slow due to an error on the channel despite real-time network transmission synchronization, and replace the corresponding channel, the response The time checker 123 receives the synchronization response of each channel from the check response signal receiver 122 and determines whether there is a channel whose confirmed synchronization response time has elapsed the preset synchronization error time (for example, 2.1 ms). Check, and if there is a channel that has elapsed the preset synchronization error time, this can be notified to the error notification viewer 126 provided in the processor unit 120. Accordingly, the error notification unit 126 receives notification of channels that have elapsed the preset synchronization error time from the response time checker 123 and notifies the operator or manager of the channel on which the synchronization error occurred, so that the corresponding channel can be replaced. I can do it for you.

When performing real-time network transmission control in the above-described step S603, for more accurate real-time network transmission synchronization, the response time checker 123 determines the transmission time provided in the processor unit 120 when performing the first operation or upon resetting. The operation of the initialization manager 127 can be controlled. Accordingly, the transmission time initialization manager 127 initializes the network transmission time for each channel of the transmission time setting device 125 under the control of the response time checker 123.

When performing real-time network transmission control in the above-described step S603, for more accurate real-time network transmission synchronization, the transmission time initialization manager 127 performs first and second initialization checks under the control of the response time checker 123. By generating a signal, as shown in FIG. 5, for example, in the case of 4 multi-channels, the first initialization check signal (rc1-1, rc1-2, rc1-3, rc1-4) is transmitted to the transmission time setter. It transmits directly to each of the multiple channels of the audio input/output board 200 without going through (125), and at the same time, the second initialization check signal (rc2-1, rc2-2, rc2-3, rc2-4) is transmitted through a transmission time setter. It can be transmitted to each of the multiple channels of the audio input/output board 200 via (125). Accordingly, each multi-channel receiver receives the first initialization check signal (rc1-1, rc1-2, rc1-3, rc1-4) transmitted from the transmission time initialization manager 127, processes the signal, and then The first initialization check response signal is generated as a corresponding first initialization response and transmitted to the check response signal receiver 122, and at the same time, the second initialization check signal (rc2-) transmitted from the transmission time initialization manager 127 is generated. 1, rc2-2, rc2-3, and rc2-4) are respectively received and signal processed, and then a second initialization check response signal is generated as a corresponding second initialization response and transmitted to the check response signal receiver 122, respectively. I can do it for you. Then, the check response signal receiver 122 receives the first initialization check response signal transmitted from each multi-channel receiver under the control of the response time checker 123 and converts the first initialization response of each channel into the response time. At the same time as notifying the checker 123, the second initialization check response signal transmitted from each multi-channel receiver is received, and the second initialization response of each channel is notified to the response time checker 123. Accordingly, the response time checker 123 receives the first initialization response of each channel from the check response signal receiver 122, checks the first initialization response time of each channel, and reports it to the response difference calculator 124. At the same time as zooming, the second initialization response of each channel is notified from the check response signal receiver 122, and the second initialization response time of each channel can be checked and reported to the response difference calculator 124. At this time, the response difference calculator 124 calculates the difference time between the first initialization response time and the second initialization response time of each channel notified from the response time checker 123 and reports it to the transmission time initialization manager 127. I can do it for you.

When performing real-time network transmission control in the above-described step S603, for more accurate real-time network transmission synchronization, for example, when there are four multiple channels, the response time checker 123 performs a first initialization of the first channel. Confirm that the response time is 2ms, the first initialization response time of the second channel is 1.9ms, the first initialization response time of the third channel is 1.8ms, and the first initialization response time of the fourth channel is 1.8ms; At the same time, the second initialization response time of the first channel is 2 ms, the second initialization response time of the second channel is 1.9 ms, the second initialization response time of the third channel is 1.8 ms, and the second initialization response time of the fourth channel is 1.8 ms. You can see that the response time is 1.6ms. Accordingly, in the response difference calculator 124, the first channel first initialization response time of 2 ms, the second channel first initialization response time of 1.9 ms, and the third channel first initialization response time of 1.8 ms notified from the response time checker 123. At the same time as checking the 1st initialization response time and the 4th channel 1st initialization response time of 1.8ms, the 1st channel 2nd initialization response time of 2ms and the 2nd channel 1st channel of 1.9ms are notified from the response time checker 123. You can check the 2nd initialization response time, the 3rd channel 2nd initialization response time of 1.8ms, and the 4th channel 2nd initialization response time of 1.6ms, and also the difference between the 1st initialization response time and the 2nd initialization response time of each channel. The times 0ms, 0ms, 0ms, and 0.2ms can be calculated respectively. Then, the transmission time initialization manager 127 performs network transmission for the channel (e.g., the fourth channel) where the initialization difference time occurred among the initialization difference times of 0 ms, 0 ms, 0 ms, and 0.2 ms notified from the response difference calculator 124. You can reset the time.

When real-time network transmission control is performed in step S603 described above, the interface unit 130 performs an interface with the audio input/output board unit 200 and a network interface according to a drive control signal input from the processor unit 120. And in the audio input/output board 200, which has at least two or more multi-channel audio input channels and at least two or more multi-channel audio output channels, an audio signal is transmitted under the control of the processor unit 120. Input and output to perform real-time network transmission (S604).

When performing real-time network transmission in the above-described step S604, the interface unit 130, which has an audio interface and a network interface, has an I2C interface in the case of an audio interface, and sets the operation mode of the ADC and of-flow ( Over-flow) check, entering power down mode, and register settings necessary for mute control can be made through the corresponding I2C interface, and also the main board 100 and the audio input/output board 200 In the case of interface, the interface can be interfaced through 26 pins and 18 pins, respectively.

When performing real-time network transmission in the above-described step S604, the interface unit 130 uses an Ethernet PHY chip and an RJ45 jack with a magnetic transformer to serve as a physical network interface. It can be used, and in the case of the Ethernet PHY chip, it can support Ethernet speeds of 10/100/1000Mbps, and can be connected to MAC (media access control) through RGMII (reduced gigabit media independent interface), and the signal line of RGMII In this case, it can be designed to have an impedance of 50 ohm, and in the case of a signal line connection between PHY and RJ45 jack, it can be designed to have an impedance of 100 ohm, and in the case of Ethernet MAC and PHY, it can be designed to have an impedance of 100 ohm through the SMI interface. By setting the internal registers of the IC, operating environments such as speed, auto-negotiation settings, and low-power operation can be set.

In performing real-time network transmission in the above-described step S604, the audio input/output board 200 requires +48V dc power for the op-amp operation of the ADC input buffer circuit to supply power to the condenser microphone in the case of the audio input board - 12Vdc, +12Vdc power can be added.

As mentioned above, the embodiment of the present invention is not implemented only through the above-described device and/or operating method, but through a program for realizing the function corresponding to the configuration of the embodiment of the present invention, a recording medium on which the program is recorded, etc. It may be implemented, and such implementation can be easily implemented by an expert in the technical field to which the present invention belongs based on the description of the embodiments described above. Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements can be made by those skilled in the art using the basic concept of the present invention defined in the following claims. It falls within the scope of rights.

10: Multi-channel audio signal transmission system
100: main board
110: clock generator
120: Processor unit
121: Synchronization check signal generator
122: Check response signal receiver
123: Response time checker
124: Response difference calculator
125: Transmission time setting machine
126: View error message
127: Transmission time initialization manager
130: Interface unit
200: Audio input/output board

Claims (4)

In a multi-channel audio signal transmission system,
The multi-channel audio signal transmission system includes a main board and an audio input/output board;
The main board includes a clock generator that generates a clock signal by a frequency control signal;
A frequency control signal is generated and input to the clock generator, a drive control signal is generated according to the clock signal generated by the clock generator, and an audio signal is input and output by applying AVB, a standardized audio and video transmission standard. A processor unit that controls real-time network transmission for multiple channels on the board;
and an interface unit that performs an interface with the audio input/output board unit and a network interface according to a driving control signal generated by the processor unit.
The audio input/output board has an audio input channel formed of at least two or more multi-channels and an audio output channel formed of at least two multi-channels, and inputs and outputs audio signals under the control of the processor unit to perform real-time network transmission. Let it be done,
The clock generator receives an analog waveform signal and compares the frequency converted to a digital signal with the frequency multiplied by digital logic by the frequency control signal of the processor unit to adjust and output the desired clock frequency in the system. A clock signal is generated in an adjusted manner, and the clock generator generates it in a frequency multiplier PLL IC in the case of a low-jitter clock signal with little waveform distortion, and in the case of a generated low-jitter 24MHz signal, the processor unit It is supplied as the main clock, and the clock generator inputs it as the reference clock of the PLL IC that supplies the MCLK signal to the ADC and DAC operating at a sampling rate of 48KHz,
The processor unit is provided with a multi-core processor that has at least two tiles with at least two cores built-in, and performs multitasking of input/output, signal processing, and user program execution, and the processor unit performs multitasking for each tile. It has 8 built-in cores and is designed with an internal memory sharing structure so that each core can access common memory, maintains a processing speed of 2,000 MIPS, supports USB and Gigabit Ethernet, and supports analog audio input and For output, it is provided with programming for ADC and DAC control and LED display control operations through the I2C interface of the interface unit, and is responsible for controlling the chip designed on the audio input/output board,
The processor unit includes a synchronization check signal generator that generates a synchronization check signal under control and transmits it to each of the multiple channels;
a check response signal receiver that receives synchronization check response signals transmitted from each receiver of multiple channels according to control and notifies the synchronization response of each channel;
a response time checker that controls the operations of the synchronization check signal generator and the check response signal receiver, receives synchronization responses of each channel from the check response signal receiver, and checks the synchronization response time of each channel;
a response difference calculator that checks the latest synchronization response time among the synchronization response times of each channel confirmed by the response time checker and calculates a difference time from the synchronization response time of each channel based on the latest confirmed synchronization response time;
a transmission time setting device that sets network transmission times for the multi-channels so that each audio signal is delayed by the synchronization difference time calculated by the response difference calculator and transmitted over the network;
An error notification viewer that receives a channel that has elapsed a preset synchronization error time from the response time checker and notifies the operator or manager of the channel in which the synchronization error occurred; and
A transmission time initialization manager that initializes the network transmission time for each channel of the transmission time setter under the control of the response time checker,
The synchronization check signal generator directly transmits the synchronization check signal to each of the multi-channels without going through the transmission time setting device,
The receiver receives the synchronization check signal transmitted from the synchronization check signal generator, processes the signal, generates a synchronization check response signal as a corresponding synchronization response, and transmits the synchronization check signal to the check response signal receiver,
The response time checker controls the operations of the synchronization check signal generator and the check response signal receiver when performing the first operation, upon reset, or at a preset period, and the response time checker controls each channel from the check response signal receiver. Upon receiving the synchronization response, it is checked whether there is a channel whose synchronization response time has elapsed the preset synchronization error time, and if there is a channel whose synchronization error time has elapsed, this is notified to the error notification display,
The check response signal receiver receives the first initialization check response signal transmitted from each receiver of multiple channels under the control of the response time checker and notifies the response time checker of the first initialization response of each channel. At the same time, the second initialization check response signal transmitted from each multi-channel receiver is received, and the second initialization response of each channel is notified to the response time checker,
The receiver receives the first initialization check signal transmitted from the transmission time initialization manager, processes the first initialization check signal, and generates a first initialization check response signal as a corresponding first initialization response, respectively, to the check response signal receiver. At the same time as transmitting, the second initialization check signal transmitted from the transmission time initialization manager is received and processed, and a second initialization check response signal is generated as a corresponding second initialization response to the check response signal receiver. Send each to
The response time checker controls the operation of the transmission time initialization manager when performing the first operation or upon reset, and receives the first initialization response of each channel from the check response signal receiver to check the first initialization response time of each channel. At the same time as notifying the response difference calculator, the second initialization response of each channel is notified from the check response signal receiver, and the second initialization response time of each channel is confirmed and notified to the response difference calculator,
The response difference calculator calculates the difference time between the first initialization response time and the second initialization response time of each channel notified from the response time checker and reports the difference time to the transmission time initialization manager,
The transmission time initialization manager generates first and second initialization check signals under the control of the response time checker, and transmits the first initialization check signal directly to each of the multi-channels without going through the transmission time setting device. At the same time, a second initialization check signal is transmitted to each of the multiple channels through the transmission time setting device, and the transmission time initialization manager determines the channel in which the initialization difference time occurred among the initialization difference times notified from the response difference calculator. Resets the network transmission time,
The interface unit is provided with an I2C interface, so that ADC operation mode setting, over-flow confirmation, power-down mode entry, and mute control register setting are performed through the I2C interface, and the main board and the audio input/output board In the case of the interface, an audio interface that interfaces through 26 pins and 18 pins, respectively; And for physical network interface, an RJ45 jack with a built-in Ethernet PHY chip and magnetic transformer is used. The Ethernet PHY chip supports Ethernet speeds of 10/100/1000Mbps and connects to MAC through RGMII. In the case of the RGMII signal line, it is designed to have an impedance of 50 ohms, and in the case of the signal line connection between the PHY and RJ45 jack, it is designed to have an impedance of 100 ohms. In the case of the Ethernet MAC and PHY, the internal register of the PHY IC is connected through the SMI interface. It has a network interface that sets the operating environment for speed, auto-negotiation settings, and low-power operation by setting,
The audio input/output board is a multi-channel audio characterized in that, in the case of the audio input board, +48V dc power is added to supply power to the condenser microphone, and -12Vdc and +12Vdc power are added for operation of the operational amplifier of the ADC input buffer circuit. Signal transmission system. delete delete delete