KR102635683B1 - Nonvolatile memory device - Google Patents

Abstract

A non-volatile memory device according to the present technology includes a memory block including a plurality of cell strings, each of which includes memory cells electrically connected to word lines stacked on a substrate, and a plurality of cell strings electrically connected to ends of the cell strings. sub-common sources and a plurality of bit lines electrically connected to other ends of the cell strings, wherein the memory block includes sub-blocks corresponding to each of the sub-common sources, and the same among the cell strings Cell strings electrically connected to bit lines may be included in the same subblock.

Description

Nonvolatile memory device {NONVOLATILE MEMORY DEVICE}

The present invention relates to semiconductor memory devices, and specifically to non-volatile memory devices.

Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP), and are broadly divided into volatile memory devices and non-volatile memory. It is classified as a nonvolatile memory device.

A volatile memory device is a memory device in which the stored data disappears when the power supply is cut off. Volatile memory devices include SRAM (Static Random Access Memory), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). Meanwhile, a non-volatile memory device is a memory device that retains stored data even when the power supply is cut off. Non-volatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), and EEPROM (EEPROM). (Electrically Erasable and Programmable ROM), flash memory, PRAM (Phase Change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

Recently, research on semiconductor memory devices with a three-dimensional structure has been actively conducted in order to improve the degree of integration of semiconductor memory devices.

Embodiments of the present invention can provide a non-volatile memory device that can improve memory efficiency and prevent erase disturb.

A non-volatile memory device according to an embodiment of the present invention includes a memory block including a plurality of cell strings, each of which includes memory cells electrically connected to word lines stacked on a substrate, and a memory block at one end of the cell strings. It includes a plurality of sub-common sources electrically connected and a plurality of bit lines electrically connected to other ends of the cell strings, wherein the memory block includes sub-blocks respectively corresponding to the sub-common sources, and the cell Among the strings, cell strings electrically connected to the same bit line may be included in the same subblock.

A non-volatile memory device according to an embodiment of the present invention includes a memory block electrically connected to word lines stacked on a substrate, a first sub common source and a second sub common source arranged in the direction of the word lines. and formed on the memory block and including a plurality of first bit lines corresponding to the first sub common source and a plurality of second bit lines corresponding to the second sub common source, the memory block comprising: A first sub-block including a plurality of first cell strings electrically connected between the first bit lines and the first sub common source, and electrically connected between the second bit lines and the second sub common source. It may include a second sub-block including a plurality of connected second cell strings.

A non-volatile memory device according to an embodiment of the present invention includes bit lines including a plurality of odd bit lines and a plurality of even bit lines, a memory block disposed below the bit lines, and a lower portion of the memory block. is disposed in and includes a first sub common source and a second sub common source arranged in the direction of the bit lines, wherein the memory block includes a plurality of units electrically connected between the odd bit lines and the first sub common source. It may include a first sub-block including first cell strings, and a second sub-block including a plurality of second cell strings electrically connected between the even bit lines and the second sub common source.

According to embodiments of the present invention, memory efficiency can be improved and erase disturb can be prevented.

1 is a diagram showing a non-volatile memory device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the memory cell array of FIG. 1.
FIG. 3 is a circuit diagram showing an embodiment of a structure corresponding to one of the memory blocks shown in FIG. 2.
FIG. 4 is a plan view illustrating an example of a structure corresponding to one of the memory blocks shown in FIG. 2 .
FIG. 5 is a perspective view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2.
FIG. 6 is a diagram illustrating an example of a bias condition during an erase operation of the first sub-block (Sub-block1).
FIG. 7 is a perspective view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2.
FIG. 8 is a perspective view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2.
FIG. 9 is a plan view schematically showing peripheral circuits formed on the circuit layer (PERI) of FIG. 8.
FIG. 10 is a circuit diagram showing an embodiment of a structure corresponding to one of the memory blocks shown in FIG. 2.
FIG. 11 is a plan view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2.
Figure 12 is a perspective view showing a portion of Figure 11.
FIG. 13 is a cross-sectional view showing a portion of FIG. 11.
Figure 14 is a diagram schematically showing a memory system including a non-volatile memory device according to an embodiment of the present invention.
Figure 15 is a block diagram schematically showing a computing system including a non-volatile memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 1 is a block diagram showing a non-volatile memory device 100 according to an embodiment of the present invention.

Referring to FIG. 1 , the non-volatile memory device 100 may include a memory cell array 110 and peripheral circuitry. The peripheral circuit may include a row decoder 120, a page buffer 130, an input/output buffer 140, a control logic 150, a voltage generator 160, and a source driver 170.

The memory cell array 110 may be electrically connected to the row decoder 120 through word lines (WL) and select lines (DSL and SSL). The memory cell array 110 may be electrically connected to the page buffer 130 through bit lines BL. The memory cell array 110 may be electrically connected to the source driver 170 through the sub common sources SCSL1 and SCSL2.

The memory cell array 110 may include a plurality of memory blocks. The memory cell array 110 may have a three-dimensional structure. Each memory block may include a plurality of cell strings arranged vertically on a semiconductor substrate. A cell string may be a unit of memory cells connected in series. Memory cells included in one cell string can be selected by the same selection transistor. Each memory block may include a plurality of pages. A page may be a unit of memory cells connected to the same word line.

Each memory block may include at least two sub-blocks. A subblock may correspond to an erase unit. Each page can be divided into subblocks.

The sub blocks may respectively correspond to sub common sources (SCSL1 and SCSL2). The sub common sources SCSL1 and SCSL2 may be electrically connected to the source driver 170. During an erase operation, the voltage from the source driver 170 may be independently applied to the sub-common sources SCSL1 and SCSL2. During an erase operation, an erase voltage (e.g., 20V) may be applied to the sub-common source (SCSL) corresponding to the selected sub-block, and an unselected erase voltage (e.g., 20 V) may be applied to the sub-common source (SCSL) corresponding to the unselected sub-block. 0V) can be applied. Accordingly, the non-volatile memory device 100 can perform an erase operation on a sub-block basis.

The row decoder 120 may select one of the memory blocks of the cell array 110 in response to the address ADD. Additionally, the row decoder 120 may select one of the word lines (WL) of the selected memory block. The row decoder 120 may transmit a driving signal from the voltage generator 160 to the word lines (WL) or the selection lines (DSL and SSL) of the selected memory block. In order to transmit a driving signal to the word lines (WL) or selection lines (DSL, SSL) of the selected memory block, the row decoder 120 passes a pass corresponding to each of the memory blocks included in the memory cell array 110. It may include transistor stages. Each pass transistor stage may include a plurality of pass transistors that provide driving signals to the word lines (WL) or select lines (DSL, SSL) of the corresponding memory block in response to the block selection signal.

During an erase operation, the row decoder 120 may apply the voltage provided from the voltage generator 160 to the word lines (WL) and the selection lines (DSL and SSL) of the selected memory block. For example, during an erase operation, the row decoder 120 may apply the ground voltage (Vss) to word lines of the selected memory block. Then, the row decoder 120 applies a ground voltage (Vss) to the selection lines (DSL, SSL) of the selected memory block, and maintains a constant constant from the time of applying the ground voltage (Vss) to the selection lines (DSL, SSL). After time elapses, the selection lines (DSL, SSL) can be floated.

The page buffer 130 may operate as a write driver or a sense amplifier depending on the operation mode. During a program operation, the page buffer 130 may transmit a voltage corresponding to data to be programmed to the bit lines BL of the memory cell array 110. During a read operation, the page buffer 130 may detect data stored in the selected memory cell through the bit lines BL and transfer it to the input/output buffer 140. During an erase operation, the page buffer 130 may cause the bit lines BL of the memory cell array 110 to float.

The input/output buffer 140 can transfer write data input from the outside to the page buffer 130 during program operation. The input/output buffer 140 may output data provided from the page buffer 130 to the outside during a read operation. The input/output buffer 140 may transmit an address (ADD) or command (CMD) to the row decoder 120 or control logic 150.

The control logic 150 may control the page buffer 130 and the voltage generator 160 to access selected memory cells in response to a command (CMD) transmitted from the input/output buffer 140. The control logic 150 may control the source driver 170 to apply an erase voltage to the sub common source (SCSL) corresponding to the selected sub block during an erase operation. During an erase operation, the control logic 150 may control the source driver 170 to apply a non-erase voltage to the sub common source (SCSL) corresponding to the unselected sub block.

The voltage generator 160 may be electrically connected to the control logic 150, row decoder 120, and source driver 170. The voltage generator 160 may operate under the control of the control logic 150. Voltage generator 160 may be configured to generate high voltage. The high voltage generated by the voltage generator 160 may be transmitted to a plurality of word lines (WL) and select lines (DSL, SSL) connected to the memory cell array 110 through the row decoder 120. The high voltage generated by the voltage generator 160 may be transmitted to the sub common source (SCSL) connected to the memory cell array 110 through the source driver 170.

The source driver 170 is controlled by the control logic 150 and can receive various voltages from the voltage generator 160. During an erase operation, the source driver 170 is controlled by the control logic 150 to apply an erase voltage to the sub common source corresponding to the selected sub block. During an erase operation, the source driver 170 is controlled by the control logic 150 to apply a non-erase voltage to the sub common source corresponding to the unselected sub block.

To improve integration, a method of increasing the number of memory cells included in a unit cell string has been proposed. However, as the number of memory cells included in the unit cell string increases, the number of word lines increases as much as the number of memory cells, and accordingly, the number of pass transistors that provide driving signals to the word lines increases, thereby increasing the row decoder. The area of (120) will increase. Additionally, since the number of wires connecting the word lines and the row decoder 120 increases corresponding to the increased number of word lines, the wire patterning margin will be reduced.

Accordingly, as a way to improve integration and simultaneously prevent the occurrence of the above-mentioned problems, a method of increasing the number of cell strings included in a unit memory block was proposed. In order to improve the efficiency of non-volatile memory devices, it is necessary to shorten the time required to erase data stored in a memory block and then rewrite the data. However, if the number of cell strings included in a unit memory block increases, an erase operation using an existing scheme that performs erase on a memory block basis will take a lot of time, leading to a decrease in memory efficiency.

In this embodiment, each memory block can be divided into two or more sub-blocks and an erase operation can be performed on a sub-block basis. Subblock-level erasing is a method of erasing a portion of the memory block capacity, and has the advantage of improving memory efficiency by quickly and efficiently erasing small amounts of data.

Hereinafter, the memory cell array 110 will be described in more detail with reference to FIG. 2 as follows.

Referring to FIG. 2 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKn.

Although not shown, each memory block (BLK1 to BLKn) may have a three-dimensional structure. Each of the memory blocks BLK1 to BLKn may include a structure extended along the bit line direction (BLD), the word line direction (WLD), and the height direction (VD). Each of the memory blocks BLK1 to BLKn may include a plurality of cell strings extended along the height direction VD. A plurality of cell strings may be provided along the bit line direction (BLD) and the word line direction (WLD).

Each memory block (BLK1 to BLKn) is electrically connected to a plurality of bit lines, at least one drain selection line, a plurality of word lines, at least one source selection line, and at least two sub common sources. You can. Each cell string may be electrically connected to one bit line, at least one drain select line, a plurality of word lines, at least one source select line, and one sub common source.

The configuration of each memory block (BLK1 to BLKn) will become clearer through the following description with reference to FIGS. 3 to 13.

FIG. 3 is a circuit diagram showing one of the memory blocks shown in FIG. 2.

Referring to FIG. 3, the memory block BLK may include a plurality of cell strings CS11, CS21, CS12, CS22, CS13, CS23, CS14, and CS24.

The cell strings CS11 and CS21 may be electrically connected between the bit line BL1 and the first sub common source SCSL1, and the cell strings CS12 and CS22 may be electrically connected between the bit line BL2 and the first sub common source. It can be electrically connected between sources (SCSL1). The cell strings CS13 and CS23 may be electrically connected between the bit line BL3 and the second sub common source SCSL2, and the cell strings CS14 and CS24 may be electrically connected between the bit line BL4 and the second sub common source. It can be electrically connected between sources (SCSL2).

The memory block BLK may include a plurality of sub-blocks (Sub-block1 and Sub-block2). Sub-block1 may include cell strings (CS11, CS21, CS12, CS22), and sub-block2 may include cell strings (CS13, CS23, CS14, CS24). there is. Hereinafter, for convenience of explanation, the sub-block1 will be defined as the first subblock, and the subblock2 will be defined as the second subblock.

The first sub-block (Sub-block1) corresponds to the first sub-common source (SCSL1), and the cell strings (CS11, CS21, CS12, CS22) included in the first sub-block (Sub-block1) correspond to the first sub-common source (SCSL1). It can be commonly electrically connected to a common source (SCSL1). The second sub-block (Sub-block2) corresponds to the second sub-common source (SCSL2), and the cell strings (CS13, CS23, CS14, and CS24) included in the second sub-block (Sub-block2) correspond to the second sub-common source (SCSL2). It can be commonly electrically connected to a common source (SCSL2). That is, cell strings included in the same sub-block may be electrically connected to the same sub-common source, and cell strings included in different sub-blocks may be electrically connected to different sub-common sources.

The first and second sub common sources SCSL1 and SCSL2 may be arranged along the word line direction WLD. Like the first and second sub common sources (SCSL1 and SCSL2), the first and second sub blocks (Sub-block1 and Sub-block2) may be arranged along the word line direction (WLD).

The cell strings CS11 and CS21 included in the first sub-block (Sub-block1) may be electrically connected to the bit line BL1, and the cell strings CS11 and CS21 included in the first sub-block (Sub-block1) may be electrically connected to the bit line BL2. The cell strings CS12 and CS22 may be electrically connected. The cell strings CS13 and CS23 included in the second sub-block (Sub-block2) may be electrically connected to the bit line BL3, and the cell strings CS13 and CS23 included in the second sub-block (Sub-block2) may be electrically connected to the bit line BL4. The cell strings CS14 and CS24 may be electrically connected. That is, cell strings electrically connected to the same bit line may be included in the same sub-block, and cell strings included in different sub-blocks may be electrically connected to different bit lines.

The bit lines (BL1, BL2) correspond to the first sub-block (Sub-block1) and can be electrically connected to the cell strings (CS11, CS21, CS12, and CS22) included in the first sub-block (Sub-block1). The bit lines (BL3, BL4) correspond to the second sub-block (Sub-block2) and are electrically connected to the cell strings (CS13, CS23, CS14, and CS24) included in the second sub-block (Sub-block2). can be connected Hereinafter, for convenience of explanation, the bit lines BL1 and BL2 corresponding to the first sub-block (Sub-block1) are defined as the first bit lines, and the bit lines corresponding to the second sub-block (Sub-block2) are defined as the first bit lines. (BL3, BL4) will be defined as second bit lines.

Each of the cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, and CS24) includes a drain select transistor (DST) connected in a direction perpendicular to the main surface of the substrate (not shown), and a plurality of memory cells (MC1 ~ MC4), and may include a source select transistor (SST). In each of the cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, and CS24), the memory cells (MC1 to MC4) may be connected in series between the drain select transistor (DST) and the source select transistor (SST). . Memory cells MC1 to MC4 may include main memory cells used to store valid data. In addition to the main memory cells, the memory cells MC1 to MC4 may further include dummy memory cells that are not used to store valid data.

One end of the source select transistors (SST) of the cell strings (CS11, CS21, CS12, and CS22) included in the first sub-block (Sub-block1) is electrically connected to the memory cells (MC0), and the other ends are connected to the first sub-block (Sub-block1). 1 It can be commonly electrically connected to the sub common source (SCSL1). One end of the source select transistors (SST) of the cell strings (CS13, CS23, CS14, and CS24) included in the second sub-block (Sub-block2) is electrically connected to the memory cells (MC0), and the other ends are connected to the second sub-block (Sub-block2). 2 It can be electrically connected in common to the sub common source (SCSL2).

One end of the drain select transistors (DST) of the cell strings (CS11, CS21, CS12, and CS22) included in the first sub-block (Sub-block1) are electrically connected to the first bit lines (BL1 and BL2). Other ends may be electrically connected to the memory cells MC4. One end of the drain select transistors (DST) of the cell strings (CS13, CS23, CS14, and CS24) included in the second sub-block (Sub-block2) is electrically connected to the second bit lines (BL3 and BL4). And the other ends may be electrically connected to the memory cells MC4.

Below, cell strings are defined in row, column, and height units. Cell strings commonly connected to one bit line may form one column. For example, cell strings CS11 and CS21 connected to the bit line BL1 may form a first row. Cell strings CS12 and CS22 connected to the bit line BL2 may form a second row. Cell strings CS13 and CS23 connected to the bit line BL3 may form a third column. Cell strings CS14 and CS24 connected to the bit line BL4 may form a fourth column.

Cell strings connected to one drain selection line may form one row. For example, cell strings CS11, CS12, CS13, and CS14 connected to the drain selection line DSL1 may form a first row. Cell strings CS21, CS22, CS23, and CS24 connected to the drain selection line DSL2 may form a second row. The direction from the source select transistors (SST) to the drain select transistors (DST) may be the height direction (VD).

Among the cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, CS24) included in the first and second sub-blocks (Sub-block1, Sub-block2), the cell strings in the same row select the same drain. It can be electrically connected to a line. Different rows of cell strings may be electrically connected to different drain select lines.

Cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, CS24) included in the first and second sub-blocks (Sub-block1, Sub-block2) share the source selection line (SSL). You can. Memory cells of the same height in the cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, CS24) of the first and second sub-blocks (Sub-block1, Sub-block2) share word lines. You can. That is, word lines of cell strings included in different sub-blocks at the same height may be electrically connected in common.

Memory cells connected to the same word line may constitute one page, and the memory block BLK may include a plurality of pages arranged in the height direction VD. For example, eight memory cells connected to the word line WL1 can configure one page. Among the eight memory cells included in the unit page, four memory cells belonging to cell strings (CS11, CS21, CS12, CS22) are included in the first sub-block (Sub-block1), and cell strings (CS13, CS23) , CS14, CS24) may be included in the second sub-block (Sub-block2). That is, each page can be divided into sub-blocks (Sub-block1, Sub-block2).

By way of example, in FIG. 3, the memory block BLK is shown as including two sub-blocks (Sub-block1 and Sub-block2). However, the number of sub-blocks included in a memory block is not limited to this, and two or more sub-blocks may be provided along the word line direction (WLD).

By way of example, in FIG. 3, each sub-block (Sub-block1, Sub-block2) is shown as including four cell strings. However, the number of cell strings included in each sub-block (Sub-block1, Sub-block2) is not limited to this, and the cell strings included in each sub-block (Sub-block1, Sub-block2) are aligned in the bit line direction. One or more lines may be provided along the (BLD) and word line directions (WLD).

For example, in FIG. 3, the source selection transistors (SST) are shown as being electrically connected in common to one source selection line (SSL). However, like the drain selection transistors (DST), the source selection transistors (SST) in the same row are commonly electrically connected to one source selection line, and the source selection transistors (SST) in different rows are connected to different source selection lines. The structure of the memory block BLK may be changed and applied to be electrically connected to selection lines.

By way of example, in FIG. 3, one drain select transistor (DST) and one source select transistor (SST) are shown in each cell string. However, two or more drain selection transistors or two or more source selection transistors may be provided in each cell string.

By way of example, in FIG. 3 , each cell string is shown as including four memory cells MC1 to MC4. However, at least one memory cell may be provided in each cell string.

FIG. 4 is a plan view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2, and FIG. 5 shows an example of a structure corresponding to one of the memory blocks shown in FIG. 2. This is a perspective view. To simplify the drawing, the bit lines BL1 to BL4 are omitted in FIG. 4 .

Referring to FIGS. 4 and 5, the non-volatile memory device includes three memory devices formed on a substrate 10, first and second sub common sources (SCSL1 and SCSL2), and first and second sub common sources (SCSL1 and SCSL2). It may include a memory block (BLK) with a dimensional structure, and a plurality of bit lines (BL1 to BL4) formed on the memory block (BLK).

Exemplarily, in FIGS. 4 and 5 , the number of sub common sources (SCSL) corresponding to a single memory block (BLK) is shown to be two. However, the number of sub common sources (SCSL) corresponding to a single memory block (BLK) is not limited to this, and two or more sub common sources (SCSL) corresponding to a single memory block (BLK) may be provided. .

By way of example, in FIG. 5 , the number of bit lines corresponding to a single memory block BLK is shown to be four. However, the number of bit lines corresponding to a single memory block BLK is not limited to this, and two or more bit lines corresponding to a single memory block BLK may be provided.

The three-dimensional memory block (BLK) includes a source selection line (SSL), a plurality of word lines (WL), a drain selection line (DSL), and a source selection line (SSL) stacked on the first and second sub common sources (SCSL1 and SCSL2). and a plurality of channel films (CH). Each of the channel films (CH) may pass through the selection lines (SSL, DSL) and word lines (WL).

In this embodiment, the channel films CH have a pillar structure that completely fills the center area. However, the present invention is not limited to this, and the channel films CH may have a tube shape with an open central region. In this case, the open central region may be filled with an insulating film. A memory layer (M) may be formed on the surfaces of the channel layers (CH). The memory layer M may include a tunnel insulating layer, a charge storage layer, and a charge blocking layer, or may include some of these. Here, the charge storage film may include at least one of a floating gate such as a polysilicon film that stores charges, a trap film such as a nitride film that traps charges, and nano dots. For reference, the memory layer M may include a phase change material instead of a charge storage layer. Additionally, a memory layer (not shown) may be additionally formed, interposed between the memory layer M and the word lines WL and surrounding the upper and lower surfaces of the word lines WL. Here, the additionally formed memory layer may include a tunnel insulating layer, a charge storage layer, and a charge blocking layer, or may include some of them. Additionally, the charge blocking film of the additionally formed memory film may be a stacked film of an oxide film and a high dielectric constant material film.

A source selection transistor (SST) is formed in the area where the source selection line (SSL) surrounds the channel film (CH), and memory cells (MC) are formed in the area where the word lines (WL) surround the channel film (CH). A drain select transistor (DST) is formed in a portion where the drain select line (DSL) surrounds the channel film (CH). By the above structure, a plurality of cell strings (CS) each including a drain select transistor (DST), memory cells (MC), and source select transistor (SST) formed along each of the channel films (CH) are configured. You can.

As in the embodiment shown in FIG. 5 , the first and second sub common sources SCSL1 and SCSL2 may be formed on the substrate 10 . The substrate 10 may include a bulk silicon substrate. The bulk silicon substrate may include other semiconductor materials such as group III, group IV, and/or group V elements. The first and second sub common sources SCSL1 and SCSL2 may be well regions formed by implanting p-type or n-type impurities into the substrate 10 .

Unlike the embodiment shown in FIG. 5, the first and second sub common sources SCSL1 and SCSL2 may be formed in a semiconductor layer disposed between the substrate 10 and the memory block BLK. A circuit layer may be further formed between the semiconductor substrate 10 and the semiconductor layer. Peripheral circuits may be formed in the circuit layer. The peripheral circuit may include the row decoder 120, page buffer 130, input/output buffer 140, control logic 150, voltage generator 160, and source driver 170 shown in FIG. 1. This structure will become clearer through examples described later with reference to FIG. 8.

Referring again to FIG. 5 , a separation structure 11 may be formed on the substrate 10 between the first sub-common source (SCSL1) and the second sub-common source (SCSL2). The separation structure 11 may be an insulating film. Alternatively, the separation structure 11 may be an impurity region doped with a conductivity type opposite to that of the first and second sub common sources SCSL1 and SCSL2. The separation structure 11 may have a line shape extending in the bit line direction (BLD), and the first and second sub common sources (SCSL1 and SCSL2) extend in the word line direction (WLD) with the separation structure 11 in between. ) can be arranged.

The memory block BLK includes a first sub-block (Sub-block1) corresponding to the first sub-common source (SCSL1) and a second sub-block (Sub-block2) corresponding to the second sub-common source (SCSL2). can do. The first sub-block (Sub-block1) and the second sub-block (Sub-block2) may be disposed on top of the sub common sources (SCSL1 and SCSL2) corresponding to each other. Accordingly, the first and second sub-blocks (Sub-block1 and Sub-block2) may be arranged in the same word line direction (WLD) as the first and second sub-common sources (SCSL1 and SCSL2).

Each of the first and second sub-blocks (Sub-block1 and Sub-block2) may include a plurality of cell strings (CS). One end of the cell strings CS included in the first sub-block Sub-block1 may be commonly electrically connected to the first sub common source SCSL1. One end of the cell strings CS included in the second sub-block Sub-block2 may be commonly electrically connected to the second sub common source SCSL2. That is, cell strings included in the same sub-block may be electrically connected to the same sub-common source, and cell strings included in different sub-blocks may be electrically connected to different sub-common sources.

The bit lines BL1 to BL4 include first bit lines BL1 and BL2 corresponding to the first sub-block (Sub-block1) and second bit lines corresponding to the second sub-block (Sub-block2). May include (BL3,BL4). The first bit lines (BL1, BL2) and the second bit lines (BL3, BL4) may be disposed on corresponding sub-blocks (Sub-block1, Sub-block2), respectively.

Other ends of the cell strings included in the first sub-block (Sub-block1) may be electrically connected to the first bit lines (BL1 and BL2). Other ends of the cell strings included in the second sub-block (Sub-block2) may be electrically connected to the second bit lines BL3 and BL4.

All cell strings connected to the bit line BL1 may be included in the first sub-block (Sub-block1), and all cell strings connected to the bit line BL2 may be included in the first sub-block (Sub-block1). Additionally, all cell strings connected to the bit line BL3 may be included in the second sub-block (Sub-block2), and all cell strings connected to the bit line BL4 may be included in the second sub-block (Sub-block2). there is. That is, cell strings connected to the same bit line may be included in the same subblock, and cell strings included in different subblocks may be connected to different bit lines.

FIG. 6 shows an example of a bias condition during an erase operation of the first sub-block (Sub-block1) of FIG. 3.

Among the first and second sub-blocks (Sub-block1, Sub-block2) included in the memory block (BLK) shown in FIG. 6, the first sub-block (Sub-block1) is selected for erasure and the second sub-block (Sub-block1) is selected for erasure. Assume that Sub-block2) is erase-protected.

During an erase operation, a ground voltage (Vss) may be applied to the word lines (WL) of the selected memory block (BLK), and the word lines (WL) of the unselected memory block may be floated. Additionally, an erase voltage (Verase) is applied to the first sub common source (SCSL1) corresponding to the first sub-block (Sub-block1) selected for erasing, and a second sub-common source (Verase) corresponding to the second sub-block (Sub-block2) that is erase-inhibited. 2 A non-selective erase voltage (Vunerase) will be applied to the sub common source (SCSL2). Here, the erase voltage (Verase) may have a value of 20V, and the non-selected erase voltage (Vunerase) may be a ground level (Vss) or a floating level.

The bit lines (BL1 to BL4) can be floating, and the source selection line (SSL) and drain selection lines (DSL1 and DSL2) are erased to the first sub common source (SCSL1) after receiving the ground voltage (Vss). The voltage (Vrease) may be plotted after a certain period of time has elapsed from the point of application.

Before the source selection line (SSL) and the drain selection lines (DSL1, DSL2) are floated, the first sub-common voltage is applied to the source selection line (SSL) and the drain selection lines (DSL1, DSL2). The erase voltage Verase applied to the source SCSL1 will be transmitted to the channel films CH and the first bit lines BL1 and BL2 of the cell strings included in the first sub-block Sub-block1.

Unlike this embodiment, assume that cell strings connected to the same bit line are included in different sub-blocks. In this case, during an erase operation, the erase voltage applied to the sub-common source corresponding to the selected sub-block is transferred to another unselected sub-block through the bit line, and as a result, the unselected sub-block will be unintentionally erased.

In this embodiment, all cell strings connected to the same bit line are included in the same sub-block, and cell strings included in different sub-blocks are electrically connected to different bit lines. Accordingly, it is possible to prevent the erase voltage (Verase) applied to the sub-common source corresponding to the selected sub-block from being transmitted to another unselected sub-block through the bit line. In other words, it is possible to prevent unintentional erasure of unselected sub-blocks.

In the embodiment referring to FIGS. 3 to 6, the channel films CH are formed in an 'I' shape, and the bit lines BL1 to BL2 are disposed on the memory block BLK. It shows that the sub-common sources (SCSL1 and SCSL2) are placed below the memory block (BLK).

However, as shown in FIG. 7, a pair of channel films (CH1, CH2) are connected in a 'U' shape through a pipeline channel film (PLC) formed under the memory block (BLK), and the bit lines (BL1, BL2, BL3, BL4) and sub common sources (SCSL1, SCSL2) may all be placed on top of the memory block (BLK). In this case, the sub common sources SCSL1 and SCSL2 may be formed of wires extending in a direction parallel to the bit lines BL1 and BL2.

FIG. 8 is a perspective view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2, and FIG. 9 is a plan view schematically showing a peripheral circuit formed in the circuit layer (PERI) of FIG. 8.

Referring to FIG. 8, a semiconductor layer 20 may be formed between the substrate 10 and the memory block BLK. The semiconductor layer 20 may include silicon (Si), germanium (Ge), or a mixture thereof, and may be a semiconductor doped with impurities such as group III, group IV, and/or group V elements, or a semiconductor that is not doped with impurities. It may be an intrinsic semiconductor.

The memory block BLK may include a source select line (SSL), a plurality of word lines (WL), a drain select line (DSL), and a plurality of channel films (CH) stacked on the substrate 10. there is.

The memory block BLK may include a first sub-block (Sub-block1) and a second sub-block (Sub-block2). The first sub-block (Sub-block1) and the second sub-block (Sub-block2) may be arranged in the word line direction (WLD) with the open area (OFC) interposed therebetween. That is, the first sub-block (Sub-block1) and the second sub-block (Sub-block2) may be spaced apart from each other with the open area (OFC) in between.

The drain select lines (DSL), source select line (SSL), and word lines (WL) of the memory block (BLK) are cut in the open area (OFC), so that the drain select line of the first sub-block (Sub-block1) DSL, source select line (SSL) and word lines (WL) and drain select lines (DSL), source select line (SSL) and word lines (WL) of the second sub-block (Sub-block2) can be physically separated.

A first sub common source (SCSL1) may be formed in the semiconductor layer 20 under the first sub-block (Sub-block1), and a second sub-common source (SCSL1) may be formed in the semiconductor layer 20 under the second sub-block (Sub-block2). A sub common source (SCSL2) may be formed. A separation structure 11 may be formed in the semiconductor layer 20 in the open area OFC.

The first and second sub common sources SCSL1 and SCSL2 may be well regions formed by doping the semiconductor layer 20 with p-type or n-type impurities. The separation structure 11 may be an insulating film. Alternatively, the separation structure 11 may be an impurity region doped with a conductivity type opposite to that of the first and second sub common sources SCSL1 and SCSL2.

A circuit layer (PERI) may be formed between the semiconductor layer 20 and the substrate 10. Peripheral circuits may be formed in the circuit layer (PERI). The peripheral circuit may include the row decoder 120, page buffer 130, input/output buffer 140, control logic 150, voltage generator 160, and source driver 170 shown in FIG. 1.

Referring to FIG. 9, a row decoder 120 and a source driver 170 may be disposed in the circuit layer (PERI) of the open area (OFC). In FIG. 9, only the row decoder 120 and source driver 170 are shown for convenience. Other peripheral circuits other than the row decoder 120 and the source driver 170, such as the page buffer 130, the input/output buffer 140, the control logic 150, and the voltage generator 160, are located outside the open area (OFC). It may be understood as being placed on the circuit layer (PERI).

Referring again to FIGS. 8 and 9, the drain select line (DSL) of the first sub-block (Sub-block1) and the drain select line (DSL) of the second sub-block (Sub-block2) are connected to contact plugs (not shown). ) and are electrically connected to each other by wiring (not shown) and may share one pass transistor. The source selection line (SSL) of the first sub-block (Sub-block1) and the source selection line (SSL) of the second sub-block (Sub-block2) are mutually connected by contact plugs (not shown) and wiring (not shown). They are electrically connected and can share one pass transistor. The word lines (WL) connected to the first sub-block (Sub-block1) and the word lines (WL) connected to the second sub-block (Sub-block2) are disposed at the same height and have contact plugs (not shown). and may be electrically connected to each other by wiring (not shown) and may share one pass transistor. That is, the source select line (SSL), drain select line (DSL), and word lines (WL) connected to different sub-blocks at the same height may be commonly connected to one pass transistor, and provide the same operating voltage from the pass transistor. You can receive it.

For electrical connection with contact plugs that transmit the driving signals provided from the pass transistors to the drain select line (DSL), source select line (SSL), and word lines (WL), a first sub-block (Sub-block1) ) of the drain select lines (DSL), source select lines (SSL), and word lines (WL) are formed to protrude toward the open area (OFC) toward the bottom. That is, the drain select lines (DSL), source select lines (SSL), and word lines (WL) of the first sub-block (Sub-block1) may be patterned in a staircase shape in the open area (OFC). Similarly, the drain select lines (DSL), source select lines (SSL), and word lines (WL) of the second sub-block (Sub-block2) may be patterned in a staircase shape in the open area (OFC).

The source driver 170 is disposed on the circuit layer (PERI) of the open area (OFC) and may be electrically connected to the first sub-common source (SCSL1) and the second sub-common source (SCSL2). That is, the first sub-common source (SCSL1) and the second sub-common source (SCSL2) may share one source driver 170.

Unlike this embodiment, assume that the source driver is placed on the left side of the first sub-block (Sub-block1) (or on the right side of the second sub-block (Sub-block2)). In this case, the first sub-block (Sub-block2) The distance from the source driver on the left side of block 1) to the second sub-common source (SCSL2) (or the distance from the source driver on the right side of the second sub-block (Sub-block2) to the first sub-common source (SCSL1)) is long. As a result, the source voltage output from the source driver will be provided to the second sub-common source (SCSL2) (or the first sub-common source (SCSL1)) with its integrity degraded during the transfer process. And, as a source voltage with reduced integrity is provided to the second sub-common source (SCSL2) (or the first sub-common source (SCSL1)), the operating characteristics of the non-volatile memory device may deteriorate or malfunction.

Meanwhile, if the source driver is placed on the left side of the first sub-block (Sub-block1) and the right side of the second sub-block (Sub-block2), the source voltage output from the source driver is maintained without significant deterioration in integrity. It will be delivered to the first sub common source (SCSL1) and the second sub common source (SCSL2). However, as the number of source drivers increases to two, the area occupied by the source drivers increases, which will increase the chip size.

In this embodiment, since the source driver 170 is disposed in the open area (OFC) between the first sub-block (Sub-block1) and the second sub-block (Sub-block2), the first sub-common The distance from the source (SCSL1) and the distance from the source driver 170 to the second sub-common source (SCSL2) are short. Therefore, by using one source driver, an intact source voltage can be provided to the first sub-common source (SCSL1) and the second sub-common source (SCSL2), and there is no need to increase the number of source drivers. It is possible to prevent an increase in occupied area and subsequent increase in chip size.

Above, in the embodiment with reference to FIGS. 3 to 9, the sub common sources SCSL1 and SCSL2 are exemplarily arranged along the word line direction WLD.

However, the arrangement direction of the sub common sources SCSL1 and SCSL2 is not limited to this, and the sub common sources SCSL1 and SCSL2 may be arranged in the bit line direction BLD. This embodiment will become clearer through the following description with reference to FIGS. 10 to 13.

FIG. 10 is a circuit diagram showing one of the memory blocks shown in FIG. 2.

Referring to FIG. 10, the memory block BLK may include a plurality of cell strings CS11, CS21, CS12, CS22, CS13, CS23, CS14, and CS24. The bit lines (BLo1 to BLo2 and BLe1 to BLe2) may include odd bit lines (BLo1 to BLo2) and even bit lines (BLe1 to BLe2).

The cell strings CS11 and CS21 may be electrically connected between the odd bit line BLo1 and the first sub common source SCSL1, and the cell strings CS12 and CS22 may be electrically connected between the even bit line BLe1 and the second sub common source SCSL1. It can be electrically connected between sub-common sources (SCSL2). The cell strings CS13 and CS23 may be electrically connected between the odd bit line BLo2 and the first sub common source SCSL1, and the cell strings CS14 and CS24 may be electrically connected between the even bit line BLe2 and the second sub common source SCSL1. It may be electrically connected between sub-common sources (SCSL2).

The memory block BLK may include a plurality of sub-blocks (Sub-block1 and Sub-block2). For example, the memory block BLK includes a first sub-block 1 including cell strings CS11, CS21, CS13, and CS23, and a second sub-block 1 including cell strings CS12, CS22, CS14, and CS24. It may include a sub-block (Sub-block2).

The first sub-block (Sub-block1) corresponds to the first sub common source (SCSL1), and the cell strings (CS11, CS21, CS13, and CS23) included in the first sub-block (Sub-block1) correspond to the first sub common source (SCSL1). It can be commonly electrically connected to a common source (SCSL1). The second sub-block (Sub-block2) corresponds to the second sub common source (SCSL2), and the cell strings (CS12, CS22, CS14, CS24) included in the first sub-block (Sub-block2) correspond to the second sub-common source (SCSL2). It can be commonly electrically connected to a common source (SCSL2). That is, cell strings included in the same sub-block may be electrically connected to the same sub-common source, and cell strings included in different sub-blocks may be electrically connected to different sub-common sources.

Cell strings (CS11, CS21, CS13, CS23) included in the first sub-block (Sub-block1) may be electrically connected to the odd bit lines (BLo1, BLo2), and the even bit lines (BLe1, BLe2) The cell strings CS12, CS22, CS14, and CS24 included in the second sub-block (Sub-block2) may be electrically connected.

Each of the first and second sub common sources (SCSL1 and SCSL2) may have a structure extending in the word line direction (WLD), and the first and second sub common sources (SCSL1 and SCSL2) may extend in the bit line direction (BLD). ) can be arranged.

Each of the cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, and CS24) includes a drain select transistor (DST) connected in a direction perpendicular to the main surface of the substrate (not shown), and a plurality of memory cells (MC1 ~ MC4), and may include a source select transistor (SST). In each of the cell strings (CS11, CS21, CS12, CS22, CS13, CS23, CS14, and CS24), the memory cells (MC1 to MC4) may be connected in series between the drain select transistor (DST) and the source select transistor (SST). . Memory cells MC1 to MC4 may include main memory cells used to store valid data. In addition to the main memory cells, the memory cells MC1 to MC4 may further include dummy memory cells that are not used to store valid data.

One end of the source select transistors (SST) of the cell strings (CS11, CS21, CS13, and CS23) included in the first sub-block (Sub-block1) is electrically connected to the memory cells (MC0), and the other ends are connected to the first sub-block (Sub-block1). 1 It can be commonly electrically connected to the sub common source (SCSL1). One end of the source select transistors (SST) of the cell strings (CS12, CS22, CS14, CS24) included in the second sub-block (Sub-block2) is electrically connected to the memory cells (MC0), and the other ends are connected to the second sub-block (Sub-block2). 2 It can be electrically connected in common to the sub common source (SCSL2).

One end of the drain select transistors (DST) of the cell strings (CS11, CS21, CS13, and CS23) included in the first sub-block (Sub-block1) are electrically connected to the odd bit lines (BLo1 and BLo2) and other The stages may be electrically connected to the memory cells MC4. One end of the drain select transistors (DST) of the cell strings (CS12, CS22, CS14, and CS24) included in the second sub-block (Sub-block2) is electrically connected to the even bit lines (BLe1 and BLe2). Other ends may be electrically connected to the memory cells MC4.

By way of example, in FIG. 10 , the memory block BLK is shown as including two sub-blocks (Sub-block1 and Sub-block2). However, the number of sub-blocks included in a memory block is not limited to this, and two or more sub-blocks may be provided.

By way of example, in FIG. 10, each sub-block (Sub-block1, Sub-block2) is shown as including four cell strings. However, the number of cell strings included in each sub-block (Sub-block1, Sub-block2) is not limited to this, and the cell strings included in each sub-block (Sub-block1, Sub-block2) are aligned in the bit line direction. One or more each may be provided in (BLD) and word line direction (WLD).

Exemplarily, in FIG. 10, the source selection transistors (SST) are shown as being commonly connected to one source selection line (SSL). However, like the drain select transistors (DST), the source select transistors (SST) in the same row are commonly connected to one source select line, and the source select transistors (SST) in different rows are connected to different source select lines. The structure of the memory block (BLK) may be changed and applied to be connected to the memory block (BLK).

By way of example, in FIG. 10 , one drain select transistor (DST) and one source select transistor (SST) are shown to be provided in each cell string. However, two or more drain select transistors or two or more source select transistors may be provided in each cell string.

By way of example, in FIG. 10 , each cell string is shown as including four memory cells MC1 to MC4. However, at least one memory cell may be provided in each cell string.

FIG. 11 is a plan view showing an example of a structure corresponding to one of the memory blocks shown in FIG. 2, FIG. 12 is a perspective view showing a portion of FIG. 11, and FIG. 13 is a portion showing a portion of FIG. 11. This is a cross-sectional view.

Referring to FIG. 11, the non-volatile memory device includes first and second sub common sources (SCSL1 and SCSL2), a memory block (BLK) formed on the first and second sub common sources (SCSL1 and SCSL2), and a memory block. It may include a plurality of odd bit lines (BLo1 to 6) and a plurality of even bit lines (BLe1 to 6) formed on (BLK).

Exemplarily, in FIGS. 11 to 13 , the number of sub common sources (SCSL) corresponding to a single memory block (BLK) is shown to be two. However, the number of sub common sources (SCSL) corresponding to a single memory block (BLK) is not limited to this, and two or more sub common sources (SCSL) corresponding to a single memory block (BLK) may be provided. .

By way of example, in FIG. 11, the number of odd bit lines and even bit lines is shown to be 6 each. However, the number of odd bit lines and even bit lines is not limited to this, and more than one odd bit line and one even bit line may be provided.

Referring to FIGS. 12 and 13 , the first and second sub common sources SCSL1 and SCSL2 may be formed on the substrate 10 . Substrate 10 may include a bulk silicon substrate. The bulk silicon substrate may include other semiconductor materials such as group III, group IV, and/or group V elements. The first and second sub common sources SCSL1 and SCSL2 may be well regions formed by implanting p-type or n-type impurities into the substrate 10 .

The first sub common source (SCSL1) may include a plurality of segments (SCSL1-1, SCSL1-2, and SCSL1-3). Hereinafter, for convenience of explanation, the segments SCSL1-1, SCSL1-2, and SCSL1-3 included in the first sub common source SCSL1 will be defined as first segments. Each of the first segments (SCSL1-1, SCSL1-2, and SCSL1-3) may extend in the word line direction (WLD) and be electrically connected to each other.

The second sub common source (SCSL2) may include a plurality of segments (SCSL2-1 and SCSL2-2). Hereinafter, for convenience of explanation, the segments SCSL2-1 and SCSL2-2 included in the second sub common source SCSL2 will be defined as second segments. Each of the second segments SCSL2-1 and SCSL2-2 may extend in the word line direction WLD and be electrically connected to each other.

The first segments (SCSL1-1, SCSL1-2, SCSL1-3) and the second segments (SCSL2-1, SCSL2-2) may be alternately arranged along the bit line direction (BLD).

A separation structure 11 may be formed on the substrate 10 between the first segments SCSL1-1, SCSL1-2, and SCSL1-3 and the second segments SCSL2-1 and SCSL2-2. The separation structure 11 may be an insulating film. Alternatively, the separation structure 11 may be an impurity region doped with a conductivity type opposite to that of the first and second sub common sources SCSL1 and SCSL2. The separation structure 11 may have a line shape extending in the word line direction (WLD) and include first segments (SCSL1-1, SCSL1-2, SCSL1-3) and second segments (SCSL2-1, SCSL2). -2) may be alternately arranged along the bit line direction (BLD) with the separation structure 11 in between.

Unlike the embodiment shown in FIGS. 12 and 13, a semiconductor layer may be further formed between the substrate 10 and the memory block BLK, and the first segments SCSL1-1, SCSL1-2, and SCSL1- 3), the second segments SCSL2-1 and SCSL2-2 and the separation structure 11 may be formed in the semiconductor layer. Additionally, a circuit layer may be formed between the semiconductor substrate 10 and the semiconductor layer. Peripheral circuits may be formed in the circuit layer. The peripheral circuit may include the row decoder 120, page buffer 130, input/output buffer 140, control logic 150, voltage generator 160, and source driver 170 shown in FIG. 1. The embodiment including the semiconductor layer and the circuit layer may be understood by referring to the embodiment previously described with reference to FIG. 8 .

Referring again to FIGS. 12 and 13 , the memory block BLK may have a three-dimensional structure. The memory block BLK may include a source select line (SSL), a plurality of word lines (WL), a drain select line (DSL), and a plurality of channel films (CH) stacked on the substrate 10. there is.

The channel films (CH) may penetrate the selection lines (SSL, DSL) and word lines (WL). In this embodiment, the channel films CH have a pillar structure that completely fills the center area. However, the present invention is not limited to this, and the channel films CH may have a tube shape with an open central region. In this case, the open central region may be filled with an insulating film. A memory layer (M) may be formed on the surfaces of the channel layers (CH). The memory layer M may include a tunnel insulating layer, a charge storage layer, and a charge blocking layer, or may include some of these. Here, the charge storage film may include at least one of a floating gate such as a polysilicon film that stores charges, a trap film such as a nitride film that traps charges, and nano dots. For reference, the memory layer M may include a phase change material instead of a charge storage layer. Additionally, a memory layer (not shown) may be additionally formed, interposed between the memory layer M and the word lines WL and surrounding the upper and lower surfaces of the word lines WL. Here, the additionally formed memory layer may include a tunnel insulating layer, a charge storage layer, and a charge blocking layer, or may include some of them. Additionally, the charge blocking film of the additionally formed memory film may be a stacked film of an oxide film and a high dielectric constant material film.

A source selection transistor (SST) is formed in the area where the source selection line (SSL) surrounds the channel film (CH), and memory cells (MC) are formed in the area where the word lines (WL) surround the channel film (CH). A drain select transistor (DST) is formed in a portion where the drain select line (DSL) surrounds the channel film (CH). By the above structure, a plurality of cell strings (CS) each including a drain select transistor (DST), memory cells (MC), and source select transistor (SST) formed along each of the channel films (CH) are configured. You can.

The memory block BLK may include a first sub-block (Sub-block1) corresponding to the first sub-common source (SCSL1) and a second sub-block (Sub-block2) corresponding to the second sub-common source (SCSL2). You can. The first sub-block (Sub-block1) and the second sub-block (Sub-block2) may be disposed on top of the sub common sources (SCSL1 and SCSL2) corresponding to each other. Accordingly, the first and second sub-blocks (Sub-block1, Sub-block2) are the first segments (SCSL1-1, SCSL1-2, SCSL1-3) and the first sub-common source (SCSL1). 2 It may be arranged along the bit line direction (BLD) in the same way as the second segments (SCSL2-1 and SCSL2-2) included in the sub-common source (SCSL2).

The bit lines (BLo1, BLe1, BLo2, BLe2) may include odd bit lines (BLo1, BLo2) and even bit lines (BLe1, BLe2).

The odd bit lines (BLo1, BLo2) are electrically connected to the cell strings (CS) included in the first sub-block (Sub-block1), and the even bit lines ((BLe1, BLe2) are electrically connected to the cell strings (CS) included in the first sub-block (Sub-block1). It can be electrically connected to the cell strings (CS) included in (Sub-block2). That is, cell strings connected to the same bit line can be included in the same sub-block, and cell strings included in different sub-blocks can be connected to each other. Can be connected to other bit lines.

The source select line (SSL), word lines (WL), and drain select line (DSL) include first segments (SCSL1-1, SCSL1-2, SCSL1-3) and second segments (SCSL2-1, SCSL2- 2) Slits (SLIT) may be formed to expose the source selection line (SSL), word lines (WL), and drain selection line (DSL) may be divided into a plurality of slits (SLIT). .

Source lines SL1 and SL2 may be further formed on the memory block BLK. The source lines SL1 and SL2 may be placed in a lower layer than the bit lines BLo1, BLe1, BLo2, and BLe2. Although not shown, the source lines (SL1, SL2) may be disposed on the same layer as the bit lines (BLo1, BLe1, BLo2, BLe2) or on a layer above the bit lines (BLo1, BLe1, BLo2, BLe2), or at least It may be distributed over two or more floors.

The source lines SL1 and SL2 are a first source line SL1 for providing source power to the first sub common source SCSL1 and a second source line SL1 for providing source power to the second sub common source SCSL2. It may include a line (SL2).

Among the slits SLIT formed in the memory block BLK, the first source line SL1 and the first segments are located inside the slits located on the first segments SCSL1-1, SCSL1-2, and SCSL1-3. First contact plugs CNT1 may be formed to electrically connect SCSL1-1, SCSL1-2, and SCSL1-3.

Among the slits SLIT formed in the memory block BLK, the inside of the slits located on the second segments SCSL2-1 and SCSL2-2 include the second source line SL2 and the second segments SCSL2-1. , Second contact plugs (CNT2) that electrically connect SCSL2-2) may be formed.

Figure 14 is a block diagram schematically showing a memory system including a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 14 , a memory system 600 according to an embodiment of the present invention may include a non-volatile memory device 620 and a memory controller 610.

The non-volatile memory device 620 is comprised of the non-volatile memory device described above and may be operated in the manner described above. The memory controller 610 will be configured to control the non-volatile memory device 620. By combining the non-volatile memory device 620 and the memory controller 610, it may be provided as a memory card or a solid state disk (SSD). SRAM 611 is used as an operating memory of the processing unit 612. The host interface 613 includes a data exchange protocol for a host connected to the memory system 600.

The error correction block 614 detects and corrects errors included in data read from the non-volatile memory device 620.

Memory interface 615 interfaces with the non-volatile memory device 620 of the present invention. The processing unit 612 performs various control operations for data exchange of the memory controller 610.

Although not shown in the drawing, it is common knowledge in the field that the memory system 600 according to the present invention may be further provided with a ROM (not shown) that stores code data for interfacing with a host. It is self-evident to those who have mastered it. The non-volatile memory device 620 may be provided in a multi-chip package consisting of a plurality of flash memory chips.

The memory system 600 of the present invention described above can be provided as a highly reliable storage medium with a low probability of error occurrence. In particular, the non-volatile memory device of the present invention can be provided in a memory system such as a semiconductor disk device (Solid State Disk (hereinafter referred to as SSD)), which has been actively studied recently. In this case, the memory controller 610 will be configured to communicate with the outside (e.g., a host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, and IDE. will be.

Figure 15 is a block diagram schematically showing a computing system including a non-volatile memory device according to an embodiment of the present invention.

Referring to FIG. 15, the computing system 700 according to the present invention includes a microprocessor 720, a RAM 730, a user interface 740, a baseband chipset, and It may include the same modem 750 and memory system 710. If the computing system 700 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 700 is required. Additional information will be provided. Although not shown in the drawing, it is common in this field that the computing system 700 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), a mobile DRAM, etc. It is self-evident to those who have acquired knowledge. The memory system 710 may, for example, constitute a solid state drive/disk (SSD) that uses non-volatile memory to store data. Alternatively, the memory system 710 may be provided as fusion flash memory (eg, one-NAND flash memory).

The embodiments of the present invention described above are not only implemented through devices and methods, but may also be implemented through programs that realize functions corresponding to the configurations of the embodiments of the present invention or recording media on which the programs are recorded. Any expert in the technical field to which the present invention pertains can easily implement the present invention based on the description of the above-described embodiments.

Although the detailed description of the present invention described above has been described with reference to embodiments of the present invention, those skilled in the art or have ordinary knowledge in the relevant technical field will understand the spirit and scope of the present invention as described in the claims to be described later. It will be understood that various modifications and changes can be made to the present invention without departing from the technical scope.

Claims (20)

A memory block including a plurality of cell strings each including memory cells electrically connected to word lines stacked on a substrate;
a plurality of sub-common sources electrically connected to one end of the cell strings; and
A plurality of bit lines electrically connected to other ends of the cell strings,
The memory block includes a plurality of sub-blocks each corresponding to the plurality of sub-common sources, and among the cell strings, cell strings electrically connected to the same bit line are included in the same sub-block,
Each of the plurality of cell strings includes a first selection transistor connected to one of the plurality of bit lines, a second selection transistor connected to one of the plurality of sub-common sources, and a space between the first selection transistor and the second selection transistor. Includes a plurality of memory cells connected in series,
Cell strings included in a single sub-block are commonly connected to one corresponding sub-common source, and cell strings included in different sub-blocks are connected to different sub-common sources.
The plurality of bit lines are grouped into a plurality of bit line groups corresponding to the plurality of sub blocks, and cell strings included in a single sub block are connected to bit lines included in one bit line group and are connected to different sub blocks. Cell strings included in a block are connected to bit lines included in different bit line groups,
A non-volatile memory device in which, during an erase operation, an erase voltage is applied to a sub-common source corresponding to a selected sub-block, and an unselected erase voltage is applied to a sub-common source corresponding to an unselected sub-block. delete delete ◈Claim 4 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 1, wherein the cell strings included in different sub-blocks are electrically connected to different bit lines. ◈Claim 5 was abandoned upon payment of the setup registration fee.◈ The method of claim 1, wherein among the cell strings, cell strings included in the same sub-block are electrically connected to the same sub-common source, and cell strings included in different sub-blocks are electrically connected to different sub-common sources. Non-volatile memory device. ◈Claim 6 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 1, wherein the sub-common sources are arranged in a word line direction. ◈Claim 7 was abandoned upon payment of the setup registration fee.◈ The method of claim 1, wherein the bit lines include at least one odd bit line and at least one even bit line,
The sub blocks include a first sub block including cell strings electrically connected to the odd bit line; and
A non-volatile memory device including a second sub-block including cell strings electrically connected to the even bit line. ◈Claim 8 was abandoned upon payment of the setup registration fee.◈ The method of claim 7, wherein the sub common sources are a first sub common source electrically connected to cell strings of the first sub block; and
A second sub common source electrically connected to the cell strings of the second sub block. ◈Claim 9 was abandoned upon payment of the setup registration fee.◈ 9. The method of claim 8, wherein the first sub-common source includes a plurality of first segments and the second sub-common source includes a plurality of second segments,
The first segments and the second segments are arranged alternately along the bit line direction. ◈Claim 10 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 9, further comprising slits passing through the memory block to expose the first segments and the second segments. ◈Claim 11 was abandoned upon payment of the setup registration fee.◈ The memory device of claim 10, further comprising: a first source line and a second source line disposed on an upper portion of the memory block;
First contact plugs disposed inside the slits exposing the first segments and electrically connecting the first segments and the first source line; And
A non-volatile memory device further comprising second contact plugs disposed within the slits exposing the second segments and electrically connecting the second segments to the second source line. ◈Claim 12 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 1, wherein the sub-common sources are disposed below the memory block and the bit lines are disposed above the memory block. ◈Claim 13 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 12, wherein the sub-common sources are formed on the substrate or a semiconductor layer disposed between the substrate and the memory block. ◈Claim 14 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 13, wherein the sub-common sources include well regions formed in the substrate or the semiconductor layer. ◈Claim 15 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 13, further comprising an isolation structure formed on the substrate or the semiconductor layer between the sub-common sources. ◈Claim 16 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 1, wherein the sub-common sources and the bit lines are disposed on an upper portion of the memory block. ◈Claim 17 was abandoned upon payment of the setup registration fee.◈ The non-volatile memory device of claim 16 , wherein the sub-common sources include wires extending in a length direction of the bit lines. a memory block electrically connected to word lines stacked on a substrate;
a first sub common source and a second sub common source arranged in the direction of the word lines; and
It is formed on the memory block and includes a plurality of first bit lines corresponding to the first sub common source and a plurality of second bit lines corresponding to the second sub common source,
The memory block includes a first sub-block including a plurality of first cell strings electrically connected between the first bit lines and the first sub-common source; and
A second sub-block including a plurality of second cell strings electrically connected between the second bit lines and the second sub common source,
Each of the plurality of first cell strings includes a first selection transistor connected to one of the plurality of first bit lines, a second selection transistor connected to the first sub common source, the first selection transistor and the second selection transistor. It includes a plurality of first memory cells connected in series therebetween,
Each of the plurality of second cell strings includes a third selection transistor connected to one of the plurality of second bit lines, a fourth selection transistor connected to the second sub common source, the third selection transistor, and the fourth selection transistor. It includes a plurality of second memory cells connected in series therebetween,
The plurality of first cell strings are commonly connected to the first sub common source, and the plurality of second cell strings are commonly connected to the second sub common source,
During an erase operation, an erase voltage is applied to a sub-common source corresponding to a selected sub-block among the first and second sub-blocks, and an unselected erase voltage corresponds to an unselected sub-block among the first and second sub-blocks. A non-volatile memory device applied to a sub-common source. bit lines including a plurality of odd bit lines and a plurality of even bit lines;
a memory block disposed below the bit lines; and
It includes a first sub-common source and a second sub-common source disposed below the memory block and arranged in the direction of the bit lines,
The memory block is a first sub-block including a plurality of first cell strings electrically connected between the plurality of odd bit lines and the first sub common source; And
A second sub-block including a plurality of second cell strings electrically connected between the plurality of even bit lines and the second sub common source,
Each of the plurality of first cell strings includes a first selection transistor connected to one of the plurality of odd bit lines, a second selection transistor connected to the first sub common source, and a space between the first selection transistor and the second selection transistor. Includes a plurality of first memory cells connected in series to,
Each of the plurality of second cell strings includes a third selection transistor connected to one of the plurality of even bit lines, a fourth selection transistor connected to the second sub common source, and a space between the third selection transistor and the fourth selection transistor. It includes a plurality of second memory cells connected in series to,
The plurality of first cell strings are commonly connected to the first sub common source, and the plurality of second cell strings are commonly connected to the second sub common source,
During an erase operation, an erase voltage is applied to a sub-common source corresponding to a selected sub-block among the first and second sub-blocks, and an unselected erase voltage corresponds to an unselected sub-block among the first and second sub-blocks. A non-volatile memory device applied to a sub-common source. ◈Claim 20 was abandoned upon payment of the setup registration fee.◈ 20. The method of claim 19, wherein the first sub-common source includes a plurality of first segments and the second sub-common source includes a plurality of second segments,
The first segments and the second segments are arranged alternately along the bit line direction.

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