KR102630023B1 - delay interpolator - Google Patents

Abstract

The delay interpolator includes pull-up devices, each of which is coupled between a supply rail and a node, and pull-down devices, each of which is coupled between a node and ground. . The delay interpolator also includes a first control circuit coupled to the pull-up devices, the first control circuit comprising a first input configured to receive a first signal, and a second signal configured to receive a second signal delayed with respect to the first signal. It has a second input, and a control input configured to receive a first delay code. The delay interpolator further includes a second control circuit coupled to the pull-down devices, the second control circuit comprising a first input configured to receive the first signal, a second input configured to receive the second signal, and a second control circuit coupled to the pull-down devices. 2 has a control input configured to receive a delay code.

Description

delay interpolator

[0001] This patent application is entitled Regular Continuing Application No. 17/506/902, filed with the U.S. Patent and Trademark Office on October 21, 2021, and U.S. Patent and Trademark Office No. Priority and benefit are claimed to Patent Application No. 17/240,926, the entire contents of which are incorporated herein by reference as if fully set forth in their entirety below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to delay circuits, and more particularly to delay interpolators.

[0003] A delay circuit may be used to delay a signal by an adjustable (i.e., tunable) delay. Adjustable delay can be used to adjust the timing of a signal relative to another signal, for example, by delaying the signal by a corresponding amount. For example, a delay circuit may be used in a memory interface to center the edges of a clock signal used for data capture between transitions of the data signal.

[0004] A brief summary of one or more implementations is presented below to provide a basic understanding of such implementations. This summary is not a comprehensive overview of all considered implementations, and is not intended to identify key or important elements of all implementations or delineate the scope of any or all implementations. The sole purpose of this summary is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] The first aspect relates to a delay interpolator. The delay interpolator includes pull-up devices, each of which is coupled between a supply rail and a node, and pull-down devices, each of which is coupled between a node and ground. . The delay interpolator also includes a first control circuit coupled to the pull-up devices, the first control circuit comprising a first input configured to receive a first signal, and a second signal configured to receive a second signal delayed with respect to the first signal. It has a second input, and a control input configured to receive a first delay code. The delay interpolator further includes a second control circuit coupled to the pull-down devices, the second control circuit comprising a first input configured to receive the first signal, a second input configured to receive the second signal, and a second control circuit coupled to the pull-down devices. 2 has a control input configured to receive a delay code.

[0006] A second aspect relates to a method of operating a delay interpolator. The delay interpolator includes pull-up devices coupled between the supply rail and the node, and pull-down devices coupled between the node and ground. The method includes receiving a first signal, receiving a second signal delayed with respect to the first signal, inputting the first signal to a programmable number of pull-up devices based on the first delay code, - inputting a second signal to the remaining pull-up devices among the up devices, inputting a first signal to a programmable number of pull-down devices based on the second delay code, and the pull-down device and inputting a second signal to the remaining pull-down devices.

[0007] The third aspect relates to systems. The system includes a delay circuit having an input, a first output, and a second output. The system also includes a delay interpolator. The delay interpolator includes pull-up devices, each of which is coupled between a supply rail and a node, and pull-down devices, each of which is coupled between a node and ground. . The delay interpolator also includes a first control circuit coupled to the pull-up devices, the first control circuit having a first input coupled to a first output of the delay circuit and a second output of the delay circuit. and a control input configured to receive a first delay code. The delay interpolator also includes a second control circuit coupled to the pull-down devices, the second control circuit comprising: a first input coupled to a first output of the delay circuit, a second output coupled to the delay circuit and a control input configured to receive a second delay code.

[0008] Figure 1 illustrates an example of a delay circuit in accordance with certain aspects of the disclosure.
[0009] Figure 2 shows an example implementation of a coarse delay circuit in accordance with certain aspects of the present disclosure.
[0010] Figure 3 shows an example implementation of a delay device in a coarse delay circuit in accordance with certain aspects of the present disclosure.
[0011] Figure 4 shows an example implementation of a fine delay circuit in accordance with certain aspects of the present disclosure.
[0012] Figure 5 shows an example implementation of a delay device within a fine delay circuit in accordance with certain aspects of the disclosure.
[0013] Figure 6 shows an example of a delay circuit including a delay interpolator in accordance with certain aspects of the present disclosure.
[0014] Figure 7 shows an example implementation of a coarse delay circuit configured to output two delayed signals in accordance with certain aspects of the present disclosure.
[0015] Figure 8 illustrates an example implementation of a delay interpolator in accordance with certain aspects of the present disclosure.
[0016] Figure 9 shows an example implementation of a first control circuit and a second control circuit in accordance with certain aspects of the present disclosure.
[0017] Figure 10 shows an example implementation of control devices within a first control circuit and a second control circuit in accordance with certain aspects of the disclosure.
[0018] Figure 11 is a plot showing example waveforms for different delay settings in accordance with certain aspects of the present disclosure.
[0019] Figure 12 illustrates an example implementation of an output buffer in accordance with certain aspects of the disclosure.
[0020] Figure 13 shows an example implementation of switches in an output buffer in accordance with certain aspects of the present disclosure.
[0021] Figure 14 shows another example implementation of a coarse delay circuit in accordance with certain aspects of the present disclosure.
[0022] Figure 15 illustrates an example of a data interface including a delay circuit in accordance with certain aspects of the present disclosure.
[0023] Figure 16 is a flow diagram illustrating a method of operating a delay interpolator in accordance with certain aspects of the present disclosure.

[0024] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0025] Figure 1 shows an example of a delay circuit 110 in accordance with certain aspects of the present disclosure. Delay circuit 110 is configured to receive a signal at input 112, delay the signal by an adjustable (i.e., tunable) delay, and output the delayed signal at output 114. The signal may be a clock signal, a data signal, or another type of signal. In this example, the delay of delay circuit 110 is set by delay control circuit 150, as discussed further below.

[0026] The delay circuit 110 includes a coarse delay circuit 120 and a fine delay circuit 130. Coarse delay circuit 120 has an input 122 coupled to input 112 of delay circuit 110, and an output 124. The fine delay circuit 130 has an input 132 coupled to the output 124 of the delay of the coarse delay circuit 120, and an output 134 coupled to the output 114 of the delay circuit 110. . In this example, the delay of delay circuit 110 is approximately equal to the sum of the delays of coarse delay circuit 120 and the delay of fine delay circuit 130.

[0027] The coarse delay circuit 120 is configured to provide coarse adjustments of the delay of the delay circuit 110, and the fine delay circuit 130 is configured to provide fine adjustments of the delay of the delay circuit 110. More specifically, coarse delay circuit 120 allows delay control circuit 150 to adjust the delay of delay circuit 110 in coarse delay steps, and fine delay circuit 130 allows delay control circuit 150 Allows the delay of the delay circuit 110 to be adjusted into fine delay steps between coarse delay steps. In this example, one fine delay step can be given by:

(One)

here is the fine delay step, is the coarse delay step, and R is the ratio of one coarse delay step to one fine delay step, where R is greater than 1. In certain aspects, delay control circuit 150 receives a delay code and adjusts the delay of coarse delay circuit 120 and/or the delay of fine delay circuit 130 accordingly, based on the received delay code. Adjust the delay of the delay circuit 110.

[0028] In certain aspects, coarse delay circuit 120 includes multiple delay devices, one or more of the delay devices (e.g., using switches, logic gates, and/or one or more multiplexers) It may be selectively placed within the delay path of the coarse delay circuit 120 under the control of the delay control circuit 150. The delay path is coupled between input 122 and output 124 of coarse delay circuit 120. In these aspects, delay control circuit 150 adjusts the delay of coarse delay circuit 120 by controlling the number of delay devices in the delay path. The greater the number of delay devices in the delay path, the longer the delay. In this example, each of the delay devices may have a delay approximately equal to one coarse delay step. Each of the delay devices may also be referred to as a delay stage, delay unit, or other terminology.

[0029] Figure 2 shows an example implementation of a coarse delay circuit 120 in accordance with certain aspects of the present disclosure. In this example, coarse delay circuit 120 includes multiple delay devices 210-1 through 210-N arranged in a trombone configuration. Each of the delay devices 210-1 through 210-N has a respective first input 212-1 through 212-N (labeled “f _in ”), a respective first output 214-1 through 214- N) (labeled “f _out ”), respective second inputs 216-1 through 216-N (labeled “r _in ”), and respective second outputs 218-1 through 218-N. ) (labeled "r _out ").

[0030] In this example, the delay devices 210-1 through 210-N have first inputs 212-1 through 212-N and first outputs of the delay devices 210-1 through 210-N. Coupled along forward path 230 using fields 214-1 through 214-N. The delayed signal is received at input 122 of coarse delay circuit 120 and propagates along forward path 230 in direction 240 (i.e., left to right in Figure 2). In this example, first input 212-1 of delay device 210-1 is coupled to input 122 of coarse delay circuit 120. As shown in Figure 2, the first output (214-1 to 214-(N-1)) of each of the delay devices (210-1 to 210-(N-1)) is the next delay in the forward direction (240). Coupled to first inputs 212-2 through 212-N of devices 210-2 through 210-N. In this example, the first output 214-N of delay device 210-N may be coupled to the second input 216-N of delay device 210-N.

[0031] The delay devices 210-1 to 210-N also have second inputs 216-1 to 216-N and second outputs 218 of the delay devices 210-1 to 210-N. -1 to 218-N) are coupled along the return path 235. The delayed signal propagates in direction 245 (i.e., from right to left in FIG. 2) along return path 235 and is output at output 124 of coarse delay circuit 120. As shown in FIG. 2 , in this example, the second output 218-2 through 218-N of each of the delay devices 210-2 through 210-N is connected to the next delay device 210 in the return direction 245. -1 to 210-(N-1)) are coupled to the second inputs (216-1 to 216-(N-1)). The second output 218-1 of delay device 210-1 is coupled to the output 124 of coarse delay circuit 120.

[0032] In this example, each of the delay devices 210-1 through 210-N may be selectively enabled or disabled by the delay control circuit 150. When enabled, the delay device may be configured by delay control circuit 150 to operate in either the first mode or the second mode. In the first mode, the delay device passes the delayed signal from the respective first inputs (212-1 to 212-N) to the respective first outputs (214-1 to 214-N) in the forward direction (240), A delayed signal is transmitted from each second input (216-1 to 216-N) to each second output (218-1 to 218-N) in the return direction 245. In the second mode, the delay device transfers the delayed signal from the respective first inputs 212-1 to 212-N to the respective second outputs 218-1 to 218-N. Accordingly, in the second mode, the delay device routes the signal from the forward path 230 to the return path 235. In this case, the signal propagates in the forward direction 240 through delay devices located behind the delay device operating in the second mode (i.e., delay devices located to the right of the delay device operating in the second mode in Figure 2). It doesn't work.

[0033] In this example, delay control circuit 150 controls which of delay devices 210-1 through 210-N are used to route the signal from forward path 230 to return path 235. The delay of the coarse delay circuit 120 is controlled by controlling which of the delay devices 210-1 to 210-N operates in the second mode. In this example, delay control circuit 150 modifies the coarse delay circuit 120 by selecting a delay device farther down the forward path 230 to route the signal from forward path 230 to return path 235. Increases delay. This increases the delay of coarse delay circuit 120 by causing the signal to propagate through a greater number of delay devices 210-1 through 210-N. In this example, the delay control circuit 150 operates the delay devices used to route the signal from the forward path 230 to the return path 235 in a second mode and the leading delay devices (i.e. , in FIG. 2, delay devices located to the left of the delay device operating in the second mode). In this example, one coarse delay step may be equal to the sum of the delay over one delay device in the forward direction 240 and the delay over one delay device in the return direction 245.

[0034] It is noted that the individual connections between delay control circuit 150 and delay devices 210-1 through 210-N are not explicitly shown in FIG. 2.

[0035] Figure 3 shows an example implementation of a delay device 310 that may be used in a trombone configuration, in accordance with certain aspects. Delay device 310 may be used to implement each of the delay devices 210-1 through 210-N shown in FIG. 2 (e.g., each of the delay devices 210-1 through 210-N in FIG. 3 may be a separate instance of the delay device 310). In this example, delay device 310 has a first input 312, a first output 314, a second input 316, and a second output 318. The delay device 310 includes a first delay buffer 320, a second delay buffer 330, and a third delay buffer 340. First delay buffer 320 has an input 322 coupled to a first input 312 and an output 324 coupled to a first output 314 . The second delay buffer 330 has an input 332 coupled to a second input 316 and an output 334 coupled to a second output 318. The third delay buffer 340 has an input 342 coupled to the output 324 of the first delay buffer 320, and an output 344 coupled to the input 332 of the second delay buffer 330. has

[0036] In this example, delay control circuit 150 selectively enables or disables first delay buffer 320 and second delay buffer 330 via control line 350, and control line ( The third delay buffer 340 is selectively enabled or disabled through 355). In this example, delay buffers 320, 330, and 340 each delay the signal by a respective delay when enabled by delay control circuit 150, and when disabled by delay control circuit 150. It can be configured to block the signal when Each of delay buffers 320, 330, and 340 may be implemented as a tri-state inverter, NAND gate, or other type of delay buffer.

[0037] In this example, delay control circuit 150 may disable delay device 310 by disabling delay buffers 320, 330, and 340. Delay control circuit 150 may operate delay device 310 in a first mode by enabling first delay buffer 320 and second delay buffer 330 and disabling third delay buffer 340. You can. In the first mode, first delay buffer 320 delays a signal received at first input 312 on forward path 230 and outputs the delayed signal at first output 314. The second delay buffer 330 delays the signal received at the second input 316 on the return path 235 and outputs the delayed signal at the second output 318. Accordingly, in the first mode, the first delay buffer 320 delays the signal on the forward path 230 and the second delay buffer 330 delays the signal on the return path 235.

[0038] The delay control circuit 150 operates the delay device 310 in a second mode by enabling the first delay buffer 320, the second delay buffer 330, and the third delay buffer 340. You can do it. In the second mode, the third delay buffer 340 transfers the signal at the output 324 of the first delay buffer 320 on the forward path 230 to the input of the second delay buffer 330 on the return path 235. Forward to (332). Accordingly, in the second mode, delay device 310 routes the signal from forward path 230 to return path 235 through third delay buffer 340.

[0039] Figure 4 shows an example implementation of a fine delay circuit 130, in accordance with aspects of the present disclosure. In this example, the fine delay circuit 130 includes a number of delay devices 410-1 through 410-M coupled in series to form a delay line (i.e., a delay chain). As a result, the delay of the fine delay circuit 130 is approximately equal to the sum of the delays of the delay devices 410-1 to 410-M.

[0040] Delay devices 410-1 through 410-M each have a respective input 412-1 through 412-M (labeled “in”) and a respective output (labeled “out”) (414-1 to 414-M).

Input 412-1 of delay device 410-1 is coupled to input 132 of fine delay circuit 130, and output 414-M of delay device 410-M is coupled to fine delay circuit ( It is coupled to the output 134 of 130). The output (414-1 to 414-(N-1)) of each of the delay devices (410-1 to 410-(N-1)) is the input of the next delay device (410-2 to 410-N) in the delay line. Coupled to (412-2 to 412-N).

[0041] In certain aspects, the delay control circuit 150 controls the delay of the fine delay circuit 130 by adjusting the delay of each of the delay devices 410-1 through 410-M. For example, each of delay devices 410-1 through 410-M may include a variable capacitive load, where delay control circuit 150 controls each delay device 410 by adjusting the individual capacitive load. Adjust the delay from -1 to 410-M). In this example, the larger the capacitive load of the delay device, the longer the delay of the delay device.

[0042] FIG. 5 shows an example implementation of a delay device 510 that may be used in the fine delay circuit 130, in accordance with certain aspects. Delay device 510 may be used to implement each of the delay devices 410-1 through 410-M shown in FIG. 4 (e.g., each of the delay devices 410-1 through 410-M shown in FIG. 5 may be a separate instance of the delay device 510). In this example, delay device 510 has an input 512 and an output 514. Delay device 510 includes a delay buffer 520 and a variable capacitor 530. Delay buffer 520 has an input 522 coupled to input 512 of delay device 510 and an output 524 coupled to output 514 of delay device 510 . Delay buffer 520 may be implemented as an inverter or another type of delay buffer.

[0043] The variable capacitor 530 is coupled to the output 524 of the buffer 520. In this example, variable capacitor 530 has an adjustable (i.e., tunable) capacitance that is controlled by delay control circuit 150. This allows delay control circuit 150 to adjust the capacitive load at the output 524 of delay buffer 520 (and therefore the delay of delay device 510) by adjusting the capacitance of variable capacitor 530. The larger the capacitance of capacitor 530, the larger the capacitive load and therefore the longer the delay of delay device 510.

[0044] In this example, coarse delay and fine delay are adjusted using different circuit delay techniques. The delay control circuit 150 adjusts the delay of the coarse delay circuit 120 by adjusting the number of delay devices 210-1 to 210-N in the delay path of the coarse delay circuit 120, and the delay device The delay of the fine delay circuit 130 is adjusted by adjusting the capacitive loads of fields 410-1 to 410-M. Because different circuit delay techniques are used for coarse delay adjustments and fine delay adjustments, changes in one coarse delay step and changes in one fine delay step due to process voltage temperature (PVT) variations. There is no relationship between them. As a result, the ratio of one coarse delay step to one fine delay step may not be well controlled, which may cause conversion errors when switching from fine delay to coarse delay.

[0045] Figure 6 shows an example delay circuit 610 in accordance with certain aspects of the present disclosure. Delay circuit 610 is configured to receive a signal at input 612, delay the signal by an adjustable (i.e., tunable) delay, and output the delayed signal at output 614. The signal may be a clock signal, a data signal, or another type of signal. In this example, the delay of delay circuit 610 is set by delay control circuit 650, as discussed further below.

[0046] The delay circuit 610 includes a coarse delay circuit 620 and a delay interpolator 630. Coarse delay circuit 620 has an input 622 coupled to input 612 of delay circuit 610, a first output 624, and a second output 626. Delay interpolator 630 has a first input 634 coupled to a first output 624 of coarse delay circuit 620 and a second input 634 coupled to a second output 626 of coarse delay circuit 620. It has an input 636, and an output 638 coupled to an output 614 of delay circuit 610.

Coarse delay circuit 620 is configured to provide coarse adjustments of the delay of delay circuit 610, and delay interpolator 630 is configured to provide fine adjustments of the delay of delay circuit 610. More specifically, coarse delay circuit 620 allows delay control circuit 650 to adjust (i.e., tune) the delay of delay circuit 610 into coarse delay steps, and delay interpolator 630 Delay control circuit 650 allows the delay of delay circuit 610 to be adjusted in fine delay steps between coarse delay steps. The relationship between one coarse delay step and one fine delay step can be defined by equation (1) discussed above.

[0048] In the example of FIG. 6, coarse delay circuit 620 is configured to receive a delayed signal at input 622. The coarse delay circuit 620 is configured to delay the received signal by an adjustable (i.e., tunable) delay under the control of the delay control circuit 650 to provide the first signal. Coarse delay circuit 620 is also configured to provide a second signal by delaying the received signal by an adjustable (i.e., tunable) delay and an additional delay, wherein the second signal is delayed by an additional delay relative to the first signal. do. The coarse delay circuit 620 is configured to output a first signal at the first output 624 and a second signal at the second output 626. Accordingly, each of the first signal and the second signal is a delayed version of the received signal, where the second signal is delayed by an additional delay relative to the first signal. The first signal may also be referred to as an 'early' signal, since it is earlier than the second signal by an additional delay, and the second signal is delayed by an additional delay relative to the first signal, so the second signal is It may also be referred to as a “late” signal. The received signal is input to the coarse delay circuit 620 and may therefore also be referred to as an input signal.

[0049] In certain aspects, the coarse delay circuit 620 is configured to delay the second signal with respect to the first signal by one coarse delay step. In one example, delay control circuit 650 may be configured to control coarse delay circuit 620 (e.g., using a delay control signal to control switches, logic gates, and/or one or more multiplexers of coarse delay circuit 620). The adjustable (i.e., tunable) delay of the first signal can be adjusted (i.e., tuned) by controlling the number of delay devices in the delay path between the input 622 and the first output 624. In this example, coarse delay circuit 620 receives a delay control signal from delay control circuit 650 and adjusts the adjustable (i.e., tunable) delay to a multiple of one coarse delay step based on the delay control signal. (i.e. tune). The multiple may be an integer greater than 1. In this example, coarse delay circuit 620 may provide the second signal by delaying the first signal with an additional delay device having a delay of one coarse delay step. Accordingly, in this example, the delay of the second signal tracks changes in the delay of the first signal, while maintaining a delay of one coarse delay step between the second signal and the first signal.

[0050] Delay interpolator 630 is configured to receive a first signal at a first input 634 and a second signal at a second input 636. Interpolator 630 is configured to interpolate between the first signal and the second signal to produce a delay that is a fraction of the delay between the first signal and the second signal. For the example where the delay between the first signal and the second signal is equal to one coarse delay step, interpolator 630 generates a delay that is a fraction of one coarse delay step. In certain aspects, delay control circuit 650 controls the fine delay of delay circuit 610 by controlling the interpolation of delay interpolator 630 (e.g., using a digital delay code).

[0051] The delay interpolator 630 allows the ratio of one coarse delay step to one fine delay step to be more precisely controlled compared to the delay circuit 110 of FIG. 1. This means that the interpolation between the first and second signals by the delay interpolator 630 changes the delay between the first and second signals caused by changes in the coarse delay circuit 620 due to PVT variations. This is because it tracks steps (e.g., one coarse delay step). As a result, the fine delay provided by the interpolation is limited by changes in delay between the first and second signals caused by changes in the coarse delay circuit 620 due to PVT variations (e.g., one coarse delay step), resulting in more precise control of the ratio of one coarse delay step to one fine delay step across PVT variations.

[0052] Figure 7 shows an example implementation of coarse delay circuit 620 in accordance with certain aspects. In this example, coarse delay circuit 620 includes delay devices 210-1 through 210-N coupled in a trombone configuration. First input 212-1 of delay device 210-1 is coupled to input 612 of coarse delay circuit 620. Delay control circuit 650 controls delay device 210 by selecting a delay device in a trombone configuration to be used to route the signal from forward path 230 to return path 235, as discussed above with reference to FIG. Controls the delay at the second output (218-1) of -1). In this example, delay control circuit 650 adjusts the delays of the first and second signals by selecting a delay device in a trombone configuration used to route the signal from forward path 230 to return path 235 ( In other words, tuning).

[0053] In this example, coarse delay circuit 620 also includes a first delay device 710, a second delay device 720, and a third delay device 730. Each of delay devices 710, 720, and 730 may be structurally identical or similar to a delay device in a trombone configuration (e.g., implemented as example delay device 310 shown in FIG. 3). In this example, each of delay devices 710, 720, and 730 may be configured to operate in a first mode.

[0054] In this example, the first input 712 of the first delay device 710 is coupled to the second output 218-1 of the delay device 210-1, and the first delay device 710 The first output 714 of is coupled to the second input 716 of the first delay device 710, and the second output 718 of the first delay device 710 is coupled to the coarse delay circuit 620. Coupled to the first output 624. The first delay device 710 receives a signal from the second output 218-1 of the delay device 210-1 and delays the signal by one coarse delay step to produce the first output of the coarse delay circuit 620 ( The first signal is provided to 624).

[0055] In this example, the first input 722 of the second delay device 720 is coupled to the second output 218-1 of the delay device 210-1, and the second delay device 720 The first output 724 of is coupled to the first input 732 of the third delay device 720, and the first output 734 of the third delay device 730 is coupled to the first input 732 of the third delay device 730. coupled to the second input 736, the second output 738 of the third delay device 730 is coupled to the second input 726 of the second delay device, and the second delay device 720 The second output 728 of is coupled to the second output 626 of the coarse delay circuit 620. Second delay device 720 receives a signal from second output 218-1 of delay device 210-1. The second delay device 720 and the third delay device 730 delay the signal by two coarse delay steps to provide a second signal at the second output 626 of the coarse delay circuit 620.

Accordingly, in this example, the first signal delays the signal from the second output 218-1 of delay device 210-1 by one coarse delay step using first delay device 710. and the second signal is provided by the second output 218-1 of the delay device 210-1 by two coarse delay steps using the second delay device 720 and the third delay device 730. It is provided by delaying the signal from. As a result, the delay between the first and second signals is one coarse delay step in this example.

[0057] It should be appreciated that the coarse delay circuit 620 is not limited to a tunable delay circuit with a trombone configuration. For example, coarse delay circuit 620 may be implemented with another type of tunable delay circuit in which a second signal may be provided by delaying a first signal by one or more additional delay devices. Another example implementation of coarse delay circuit 620 is discussed below with reference to FIG. 14.

[0058] Figure 8 shows an example implementation of a delay interpolator 630, in accordance with certain aspects of the present disclosure. Delay interpolator 630 includes a plurality of pull-up devices 810-1 to 810-K, a plurality of pull-down devices 815-1 to 815-L, a capacitor 845, and an output buffer 860. Includes.

[0059] Each of the pull-up devices 810-1 through 810-K is coupled between a node 830 and a voltage supply rail 870, where the voltage supply rail 870 provides a supply voltage (Vdd). to provide. As discussed further below, each of pull-up devices 810-1 through 810-K pulls node 830 high (e.g., pulls node 830 high) when the pull-up device is turned on. It is configured to pull to Vdd). In the example of Figure 8, each of the pull-up devices 810-1 through 810-K includes an individual transistor 820-1 through 820-K (e.g., an individual p-type field effect transistor (PFET)). Includes. In an example where each of the transistors 820-1 to 820-K is implemented as a PFET, when the gate of the individual transistor 820-1 to 820-K is driven low (e.g., approximately ground), the pull-up device Each of fields 810-1 to 810-K is turned on. In this example, the source of each of transistors 820-1 through 820-K is coupled to supply rail 870, and the drain of each of transistors 820-1 through 820-K is coupled to node 830. It rings.

[0060] Each of the pull-down devices 815-1 to 815-L is coupled between the node 830 and ground. As discussed further below, each of pull-down devices 815-1 through 815-L pulls node 830 low (e.g., pulls node 830 low) when the pull-down device is turned on. It is configured to pull to ground. In the example of Figure 8, each of the pull-down devices 815-1 through 815-L includes an individual transistor 825-1 through 825-L (e.g., an individual n-type field effect transistor (NFET)). Includes. In an example where each of the transistors 825-1 to 825-L is implemented as an NFET, when the gate of the individual transistor 825-1 to 825-L is driven high (e.g., Vdd), the pull-down devices (815-1 to 815-L) are each turned on. In this example, the drain of each of the transistors 825-1 through 825-L is coupled to node 830, and the source of each of the transistors 825-1 through 825-L is coupled to ground. The number of pull-down devices 815-1 to 815-L and the number of pull-up devices 810-1 to 810-K may be the same or different.

[0061] Capacitor 845 is coupled between node 830 and ground. Output buffer 860 has an input 862 coupled to node 830 and an output 864 coupled to output 638 of delay interpolator 630. Accordingly, in this example, output 864 of output buffer 860 provides a delayed signal at output 638 of delay interpolator 630. In the discussion below, output buffer 860 is assumed to be non-inverting. However, it should be recognized that this does not have to be the case.

[0062] Delay interpolator 630 also includes a first control circuit 840 and a second control circuit 850. The first control circuit 840 has a first input 842 coupled to a first input 634 of the delay interpolator 630, and a second input 636 of the delay interpolator 630. It has a second input (844). Accordingly, first input 842 receives a first signal and second input 844 receives a second signal. First control circuit 840 also has a control input 846 configured to receive a first delay code from delay control circuit 650. First control circuit 840 is also coupled to pull-up devices 810-1 through 810-K. In an example where each of the pull-up devices 810-1 through 810-K includes individual transistors 820-1 through 820-K, the first control circuit 840 includes transistors 820-1 through 820. -K) Coupled to each gate.

[0063] In one example, the first control circuit 840 uses pull-up devices 810-1 through 810-K to output 638 of the delay interpolator 630 based on the first delay code. ) to control the fine delay of the rising edge. In this example, the first control circuit 840 may direct a programmable number (n) of pull-up devices 810-1 to 810-K based on a first delay code to receive the input at the first input 842. Input the first signal, and the remaining pull-up devices among the pull-up devices (810-1 to 810-K) (i.e., K-n pull-up devices (810-1 to 810-K), K is configured to input the second signal received at the second input 844 to the total number of pull-up devices (810-1 to 810-K). In this example, the delay interpolation is the number n of pull-up devices 810-1 to 810-K driven by the first signal and the number n of pull-up devices 810-K driven by the second signal. This is achieved by controlling the number (i.e. K-n) from 1 to 810-K). Delay interpolation is performed by the first control circuit 840 increasing the number (n) of the pull-up devices (810-1 to 810-K) driven by the first signal (i.e., increasing the number (n) ) By inputting the first signal to the pull-up devices (810-1 to 810-K)), the fine delay of the rising edge is reduced and the pull-up devices (810-1 to 810) driven by the first signal -Increasing the fine delay of the rising edge by reducing the number (n) of (K) (i.e., by inputting the first signal to a smaller number (n) of pull-up devices 810-1 to 810-K) Make it possible to do it. In this example, the programmable number (n) is the number of pull-up devices 810-1 to 810-K through which the first control circuit 840 inputs the first signal based on the first delay code.

[0064] The second control circuit 850 has a first input 852 coupled to a first input 634 of the delay interpolator 630 and a second input 636 coupled to the delay interpolator 630. It has a second input 854 that is ringed. Accordingly, first input 852 receives a first signal and second input 854 receives a second signal. Second control circuit 850 also has a control input 856 configured to receive a second delay code from delay control circuit 650. The second control circuit 850 is also coupled to the pull-down devices 815-1 through 815-L. In the example where each of the pull-down devices 815-1 through 815-L includes individual transistors 825-1 through 825-L, the second control circuit 850 includes the transistors 825-1 through 825. -L) Coupled to each gate.

[0065] In one example, the second control circuit 850 uses the pull-down devices 815-1 through 815-L to control the output 638 of the delay interpolator 630 based on the second delay code. ), you can control the fine delay of the falling edge. In this example, the second control circuit 850 connects the first signal received at the first input 852 to a programmable number (n) of pull-down devices 815-1 to 815 based on the second delay code. -L), and the second signal received at the second input 854 is connected to the remaining pull-down devices (i.e., L-m pull-down devices) among the pull-down devices 815-1 to 815-L. devices 815-1 to 815-L, where L is the total number of pull-down devices 815-1 to 815-L). In this example, the delay interpolation is the number (m) of pull-down devices 815-1 to 815-L driven by the first signal and the pull-down devices 815-L driven by the second signal. This is achieved by controlling the number (i.e. L-m) from 1 to 815-L). Delay interpolation is performed by the second control circuit 850 increasing the number (m) of the pull-down devices (815-1 to 815-L) driven by the first signal (i.e., increasing the number (m) ) By inputting the first signal to the pull-down devices (815-1 to 815-L)), the fine delay of the falling edge is reduced, and the pull-down devices (815-1) driven by the first signal to 815-L) by reducing the number (m) of the falling edge (i.e., by inputting the first signal to a smaller number (m) of pull-down devices 815-1 to 815-L). allows to increase. In this example, the programmable number (m) is the number of pull-down devices 815-1 to 815-L through which the second control circuit 850 inputs the first signal based on the second delay code.

[0066] In this example, the first control circuit 840 controls the input of the first signal and the second signal to the pull-up devices 810-1 through 810-K based on the first delay code and , and the second control circuit 850 controls the input of the first signal and the second signal to the pull-down devices 815-1 to 815-L based on the second delay code. Accordingly, first control circuit 840 and second control circuit 850 achieve a fine delay of the rising edge at output 638 and output 638 by using different codes for the first delay code and the second delay code. Allows the fine delay of the falling edge in to be adjusted independently. This feature can be used to adjust the duty cycle of the delayed signal at output 638, as discussed further below. For applications where duty cycle adjustment is not required, the same code may be used for the first and second delay codes (i.e., the first and second delay codes may be the same).

[0067] In this example, the first signal and the second signal are input to the pull-up devices 810-1 through 810-K through control paths within the first control circuit 840. The control paths may include logic gates that control the input of the first signal and the second signal to the pull-up devices 810-1 to 810-K based on the first delay code. An example implementation of the control paths of first control circuit 840 is discussed below with reference to FIG. 10 . The control paths may be non-inverting or inverting (i.e., inverting the first signal and/or the second signal before being input to the pull-up devices 810-1 through 810-K).

[0068] Also, in this example, the first signal and the second signal are input to the pull-down devices 815-1 through 815-L through control paths within the second control circuit 850. The control paths may include logic gates that control the input of the first signal and the second signal to the pull-down devices 815-1 to 815-L based on the second delay code. An example implementation of the control paths of the second control circuit 850 is discussed below with reference to FIG. 10 . The control paths may be non-inverting or inverting (i.e., inverting the first signal and/or the second signal before being input to the pull-down devices 815-1 through 815-L).

[0069] Accordingly, the first control circuit 840 and the second control circuit 850 include pull-up devices 810-1 to 810-K and pull-down devices 815-1 to 815-L. Provides separate control paths for . The separate control paths help prevent glitching at the output 638 of delay interpolator 630 for changes in the first delay code and/or the second delay code.

[0070] Figure 9 shows an example implementation of a first control circuit 840 in accordance with certain aspects. In this example, the first control circuit 840 includes a number of control devices 910-1 through 910-K, each of the control devices 910-1 through 910-K comprising pull-up devices ( It is configured to control the input of the first signal and the second signal to each pull-up device among (810-1 to 810-K).

[0071] In this example, each of the control devices 910-1 through 910-K has a respective first input coupled to the first input 842 of the first control circuit 840 to receive a first signal. (912-1 through 912-K) and respective second inputs (916-1 through 916-K) coupled to the second input (844) of the first control circuit (840) to receive the second signal. have Each of the control devices 910-1 through 910-K also has a respective control input 914-1 through 914-K, and a respective pull-up among the pull-up devices 810-1 through 810-K. It has respective outputs 918-1 through 918-K coupled to the device (e.g., gates of respective transistors 820-1 through 820-K). In this example, the first delay code may be a thermometer code d1<K-1:0>, where the thermometer code d1<K-1:0> includes a number of bits, where each bit is It is used to control the input of each pull-up device among the pull-up devices 810-1 to 810-K. In this example, the control inputs 914-1 through 914-K of each of the control devices 910-1 through 910-K input individual bits of the bits of the thermometer code d1<K-1:0>. configured to receive. For example, control input 914-1 of control device 910-1 receives bit d1<0> of thermometer code d1<K-1:0>.

[0072] In operation, each of the control devices 910-1 to 910-K operates an individual pull-up device ( 810-1 to 810-K) and is configured to input a first signal or a second signal. For example, each of the control devices 910-1 to 910-K inputs a first signal to an individual pull-up device when each bit has a first logic value and each bit has a second logic value. It may be configured to input a second signal to each pull-up device when it has a value. For example, the first logic value may be 1 and the second logic value may be 0, or vice versa. In this example, the first control circuit 840 operates when all bits of the thermometer code d1<K-1:0> have a first logic value (i.e., the first signal is transmitted to the pull-up devices 810 -1 to 810-K) all entered) sets the minimum delay.

[0073] Figure 9 also shows an example implementation of the second control circuit 850 in accordance with certain aspects. In this example, the second control circuit 850 includes multiple control devices 920-1 through 920-L, each of the control devices 920-1 through 920-L comprising pull-down devices ( It is configured to control the input of the first signal and the second signal to each pull-down device among (815-1 to 815-L).

[0074] In this example, each of the control devices 920-1 through 920-L has a respective first input coupled to the first input 852 of the second control circuit 850 to receive a first signal. (922-1 through 922-L), and respective second inputs (926-1 through 926-L) coupled to second inputs (854) of second control circuit (850) to receive a second signal. have Each of the control devices 920-1 through 920-L also has a respective control input 924-1 through 924-L, and a respective pull-down input of the pull-down devices 815-1 through 815-L. It has respective outputs 928-1 through 928-L (e.g., gates of respective transistors 825-1 through 825-L) coupled to the device. In this example, the second delay code is the thermometer code d2. <L-1:0>), and the thermometer code (d2<L-1:0>) includes a number of bits, where each bit corresponds to the pull-down devices 815-1 to 815-L. ) is used to control the input of the individual pull-down device. In this example, the control inputs 924-1 to 924-L of each of the control devices 920-1 to 920-L are connected to the thermometer code ( d2<L-1:0>). For example, control input 924-1 of control device 920-1 is configured to receive an individual bit of the bits of d2<L-1. :0>) bit (d2<0>) is received.

[0075] In operation, each of the control devices 920-1 to 920-L operates an individual pull-down device ( 815-1 to 815-L) and is configured to input a first signal or a second signal. For example, each of the control devices 920-1 to 920-L inputs a first signal to an individual pull-down device when each bit has a first logic value and each bit has a second logic value. It may be configured to input a second signal to the respective pull-down device when it has a value, or vice versa.

[0076] Figure 10 shows an example implementation of control device 910-1 in accordance with certain aspects. The example implementation of control device 910-1 shown in FIG. 10 may be duplicated for each of the other control devices 910-2 through 910-K.

[0077] In the example of FIG. 10, control device 910-1 includes OR gate 1040 and NAND gate 1030. OR gate 1040 has a first input 1042, a second input 1044, and an output 1046. The first input 1042 of the OR gate 1040 is coupled to the second input 916-1 of the control device 910-1 and thus receives a second signal. The second input 1044 of the OR gate 1040 is coupled to the control input 914-1 of the control device 910-1 and thus receives bit d1<0> of the first delay code. NAND gate 1030 has a first input 1032, a second input 1034, and an output 1036. The first input 1032 of the NAND gate 1030 is coupled to the output 1046 of the OR gate 1040. The second input 1034 of the NAND gate 1030 is coupled to the first input 912-1 of the control device 910-1 and thus receives the first signal. The output 1036 of NAND gate 1030 is coupled to pull-up device 810-1.

[0078] In this example, pull-up device 810-1 includes individual transistors 820-1 implemented as PFETs. Thus, in this example, pull-up device 810-1 is turned on when control device 910-1 outputs 0 to the gate of transistor 820-1, and control device 910-1 When 1 is output to the gate of the transistor 820-1, it is turned off.

[0079] When the bit (d1<0>) is 1, the OR gate 1040 outputs 1 to the NAND gate 1030. This causes the NAND gate 1030 to invert the first signal and input the inverted first signal to the pull-up device 810-1, which pulls the pull-up device 810-1 at the rising edge of the first signal. Turn on. This is because NAND gate 1030 inverts the rising edge of the first signal to a falling edge at the gate of transistor 820-1, which in this example turns on pull-up device 810-1.

[0080] When the bit (d1<0>) is 0, the OR gate 1040 outputs 1 to the NAND gate 1030 at the rising edge of the second signal. Before the rising edge of the second signal arrives, the OR gate 1040 outputs 0 to the NAND gate 1030, which causes the NAND gate 1030 to Causes 1 to be output to the gate. As a result, the pull-up device 810-1 remains turned off at the rising edge of the first signal. When the rising edge of the second signal arrives (e.g., after one coarse delay step from the rising edge of the first signal), the OR gate 1040 outputs 1 to the NAND gate 1030. This causes the output 1036 of NAND gate 1030 to be low, which turns on pull-up device 810-1 in this example. Accordingly, in this example, when bit d1<0> is 0, pull-up device 810-1 does not turn on until the rising edge of the second signal.

[0081] Accordingly, in this example, the first signal is input to the pull-up device 810-1 when the corresponding bit (d1<0>) of the first delay code is 1, and the corresponding bit of the first delay code is 1. When the bit (d1<0>) is 0, the second signal is input to the pull-up device 810-1. In this example, control device 910-1 turns pull-up device 810-1 on the rising edge of the first signal or the rising edge of the second signal depending on the bit value of bit d1<0>. To turn on, the rising edges of the first signal and the second signal are inverted.

[0082] As discussed above, the example implementation of control device 910-1 may be replicated for each of the other control devices 910-2 through 910-K, where the other control devices 910- 2 through 910-K) each receives a respective one of the bits of the first delay code and is coupled to a respective pull-up device among the pull-up devices 810-2 through 810-K.

[0083] Control device 910-1 is not limited to the example implementation illustrated in FIG. 10, and control device 910-1 may be implemented with various combinations of logic gates configured to perform the functions described herein. It must be recognized that it can be done.

[0084] Figure 10 also shows an example implementation of a control device 920-1 for controlling the input of the first and second signals to the pull-down device 815-1. The example implementation of control device 920-1 shown in FIG. 10 may be duplicated for each of the other control devices 920-2 through 920-L.

[0085] In the example of FIG. 10, control device 920-1 includes AND gate 1070 and NOR gate 1060. AND gate 1070 has a first input 1072, a second input 1074, and an output 1076. The first input 1072 of the AND gate 1070 is coupled to the second input 926-1 of the control device 920-1 and thus receives a second signal. The second input 1074 of the AND gate 1070 is coupled to the control input 924-1 of the control device 920-1 and thus receives bit d2<0> of the second delay code. NOR gate 1060 has a first input 1062, a second input 1064, and an output 1066. The first input 1062 of the NOR gate 1060 is coupled to the output 1076 of the AND gate 1070. The second input 1064 of the NOR gate 1060 is coupled to the first input 922-1 of the control device 920-1 and thus receives the first signal. The output 1066 of NOR gate 1060 is coupled to pull-down device 815-1.

[0086] In this example, pull-down device 815-1 includes individual transistors 825-1 implemented as NFETs. Thus, in this example, pull-down device 815-1 is turned on when control device 920-1 outputs a 1 to the gate of transistor 825-1, and control device 920-1 When 0 is output to the gate of transistor 825-1, it is turned off.

[0087] When the bit (d2<0>) is 0, the AND gate 1070 outputs 0 to the NOR gate 1060. This causes the NOR gate 1060 to invert the first signal and input the inverted first signal to the pull-down device 815-1, which pulls the pull-down device 815-1 at the falling edge of the first signal. Turn on. This is because NOR gate 1060 inverts the falling edge of the first signal to a rising edge at the gate of transistor 825-1, which in this example turns on pull-down device 815-1.

[0088] When the bit d2<0> is 1, the AND gate 1070 outputs 0 to the NOR gate 1060 at the falling edge of the second signal. Before the falling edge of the second signal arrives, the AND gate 1070 outputs 1 to the NOR gate 1060, which causes the NOR gate 1060 to Causes 0 to be output to the gate. As a result, the pull-down device 815-1 remains turned off on the falling edge of the first signal. When the falling edge of the second signal arrives (e.g., after one coarse delay step from the falling edge of the first signal), the AND gate 1070 outputs 0 to the NOR gate 1060. This causes the output 1066 of NOR gate 1060 to be high, which turns on pull-down device 815-1 in this example. Accordingly, in this example, when bit d2<0> is 1, the pull-down device 815-1 is not turned on until the falling edge of the second signal.

[0089] Accordingly, in this example, the first signal is input to the pull-down device 815-1 when the corresponding bit (d2<0>) of the second delay code is 0, and the corresponding bit of the second delay code is 0. When the bit (d2<0>) is 1, the second signal is input to the pull-down device 815-1. In this example, control device 920-1 turns pull-down device 815-1 on the falling edge of the first signal or the falling edge of the second signal depending on the bit value of bit d2<0>. To turn on, the falling edges of the first signal and the second signal are inverted.

[0090] As discussed above, the example implementation of control device 920-1 may be replicated for each of the other control devices 920-2 through 920-K, where the other control devices 920- 2 through 920-L) each receives a respective one of the bits of the second delay code and is coupled to a respective pull-down device among the pull-down devices 815-2 through 815-L.

[0091] Control device 920-1 is not limited to the example implementation illustrated in FIG. 10, and control device 920-1 may be implemented with various combinations of logic gates configured to perform the functions described herein. It must be recognized that it can be done.

[0092] Figure 11 shows example voltage waveforms 1110-1 through 1110-8 at node 830 for different delay settings of a first delay code and a second delay code according to certain aspects. This is a timing diagram. Waveform 1110-1 indicates that all pull-up devices 810-1 through 810-K receive the first signal and all pull-down devices 815-1 through 815-L receive the first signal. Corresponds to the delay setting. In the example shown in FIG. 11 , output buffer 860 has a rising edge threshold and a falling edge threshold, where output buffer 860 determines when a rising edge at input 862 crosses the rising edge threshold. configured to transition output 864 from 0 to 1 and configured to transition output 864 from 1 to 0 when a falling edge at input 862 crosses a falling edge threshold.

[0093] In the example of Figure 11, the rising edge of the first signal arrives at delay interpolator 630 at time t1. As shown by waveforms 1110-1 to 1110-8 in FIG. 11, the slew rate at node 830 is different for different delay settings of the first delay code. In this example, when the number of pull-up devices 810-1 through 810-K receiving the first signal is smaller, the slew rate is slower. This is because there are fewer pull-up devices 810-1 to 810-K turned on, resulting in less current charging the capacitor 845 to pull up node 830. For example, waveform 1110-8 corresponds to a delay setting such that one fewer pull-up device receives the first signal compared to waveform 1110-7. This causes waveform 1110-8 to have a slower slew rate than waveform 1110-7, as shown in Figure 11.

[0094] The corresponding rising edge of the second signal arrives at delay interpolator 630 at time t2 (e.g., one coarse delay step after the rising edge of the first signal). At this point, waveforms 1110-1 through 1110-8 for different delay settings have the same slew rate. This is because the rising edge of the second signal causes the remaining pull-up devices to turn on. In other words, after the rising edge of the second signal arrives, all of the pull-up devices 810-1 to 810-K are turned on. As shown in Figure 11, waveforms 1110-1 through 1110-8 for different delay settings cross the rising edge threshold of output buffer 860 at different times. This causes the output 864 of the output buffer 860 to transition from 0 to 1 at different times for different delay settings of the first delay code, resulting in different delays at the output 864 for different delay settings. do.

[0095] In the example of Figure 11, the different waveforms 1110-1 through 1110-8 are approximately equally spaced at the rising edge threshold. This results in approximately uniform fine delay steps at the output 864 of the output buffer 860. In this example, the uniform spacing between the different waveforms 1110-1 through 1110-8 at the rising edge threshold (and thus the approximately uniform fine delay steps at the output 864) is This is achieved by setting the rising edge threshold higher than waveforms 1110-2 to 1110-8 until the arrival of the rising edge.

[0096] In the example of Figure 11, the falling edge of the first signal arrives at delay interpolator 630 at time t3. As shown by waveforms 1110-1 to 1110-8 in FIG. 11, the slew rate at node 830 is different for different delay settings of the second delay code. In this example, when the number of pull-down devices 815-1 through 815-L receiving the first signal is smaller, the slew rate is slower. This is because there are fewer pull-down devices 815-1 to 815-L turned on, resulting in less current discharging the capacitor 845 to pull down the node 830.

[0097] The corresponding falling edge of the second signal arrives at delay interpolator 630 at time t4 (e.g., one coarse delay step after the falling edge of the first signal). At this point, waveforms 1110-1 through 1110-8 for different delay settings have the same slew rate. This is because the falling edge of the second signal causes the remaining pull-down devices to turn on. In other words, after the falling edge of the second signal arrives, all of the pull-down devices 815-1 to 815-L are turned on. As shown in Figure 11, waveforms 1110-1 through 1110-8 for different delay settings cross the falling edge threshold of output buffer 860 at different times. This causes the output 864 of the output buffer 860 to transition from 1 to 0 at different times for different delay settings of the second delay code, resulting in different delays at the output 864 for different delay settings. do.

[0098] In the example of Figure 11, the different waveforms 1110-1 through 1110-8 are approximately equally spaced at the falling edge threshold. This results in approximately uniform fine delay steps at the output 864 of the output buffer 860. In this example, the uniform spacing between the different waveforms 1110-1 through 1110-8 at the falling edge threshold (and the resulting approximately uniform fine delay steps at the output 864) is This is achieved by setting the falling edge threshold lower than waveforms 1110-2 through 1110-8, until the arrival of the falling edge.

[0099] In the example of FIG. 11, the rising edge threshold and falling edge threshold are such that the output buffer 860 can achieve approximately uniform fine delay steps at the output 864 for both rising and falling edges. let it be In the example of Figure 11, using a single threshold for output buffer 860 results in non-uniform fine delay steps. In this regard, Figure 11 shows an example of a single threshold 1120 located approximately at Vdd/2. As shown in Figure 11, waveforms 1110-1 through 1110-8 are not uniformly spaced at threshold 1120, resulting in non-uniformity for both rising and falling edges of output 864. One minute delay step results.

However, it should be noted that in other implementations, output buffer 860 may have a single threshold. In this example, output buffer 860 switches output 864 from 0 to 1 when the voltage at input 862 rises above the threshold and output (864) transitions from 0 to 1 when the voltage at input 862 falls below the threshold. 864) from 1 to 0. For example, the waveforms for different delay settings for the rising edge remain below Vdd/2 until the arrival of the second signal, and the waveforms for different delay settings for the falling edge remain above Vdd/2 until the arrival of the second signal. A single threshold may be used for the case where . In this case, output buffer 860 can achieve approximately uniform fine delay steps at output 864 for both rising and falling edges by setting the threshold to approximately Vdd/2. The advantage of using a rising edge threshold and a falling edge threshold for the output buffer 860 instead of a single threshold is that the rising edge threshold and falling edge threshold are approximately This relaxes the requirements on the waveforms to achieve uniform fine delay steps.

[0101] In the example discussed above with reference to FIG. 11, output buffer 860 transitions output 864 from 0 to 1 when a rising edge at input 862 crosses the rising edge threshold and input ( When the falling edge at 862) exceeds the falling edge threshold, output 864 switches from 1 to 0. However, it should be appreciated that output buffer 860 is not limited to this example. In other implementations, output buffer 860 may be an inverting output buffer, where output buffer 860 changes output 864 from 0 to 1 when a rising edge at input 862 crosses a rising edge threshold. and transitions output 864 from 0 to 1 when the falling edge at input 862 exceeds the falling edge threshold. In these implementations, the first control circuit 840 can be used to tune the fine delay of the falling edge at the output 638 of the delay interpolator 630, and the second control circuit 850 can be used to tune the delay interpolator 630. It can be used to tune the fine delay of the rising edge at the output 638 of 630. Typically, output buffer 860 transitions output 864 from a first logic state to a second logic state when a rising edge at input 862 crosses a rising edge threshold and a falling edge at input 862. The output 864 may be configured to transition from the second logic state to the first logic state when the edge crosses the falling edge threshold. The first logic state may be 0 and the second logic state may be 1, or vice versa.

[0102] Figure 12 shows an example implementation of an output buffer 860, in accordance with certain aspects of the disclosure. In this example, output buffer 860 includes a first inverter 1218, a second inverter 1258, and a threshold circuit 1238. First inverter 1218 has an input 1222 coupled to an input 862 of an output buffer 860, and an output 1224. The second inverter 1258 has an input 1252 coupled to the output 1224 of the first inverter 1218 and an output 1254 coupled to the output 864 of the output buffer 860. In the example of Figure 12, first inverter 1218 and second inverter 1258 are implemented using complementary inverters. More specifically, first inverter 1218 includes PFET 1225 and NFET 1220, wherein the gates of PFET 1225 and NFET 1220 are coupled to input 1222, and PFET 1225 The source of is coupled to supply rail 870, the drains of PFET 1225 and NFET 1220 are coupled to output 1224, and the source of NFET 1220 is coupled to ground. Second inverter 1258 includes PFET 1255 and NFET 1250, where the gates of PFET 1255 and NFET 1250 are coupled to input 1252 and the source of PFET 1255 is supplied. Coupled to rail 870, the drains of PFET 1255 and NFET 1250 are coupled to output 1254, and the source of NFET 1250 is coupled to ground.

[0103] In this example, the threshold circuit 1238 is configured to switch the input 1222 of the first inverter 1218 between a rising edge threshold and a falling edge threshold based on the first signal, as discussed further below. It is composed. Threshold circuit 1238 includes PFET 1240 and first switch 1245. The gate of PFET 1240 is coupled to the gate of PFET 1225 in first inverter 1218, and the drain of PFET 1240 is coupled to the drain of PFET 1225 in first inverter 1218. First switch 1245 is coupled between the source of PFET 1240 and supply rail 870. First switch 1245 has a control input 1247 coupled to a first input 634 of delay interpolator 630 to receive a first signal.

[0104] In this example, the first switch 1245 is configured to turn on when the first signal is 1 and to turn off when the first signal is 0. When first switch 1245 is turned on, first switch 1245 couples the source of PFET 1240 to supply rail 870, which connects PFET 1240 to the PFET(s) of first inverter 1218. 1225) and is coupled in parallel. As a result, PFET 1240 increases the current drive from supply rail 870 to output 1224 of first inverter 1218, which increases the threshold of first inverter 1218 to the rising edge threshold. In this example, the rising edge threshold can be set to the desired voltage by appropriately setting the ratio between the size (e.g., width) of PFET 1240 and the size (e.g., width) of NFET 1220. The larger the ratio, the higher the rising edge threshold.

[0105] Threshold circuit 1238 also includes NFET 1235 and second switch 1230. The gate of NFET 1235 is coupled to the gate of NFET 1220 in first inverter 1218, and the drain of NFET 1235 is coupled to the drain of NFET 1220 in first inverter 1218. Second switch 1230 is coupled between the source of NFET 1235 and ground. The second switch 1230 has a control input 1232 coupled to the first input 634 of the delay interpolator 630 to receive a first signal.

[0106] In this example, the second switch 1230 is configured to turn on when the first signal is 0 and to turn off when the first signal is 1. When second switch 1230 is turned on, second switch 1230 couples the source of NFET 1235 to ground, which places NFET 1235 in parallel with NFET 1220 of first inverter 1218. Couple with As a result, NFET 1235 increases the current drive from the output 1224 of first inverter 1218 to ground, which reduces the threshold of first inverter 1218 to the falling edge threshold. In this example, the falling edge threshold can be set to the desired voltage by appropriately setting the ratio between the size (e.g., width) of NFET 1235 and the size (e.g., width) of PFET 1225. The larger the ratio, the lower the falling edge threshold.

[0107] Thus, in this example, the threshold circuit 1238 sets the threshold of the first inverter 1218 to the rising edge threshold when the first signal is 1 and sets the threshold of the first inverter 1218 to the rising edge threshold when the first signal is 0. ) set the threshold to the falling edge threshold.

[0108] It should be appreciated that the output buffer 860 is not limited to the example implementation shown in FIG. 12. For example, output buffer 860 may be implemented using built-in hysteresis (e.g., Schmitt-trigger buffer) or another type of output buffer.

[0109] Figure 13 shows an example implementation of the first switch 1245 and the second switch 1230. In this example, first switch 1245 includes PFET 1320 coupled between PFET 1240 and supply rail 870. The gate of PFET 1320 is coupled to the first input 634 of delay interpolator 630 through inverter 1340 such that PFET 1320 turns on when the first signal is 1. Inverter 1340 has an input 1342 coupled to a first input 634 of delay interpolator 630, and an output 1344 coupled to the gate of PFET 1320.

[0110] In this example, second switch 1230 includes NFET 1330 coupled between NFET 1235 and ground. The gate of NFET 1330 is coupled to the first input 634 of delay interpolator 630 through inverter 1340 such that NFET 1330 is turned on when the first signal is zero. The output 1344 of inverter 1340 is also coupled to the gate of NFET 1330.

[0111] In the examples discussed above, output buffer 860 is assumed to be non-inverting. However, it should be recognized that this does not have to be the case. When the output buffer 860 is inverting, the first control circuit 840 can control the fine delay of the falling edge at the output 638 of the delay interpolator 630 based on the first delay code, The second control circuit 850 may control the fine delay of the rising edge of the output 638 of the delay interpolator 630 based on the second delay code. For example, the example output buffer 860 shown in FIG. 12 can be inverted by omitting the second inverter 1258 or adding another inverter.

[0112] As discussed above, coarse delay circuit 620 is not limited to the example implementations shown in FIG. 7. In this regard, FIG. 14 illustrates another example implementation of coarse delay circuit 620 in accordance with certain aspects. In this example, coarse delay circuit 620 includes multiple delay devices 1410-1 through 1410-N coupled in series to form a delay line (e.g., a delay chain). Each of the delay devices 1410-1 through 1410-N has a respective input (labeled “in”) and a respective output (labeled “out”). Each of the delay devices 1410-1 to 1410-N has one coarse delay step ( ) can have a delay. The input of delay device 1410-1 is coupled to input 622 of coarse delay circuit 620. The output of each of the delay devices 1410-1 through 1410-(N-1) is coupled to the input of the next delay device 1410-2 through 1410-N in the delay line.

[0113] The coarse delay circuit 620 also includes a multiplexer 1430 having a number of inputs 1432-1 through 1432-N, an output 1434, and a select input 1436. Each of the inputs 1432-1 through 1432-N of the multiplexer 1430 is coupled to the output of a respective one of the delay devices 1410-1 through 1410-N of the delay line. As a result, each of inputs 1432-1 through 1432-N is coupled to a different point on the delay line corresponding to a different delay. The output 1434 of the multiplexer 1430 is coupled to the first output 624 and the select input 1436 of the multiplexer 130 is coupled to the delay control circuit 650.

[0114] The multiplexer 1430 receives a selection signal from the delay control circuit 650 at the selection input 1436 and selects one of the inputs 1432-1 to 1432-N of the multiplexer 1430 based on the received selection signal. It is configured to select one input, and the selected one input among the inputs 1432-1 to 1432-N is coupled to the output 1434 of the multiplexer 1430. Since each of the inputs 1432-1 through 1432-N is coupled to a different point on the delay line corresponding to a different delay, the delay control circuit 650 can operate on any of the inputs 1432-1 through 1432-N. By controlling whether this is selected by multiplexer 1430, the select signal can be used to control the tunable delay of coarse delay circuit 620. Accordingly, in this example, the select signal is a delay control signal used by delay control circuit 650 to tune the delay of coarse delay circuit 620. Output 1434 of multiplexer 1430 provides a first signal at first output 624.

[0115] In this example, the coarse delay circuit 620 also includes an additional delay device 1440 coupled between the output 1434 of the multiplexer 1430 and the second output 626 to provide a second signal. Includes. An additional delay device 1440 converts the first signal at the output 1434 of the multiplexer 1430 into one coarse delay step ( ) can be delayed to provide a second signal from the second output 626. Therefore, in this example, the second delay signal is one coarse delay step ( ) is delayed. Because the delay between the first signal and the second signal is created by the additional delay device 1440 in the coarse delay circuit 620, the delay between the first signal and the second signal is caused by PVT variations in the coarse delay circuit ( Track changes in the coarse delay step caused by changes in 620).

[0116] As discussed above with respect to FIG. 8 , first control circuit 840 and second control circuit 850 provide a fine delay of the rising edge at output 638 and a fine delay of the falling edge at output 638. can be adjusted independently, which can be used to adjust the duty cycle of the delayed signal at output 638. For example, the duty cycle of the delayed signal at output 638 can be increased by increasing the delay of the falling edge relative to the rising edge (e.g., by increasing the delay setting of the second delay code). The duty cycle of the delayed signal at output 638 may be reduced by reducing the delay of the falling edge relative to the rising edge (eg, by reducing the delay setting of the second delay code).

[0117] For example, duty cycle adjustment may be used in the data interface to achieve a duty cycle of approximately 50 percent. In one example, the data interface may be a double-data rate (DDR) memory interface, where data is captured from a data signal received on both rising and falling edges of a clock signal. In this example, a 50 percent duty cycle is desirable for the clock signal so that data capture on the rising and falling edges of the clock signal are evenly spaced. In this example, delay circuit 610 may be used to delay the clock signal (e.g., to center edges of the clock signal between transitions of the data signal). Additionally, first control circuit 840 and second control circuit 850 may be used to adjust the duty cycle of the delayed clock signal to achieve a 50 percent duty cycle.

[0118] In this regard, Figure 15 illustrates an example of a data interface 1505 (e.g., a DDR memory interface) in accordance with certain aspects of the present disclosure. In this example, data interface 1505 includes delay circuit 610 and delay control circuit 650. Data interface 1505 also includes a duty-cycle detector 1510 and latch 1520. Duty-cycle detector 1510 has an input 1512 coupled to an output 614 of delay circuit 610, and an output 1514 coupled to delay control circuit 650. Latch 1520 has a data input 1524, a clock input 1522, and an output 1526.

[0119] In this example, delay circuit 610 receives a clock signal at input 612, delays the clock signal, and outputs the delayed clock signal at output 614. In one example, latch 1520 receives a data signal at data input 1524, and delay control circuit 650 adjusts the delay of delay circuit 610 to delay edges of the clock signal between transitions of the data signal. Sort them. In this example, latch 1520 receives a delayed clock signal at clock input 1522 and captures (i.e., latches) data bits from the received data signal on the rising and falling edges of the delayed clock signal, And data bits are output at output 1526. For an example of a memory interface, data bits may be output to read-write circuitry to write the data bits to memory and/or to a processor for further processing.

[0120] In this example, duty-cycle detector 1510 detects the duty cycle of the delayed clock signal, compares the detected duty cycle to a target duty cycle (e.g., 50 percent), and compares the detected duty cycle with the target. and to send commands to the delay control circuit 650 based on the comparison to adjust the duty cycle to reduce the difference between the duty cycles. For example, if the detected duty cycle is greater than the target duty cycle, duty-cycle detector 1510 may instruct delay control circuit 650 to decrease the duty cycle. In response, delay control circuit 650 may reduce the duty cycle by reducing the delay of falling edges relative to rising edges (e.g., by reducing the delay setting of the second delay code). If the detected duty cycle is less than the target duty cycle, duty-cycle detector 1510 may command delay control circuit 650 to increase the duty cycle. In response, delay control circuit 650 may increase the duty cycle by increasing the delay of falling edges relative to rising edges (eg, by increasing the delay setting of the second delay code).

[0121] In one example, data interface 1505 may also include a coarse duty cycle adjuster (not shown). In this example, duty-cycle detector 1510 uses a coarse duty cycle adjuster to make coarse adjustments to the duty cycle of the clock signal and determines the duty cycle of the clock signal based on a comparison of the target duty cycle and the detected duty cycle. Delay circuit 610 can be used to make fine adjustments to the cycle.

[0122] Figure 16 illustrates a method 1600 of operating a delay interpolator in accordance with certain aspects of the disclosure. A delay interpolator (e.g., delay interpolator 630) may be configured to use pull-up devices (e.g., pull-up devices) coupled between a supply rail (e.g., supply rail 870) and a node (e.g., node 830). up devices 810-1 through 810-K), and pull-down devices coupled between the node and ground (eg, pull-down devices 815-1 through 815-L).

[0123] At block 1610, a first signal is received. For example, the first signal may be received from a coarse delay circuit (eg, coarse delay circuit 620).

[0124] At block 1620, a second signal delayed with respect to the first signal is received. For example, the second signal may be received from a coarse delay circuit (e.g., coarse delay circuit 620). In one example, the second signal may be delayed relative to the first signal by one coarse delay step of the coarse delay circuit. In certain aspects, a coarse delay circuit delays an input signal (e.g., a data signal, clock signal, etc.) by a tunable delay to provide a first signal and delays the input signal by a tunable delay and an additional delay (e.g., one coarse delay). step) and provides the second signal.

[0125] At block 1630, a first signal is input to a programmable number of pull-up devices based on a first delay code. For example, the first signal may be input by the first control circuit 840 to a programmable number (eg, n) of pull-up devices based on the first delay code. In this example, the programmable number n is the pull-up devices (e.g., pull-up devices 810-1 to 810-K) through which the first control circuit 840 inputs the first signal based on the first delay code. )) is the number.

[0126] At block 1640, a second signal is input to the remaining one of the pull-up devices. For example, the second signal may be input to the remaining one of the pull-up devices by the first control circuit 840.

[0127] At block 1650, a first signal is input to a programmable number of pull-down devices based on a second delay code. For example, the first signal may be input by the second control circuit 850 to a programmable number (eg, m) of pull-down devices based on the second delay code. In this example, the programmable number (m) is the pull-down devices (e.g., pull-down devices 815-1 to The number is 815-L)).

[0128] At block 1660, a second signal is input to the remaining one of the pull-down devices. For example, the second signal may be input to the remaining pull-down devices by the second control circuit 850.

[0129] In one example, the first delay code and the second delay code may be different (eg, to adjust the duty cycle). In another example, the first delay code and the second delay code may be the same. For example, in cases where the delay circuit 610 is used for interpolation, the first delay code and the second delay code may be the same.

[0130] In certain aspects, the first delay code includes bits (e.g., d1<K-1:0>). In these aspects, inputting the first signal to a programmable number of pull-up devices based on the first delay code comprises, for each of the pull-up devices, an individual one of the bits of the first delay code. and inputting a first signal to a pull-up device when has a first logic value. In these aspects, inputting the second signal to the remaining one of the pull-up devices may be such that, for each of the pull-up devices, each of the bits of the first delay code is connected to the second logic. Having a value may include inputting a second signal to a pull-up device.

[0131] In certain aspects, the second delay code includes bits (e.g., d2<L-1:0>). In these aspects, inputting the first signal to a programmable number of pull-down devices based on the second delay code comprises, for each of the pull-down devices, an individual one of the bits of the second delay code. and inputting a first signal to a pull-down device when has a first logic value. In these aspects, inputting the second signal to the remaining one of the pull-down devices may cause, for each of the pull-down devices, individual bits of the second delay code to have a second logic value. It may include inputting the second signal to the pull-down device.

[0132] Implementation examples are described in the following numbered clauses.

[0133] 1. The delayed interpolator is,

[0134] Pull-up devices, each of which is coupled between a supply rail and a node;

[0135] Pull-down devices—each of the pull-down devices coupled between a node and ground;

[0136] A first control circuit coupled to pull-up devices, the first control circuit comprising: a first input configured to receive a first signal, a second input configured to receive a second signal delayed with respect to the first signal, and a control input configured to receive a first delay code; and

[0137] A second control circuit coupled to the pull-down devices, the second control circuit comprising a first input configured to receive the first signal, a second input configured to receive the second signal, and a second control circuit coupled to the pull-down devices. It has a control input configured to receive a delay code.

[0138] 2. The delay interpolator of clause 1, wherein each of the pull-up devices includes a respective transistor having a gate coupled to a first control circuit.

[0139] 3. The delay interpolator of clause 2, wherein each of the pull-down devices includes a respective transistor having a gate coupled to a second control circuit.

[0140] 4. The delay interpolator of any of clauses 1 to 3, wherein each of the pull-up devices has a gate coupled to the first control circuit, a source coupled to the supply rail, and a node coupled to the node. It includes individual p-type field effect transistors with ringed drains.

[0141] 5. The delay interpolator of any of clauses 1 through 4, wherein each of the pull-down devices has a gate coupled to a second control circuit, a drain coupled to a node, and a ground coupled to ground. It includes individual n-type field effect transistors having a source.

[0142] 6. In the delay interpolator of any one of clauses 1 to 5, the first delay code and the second delay code are different.

[0143] 7. In the delay interpolator of any one of clauses 1 to 5, the first delay code and the second delay code are the same.

[0144] 8. The delay interpolator of any one of clauses 1 to 7 further includes an output buffer, having an input coupled to the node, and an output.

[0145] 9. In the delay interpolator of clause 8, the output buffer has a rising edge threshold and a falling edge threshold, and the output buffer transition the output from the first logic state to the second logic state, and transition the output of the output buffer from the second logic state to the first logic state when a falling edge at the input of the output buffer exceeds the falling edge threshold. .

[0146] 10. The delay interpolator of any one of clauses 1 to 9 further includes a capacitor coupled between the node and ground.

[0147] 11. The delayed interpolator of any one of clauses 1 to 10 is:

[0148] The first delay code includes a number of bits;

[0149] The first control circuit includes a first plurality of control devices; and

[0150] Each of the first plurality of control devices includes: a respective first input coupled to a first input of the first control circuit, a respective second input coupled to a second input of the first control circuit, a respective first input coupled to a first input of the first control circuit, 1 has a respective control input configured to receive an individual one of the bits of the delay code, and a respective output coupled to a respective one of the pull-up devices.

[0151] 12. The delay interpolator of clause 11, wherein each of the first plurality of control devices controls a respective pull-up device of the pull-up devices based on the logic value of an individual one of the bits of the first delay code. It is configured to input a first signal or a second signal to the up device.

[0152] 13. The delayed interpolator of clause 11 or clause 12 is:

[0154] The second delay code includes a number of bits;

[0155] The second control circuit includes a second plurality of control devices; and each of the second plurality of control devices comprises: a respective first input coupled to a first input of the second control circuit, a respective second input coupled to a second input of the second control circuit, a second delay It has a respective control input configured to receive an individual one of the bits of the code, and a respective output coupled to a respective one of the pull-down devices.

[0156] 14. The delayed interpolator in clause 13 is:

[0157] Each of the first plurality of control devices sends a first signal or a second signal to an individual one of the pull-up devices based on the logic value of an individual one of the bits of the first delay code. is configured to enter; and

[0158] Each of the second plurality of control devices sends a first signal or a second signal to an individual one of the pull-down devices based on the logic value of an individual one of the bits of the second delay code. It is configured to input .

[0159] 15. The delay interpolator of any of clauses 1 to 14, wherein the first control circuit inputs a first signal to a programmable number of pull-up devices based on a first delay code, and And configured to input a second signal to the remaining pull-up devices among the pull-up devices.

[0160] 16. The delay interpolator of any of clauses 1 to 15, wherein the second control circuit inputs a first signal to a programmable number of pull-down devices based on a second delay code, and And it is configured to input a second signal to the remaining pull-down devices among the pull-down devices.

[0161] 17. A method of operating a delay interpolator comprising pull-up devices coupled between a supply rail and a node, and pull-down devices coupled between a node and ground, the method comprising:

[0162] Receiving a first signal;

[0163] Receiving a second signal delayed with respect to the first signal;

[0164] Inputting a first signal to a programmable number of pull-up devices based on a first delay code;

[0165] Inputting a second signal to the remaining pull-up devices among the pull-up devices;

[0166] Inputting a first signal to a programmable number of pull-down devices based on a second delay code; and

[0167] Inputting a second signal to the remaining pull-down devices among the pull-down devices.

[0168] 18. In the method of clause 17, the first delay code and the second delay code are different.

[0169] 19. In the method of clause 17, the first delay code and the second delay code are the same.

[0170] 20. The method of any one of Articles 17 to 19 is:

[0171] The first delay code includes bits; and

[0172] Inputting a first signal to a programmable number of pull-up devices based on a first delay code:

[0173] For each of the pull-up devices, inputting a first signal to the pull-up device when an individual one of the bits of the first delay code has a first logic value.

[0174] 21. The method of clause 20, wherein inputting the second signal to the remaining pull-up devices among the pull-up devices includes:

[0175] For each of the pull-up devices, inputting a second signal to the pull-up device if an individual one of the bits of the first delay code has a second logic value.

[0176] 22. In the method of any one of clauses 17 to 21,

[0177] The second delay code includes bits; and

[0178] Inputting the first signal to a programmable number of pull-down devices based on the second delay code:

[0179] For each of the pull-down devices, inputting a first signal to the pull-down device when an individual one of the bits of the second delay code has a first logic value.

[0180] 23. In the method of clause 22, the step of inputting the second signal to the remaining pull-down devices among the pull-down devices is:

[0181] For each of the pull-down devices, inputting a second signal to the pull-down device if each of the bits of the second delay code has a second logic value.

[0182] 24. As a system,

[0183] a delay circuit having an input, a first output, and a second output; and

[0184] It includes a delayed interpolator, and the delayed interpolator is:

[0185] Pull-up devices, each of which is coupled between a supply rail and a node;

[0186] Pull-down devices—each of the pull-down devices coupled between a node and ground;

[0187] First control circuit coupled to pull-up devices, the first control circuit comprising: a first input coupled to a first output of the delay circuit, a second input coupled to a second output of the delay circuit , and a control input configured to receive a first delay code; and

[0188] comprising a second control circuit coupled to the pull-down devices, the second control circuit comprising: a first input coupled to a first output of the delay circuit, a second output of the delay circuit; It has a second input, and a control input configured to receive a second delay code.

[0189] 25. The system of clause 24, wherein the delay circuit receives an input signal at an input of the delay circuit, delays the input signal by a tunable delay to provide a first signal at a first output of the delay circuit, and and configured to delay the input signal by a tunable delay and an additional delay to provide a second signal at a second output of the delay circuit.

[0190] 26. The system of clause 25, wherein the delay circuit is configured to tune the tunable delay by a multiple of the delay step based on the delay control signal, and the additional delay is equal to the delay step.

[0191] 27. The system of either clause 25 or clause 26, wherein the first control circuit inputs a first signal to a programmable number of pull-up devices based on a first delay code, and pulls configured to input a second signal to the remaining pull-up devices among the -up devices.

[0192] 28. The system of any of clauses 25 through 27, wherein the second control circuit inputs the first signal to a programmable number of pull-down devices based on a second delay code, and pulls the pull-down device. -Configured to input a second signal to the remaining pull-down devices among the down devices.

[0193] 29. The system of any of clauses 24 to 28, wherein the delay interpolator further comprises an output buffer having an input coupled to the node and an output.

[0194] 30. The system of clause 29, wherein the output buffer has a rising edge threshold and a falling edge threshold, and the output buffer blocks the output of the output buffer when a rising edge at the input of the output buffer crosses the rising edge threshold. transition from the first logic state to the second logic state, and transition the output of the output buffer from the second logic state to the first logic state when a falling edge at the input of the output buffer exceeds the falling edge threshold.

[0195] 31. The system of clause 29 or clause 30 further comprises a latch having a data input, a clock input coupled to the output of the output buffer, and an output.

[0196] 32. In the system of any one of clauses 24 to 31, the first delay code and the second delay code are different.

[0197] 33. In the system of any one of clauses 24 to 31, the first delay code and the second delay code are the same.

[0198] 34. In the system of Article 25,

[0199] The first delay code includes a number of bits;

[0200] The first control circuit includes a first plurality of control devices; and

[0201] Each of the first plurality of control devices includes: a respective first input coupled to a first input of the first control circuit, a respective second input coupled to a second input of the first control circuit, a 1 a respective control input configured to receive an individual one of the bits of the delay code, and a respective output coupled to a respective pull-up device of the pull-up devices.

[0202] 35. The system of clause 34, wherein each of the first plurality of control devices is configured to control a respective one of the pull-up devices based on a logic value of an individual one of the bits of the first delay code. It is configured to input a first signal or a second signal.

[0203] 36. In the system of clause 34 or clause 35,

[0204] The second delay code includes a number of bits;

[0205] The second control circuit includes a second plurality of control devices; and

[0206] Each of the second plurality of control devices includes: a respective first input coupled to a first input of the second control circuit, a respective second input coupled to a second input of the second control circuit, a 2. It has a respective control input configured to receive an individual one of the bits of the delay code, and a respective output coupled to a respective one of the pull-down devices.

[0207] 37. In the system of clause 36:

[0208] Each of the first plurality of control devices sends a first signal or a second signal to an individual one of the pull-up devices based on the logic value of an individual one of the bits of the first delay code. is configured to enter; and

[0209] Each of the second plurality of control devices sends a first signal or a second signal to an individual one of the pull-down devices based on the logic value of an individual one of the bits of the second delay code. It is configured to input .

[0210] 38. In the delay interpolator of clause 1, a first signal and a second signal are received from a delay circuit, and the second signal is delayed with respect to the first signal by a delay step of the delay circuit.

[0211] 39. In the delay interpolator of clause 1 or clause 38, a first signal and a second signal are received from a delay circuit, the delay circuit being configured to provide a second signal by delaying the first signal by an additional delay device. It is composed.

[0212] It should be recognized that the present disclosure is not limited to the example terminology used above to describe aspects of the disclosure. For example, a delay device may also be referred to as a delay stage, delay buffer, delay element, delay unit, or other terminology. A control device may also be referred to as control logic, control circuitry, or other terminology. A delay circuit may also be referred to as a delay line, or other terminology.

[0213] The delay control circuit 650 may be a general-purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), or other programmable logic device, or discrete hardware components (e.g. , logic gates) or any combination thereof designed to perform the functions described herein. A processor may perform the functions described herein by executing software that includes code to perform the functions. The software may be stored on a computer-readable storage medium, such as RAM, ROM, EEPROM, optical disk, and/or magnetic disk.

[0214] Within this disclosure, the word “exemplary” is used to mean “serving as an example, illustration, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Similarly, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to direct or indirect electrical coupling between two structures. It should also be recognized that the term "ground" can refer to either DC ground or AC ground, so the term "ground" encompasses both possibilities.

[0215] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other modifications without departing from the spirit or scope of the disclosure. . Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (31)

As a delayed interpolator,
pull-up devices, each of which is coupled between a supply rail and a node;
pull-down devices, each of which is coupled between the node and ground;
a first control circuit coupled to the pull-up devices, the first control circuit comprising a first input configured to receive a first signal, a second input configured to receive a second signal delayed with respect to the first signal, and a control input configured to receive a first delay code; and
a second control circuit coupled to the pull-down devices, the second control circuit comprising a first input configured to receive the first signal, a second input configured to receive the second signal, and a second control circuit coupled to the pull-down devices. 2 having a control input configured to receive a delay code,
Delay interpolator. According to claim 1,
each of the pull-up devices comprising a respective transistor having a gate coupled to the first control circuit,
Delay interpolator. According to clause 2,
each of the pull-down devices comprising a respective transistor having a gate coupled to the second control circuit,
Delay interpolator. According to claim 1,
Each of the pull-up devices includes a respective p-type field effect transistor having a gate coupled to the first control circuit, a source coupled to the supply rail, and a drain coupled to the node. ,
Delay interpolator. According to clause 4,
each of the pull-down devices comprising a respective n-type field effect transistor having a gate coupled to the second control circuit, a drain coupled to the node, and a source coupled to the ground.
Delay interpolator. According to claim 1,
The first delay code and the second delay code are different,
Delay interpolator. According to claim 1,
The first delay code and the second delay code are the same,
Delay interpolator. According to claim 1,
further comprising an output buffer having an input and an output coupled to the node,
Delay interpolator. According to clause 8,
The output buffer has a rising edge threshold and a falling edge threshold, and the output buffer controls the output of the output buffer to first logic when a rising edge at the input of the output buffer crosses the rising edge threshold. transition from a state to a second logic state, and transition the output of the output buffer from the second logic state to the first logic state when a falling edge at the input of the output buffer crosses the falling edge threshold. ,
Delay interpolator. According to clause 8,
further comprising a capacitor coupled between the node and the ground,
Delay interpolator. According to claim 1,
the first delay code includes a number of bits;
the first control circuit includes a first plurality of control devices; and
Each of the first plurality of control devices comprises: a respective first input coupled to a first input of the first control circuit, a respective second input coupled to a second input of the first control circuit, having a respective control input configured to receive an individual one of the bits of the first delay code, and a respective output coupled to an individual one of the pull-up devices,
Delay interpolator. According to claim 11,
Each of the first plurality of control devices sends the first signal or the first signal to an individual one of the pull-up devices based on a logic value of an individual one of the bits of the first delay code. configured to input 2 signals,
Delay interpolator. According to claim 11,
the second delay code includes a number of bits;
the second control circuit includes a second plurality of control devices; and
Each of the second plurality of control devices comprises: a respective first input coupled to a first input of the second control circuit, a respective second input coupled to a second input of the second control circuit, having a respective control input configured to receive an individual one of the bits of the second delay code, and a respective output coupled to an individual one of the pull-down devices,
Delay interpolator. According to claim 13,
Each of the first plurality of control devices sends the first signal or the first signal to an individual one of the pull-up devices based on a logic value of an individual one of the bits of the first delay code. configured to input 2 signals; and
Each of the second plurality of control devices applies the first signal or the first signal to an individual one of the pull-down devices based on a logic value of an individual one of the bits of the second delay code. configured to input 2 signals,
Delay interpolator. According to claim 1,
The first control circuit inputs the first signal to a programmable number of the pull-up devices based on the first delay code, and outputs the first signal to the remaining one of the pull-up devices. configured to input a second signal,
Delay interpolator. According to claim 15,
The second control circuit inputs the first signal to a programmable number of the pull-down devices based on the second delay code, and inputs the first signal to the remaining one of the pull-down devices. configured to input 2 signals,
Delay interpolator. 1. A method of operating a delay interpolator comprising pull-up devices coupled between a supply rail and a node, and pull-down devices coupled between the node and ground, comprising:
Receiving a first signal;
Receiving a second signal delayed with respect to the first signal;
inputting the first signal to a programmable number of the pull-up devices based on a first delay code;
inputting the second signal to remaining pull-up devices among the pull-up devices;
inputting the first signal to a programmable number of the pull-down devices based on a second delay code; and
Inputting the second signal to remaining pull-down devices of the pull-down devices,
How to operate a delayed interpolator. According to claim 17,
The first delay code and the second delay code are different,
How to operate a delayed interpolator. According to claim 17,
The first delay code and the second delay code are the same,
How to operate a delayed interpolator. According to claim 17,
The first delay code includes bits; and
Inputting the first signal to the programmable number of pull-up devices based on the first delay code includes:
For each of the pull-up devices, inputting the first signal to the pull-up device if an individual one of the bits of the first delay code has a first logic value,
How to operate a delayed interpolator. According to claim 20,
The step of inputting the second signal to the remaining pull-up devices among the pull-up devices is:
For each of the pull-up devices, inputting the second signal to the pull-up device if an individual one of the bits of the first delay code has a second logic value,
How to operate a delayed interpolator. According to claim 17,
the second delay code includes bits; and
Inputting the first signal to the programmable number of pull-down devices based on the second delay code:
For each of the pull-down devices, inputting the first signal to the pull-down device if an individual one of the bits of the second delay code has a first logic value,
How to operate a delayed interpolator. According to clause 22,
The step of inputting the second signal to the remaining pull-down devices among the pull-down devices is:
For each of the pull-down devices, inputting the second signal to the pull-down device if an individual one of the bits of the second delay code has a second logic value,
How to operate a delayed interpolator. As a system,
a delay circuit having an input, a first output, and a second output; and
A delay interpolator comprising:
pull-up devices, each of which is coupled between a supply rail and a node;
pull-down devices, each of which is coupled between the node and ground;
a first control circuit coupled to the pull-up devices, the first control circuit comprising: a first input coupled to a first output of the delay circuit, a second input coupled to a second output of the delay circuit; an input, and a control input configured to receive a first delay code; and
a second control circuit coupled to the pull-down devices, the second control circuit comprising: a first input coupled to a first output of the delay circuit, a second output coupled to the delay circuit; a second input, and a control input configured to receive a second delay code,
system. According to clause 24,
The delay circuit receives an input signal at the input of the delay circuit, delays the input signal by a tunable delay to provide a first signal at the first output of the delay circuit, and configured to delay the input signal by the tunable delay and an additional delay to provide a second signal at a second output.
system. According to clause 25,
wherein the delay circuit is configured to tune the tunable delay by a multiple of a delay step based on a delay control signal, and wherein the additional delay is equal to the delay step.
system. According to clause 25,
The first control circuit inputs the first signal to a programmable number of the pull-up devices based on the first delay code, and outputs the first signal to the remaining one of the pull-up devices. configured to input a second signal,
system. According to clause 27,
The second control circuit inputs the first signal to a programmable number of the pull-down devices based on the second delay code, and inputs the first signal to the remaining one of the pull-down devices. configured to input a second signal,
system. According to clause 24,
The delay interpolator further includes an output buffer having an input coupled to the node, and an output.
system. According to clause 29,
The output buffer has a rising edge threshold and a falling edge threshold, and the output buffer moves the output of the output buffer from a first logic state to a second logic state when a rising edge at the input of the output buffer exceeds the rising edge threshold. transition to a logic state, and transition the output of the output buffer from the second logic state to the first logic state when a falling edge at the input of the output buffer crosses the falling edge threshold.
system. According to clause 29,
further comprising a latch having a data input, a clock input coupled to the output of the output buffer, and an output.
system.