CN117178482A

CN117178482A - delay interpolator

Info

Publication number: CN117178482A
Application number: CN202280028265.5A
Authority: CN
Inventors: J·M·辛里奇斯
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2021-04-26
Filing date: 2022-03-24
Publication date: 2023-12-05

Abstract

A delay interpolator (630) comprising: pull-up devices (810-1, 810-K), wherein each of the pull-up devices is coupled between a supply rail (Vdd) and a node (830); and pull-down devices (815-1, 815-L), wherein each of the pull-down devices is coupled between the node and ground. The delay interpolator also includes a first control circuit (840) coupled to the pull-up device, wherein the first control circuit has a first input (842) configured to receive a first signal, a second input (844) configured to receive a second signal delayed relative to the first signal, and a control input (846) configured to receive a first delay code. The delay interpolator also includes a second control circuit (850) coupled to the pull-down device, wherein the second control circuit has a first input (852) configured to receive the first signal, a second input (854) configured to receive the second signal, and a control input (856) configured to receive a second delay code.

Description

Delay interpolator

Cross Reference to Related Applications

The present application claims priority and benefit from non-provisional continuation-in-application Ser. No. 17/506/902, filed on U.S. patent and trademark office at 10, 21, 2021, and non-provisional application Ser. No. 17/240,926, filed on U.S. patent and trademark office at 4, 2021, the entire contents of which are incorporated herein as if fully set forth below in their entirety for all applicable purposes.

Technical Field

Aspects of the present disclosure relate generally to delay circuits and, more particularly, to delay interpolators.

Background

The delay circuit may be used to delay the signal by an adjustable (i.e., tunable) delay. The adjustable delay may be used to adjust the timing of a signal relative to another signal, for example, by delaying the signal by a corresponding amount. For example, delay circuits may be used in a memory interface to center edges of a clock signal for data capture between transitions of a data signal.

Disclosure of Invention

In order to provide a basic understanding of such embodiments, the following presents a simplified summary of one or more embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

A first aspect relates to a delay interpolator. The delay interpolator includes: a pull-up device, wherein each of the pull-up devices is coupled between the power rail and the node; and a pull-down device, wherein each of the pull-down devices is coupled between the node and ground. The delay interpolator also includes a first control circuit coupled to the pull-up device, wherein the first control circuit has a first input configured to receive the first signal, a second input configured to receive a second signal delayed relative to the first signal, and a control input configured to receive the first delay code. The delay interpolator also includes a second control circuit coupled to the pull-down device, wherein the second control circuit has a first input configured to receive the first signal, a second input configured to receive the second signal, and a control input configured to receive a second delay code.

A second aspect relates to a method of operating a delayed interpolator. The delay interpolator includes a pull-up device coupled between the supply rail and a node and a pull-down device coupled between the node and ground. The method comprises the following steps: receiving a first signal; receiving a second signal delayed relative to the first signal; inputting a first signal to a programmable number of pull-up devices based on a first delay code; inputting a second signal to the remaining pull-up devices of the pull-up devices; inputting the first signal to a programmable number of pull-down devices based on the second delay code; and inputting a second signal to the remaining pull-down devices of the pull-down devices.

A third aspect relates to a system. The system includes a delay circuit having an input, a first output, and a second output. The system also includes a delay interpolator. The delay interpolator includes: a pull-up device, wherein each of the pull-up devices is coupled between the power rail and the node; and a pull-down device, wherein each of the pull-down devices is coupled between the node and ground. The delay interpolator also includes a first control circuit coupled to the pull-up device, where the first control circuit has a first input coupled to the first output of the delay circuit, a second input coupled to the second output of the delay circuit, and a control input configured to receive the first delay code. The delay interpolator also includes a second control circuit coupled to the pull-down device, wherein the second control circuit has a first input coupled to the first output of the delay circuit, a second input coupled to the second output of the delay circuit, and a control input configured to receive a second delay code.

Drawings

Fig. 1 illustrates an example of a delay circuit according to certain aspects of the present disclosure.

Fig. 2 illustrates an exemplary implementation of a coarse delay circuit in accordance with certain aspects of the present disclosure.

Fig. 3 illustrates an exemplary embodiment of a delay device in a coarse delay circuit in accordance with certain aspects of the present disclosure.

Fig. 4 illustrates an exemplary implementation of a fine delay circuit according to certain aspects of the present disclosure.

Fig. 5 illustrates an exemplary embodiment of a delay device in a fine delay circuit according to certain aspects of the present disclosure.

Fig. 6 illustrates an example of a delay circuit including a delay interpolator in accordance with certain aspects of the present disclosure.

Fig. 7 illustrates an exemplary embodiment of a coarse delay circuit configured to output two delay signals in accordance with certain aspects of the present disclosure.

Fig. 8 illustrates an exemplary implementation of a delay interpolator in accordance with certain aspects of the present disclosure.

Fig. 9 illustrates an exemplary implementation of a first control circuit and a second control circuit in accordance with certain aspects of the present disclosure.

Fig. 10 illustrates an exemplary embodiment of control devices in a first control circuit and a second control circuit in accordance with certain aspects of the present disclosure.

Fig. 11 is a graph illustrating exemplary waveforms for different delay settings in accordance with certain aspects of the present disclosure.

Fig. 12 illustrates an exemplary implementation of an output buffer in accordance with certain aspects of the present disclosure.

Fig. 13 illustrates an exemplary implementation of a switch in an output buffer in accordance with certain aspects of the present disclosure.

Fig. 14 illustrates another exemplary implementation of a coarse delay circuit according to certain aspects of the present disclosure.

Fig. 15 illustrates an example of a data interface including a delay circuit in accordance with certain aspects of the present disclosure.

Fig. 16 is a flow chart illustrating a method of operating a delay interpolator in accordance with certain aspects of the present disclosure.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Fig. 1 illustrates an example of a delay circuit 110 in accordance with certain aspects of the present disclosure. Delay circuit 110 is configured to receive a signal at input 112, delay the signal by an adjustable (i.e., tunable) delay, and output a delayed signal at output 114. The signal may be a clock signal, a data signal, or another type of signal. In this example, the delay of delay circuit 110 is set by delay control circuit 150, as discussed further below.

The delay circuit 110 includes a coarse delay circuit 120 and a fine delay circuit 130. Coarse delay circuit 120 has an input 122 coupled to input 112 of delay circuit 110 and an output 124. The fine delay circuit 130 has an input 132 coupled to the output 124 of the coarse delay circuit 120 and an output 134 coupled to the output 114 of the delay circuit 110. In this example, the delay of the delay circuit 110 is approximately equal to the sum of the delay of the coarse delay circuit 120 and the delay of the fine delay circuit 130.

The coarse delay circuit 120 is configured to provide coarse adjustment of the delay circuit 110, while the fine delay circuit 130 is configured to provide fine adjustment of the delay circuit 110. More specifically, the coarse delay circuit 120 allows the delay control circuit 150 to adjust the delay of the delay circuit 110 by coarse delay steps, while the fine delay circuit 130 allows the delay control circuit 150 to adjust the delay of the delay circuit 110 by fine delay steps between the coarse delay steps. In this example, one fine delay step may be given by:

Wherein τ _f Is a fine delay step size, τ _c Is the coarse delay step and R is the ratio of one coarse delay step to one fine delay step, where R is greater than one. In certain aspects, the delay control circuit 150 receives the delay code and adjusts the delay of the delay circuit 110 by adjusting the delay of the coarse delay circuit 120 and/or the delay of the fine delay circuit 130 accordingly based on the received delay code.

In certain aspects, coarse delay circuit 120 includes a plurality of delay devices, wherein one or more of the delay devices can be selectively placed in a delay path of coarse delay circuit 120 (e.g., using switches, logic gates, and/or one or more multiplexers) under control of delay control circuit 150. The delay path is coupled between an input 122 and an output 124 of the coarse delay circuit 120. In these aspects, delay control circuit 150 adjusts the delay of coarse delay circuit 120 by controlling the number of delay devices in the delay path. The greater the number of delay devices in the delay path, the longer the delay. In this example, each of the delay devices may have a delay approximately equal to one coarse delay step. Each of the delay devices may also be referred to as a delay stage, a delay cell, or another terminology.

Fig. 2 illustrates an exemplary implementation of coarse delay circuit 120 in accordance with certain aspects of the present disclosure. In this example, coarse delay circuit 120 includes a plurality of delay devices 210-1 through 210-N arranged in a trombone (trombone) configuration. Each of the delay devices 210-1 through 210-N has a respective first input 212-1 through 212-N (labeled "f) _in ") corresponding first outputs 214-1 through 214-N (labeled" f) _out ") corresponding second inputs 216-1 through 216-N (labeled" r _in ") and corresponding second outputs 218-1 through 218-N (labeled" r) _out ”)。

In this example, the delay devices 210-1 through 210-N are coupled along a forward path 230 using first inputs 212-1 through 212-N and first outputs 214-1 through 214-N of the delay devices 210-1 through 210-N. The delayed signal is received at input 122 of coarse delay circuit 120 and propagates along forward path 230 in direction 240 (i.e., left to right in fig. 2). In this example, a first input 212-1 of delay device 210-1 is coupled to input 122 of coarse delay circuit 120. As shown in FIG. 2, the first output 214-1 to 214- (N-1) of each of the delay devices 210-1 to 210- (N-1) is coupled to the first input 212-2 to 212-N of the next delay device 210-2 to 210-N in the forward direction 240. In this example, a first output 214-N of the delay device 210-N may be coupled to a second input 216-N of the delay device 210-N.

The delay devices 210-1 through 210-N are also coupled along a return path 235 using second inputs 216-1 through 216-N and second outputs 218-1 through 218-N of the delay devices 210-1 through 210-N. The delayed signal propagates along return path 235 in direction 245 (i.e., from right to left in fig. 2) and is output at output 124 of coarse delay circuit 120. In this example, as shown in FIG. 2, the second output 218-2 through 218-N of each of the delay devices 210-2 through 210-N is coupled to the second input 216-1 through 216- (N-1) of the next delay device 210-1 through 210- (N-1) in the return direction 245. The second output 218-1 of the delay device 210-1 is coupled to the output 124 of the coarse delay circuit 120.

In this example, each of the delay devices 210-1 through 210-N may be selectively enabled or disabled by the delay control circuit 150. When enabled, the delay device may be configured by the delay control circuit 150 to operate in either the first mode or the second mode. In the first mode, the delay device passes the delayed signals from the respective first inputs 212-1 to 212-N to the respective first outputs 214-1 to 214-N in the forward direction 240 and passes the delayed signals from the respective second inputs 216-1 to 216-N to the respective second outputs 218-1 to 218-N in the return direction 245. In the second mode, the delay devices pass the delayed signals from the respective first inputs 212-1 through 212-N to the respective second outputs 218-1 through 218-N. Thus, in the second mode, the delay device routes signals from the forward path 230 to the return path 235. In this case, the signal does not propagate through the delay device located after the delay device operating in the second mode in the forward direction 240 (i.e., the delay device located to the right of the delay device operating in the second mode in fig. 2).

In this example, delay control circuit 150 controls the delay of coarse delay circuit 120 by controlling which of delay devices 210-1 through 210-N is used to route signals from forward path 230 to return path 235 (i.e., controlling which of delay devices 210-1 through 210-N operates in the second mode). In this example, delay control circuit 150 increases the delay of coarse delay circuit 120 by selecting the delay device further down forward path 230 to route signals from forward path 230 to return path 235. This increases the delay of coarse delay circuit 120 by propagating the signal through a large number of delay devices 210-1 through 210-N. In this example, delay control circuit 150 operates the delay device for routing signals from forward path 230 to return path 235 in the second mode and operates the preceding delay device in the first mode (i.e., the delay device located to the left of the delay device operating in the second mode in fig. 2). In this example, one coarse delay step may be equal to the sum of the delay through one delay device in the forward direction 240 and the delay through one delay device in the return direction 245.

Note that the separate connections between delay control circuit 150 and delay devices 210-1 through 210-N are not explicitly shown in fig. 2.

Fig. 3 illustrates an exemplary embodiment of a delay device 310 that may be used in a trombone configuration according to certain aspects. Delay device 310 may be used to implement each of delay devices 210-1 through 210-N shown in fig. 2 (e.g., each of delay devices 210-1 through 210-N may be a separate instance of delay device 310 in fig. 3). In this example, the delay device 310 has a first input 312, a first output 314, a second input 316, and a second output 318. The delay device 310 includes a first delay buffer 320, a second delay buffer 330, and a third delay buffer 340. The first delay buffer 320 has an input 322 coupled to the first input 312 and an output 324 coupled to the first output 314. The second delay buffer 330 has an input 332 coupled to the second input 316 and an output 334 coupled to the second output 318. The third delay buffer 340 has an input 342 coupled to the output 324 of the first delay buffer 320 and an output 344 coupled to the input 332 of the second delay buffer 330.

In this example, delay control circuit 150 selectively enables or disables first delay buffer 320 and second delay buffer 330 via control line 350 and selectively enables or disables third delay buffer 340 via control line 355. In this example, each of delay buffers 320, 330, and 340 may be configured to delay a signal by a respective delay when enabled by delay control circuit 150 and mask the signal when disabled by delay control circuit 150. Each of delay buffers 320, 330, and 340 may be implemented with a tri-state inverter, a nand gate, or another type of delay buffer.

In this example, delay control circuit 150 may disable delay device 310 by disabling delay buffers 320, 330, and 340. The delay control circuit 150 may operate the delay device 310 in the first mode by enabling the first delay buffer 320 and the second delay buffer 330 and disabling the third delay buffer 340. In the first mode, the first delay buffer 320 delays the signal received at the first input 312 on the forward path 230 and outputs a delayed signal at the first output 314. The second delay buffer 330 delays the signal received at the second input 316 on the return path 235 and outputs a delayed signal at the second output 318. Thus, in the first mode, the first delay buffer 320 delays the signal on the forward path 230 and the second delay buffer 330 delays the signal on the return path 235.

The delay control circuit 150 may operate the delay device 310 in the second mode by enabling the first, second, and third delay buffers 320, 330, 340. In the second mode, the third delay buffer 340 passes the signal at the output 324 of the first delay buffer 320 on the forward path 230 to the input 332 of the second delay buffer 330 on the return path 235. Thus, in the second mode, delay device 310 routes signals from forward path 230 to return path 235 through third delay buffer 340.

Fig. 4 illustrates an exemplary implementation of the fine delay circuit 130 in accordance with aspects of the present disclosure. In this example, the fine delay circuit 130 includes a plurality of delay devices 410-1 through 410-M coupled in series to form a delay line (i.e., delay chain). Accordingly, the delay of the fine delay circuit 130 is approximately equal to the sum of the delays of the delay devices 410-1 through 410-M.

Each of the delay devices 410-1 through 410-M has a respective input 412-1 through 412-M (labeled "input") and a respective output 414-1 through 414-M (labeled "output"). An input 412-1 of the delay device 410-1 is coupled to an input 132 of the fine delay circuit 130 and an output 414-M of the delay device 410-M is coupled to an output 134 of the fine delay circuit 130. The output 414-1 through 414- (N-1) of each of the delay devices 410-1 through 410- (N-1) is coupled to the input 412-2 through 412-N of the next delay device 410-2 through 410-N in the delay line.

In certain aspects, the delay control circuit 150 controls the delay of the fine delay circuit 130 by adjusting the delay of each of the delay devices 410-1 through 410-M. For example, each of the delay devices 410-1 through 410-M may include a variable capacitive load, wherein the delay control circuit 150 adjusts the delay of each delay device 410-1 through 410-M by adjusting the corresponding capacitive load. In this example, the greater the capacitive load of the delay device, the longer the delay of the delay device.

Fig. 5 illustrates an exemplary implementation of a delay device 510 that may be used in the fine delay circuit 130 in accordance with certain aspects. Delay device 510 may be used to implement each of delay devices 410-1 through 410-M shown in fig. 4 (e.g., each of delay devices 410-1 through 410-M may be a separate instance of delay device 510 in fig. 5). In this example, delay device 510 has an input 512 and an output 514. The delay device 510 includes a delay buffer 520 and a variable capacitor 530. Delay buffer 520 has an input 522 coupled to input 512 of delay device 510 and an output 524 coupled to output 514 of delay device 510. Delay buffer 520 may be implemented with an inverter or another type of delay buffer.

Variable capacitor 530 is coupled to output 524 of buffer 520. In this example, variable capacitor 530 has an adjustable (i.e., tunable) capacitance that is controlled by delay control circuit 150. This allows the delay control circuit 150 to adjust the capacitive load at the output 524 of the delay buffer 520 (and thus the delay of the delay device 510) by adjusting the capacitance of the variable capacitor 530. The larger the capacitance of the capacitor 530, the larger the capacitive load and thus the longer the delay of the delay device 510.

In this example, different circuit delay techniques are used to adjust the coarse delay and the fine delay. The delay control circuit 150 adjusts the delay of the coarse delay circuit 120 by adjusting the number of delay devices 210-1 to 210-N in the delay path of the coarse delay circuit 120 and adjusts the delay of the fine delay circuit 130 by adjusting the capacitive loading of the delay devices 410-1 to 410-M. Because different circuit delay techniques are used for coarse and fine delay adjustment, there is no correlation between the change in one coarse delay step and the change in one fine delay step due to Process Voltage Temperature (PVT) changes. Therefore, the ratio of one coarse delay step to one fine delay step may not be well controlled, which can lead to a switching error when switching from fine to coarse delay.

Fig. 6 illustrates an exemplary delay circuit 610 in accordance with certain aspects of the present disclosure. Delay circuit 610 is configured to receive a signal at input 612, delay the signal by an adjustable (i.e., tunable) delay, and output a delayed signal at output 614. The signal may be a clock signal, a data signal, or another type of signal. In this example, the delay of delay circuit 610 is set by delay control circuit 650, as discussed further below.

Delay circuit 610 includes coarse delay circuit 620 and delay interpolator 630. Coarse delay circuit 620 has an input 622 coupled to input 612 of delay circuit 610, a first output 624, and a second output 626. Delay interpolator 630 has a first input 634 coupled to first output 624 of coarse delay circuit 620, a second input 636 coupled to second output 626 of coarse delay circuit 620, and an output 638 coupled to output 614 of delay circuit 610.

The coarse delay circuit 620 is configured to provide coarse adjustment of the delay circuit 610, and the delay interpolator 630 is configured to provide fine adjustment of the delay circuit 610. More specifically, the coarse delay circuit 620 allows the delay control circuit 650 to adjust (i.e., tune) the delay of the delay circuit 610 in coarse delay steps, while the delay interpolator 630 allows the delay control circuit 650 to adjust the delay of the delay circuit 610 in fine delay steps between coarse delay steps. The relationship between one coarse delay step and one fine delay step may be defined by equation (1) discussed above.

In the example of fig. 6, coarse delay circuit 620 is configured to receive a signal delayed at input 622. The coarse delay circuit 620 is configured to delay the received signal with an adjustable (i.e., tunable) delay under the control of the delay control circuit 650 to provide a first signal. The coarse delay circuit 620 is further configured to delay the received signal with an adjustable (i.e., tunable) delay and an additional delay to provide a second signal, wherein the second signal is delayed by the additional delay relative to the first signal. The coarse delay circuit 620 is configured to output a first signal at a first output 624 and a second signal at a second output 626. Thus, each of the first signal and the second signal is a delayed version of the received signal, wherein the second signal is delayed relative to the first signal by an additional delay. The first signal may also be referred to as an "early" signal because the first signal is earlier by an additional delay relative to the second signal, and the second signal may also be referred to as a "late" signal because the second signal is later by an additional delay relative to the first signal. The received signal may also be referred to as an input signal because the received signal is input to coarse delay circuit 620.

In certain aspects, the coarse delay circuit 620 is configured to delay the second signal by one coarse delay step relative to the first signal. In one example, delay control circuit 650 may adjust (i.e., tune) the adjustable (i.e., tunable) delay of the first signal by controlling the number of delay devices in the delay path between input 622 and first output 624 of coarse delay circuit 620 (e.g., using delay control signals that control switches, logic gates, and/or one or more multiplexers in coarse delay circuit 620). In this example, coarse delay circuit 620 receives the delay control signal from delay control circuit 650 and adjusts (i.e., tunes) the adjustable (i.e., tunable) delay by a multiple of the coarse delay step based on the delay control signal. The multiple may be an integer equal to or greater than one. In this example, the coarse delay circuit 620 may provide the second signal by delaying the first signal with an additional delay device having a delay of one coarse delay step. Thus, in this example, the delay of the second signal tracks the change in delay of the first signal while maintaining a delay of one coarse delay step between the second signal and the first signal.

The delay interpolator 630 is configured to receive a first signal at a first input 634 and a second signal at a second input 636. The interpolator 630 is configured to interpolate between the first signal and the second signal to produce a delay that is part of the delay between the first signal and the second signal. For the example where the delay between the first signal and the second signal is equal to one coarse delay step, the interpolator 630 generates the delay as part of one coarse delay step. In certain aspects, the delay control circuit 650 controls the fine delay of the delay circuit 610 by controlling the interpolation of the delay interpolator 630 (e.g., using digital delay codes).

Delay interpolator 630 allows for more precise control of the ratio of one coarse delay step to one fine delay step compared to delay circuit 110 in fig. 1. This is because interpolation between the first signal and the second signal by the delay interpolator 630 tracks the delay variation (e.g., one coarse delay step) between the first signal and the second signal caused by variations in the coarse delay circuit 620 due to PVT variations. Thus, the fine delay provided by interpolation tracks the delay variation (e.g., one coarse delay step) between the first signal and the second signal caused by variations in the coarse delay circuit 620 due to PVT variations, resulting in a more accurate control of the ratio of one coarse delay step to one fine delay step across PVT variations.

Fig. 7 illustrates an exemplary implementation of coarse delay circuit 620 in accordance with certain aspects. In this example, coarse delay circuit 620 includes delay devices 210-1 through 210-N coupled in a trombone configuration. The first input 212-1 of the delay device 210-1 is coupled to the input 612 of the coarse delay circuit 620. Delay control circuit 650 controls the delay at second output 218-1 of delay device 210-1 by selecting the delay device in the trombone configuration that is used to route the signal from forward path 230 to return path 235, as discussed above with reference to fig. 2. In this example, delay control circuit 650 adjusts (i.e., tunes) the delays of the first signal and the second signal by selecting the delay device in the trombone configuration that is used to route the signal from forward path 230 to return path 235.

In this example, coarse delay circuit 620 also includes a first delay device 710, a second delay device 720, and a third delay device 730. Each of the delay devices 710, 720, and 730 may be identical or similar in structure to the delay device in the trombone configuration (e.g., implemented using the exemplary delay device 310 shown in fig. 3). In this example, each of the delay devices 710, 720, and 730 may be configured to operate in a first mode.

In this example, a first input 712 of the first delay device 710 is coupled to the second output 218-1 of the delay device 210-1, a first output 714 of the first delay device 710 is coupled to a second input 716 of the first delay device 710, and a second output 718 of the first delay device 710 is coupled to the first output 624 of the coarse delay circuit 620. The first delay device 710 receives the signal from the second output 218-1 of the delay device 210-1 and delays the signal by one coarse delay step to provide a first signal at the first output 624 of the coarse delay circuit 620.

In this example, the first input 722 of the second delay device 720 is coupled to the second output 218-1 of the delay device 210-1, the first output 724 of the second delay device 720 is coupled to the first input 732 of the third delay device 730, the first output 734 of the third delay device 730 is coupled to the second input 736 of the third delay device 730, the second output 738 of the third delay device 730 is coupled to the second input 726 of the second delay device 720, and the second output 728 of the second delay device 720 is coupled to the second output 626 of the coarse delay circuit 620. The second delay device 720 receives the signal from the second output 218-1 of the delay device 210-1. The second delay device 720 and the third delay device 730 delay the signal by two coarse delay steps to provide a second signal at the second output 626 of the coarse delay circuit 620.

Thus, in this example, the first signal is provided by delaying the signal from the second output 218-1 of delay device 210-1 by one coarse delay step using first delay device 710, and the second signal is provided by delaying the signal from the second output 218-1 of delay device 210-1 by two coarse delay steps using second delay device 720 and third delay device 730. Thus, in this example, the delay between the first signal and the second signal is one coarse delay step.

It should be appreciated that coarse delay circuit 620 is not limited to a tunable delay circuit having a trombone configuration. For example, coarse delay circuit 620 may be implemented with another type of tunable delay circuit, where the second signal may be provided by delaying the first signal by one or more additional delay devices. Another exemplary implementation of coarse delay circuit 620 is discussed below with reference to fig. 14.

Fig. 8 illustrates an exemplary implementation of the delay interpolator 630 according to certain aspects of the present disclosure. Delay interpolator 630 includes a plurality of pull-up devices 810-1 through 810-K, a plurality of pull-down devices 815-1 through 815-L, a capacitor 845, and an output buffer 860.

Each of the pull-up devices 810-1 through 810-K is coupled between a node 830 and a voltage supply rail 870, wherein the voltage supply rail 870 provides a supply voltage Vdd. As discussed further below, each of the pull-up devices 810-1 through 810-K is configured to pull node 830 high (e.g., pull node 830 up to Vdd) when the pull-up device is turned on. In the example of fig. 8, each of the pull-up devices 810-1 through 810-K includes a respective transistor 820-1 through 820-K (e.g., a respective p-type field effect transistor (PFET)). For the example of each of the transistors 820-1 through 820-K implemented with PFETs, each of the pull-up devices 810-1 through 810-K is turned on when the gate of the respective transistor 820-1 through 820-K is driven low (e.g., substantially grounded). In this example, the source of each of transistors 820-1 through 820-K is coupled to supply rail 870, and the drain of each of transistors 820-1 through 820-K is coupled to node 830.

Each of the pull-down devices 815-1 through 815-L is coupled between node 830 and ground. As discussed further below, each of the pulldown devices 815-1 through 815-L is configured to pull node 830 low (e.g., pull node 830 to ground) when the pulldown device is turned on. In the example of FIG. 8, each of the pull-down devices 815-1 through 815-L includes a respective transistor 825-1 through 825-L (e.g., a respective n-type field effect transistor (NFET)). For the example where each of the transistors 825-1 through 825-L is implemented with an NFET, each of the pull-down devices 815-1 through 815-L is turned on when the gate of the respective transistor 825-1 through 825-L is driven high (e.g., vdd). In this example, the drain of each of the transistors 825-1 through 825-L is coupled to the node 830, while the source of each of the transistors 825-1 through 825-L is coupled to ground. The number of pull-down devices 815-1 through 815-L and the number of pull-up devices 810-1 through 810-K may be the same or different.

Capacitor 845 is coupled between node 830 and ground. The output buffer 860 has an input 862 coupled to the node 830 and an output 864 coupled to the output 638 of the delay interpolator 630. Thus, in this example, output 864 of output buffer 860 provides a delayed signal at output 638 of delay interpolator 630. In the following discussion, it is assumed that output buffer 860 is non-inverting. However, it should be appreciated that this is not always the case.

Delay interpolator 630 also includes a first control circuit 840 and a second control circuit 850. The first control circuit 840 has a first input 842 coupled to a first input 634 of the delay interpolator 630 and a second input 844 coupled to a second input 636 of the delay interpolator 630. Thus, the first input 842 receives a first signal and the second input 844 receives a second signal. The first control circuit 840 also has a control input 846 configured to receive a first delay code from the delay control circuit 650. The first control circuit 840 is also coupled to the pull-up devices 810-1 through 810-K. For examples in which each of the pull-up devices 810-1 through 810-K includes a respective transistor 820-1 through 820-K, the first control circuit 840 is coupled to the gate of each of the transistors 820-1 through 820-K.

In one example, the first control circuit 840 uses the pull-up devices 810-1 through 810-K to control the fine delay of the rising edge at the output 638 of the delay interpolator 630 based on the first delay code. In this example, the first control circuit 840 is configured to input a first signal received at the first input 842 to a programmable number n of pull-up devices 810-1 through 810-K based on the first delay code, and to input a second signal received at the second input 844 to the remaining of the pull-up devices 810-1 through 810-K (i.e., K-n of the pull-up devices 810-1 through 810-K, where K is the total number of pull-up devices 810-1 through 810-K). In this example, the delay interpolation is achieved by controlling the number n of pull-up devices 810-1 to 810-K driven by the first signal and the number (i.e., K-n) of pull-up devices 810-1 to 810-K driven by the second signal. The delay interpolation allows the first control circuit 840 to reduce the fine delay of the rising edge by increasing the number n of the pull-up devices 810-1 to 810-K driven by the first signal (i.e., inputting the first signal to a larger number n of the pull-up devices 810-1 to 810-K), and to increase the fine delay of the rising edge by reducing the number n of the pull-up devices 810-1 to 810-K driven by the first signal (i.e., inputting the first signal to a smaller number n of the pull-up devices 810-1 to 810-K). In this example, the programmable number n is the number of pull-up devices 810-1 to 810-K to which the first control circuit 840 inputs the first signal based on the first delay code.

The second control circuit 850 has a first input 852 coupled to the first input 634 of the delay interpolator 630, and a second input 854 coupled to the second input 636 of the delay interpolator 630. Thus, the first input 852 receives a first signal and the second input 854 receives a second signal. The second control circuit 850 also has a control input 856 configured to receive a second delay code from the delay control circuit 650. The second control circuit 850 is also coupled to the pull-down devices 815-1 through 815-L. For the example where each of the pull-down devices 815-1 through 815-L includes a respective transistor 825-1 through 825-L, the second control circuit 850 is coupled to the gate of each of the transistors 825-1 through 825-L.

In one example, the second control circuit 850 uses the pull-down devices 815-1 through 815-L to control the fine delay of the falling edge at the output 638 of the delay interpolator 630 based on the second delay code. In this example, the second control circuit 850 is configured to input the first signal received at the first input 852 to a programmable number m of the pulldown devices 815-1 through 815-L based on the second delay code, and to input the second signal received at the second input 854 to the remaining pulldown devices of the pulldown devices 815-1 through 815-L (i.e., L-m of the pulldown devices 815-1 through 815-L, where L is the total number of pulldown devices 815-1 through 815-L). In this example, delay interpolation is achieved by controlling the number m of pull-down devices 815-1 to 815-L driven by a first signal and the number (i.e., L-m) of pull-down devices 815-1 to 815-L driven by a second signal. The delay interpolation allows the second control circuit 850 to reduce the fine delay of the falling edge by increasing the number m of the pull-down devices 815-1 to 815-L driven by the first signal (i.e., inputting the first signal to a larger number m of the pull-down devices 815-1 to 815-L), and to increase the fine delay of the falling edge by reducing the number m of the pull-down devices 815-1 to 815-L driven by the first signal (i.e., inputting the first signal to a smaller number m of the pull-down devices 815-1 to 815-L). In this example, the programmable number m is the number of pull-down devices 815-1 to 815-L to which the second control circuit 850 inputs the first signal based on the second delay code.

In this example, the first control circuit 840 controls the first and second signals to pull up the inputs of the devices 810-1 through 810-K based on the first delay code, and the second control circuit 850 controls the first and second signals to pull down the inputs of the devices 815-1 through 815-L based on the second delay code. Thus, the first control circuit 840 and the second control circuit 850 allow for independent adjustment of the fine delay of the rising edge at the output 638 and the fine delay of the falling edge at the output 638 by using different codes for the first delay code and the second delay code. This feature can be used to adjust the duty cycle of the delayed signal at output 638, as discussed further below. For applications where no duty cycle adjustment is required, the same code may be used for the first delay code and the second delay code (i.e., the first delay code and the second delay code may be the same).

In this example, the first signal and the second signal are input to the pull-up devices 810-1 to 810-K through control paths in the first control circuit 840. The control path may include a logic gate that controls the first and second signals to pull up the inputs of the devices 810-1 through 810-K based on the first delay code. An exemplary embodiment of the control path in the first control circuit 840 is discussed below with reference to fig. 10. The control path may be non-inverting or inverting (i.e., invert the first signal and/or the second signal prior to pulling up the inputs of devices 810-1 through 810-K).

Further, in this example, the first signal and the second signal are input to the pulldown devices 815-1 to 815-L through control paths in the second control circuit 850. The control path may include a logic gate that controls the inputs of the first and second signal pull-down devices 815-1 through 815-L based on the second delay code. An exemplary embodiment of the control path in the second control circuit 850 is discussed below with reference to fig. 10. The control path may be non-inverting or inverting (i.e., invert the first signal and/or the second signal before pulling down the input of devices 815-1 through 815-L).

Accordingly, the first control circuit 840 and the second control circuit 850 provide separate control paths for the pull-up devices 810-1 through 810-K and the pull-down devices 815-1 through 815-L. The separate control paths help prevent glitches from occurring at the output 638 of the delay interpolator 630 in accordance with changes in the first delay code and/or the second delay code.

Fig. 9 illustrates an exemplary implementation of the first control circuit 840 according to certain aspects. In this example, the first control circuit 840 includes a plurality of control devices 910-1 through 910-K, wherein each of the control devices 910-1 through 910-K is configured to control the input of a respective one of the pull-up devices 810-1 through 810-K with the first signal and the second signal.

In this example, each of the control devices 910-1 through 910-K has a respective first input 912-1 through 912-K coupled to the first control circuit 840 to receive a first signal and a respective second input 916-1 through 916-K coupled to the second input 844 of the first control circuit 840 to receive a second signal. Each of the control devices 910-1 through 910-K also has a respective control input 914-1 through 914-K and a respective output 918-1 through 918-K coupled to a respective one of the pull-up devices 810-1 through 810-K (e.g., the gates of the respective transistors 820-1 through 820-K). In this example, the first delay code may be a thermometer code d1< K-1:0> comprising a plurality of bits, where each bit is used to control the input of a respective one of the pull-up devices 810-1 through 810-K. In this example, the control inputs 914-1 through 914-K of each of the control devices 910-1 through 910-K are configured to receive respective ones of the bits of the thermometer code d1< K-1:0 >. For example, control input 914-1 of control device 910-1 receives bit d1<0> of thermometer code d1< K-1:0 >.

In operation, each of the control devices 910-1 to 910-K is configured to input a first signal or a second signal to a respective pull-up device 810-1 to 810-K based on the logic value of a respective bit of the thermometer code d1< K-1:0 >. For example, each of the control devices 910-1 through 910-K may be configured to input a first signal to a respective pull-up device when a respective bit has a first logic value and to input a second signal to a respective pull-up device when a respective bit has a second logic value. For example, the first logical value may be a one and the second logical value may be zero, or vice versa. In this example, the first control circuit 840 sets a minimum delay when all bits of the thermometer code d1< K-1:0> have a first logic value (i.e., a first signal is input to all of the pull-up devices 810-1 to 810-K).

Fig. 9 also illustrates an exemplary implementation of the second control circuit 850 according to certain aspects. In this example, the second control circuit 850 includes a plurality of control devices 920-1 through 920-L, wherein each of the control devices 920-1 through 920-L is configured to control the inputs of a respective one of the pull-down devices 815-1 through 815-L with the first signal and the second signal.

In this example, each of the control devices 920-1 through 920-L has a respective first input 922-1 through 922-L coupled to the first input 852 of the second control circuit 850 to receive the first signal and a respective second input 926-1 through 926-L coupled to the second input 854 of the second control circuit 850 to receive the second signal. Each of the control devices 920-1 through 920-L also has a respective control input 924-1 through 924-L and a respective output 928-1 through 928-L coupled to a respective one of the pull-down devices 815-1 through 815-L (e.g., the gates of respective transistors 825-1 through 825-L). In this example, the second delay code may be a thermometer code d2< L-1:0> including a plurality of bits, where each bit is used to control the input of a respective one of the pull-down devices 815-1 through 815-L. In this example, the control inputs 924-1 to 924-L of each of the control devices 920-1 to 920-L are configured to receive a respective one of the bits of the thermometer code d2< L-1:0 >. For example, control input 924-1 of control device 920-1 receives bit d2<0> of thermometer code d2< L-1:0 >.

In operation, each of the control devices 920-1 through 920-L is configured to input either a first signal or a second signal to a respective pull-down device 815-1 through 815-L based on the logic value of a respective bit of thermometer code d2< L-1:0 >. For example, each of the control devices 920-1 through 920-L may be configured to input a first signal to a respective pull-down device when a respective bit has a first logic value and to input a second signal to a respective pull-down device when a respective bit has a second logic value, and vice versa.

FIG. 10 illustrates an exemplary embodiment of a control device 910-1 according to certain aspects. The exemplary embodiment of control device 910-1 shown in fig. 10 may be replicated for each of the other control devices 910-2 through 910-K.

In the example of fig. 10, control device 910-1 includes an or gate 1040 and a nand gate 1030. OR gate 1040 has a first input 1042, a second input 1044, and an output 1046. A first input 1042 of the or gate 1040 is coupled to the second input 916-1 of the control device 910-1 and thus receives the second signal. A second input 1044 of the or gate 1040 is coupled to the control input 914-1 of the control device 910-1 and thus receives the bit d1<0> of the first delay code. Nand gate 1030 has a first input 1032, a second input 1034, and an output 1036. A first input 1032 of the nand gate 1030 is coupled to an output 1046 of the or gate 1040. The second input 1034 of the NAND gate 1030 is coupled to the first input 912-1 of the control device 910-1 and thus receives the first signal. The output 1036 of NAND gate 1030 is coupled to pull-up device 810-1.

In this example, pull-up device 810-1 includes a corresponding transistor 820-1 implemented with a PFET. Thus, in this example, pull-up device 810-1 is turned on when control device 910-1 outputs zero to the gate of transistor 820-1 and turned off when control device 910-1 outputs one to the gate of transistor 820-1.

When bit d1<0> is one, OR gate 1040 outputs a one to NAND gate 1030. This causes the NAND gate 1030 to invert the first signal and input the inverted first signal to the pull-up device 810-1, which turns on the pull-up device 810-1 at the rising edge of the first signal. This is because nand gate 1030 inverts the rising edge of the first signal to a falling edge at the gate of transistor 820-1, which turns on pull-up device 810-1 in this example.

When bit d1<0> is zero, OR gate 1040 outputs a one to NAND gate 1030 on the rising edge of the second signal. Before the rising edge of the second signal arrives, OR gate 1040 outputs zero to NAND gate 1030, which causes NAND gate 1030 to output one to the gate of transistor 820-1, regardless of the logic value of the first signal. Accordingly, the pull-up device 810-1 remains turned off at the rising edge of the first signal. When the rising edge of the second signal arrives (e.g., after a coarse delay step from the rising edge of the first signal), or gate 1040 outputs a one to nand gate 1030. This causes the output 1036 of NAND gate 1030 to go low, which turns on pull-up device 810-1 in this example. Thus, in this example, when bit d1<0> is zero, pull-up device 810-1 is not turned on until the rising edge of the second signal.

Thus, in this example, a first signal is input to the pull-up device 810-1 when the corresponding bit d1<0> of the first delay code is one, and a second signal is input to the pull-up device 810-1 when the corresponding bit d1<0> of the first delay code is zero. In this example, the control device 910-1 inverts rising edges of the first signal and the second signal to turn on the pull-up device 810-1 at the rising edge of the first signal or the rising edge of the second signal according to the bit value of the bit d1<0 >.

As discussed above, the exemplary embodiment of the control device 910-1 may be replicated for each of the other control devices 910-2 through 910-K, where each of the other control devices 910-2 through 910-K receives a respective one of the bits of the first delay code and is coupled to a respective one of the pull-up devices 810-2 through 810-K.

It should be appreciated that the control device 910-1 is not limited to the exemplary embodiment illustrated in fig. 10, and that the control device 910-1 may be implemented with various combinations of logic gates configured to perform the functions described herein.

FIG. 10 also illustrates an exemplary embodiment of a control device 920-1 for controlling the inputs of the first signal and the second signal pull-down device 815-1. The exemplary embodiment of control device 920-1 shown in fig. 10 may be replicated for each of the other control devices 920-2 through 920-L.

In the example of fig. 10, control device 920-1 includes and gate 1070 and nor gate 1060. And gate 1070 has a first input 1072, a second input 1074, and an output 1076. A first input 1072 of and gate 1070 is coupled to a second input 926-1 of control device 920-1 and receives the second signal accordingly. A second input 1074 of and gate 1070 is coupled to control input 924-1 of control device 920-1 and thus receives bit d2<0> of the second delay code. Nor gate 1060 has a first input 1062, a second input 1064, and an output 1066. A first input 1062 of nor gate 1060 is coupled to an output 1076 of and gate 1070. A second input 1064 of nor gate 1060 is coupled to the first input 922-1 of control device 920-1 and receives the first signal accordingly. The output 1066 of nor gate 1060 is coupled to pull-down device 815-1.

In this example, the pull-down device 815-1 includes a corresponding transistor 825-1 implemented with an NFET. Thus, in this example, pull-down device 815-1 is turned on when controlling device 920-1 outputs a signal to the gate of transistor 825-1 and turned off when controlling device 920-1 outputs a signal to the gate of transistor 825-1.

When bit d2<0> is zero, AND gate 1070 outputs zero to NOR gate 1060. This causes nor gate 1060 to invert the first signal and input the inverted first signal to pull-down device 815-1, which turns on pull-down device 815-1 on the falling edge of the first signal. This is because nor gate 1060 inverts the falling edge of the first signal to a rising edge at the gate of transistor 825-1, which turns on pull-down device 815-1 in this example.

When bit d2<0> is one, and gate 1070 outputs zero to nor gate 1060 on the falling edge of the second signal. Before the falling edge of the second signal arrives, AND gate 1070 outputs a one to NOR gate 1060, which causes NOR gate 1060 to output a zero to the gate of transistor 825-1, regardless of the logic value of the first signal. Thus, the pull-down device 815-1 remains off on the falling edge of the first signal. When the falling edge of the second signal arrives (e.g., after a coarse delay step from the falling edge of the first signal), AND gate 1070 outputs zero to NOR gate 1060. This causes the output 1066 of nor gate 1060 to go high, which in this example turns on pull-down device 815-1. Thus, in this example, when bit d2<0> is one, pull-down device 815-1 is not turned on until the falling edge of the second signal.

Thus, in this example, the first signal is input to the pull-down device 815-1 when the corresponding bit d2<0> of the second delay code is zero, and the second signal is input to the pull-down device 815-1 when the corresponding bit d2<0> of the second delay code is one. In this example, the control device 920-1 inverts the falling edges of the first signal and the second signal to turn on the pull-down device 815-1 at the falling edge of the first signal or the falling edge of the second signal according to the bit value of the bit d2<0 >.

As discussed above, the exemplary embodiment of the control device 920-1 may be replicated for each of the other control devices 920-2 through 920-L, where each of the other control devices 920-2 through 920-L receives a respective one of the bits of the second delay code and is coupled to a respective one of the pull-down devices 815-2 through 815-L.

It should be appreciated that control device 920-1 is not limited to the exemplary embodiment illustrated in fig. 10, and that control device 920-1 may be implemented with various combinations of logic gates configured to perform the functions described herein.

Fig. 11 is a timing diagram illustrating exemplary voltage waveforms 1110-1 to 1110-8 at a node 830 for different delay settings for a first delay code and a second delay code, in accordance with certain aspects. Waveform 1110-1 corresponds to a delay setting where all pull-up devices 810-1 through 810-K receive the first signal and all pull-down devices 815-1 through 815-L receive the first signal. In the example shown in fig. 11, output buffer 860 has a rising edge threshold and a falling edge threshold, wherein output buffer 860 is configured to transition output 864 from zero to one when the rising edge at input 862 exceeds the (cross) rising edge threshold, and to transition output 864 from one to zero when the falling edge at input 862 exceeds the falling edge threshold.

In the example of fig. 11, the rising edge of the first signal reaches the delay interpolator 630 at time t 1. As shown by waveforms 1110-1 through 1110-8 in fig. 11, the slew rate at node 830 is different for different delay settings of the first delay code. In this example, the slew rate is slower when the number of pull-up devices 810-1 through 810-K receiving the first signal is smaller. This is because the number of pull-up devices 810-1 through 810-K that are turned on is smaller, which results in less current to charge capacitor 845 to pull up node 830. For example, waveform 1110-8 corresponds to a delay setting in which one less pull-up device receives the first signal than waveform 1110-7. This causes waveform 1110-8 to have a slower slew rate than waveform 1110-7, as shown in FIG. 11.

The corresponding rising edge of the second signal reaches the delay interpolator 630 at time t2 (e.g., one coarse delay step after the rising edge of the first signal). At this time, waveforms 1110-1 to 1110-8 for different delay settings have the same slew rate. This is because the rising edge of the second signal causes the remaining pull-up devices to turn on. In other words, after the rising edge of the second signal arrives, all of the pull-up devices 810-1 to 810-K are turned on. As shown in FIG. 11, waveforms 1110-1 through 1110-8 for different delay settings exceed the rising edge threshold of output buffer 860 at different times. This causes the output 864 of the output buffer 860 to transition from zero to one at different times for different delay settings of the first delay code, resulting in different delays being set at the output 864 for different delays.

In the example of FIG. 11, the different waveforms 1110-1 through 1110-8 are substantially evenly spaced apart at the rising edge threshold. This produces a substantially uniform fine delay step at output 864 of output buffer 860. In this example, uniform spacing between the different waveforms 1110-1 through 1110-8 at the rising edge threshold (and thus a substantially uniform fine delay step at output 864) is achieved by setting the rising edge threshold above the waveforms 1110-2 through 1110-8 until the rising edge of the second signal arrives.

In the example of fig. 11, the falling edge of the first signal reaches the delay interpolator 630 at time t 3. As shown by waveforms 1110-1 through 1110-8 in fig. 11, the slew rate at node 830 is different for different delay settings of the second delay code. In this example, the slew rate is slower when the number of pull-down devices 815-1 through 815-L receiving the first signal is smaller. This is because the number of pull-down devices 815-1 through 815-L that are turned on is smaller, which results in less current discharging capacitor 845 to pull down node 830.

The corresponding falling edge of the second signal reaches the delay interpolator 630 at time t4 (e.g., one coarse delay step after the falling edge of the first signal). At this time, waveforms 1110-1 through 1110-8 of different delay settings have the same slew rate. This is because the falling edge of the second signal causes the remaining pull-down devices to turn on. In other words, after the falling edge of the second signal arrives, all of the pull-down devices 815-1 to 815-L are turned on. As shown in FIG. 11, waveforms 1110-1 through 1110-8 for different delay settings exceed the falling edge threshold of output buffer 860 at different times. This causes the output 864 of the output buffer 860 to transition from one transition to zero at different times for different delay settings of the second delay code, resulting in different delays being set at the output 864 for different delays.

In the example of FIG. 11, the different waveforms 1110-1 through 1110-8 are substantially evenly spaced apart at the falling edge threshold. This produces a substantially uniform fine delay step at output 864 of output buffer 860. In this example, uniform spacing between the different waveforms 1110-1 through 1110-8 at the falling edge threshold (and thus a substantially uniform fine delay step at output 864) is achieved by setting the falling edge threshold below the waveforms 1110-2 through 1110-8 until the falling edge of the second signal arrives.

In the example in fig. 11, the rising edge threshold and falling edge threshold allow the output buffer 860 to achieve a substantially uniform fine delay step at the output 864 for both rising and falling edges. In the example of fig. 11, using a single threshold for output buffer 860 may result in uneven fine delay steps. In this regard, FIG. 11 shows an example of a single threshold 1120 at approximately Vdd/2. As shown in FIG. 11, waveforms 1110-1 through 1110-8 are not evenly spaced apart at threshold 1120, resulting in uneven fine delay steps for both rising and falling edges at output 864.

However, it should be appreciated that in other embodiments, the output buffer 860 may have a single threshold. In this example, output buffer 860 is configured to transition output 864 from zero to one when the voltage at input 862 rises above a threshold, and to transition output 864 from one to zero when the voltage at input 862 falls below the threshold. For example, a single threshold may be used for the case where the waveform of the different delay setting for the rising edge remains below Vdd/2 until the second signal arrives and the waveform of the different delay setting for the falling edge remains above Vdd/2 until the second signal arrives. In this case, output buffer 860 may achieve a substantially uniform fine delay step at output 864 for both rising and falling edges by setting the threshold to about Vdd/2. An advantage of using a rising edge threshold and a falling edge threshold for output buffer 860, rather than a single threshold, is that the rising edge threshold and the falling edge threshold relax the requirements on the waveform to achieve a substantially uniform fine delay step at output 864 for both rising and falling edges.

In the example discussed above with reference to fig. 11, output buffer 860 transitions output 864 from zero to one when the rising edge at input 862 exceeds the rising edge threshold, and transitions output 864 from one to zero when the falling edge at input 862 exceeds the falling edge threshold. However, it should be appreciated that output buffer 860 is not limited to this example. In other implementations, the output buffer 860 may be an inverting output buffer, where the output buffer 860 transitions the output 864 from one to zero when the rising edge at the input 862 exceeds a rising edge threshold, and transitions the output 864 from zero to one when the falling edge at the input 862 exceeds a falling edge threshold. In these embodiments, the first control circuit 840 may be used to tune the fine delay of the falling edge at the output 638 of the delay interpolator 630, while the second control circuit 850 may be used to tune the fine delay of the rising edge at the output 638 of the delay interpolator 630. In general, output buffer 860 may be configured to transition output 864 from a first logic state to a second logic state when a rising edge at input 862 exceeds a rising edge threshold, and to transition output 864 from the second logic state to the first logic state when a falling edge at input 862 exceeds a falling edge threshold. The first logic state may be zero and the second logic state may be one, or vice versa.

Fig. 12 illustrates an exemplary implementation of an output buffer 860 in accordance with certain aspects of the present disclosure. In this example, output buffer 860 includes a first inverter 1218, a second inverter 1258, and a threshold circuit 1238. The first inverter 1218 has an input 1222 coupled to an input 862 of the output buffer 860 and an output 1224. The second inverter 1258 has an input 1252 coupled to an output 1224 of the first inverter 1218 and an output 1254 coupled to an output 864 of the output buffer 860. In the example of fig. 12, first inverter 1218 and second inverter 1258 are implemented with complementary inverters. More specifically, first inverter 1218 includes PFET 1225 and NFET 1220, wherein gates of PFET 1225 and NFET 1220 are coupled to input 1222, sources of PFET 1225 are coupled to supply rail 870, drains of PFET 1225 and NFET 1220 are coupled to output 1224, and sources of NFET 1220 are coupled to ground. Second inverter 1258 includes PFET 1255 and NFET1250, wherein gates of PFET 1255 and NFET1250 are coupled to input 1252, sources of PFET 1255 are coupled to supply rail 870, drains of PFET 1255 and NFET1250 are coupled to output 1254, and sources of NFET1250 are coupled to ground.

In this example, the threshold circuit 1238 is configured to switch the input 1222 of the first inverter 1218 between a rising edge threshold and a falling edge threshold based on the first signal, as discussed further below. The threshold circuit 1238 includes a PFET 1240 and a first switch 1245. The gate of PFET 1240 is coupled to the gate of PFET 1225 in first inverter 1218 and the drain of PFET 1240 is coupled to the drain of PFET 1225 in first inverter 1218. A first switch 1245 is coupled between the source of PFET 1240 and supply rail 870. The first switch 1245 has a control input 1247 coupled to the first input 634 of the delay interpolator 630 to receive the first signal.

In this example, the first switch 1245 is configured to be on when the first signal is one and off when the first signal is zero. When the first switch 1245 is turned on, the first switch 1245 couples the source of the PFET 1240 to the supply rail 870, which couples the PFET 1240 in parallel with the PFET 1225 in the first inverter 1218. Thus, PFET 1240 increases the current drive from supply rail 870 to output 1224 of first inverter 1218, which increases the threshold of first inverter 1218 to the rising edge threshold. In this example, the rising edge threshold can be set to a desired voltage by setting the ratio of the size (e.g., width) of PFET 1240 to the size (e.g., width) of NFET 1220 accordingly. The larger the ratio, the higher the rising edge threshold.

Threshold circuit 1238 also includes NFET 1235 and second switch 1230. The gate of NFET 1235 is coupled to the gate of NFET 1220 in first inverter 1218 and the drain of NFET 1235 is coupled to the drain of NFET 1220 in first inverter 1218. A second switch 1230 is coupled between the source of NFET 1235 and ground. The second switch 1230 has a control input 1232 coupled to a first input 634 of the delay interpolator 630 to receive the first signal.

In this example, the second switch 1230 is configured to be on when the first signal is zero and off when the first signal is one. When second switch 1230 is on, second switch 1230 couples the source of NFET 1235 to ground, which couples NFET 1235 in parallel with NFET 1220 in first inverter 1218. Thus, NFET 1235 increases the current drive from output 1224 of first inverter 1218 to ground, which reduces the threshold of first inverter 1218 to a falling-edge threshold. In this example, the falling edge threshold may be set to the desired voltage by setting the ratio of the size (e.g., width) of NFET 1235 to the size (e.g., width) of PFET 1225 accordingly. The larger the ratio, the lower the falling edge threshold.

Thus, in this example, the threshold circuit 1238 sets the threshold of the first inverter 1218 to a rising edge threshold when the first signal is one and sets the threshold of the first inverter 1218 to a falling edge threshold when the first signal is zero.

It should be appreciated that output buffer 860 is not limited to the exemplary embodiment shown in fig. 12. For example, output buffer 860 may be implemented with an output buffer with built-in hysteresis (e.g., a schmitt trigger buffer) or another type of output buffer.

Fig. 13 shows an exemplary embodiment of a first switch 1245 and a second switch 1230. In this example, the first switch 1245 includes a PFET 1320 coupled between the PFET 1240 and the supply rail 870. The gate of PFET 1320 is coupled to a first input 634 of delay interpolator 630 via inverter 1340 such that PFET 1320 turns on when the first signal is one. Inverter 1340 has an input 1342 coupled to a first input 634 of delay interpolator 630 and an output 1344 coupled to the gate of PFET 1320.

In this example, second switch 1230 includes NFET 1330 coupled between NFET 1235 and ground. The gate of NFET 1330 is coupled to a first input 634 of delay interpolator 630 via inverter 1340 such that NFET 1330 turns on when the first signal is zero. The output 1344 of inverter 1340 is also coupled to the gate of NFET 1330.

In the examples discussed above, output buffer 860 is assumed to be non-inverting. However, it should be appreciated that this is not always the case. For the case where the output buffer 860 is inverted, the first control circuit 840 may control the fine delay of the falling edge at the output 638 of the delay interpolator 630 based on the first delay code, and the second control circuit 850 may control the fine delay of the rising edge at the output 638 of the delay interpolator 630 based on the second delay code. For example, the exemplary output buffer 860 shown in fig. 12 may be inverted by omitting the second inverter 1258 or adding another inverter.

As discussed above, coarse delay circuit 620 is not limited to the exemplary embodiment shown in fig. 7. In this regard, fig. 14 illustrates another exemplary implementation of coarse delay circuit 620 in accordance with certain aspects. In this example, coarse delay circuit 620 includes a plurality of delay devices 1410-1 through 1410-N coupled in series to form a delay line (e.g., a delay chain). Each of the delay devices 1410-1 through 1410-N has a respective input (labeled "input") and a respective output (labeled "output"). Each of the delay devices 1410-1 through 1410-N may have a coarse delay step τ _c Is a delay of (a). An input of delay device 1410-1 is coupled to an input 622 of coarse delay circuit 620. The output of each of the delay devices 1410-1 through 1410- (N-1) is coupled to the input of the next delay device 1410-2 through 1410-N in the delay line.

Coarse delay circuit 620 also includes a multiplexer 1430 having a plurality of inputs 1432-1 through 1432-N, an output 1434, and a select input 1436. Each of the inputs 1432-1 through 1432-N of the multiplexer 1430 is coupled to an output of a respective one of the delay devices 1410-1 through 1410-N in the delay line. Thus, each of inputs 1432-1 through 1432-N is coupled to a different point on the delay line corresponding to a different delay. An output 1434 of multiplexer 1430 is coupled to first output 624 and a select input 1436 of multiplexer 130 is coupled to delay control circuit 650.

Multiplexer 1430 is configured to receive a select signal from delay control circuit 650 at select input 1436 and to select one of inputs 1432-1 through 1432-N of multiplexer 1430 based on the received select signal, wherein the selected one of inputs 1432-1 through 1432-N is coupled to output 1434 of multiplexer 1430. Because each of inputs 1432-1 through 1432-N is coupled to a different point on the delay line corresponding to a different delay, delay control circuit 650 can use a select signal to control the tunable delay of coarse delay circuit 620 by controlling which of inputs 1432-1 through 1432-N is selected by multiplexer 1430. Thus, in this example, the selection signal is a delay control signal used by the delay control circuit 650 to tune the delay of the coarse delay circuit 620. The output 1434 of the multiplexer 1430 provides the first signal at the first output 624.

In this example, coarse delay circuit 620 also includes an additional delay device 1440 coupled between output 1434 of multiplexer 1430 and second output 626 to provide the second signal. The additional delay device 1440 may delay the first signal at the output 1434 of the multiplexer 1430 by a coarse delay step τ _c To provide a second signal at a second output 626. Thus, in this example, the second delay signal is delayed by a coarse delay step τ relative to the first delay signal _c . Since the delay between the first signal and the second signal is generated by the additional delay device 1440 in the coarse delay circuit 620, the delay between the first signal and the second signal tracks the change in coarse delay step size caused by the change in the coarse delay circuit 620 due to PVT variations.

As discussed above with reference to fig. 8, the first control circuit 840 and the second control circuit 850 allow for independent adjustment of the fine delay of the rising edge at the output 638 and the fine delay of the falling edge at the output 638, which can be used to adjust the duty cycle of the delayed signal at the output 638. For example, the duty cycle of the delayed signal at output 638 may be increased by increasing the delay of the falling edge relative to the rising edge (e.g., by increasing the delay setting of the second delay code). The duty cycle of the delayed signal at output 638 may be reduced by reducing the delay of the falling edge relative to the rising edge (e.g., by reducing the delay setting of the second delay code).

For example, duty cycle adjustment may be used in the data interface to achieve a duty cycle of about 50%. In one example, the data interface may be a Double Data Rate (DDR) memory interface, where data is captured from a received data signal on both rising and falling edges of a clock signal. In this example, a duty cycle of 50% of the clock signal is desired such that the data capture of the rising and falling edges of the clock signal are evenly spaced. In this example, delay circuit 610 may be used to delay the clock signal (e.g., center edges of the clock signal between transitions of the data signal). In addition, the first control circuit 840 and the second control circuit 850 may be used to adjust the duty cycle of the delayed clock signal to achieve a 50% duty cycle.

In this regard, fig. 15 illustrates an example of a data interface 1505 (e.g., DDR memory interface) in accordance with certain aspects of the present disclosure. In this example, data interface 1505 includes delay circuit 610 and delay control circuit 650. The data interface 1505 also includes a duty cycle detector 1510 and a latch 1520. The duty cycle detector 1510 has an input 1512 coupled to the output 614 of the delay circuit 610 and an output 1514 coupled to the delay control circuit 650. Latch 1520 has a data input 1524, a clock input 1522, and an output 1526.

In this example, delay circuit 610 receives a clock signal at input 612, delays the clock signal, and outputs a delayed clock signal at output 614. In one example, latch 1520 receives a data signal at data input 1524 and delay control circuit 650 adjusts the delay of delay circuit 610 to align the edges of the delayed clock signal between transitions of the data signal. In this example, latch 1520 receives a delayed clock signal at clock input 1522, captures (i.e., latches) data bits from the received data signal on rising and falling edges of the delayed clock signal, and outputs the data bits at output 1526. For examples of memory interfaces, data bits may be output to read-write circuitry to write data bits into memory and/or to a processor for further processing.

In this example, the duty cycle detector 1510 is configured to detect the duty cycle of the delayed clock signal, compare the detected duty cycle with a target duty cycle (e.g., 50%), and send a command to the delay control circuit 650 to adjust the duty cycle based on the comparison, thereby reducing the difference between the detected duty cycle and the target duty cycle. For example, if the detected duty cycle is greater than the target duty cycle, the duty cycle detector 1510 may instruct the delay control circuit 650 to decrease the duty cycle. In response, the delay control circuit 650 may reduce the duty cycle by reducing the delay of the falling edge relative to the rising edge (e.g., by reducing the delay setting of the second delay code). The duty cycle detector 1510 may instruct the delay control circuit 650 to increase the duty cycle if the detected duty cycle is less than the target duty cycle. In response, the delay control circuit 650 may increase the duty cycle by increasing the delay of the falling edge relative to the rising edge (e.g., by increasing the delay setting of the second delay code).

In one example, data interface 1505 may also include a coarse duty cycle adjuster (not shown). In this example, the duty cycle detector 1510 may make a coarse adjustment of the duty cycle of the clock signal using a coarse duty cycle adjuster and make a fine adjustment of the duty cycle of the clock signal using the delay circuit 610 based on the detected duty cycle versus the target duty cycle.

Fig. 16 illustrates a method 1600 of operating a delay interpolator in accordance with certain aspects of the present disclosure. The delay interpolator (e.g., delay interpolator 630) includes pull-up devices (e.g., pull-up devices 810-1 through 810-K) coupled between a supply rail (e.g., supply rail 870) and a node (e.g., node 830) and pull-down devices (e.g., pull-down devices 815-1 through 815-L) coupled between the node and ground.

In block 1610, a first signal is received. For example, the first signal may be received from a coarse delay circuit (e.g., coarse delay circuit 620).

In block 1620, a second signal delayed relative to the first signal is received. For example, the second signal may be received from a coarse delay circuit (e.g., coarse delay circuit 620). In one example, the second signal may be delayed relative to the first signal by one coarse delay step of the coarse delay circuit. In certain aspects, the coarse delay circuit delays an input signal (e.g., a data signal, a clock signal, etc.) by a tunable delay to provide a first signal and delays the input signal by a tunable delay and an additional delay (e.g., one coarse delay step) to provide a second signal.

In block 1630, a first signal is input to a programmable number of pull-up devices based on the first delay code. For example, a first signal may be input to a programmable number (e.g., number n) of pull-up devices by the first control circuit 840 based on the first delay code. In this example, the programmable number n is the number of pull-up devices (e.g., pull-up devices 810-1 through 810-K) to which the first control circuit 840 inputs the first signal based on the first delay code.

In block 1640, a second signal is input to the remaining pull-up devices of the pull-up devices. For example, the second signal may be input by the first control circuit 840 to the remaining pull-up devices in the pull-up devices.

In block 1650, the first signal is input to a programmable number of pull-down devices based on the second delay code. For example, the first signal may be input to a programmable number (e.g., number m) of pull-down devices by the second control circuit 850 based on the second delay code. In this example, the programmable number m is the number of pull-down devices (e.g., pull-down devices 815-1 through 815-L) to which the second control circuit 850 inputs the first signal based on the second delay code.

In block 1660, a second signal is input to the remaining ones of the pull-down devices. For example, the second signal may be input to the remaining pull-down devices of the pull-down devices by the second control circuit 850.

In one example, the first delay code and the second delay code may be different (e.g., to adjust the duty cycle). In another example, the first delay code and the second delay code may be the same. For example, in the case where the delay circuit 610 is used for interpolation, the first delay code and the second delay code may be the same.

In certain aspects, the first delay code comprises bits (e.g., d1< K-1:0 >). In these aspects, inputting the first signal to the programmable number of pull-up devices based on the first delay code includes: for each of the pull-up devices, a first signal is input to the pull-up device if a corresponding one of the bits of the first delay code has a first logic value. In these aspects, inputting the second signal to the remaining pull-up devices of the pull-up devices may include: for each of the pull-up devices, if a corresponding one of the bits of the first delay code has a second logic value, a second signal is input to the pull-up device.

In certain aspects, the second delay code comprises bits (e.g., d2< L-1:0 >). In these aspects, inputting the first signal to the programmable number of pull-down devices based on the second delay code includes: for each of the pull-down devices, a first signal is input to the pull-down device if a corresponding one of the bits of the second delay code has a first logic value. In these aspects, inputting the second signal to the remaining pull-down devices of the pull-down devices may include: for each of the pull-down devices, if a corresponding one of the bits of the second delay code has a second logic value, a second signal is input to the pull-down device.

An example of an embodiment is described in the following numbered clauses:

1. a delay interpolator, comprising:

a pull-up device, wherein each of the pull-up devices is coupled between the power rail and the node;

a pull-down device, wherein each of the pull-down devices is coupled between a node and ground;

a first control circuit coupled to the pull-up device, wherein the first control circuit has a first input configured to receive a first signal, a second input configured to receive a second signal delayed relative to the first signal, and a control input configured to receive a first delay code; and

a second control circuit is coupled to the pull-down device, wherein the second control circuit has a first input configured to receive the first signal, a second input configured to receive the second signal, and a control input configured to receive the second delay code.

2. The delay interpolator of clause 1, wherein each of the pull-up devices comprises a respective transistor having a gate coupled to the first control circuit.

3. The delay interpolator of clause 2, wherein each of the pull-down devices comprises a respective transistor having a gate coupled to the second control circuit.

4. The delay interpolator of any of clauses 1 to 3, wherein each of the pull-up devices comprises a respective p-type field effect transistor having a gate coupled to the first control circuit, a source coupled to the supply rail, and a drain coupled to the node.

5. The delay interpolator of any one of clauses 1 to 4, wherein each of the pull-down devices comprises a respective n-type field effect transistor having a gate coupled to the second control circuit, a drain coupled to the node, and a source coupled to ground.

6. The delay interpolator of any of clauses 1 to 5, wherein the first delay code and the second delay code are different.

7. The delay interpolator of any of clauses 1 to 5, wherein the first delay code and the second delay code are identical.

8. The delay interpolator of any of clauses 1 to 7 further comprising an output buffer having an output and an input coupled to the node.

9. The delay interpolator of clause 8, wherein the output buffer has a rising edge threshold and a falling edge threshold, and the output buffer is configured to: the output of the output buffer is transitioned from the first logic state to the second logic state when the rising edge at the input of the output buffer exceeds a rising edge threshold, and is transitioned from the second logic state to the first logic state when the falling edge at the input of the output buffer exceeds a falling edge threshold.

10. The delay interpolator of any of clauses 1 to 9 further comprising a capacitor coupled between the node and ground.

11. The delay interpolator of any of clauses 1 to 10 wherein:

the first delay code includes a plurality of bits;

the first control circuit includes a first plurality of control devices; and is also provided with

Each control device of the first plurality of control devices has a respective first input coupled to a first input of the first control circuit, a respective second input coupled to a second input of the first control circuit, a respective control input configured to receive a respective one of the bits of the first delay code, and a respective output coupled to a respective one of the pull-up devices.

12. The delay interpolator of clause 11, wherein each control device of the first plurality of control devices is configured to input the first signal or the second signal to a respective pull-up device of the pull-up devices based on a logic value of a respective bit of the bits of the first delay code.

13. The delay interpolator of clause 11 or 12, wherein:

the second delay code includes a plurality of bits;

the second control circuit includes a second plurality of control devices; and

each control device of the second plurality of control devices has a respective first input coupled to the first input of the second control circuit, a respective second input coupled to the second input of the second control circuit, a respective control input configured to receive a respective one of the bits of the second delay code, and a respective output coupled to a respective one of the pull-down devices.

14. The delay interpolator of clause 13, wherein:

each control device of the first plurality of control devices is configured to: inputting the first signal or the second signal to a corresponding one of the pull-up devices based on a logic value of a corresponding one of the bits of the first delay code; and is also provided with

Each control device of the second plurality of control devices is configured to: based on the logic value of the corresponding bit in the bits of the second delay code, the first signal or the second signalInput toCorresponding ones of the pull-down devices.

15. The delay interpolator of any of clauses 1 to 14, wherein the first control circuit is configured to input a first signal to a programmable number of pull-up devices based on the first delay code and to input a second signal to the remaining pull-up devices in the pull-up devices.

16. The delay interpolator of any of clauses 1 to 15, wherein the second control circuit is configured to input the first signal to a programmable number of pull-down devices based on the second delay code and to input the second signal to the remaining pull-down devices of the pull-down devices.

17. A method of operating a delay interpolator comprising a pull-up device coupled between a supply rail and a node and a pull-down device coupled between the node and ground, the method comprising:

Receiving a first signal;

receiving a second signal delayed relative to the first signal;

inputting a first signal to a programmable number of pull-up devices based on a first delay code;

inputting a second signal to the remaining pull-up devices of the pull-up devices;

inputting the first signal to a programmable number of pull-down devices based on the second delay code; and

the second signal is input to the remaining pull-down devices of the pull-down devices.

18. The method of clause 17, wherein the first delay code and the second delay code are different.

19. The method of clause 17, wherein the first delay code and the second delay code are the same.

20. The method according to any one of clauses 17 to 19, wherein:

the first delay code includes bits; and is also provided with

Inputting the first signal to the programmable number of pull-up devices based on the first delay code includes:

for each of the pull-up devices, a first signal is input to the pull-up device if a corresponding one of the bits of the first delay code has a first logic value.

21. The method of clause 20, wherein inputting the second signal to the remaining pull-up devices of the pull-up devices comprises:

for each of the pull-up devices, a second signal is input to the pull-up device if a corresponding one of the bits of the first delay code has a second logic value.

22. The method according to any one of clauses 17 to 21, wherein:

the second delay code includes bits; and is also provided with

Inputting the first signal to the programmable number of pull-down devices based on the second delay code includes:

for each of the pull-down devices, a first signal is input to the pull-down device if a corresponding one of the bits of the second delay code has a first logic value.

23. The method of clause 22, wherein inputting the second signal into the remaining ones of the pull-down devices comprises:

for each of the pull-down devices, a second signal is input to the pull-down device if a corresponding one of the bits of the second delay code has a second logic value.

24. A system, comprising:

a delay circuit having an input, a first output, and a second output; and

a delay interpolator, comprising:

a first control circuit coupled to the pull-up device, wherein the first control circuit has a first input coupled to the first output of the delay circuit, a second input coupled to the second output of the delay circuit, and a control input configured to receive the first delay code; and

A second control circuit coupled to the pull-down device, wherein the second control circuit has a first input coupled to the first output of the delay circuit, a second input coupled to the second output of the delay circuit, and a control input configured to receive the second delay code.

25. The system of clause 24, wherein the delay circuit is configured to: the method includes receiving an input signal at an input of a delay circuit, delaying the input signal by a tunable delay to provide a first signal at a first output of the delay circuit, and delaying the input signal by the tunable delay and an additional delay to provide a second signal at a second output of the delay circuit.

26. The system of clause 25, wherein the delay circuit is configured to tune the tunable delay to a multiple of the delay step based on the delay control signal, and the additional delay is equal to the delay step.

27. The system of any of clauses 25 or 26, wherein the first control circuit is configured to: the first signal is input to a programmable number of pull-up devices based on the first delay code and is configured to input the second signal to the remaining pull-up devices of the pull-up devices.

28. The system of any of clauses 25 to 27, wherein the second control circuit is configured to input the first signal to a programmable number of pull-down devices based on the second delay code, and to input the second signal to the remaining pull-down devices of the pull-down devices.

29. The system of any of clauses 24-28, wherein the delay interpolator further comprises an output buffer having an output and an input coupled to the node.

30. The system of clause 29, wherein the output buffer has a rising edge threshold and a falling edge threshold, and the output buffer is configured to: the output of the output buffer is transitioned from the first logic state to the second logic state when the rising edge at the input of the output buffer exceeds a rising edge threshold, and is transitioned from the second logic state to the first logic state when the falling edge at the input of the output buffer exceeds a falling edge threshold.

31. The system of clause 29 or 30, further comprising a latch having a data input, a clock input coupled to the output of the output buffer, and an output.

32. The system of any of clauses 24 to 31, wherein the first delay code and the second delay code are different.

33. The system of any of clauses 24 to 31, wherein the first delay code and the second delay code are the same.

34. The system according to clause 25, wherein:

the first delay code includes a plurality of bits;

the first control circuit includes a first plurality of control devices; and

35. The system of clause 34, wherein each control device of the first plurality of control devices is configured to input the first signal or the second signal to a respective one of the pull-up devices based on a logic value of a respective one of the bits of the first delay code.

36. The system according to clause 34 or 35, wherein:

the second delay code includes a plurality of bits;

the second control circuit includes a second plurality of control devices; and

37. The system according to clause 36, wherein:

each control device of the first plurality of control devices is configured to: inputting the first signal or the second signal to a corresponding one of the pull-up devices based on a logic value of a corresponding one of the bits of the first delay code; and

each control device of the second plurality of control devices is configured to: the first signal or the second signal is input to a corresponding one of the pull-down devices based on a logic value of a corresponding one of the bits of the second delay code.

38. The delay interpolator of clause 1, wherein the first signal and the second signal are received from a delay circuit and the second signal is delayed relative to the first signal by a delay step of the delay circuit.

39. The delay interpolator of clause 1 or 38, wherein the first signal and the second signal are received from a delay circuit, and the delay circuit is configured to provide the second signal by delaying the first signal by an additional delay device.

It is to be understood that the present disclosure is not limited to the above exemplary terms used to describe aspects of the present disclosure. For example, a delay device may also be referred to as a delay stage, a delay buffer, a delay element, a delay cell, or another terminology. The control device may also be referred to as control logic, a control circuit, or another terminology. The delay circuit may also be referred to as a delay line or another term.

The delay control circuit 650 may be implemented with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor may perform the functions described herein by executing software that includes code for performing the functions. The software may be stored on a computer readable storage medium such as RAM, ROM, EEPROM, an optical disk and/or a magnetic disk.

In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to either direct or indirect electrical coupling between two structures. It should also be appreciated that the term "ground" may refer to either DC ground or AC ground, and thus the term "ground" encompasses both possibilities.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A delay interpolator, comprising:

a pull-up device, wherein each of the pull-up devices is coupled between a supply rail and a node;

a pull-down device, wherein each of the pull-down devices is coupled between the node and ground;

a second control circuit is coupled to the pull-down device, wherein the second control circuit has a first input configured to receive the first signal, a second input configured to receive the second signal, and a control input configured to receive a second delay code.

2. The delay interpolator of claim 1, wherein each of the pull-up devices comprises a respective transistor having a gate coupled to the first control circuit.

3. The delay interpolator of claim 2, wherein each of the pull-down devices comprises a respective transistor having a gate coupled to the second control circuit.

4. The delay interpolator of claim 1, wherein each of the pull-up devices comprises a respective p-type field effect transistor having a gate coupled to the first control circuit, a source coupled to the supply rail, and a drain coupled to the node.

5. The delay interpolator of claim 4, wherein each of the pull-down devices comprises a respective n-type field effect transistor having a gate coupled to the second control circuit, a drain coupled to the node, and a source coupled to the ground.

6. The delay interpolator of claim 1, wherein the first delay code and the second delay code are different.

7. The delay interpolator of claim 1, wherein the first delay code and the second delay code are the same.

8. The delay interpolator of claim 1, further comprising an output buffer having an output and an input coupled to the node.

9. The delay interpolator of claim 8, wherein the output buffer has a rising edge threshold and a falling edge threshold, and the output buffer is configured to: the output of the output buffer is transitioned from a first logic state to a second logic state when a rising edge at the input of the output buffer exceeds the rising edge threshold, and the output of the output buffer is transitioned from the second logic state to the first logic state when a falling edge at the input of the output buffer exceeds the falling edge threshold.

10. The delay interpolator of claim 8, further comprising a capacitor coupled between the node and the ground.

11. The delay interpolator of claim 1, wherein:

the first delay code includes a plurality of bits;

Each control device of the first plurality of control devices has a respective first input coupled to the first input of the first control circuit, a respective second input coupled to the second input of the first control circuit, a respective control input configured to receive a respective one of the bits of the first delay code, and a respective output coupled to a respective one of the pull-up devices.

12. The delay interpolator of claim 11, wherein each control device of the first plurality of control devices is configured to: the first signal or the second signal is input to the respective one of the pull-up devices based on a logic value of the respective one of the bits of the first delay code.

13. The delay interpolator of claim 11, wherein:

the second delay code includes a plurality of bits;

the second control circuit includes a second plurality of control devices; and is also provided with

14. The delay interpolator of claim 13, wherein:

each control device of the first plurality of control devices is configured to: inputting the first signal or the second signal to the respective one of the pull-up devices based on a logic value of the respective one of the bits of the first delay code; and is also provided with

Each control device of the second plurality of control devices is configured to: the first signal or the second signal is input to the respective one of the pull-down devices based on a logic value of the respective one of the bits of the second delay code.

15. The delay interpolator of claim 1, wherein the first control circuit is configured to: the first signal is input to a programmable number of the pull-up devices based on the first delay code and the second signal is input to the remaining ones of the pull-up devices.

16. The delay interpolator of claim 15, wherein the second control circuit is configured to input the first signal to a programmable number of the pull-down devices based on the second delay code and to input the second signal to a remaining one of the pull-down devices.

receiving a first signal;

receiving a second signal delayed relative to the first signal;

inputting the first signal to a programmable number of the pull-up devices based on a first delay code;

inputting the second signal to the remaining pull-up devices of the pull-up devices;

inputting the first signal to a programmable number of the pull-down devices based on a second delay code; and

18. The method of claim 17, wherein the first delay code and the second delay code are different.

19. The method of claim 17, wherein the first delay code and the second delay code are the same.

20. The method according to claim 17, wherein:

the first delay code includes bits; and is also provided with

Inputting the first signal to the programmable number of the pull-up devices based on the first delay code includes:

For each of the pull-up devices, if a corresponding one of the bits of the first delay code has a first logic value, the first signal is input to the pull-up device.

21. The method of claim 20, wherein inputting the second signal to the remaining ones of the pull-up devices comprises:

for each of the pull-up devices, if the corresponding one of the bits of the first delay code has a second logic value, the second signal is input to the pull-up device.

22. The method according to claim 17, wherein:

the second delay code includes bits; and is also provided with

Inputting the first signal to the programmable number of the pull-down devices based on the second delay code includes:

for each of the pull-down devices, if a corresponding one of the bits of the second delay code has a first logic value, the first signal is input to the pull-down device.

23. The method of claim 22, wherein inputting the second signal to the remaining one of the pull-down devices comprises:

For each of the pull-down devices, if the corresponding one of the bits of the second delay code has a second logic value, the second signal is input to the pull-down device.

24. A system, comprising:

a delay circuit having an input, a first output, and a second output; and

a delay interpolator, comprising:

a first control circuit coupled to the pull-up device, wherein the first control circuit has a first input coupled to the first output of the delay circuit, a second input coupled to the second output of the delay circuit, and a control input configured to receive a first delay code; and

a second control circuit coupled to the pull-down device, wherein the second control circuit has a first input coupled to the first output of the delay circuit, a second input coupled to the second output of the delay circuit, and a control input configured to receive a second delay code.

25. The system of claim 24, wherein the delay circuit is configured to: an input signal is received at the input of the delay circuit, delayed by a tunable delay to provide a first signal at the first output of the delay circuit, and delayed by the tunable delay and an additional delay to provide a second signal at the second output of the delay circuit.

26. The system of claim 25, wherein the delay circuit is configured to tune the tunable delay by a multiple of a delay step based on a delay control signal, and the additional delay is equal to the delay step.

27. The system of claim 25, wherein the first control circuit is configured to: the first signal is input to a programmable number of the pull-up devices based on the first delay code and is configured to input the second signal to remaining ones of the pull-up devices.

28. The system of claim 27, wherein the second control circuit is configured to input the first signal to a programmable number of the pull-down devices based on the second delay code and to input the second signal to a remaining one of the pull-down devices.

29. The system of claim 24, wherein the delay interpolator further comprises an output buffer having an output and an input coupled to the node.

30. The system of claim 29, wherein the output buffer has a rising edge threshold and a falling edge threshold, and the output buffer is configured to: the output of the output buffer is transitioned from a first logic state to a second logic state when a rising edge at the input of the output buffer exceeds the rising edge threshold, and the output of the output buffer is transitioned from the second logic state to the first logic state when a falling edge at the input of the output buffer exceeds the falling edge threshold.

31. The system of claim 29, further comprising a latch having a data input, a clock input coupled to the output of the output buffer, and an output.