KR102623356B1 - Organic light emitting display device and method for driving the same - Google Patents

Abstract

The present invention provides an organic light emitting display device that can be driven without image distortion by calculating the expected current in real time without using a frame memory and lowering the constant voltage (EVDD) when a current higher than a certain value is required, and a driving method thereof. Relatedly, an organic light emitting display device according to the present invention includes a display panel composed of a plurality of pixels including organic light emitting elements that emit light by a current corresponding to a data voltage; And a panel driver that analyzes input image data every horizontal period to derive a predicted current, and reduces EVDD supplied to the organic light emitting device when the derived predicted current is higher than a threshold.

Description

Organic light emitting display device and method for driving the same}

The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device and a driving method thereof that are driven by lowering a constant voltage (EVDD) when the predicted current of the current frame is determined to be high without using a frame memory.

As the information society develops and various portable electronic devices such as mobile communication terminals and laptop computers develop, the demand for flat panel display devices applicable to them is gradually increasing.

In response to this, flat panel display devices such as liquid crystal displays (LCDs) and organic light emitting display devices are being commercialized.

Among these flat panel displays, organic light emitting display devices have a high-speed response speed, low power consumption, and do not have problems with viewing angles because they emit light themselves, so they are attracting attention as next-generation flat panel displays.

The organic light emitting display device consists of an OLED display panel that displays an image, and a driving circuit for driving the display panel.

The OLED display panel has sub-pixels defined by intersections of the plurality of gate lines and the plurality of data lines, and each sub-pixel includes an OLED composed of an anode and a cathode and an organic light-emitting layer between the anode and the cathode, and the OLED It is provided with a pixel circuit that independently drives.

The pixel circuit may be configured in various ways, but includes at least one switching transistor, a capacitor, and a driving transistor.

The switching transistor switches according to the gate signal supplied to the gate line and charges the capacitor with the data voltage supplied through the data line.

The driving transistor switches according to the data voltage stored in the capacitor to control the current flowing through the OLED.

The OLED emits light by current controlled by the driving transistor.

Each pixel of such an organic light emitting display device displays a predetermined image by controlling the size of the data current flowing to the OLED by the driving voltage (EVDD) using switching of the driving transistor according to the data voltage and causing the OLED to emit light.

In such an organic light emitting display device, the current flowing through the display panel varies depending on the input image. That is, in the case of a full black image, little current flows through the display panel, but in the case of a full white image, a lot of current flows through the display panel. Accordingly, in the case of a specific image with many white patterns, excessive current may flow through the display panel.

And, when the power supply unit outputs high power (voltage * current) above a certain value, a power down phenomenon occurs.

To prevent this phenomenon, the expected current of the output frame is calculated, and when high output is expected, the output frame is driven by lowering the luminance.

In this way, in order to calculate the expected current of the output frame, the image data of the previous frame and the image data of the current frame must be compared, so a frame memory is essential.

Additionally, the brightness of the display panel is reduced by applying an Automatic Current Limit algorithm that controls the current flowing through the display panel according to the input image of one frame.

That is, the automatic current limiting algorithm calculates the expected current in real time, and when a current higher than a certain value is required, the image is processed to black to adjust the output voltage.

However, such conventional organic light emitting display devices had the following problems.

First, since frame memory is needed to calculate the expected current of the output frame, the cost of using frame memory increases, the size of the printed circuit board (PCB) increases, and the area of the chip increases. This increases.

Second, an automatic current limiting algorithm is applied to process the output image as black, resulting in image distortion.

The present invention is intended to solve the above-described conventional problems. Instead of using frame memory, the present invention calculates the expected current in real time and lowers the constant voltage (EVDD) when a current higher than a certain value is required, thereby driving the operation without image distortion. The purpose is to provide an organic light emitting display device and a method of driving the same.

An organic light emitting display device according to the present invention for achieving the above object includes a display panel composed of a plurality of pixels including organic light emitting elements that emit light by a current corresponding to a data voltage; In addition, it is characterized by including a panel driver that analyzes input image data every horizontal period to derive a predicted current, and reduces EVDD supplied to the organic light emitting device when the derived predicted current is higher than a threshold.

Here, the panel driver may further include stopping the operation of sensing the driving characteristics or deterioration of each pixel when the derived predicted current is higher than the threshold.

The panel driver may include a timing control unit that analyzes input image data for each horizontal period to derive a predicted current and reduces EVDD supplied to the organic light emitting device when the derived predicted current is higher than a threshold value; a gate driver sequentially supplying gate signals to a plurality of gate lines under the control of the timing controller; and a data driver that converts the image data input from the timing controller into an analog data voltage and supplies it to the corresponding data line.

The timing control unit measures the luminance and corresponding current values of red (R), green (G), blue (B), and white (W), and stores the corresponding voltage, current, and luminance values for each gray. -A current table, an image processor that calculates the image data input from the set with the PLC gain of the previous frame and outputs the calculated data (Ldata'), the image data (Ldata') calculated from the image processor and the gray- Using a current table, a predicted current is derived by analyzing the input image data input every horizontal period. If the derived predicted current is higher than a threshold, the EVDD supplied to the organic light emitting device is reduced and the driving characteristics or It is characterized by having a real-time prediction current derivation unit that omits degradation sensing.

The timing control unit includes an EVDD control unit that controls the power supply unit to reduce the EVDD output according to the control of the real-time prediction current deriving unit, outputs data (Ldata') calculated by the image processing unit to the corresponding data driving IC, and vertical blanks. A data output and sensing unit that senses the driving characteristics or degradation of each pixel of the display panel during a period, and a sensing unit that stops sensing the driving characteristics or degradation of each pixel of the data output and sensing unit under control of the real-time prediction current deriving unit. It is characterized by further comprising a scheduler.

The image processing unit restores the original image data (Ldata) to track a value proportional to luminance from the image data input from the set, and performs a multiplication operation by multiplying the PLC gain value of the previous frame by the original image data (Ldata). The calculated data (Ldata') is output to the real-time prediction current derivation unit and the data output and sensing unit.

The real-time prediction current deriving unit receives the calculated image data (Ldata') from the image processing unit, calculates and accumulates the average current luminance for each horizontal line using the gray-current table, and divides one frame into a plurality of sections. The threshold value is set for each section, and the accumulated average current luminance value for each section is compared with the threshold value for each section. If the accumulated average current luminance value exceeds the threshold value for each section, an EVDD reduction control signal is sent. Output, repeat the above process for each section, and when one frame accumulation is completed, the PLC gain value is derived from the accumulated average current luminance value and output to the image processing unit to be used as the PLC gain of the previous frame when processing the next frame image. It is characterized by

In addition, the method of driving an organic light emitting display device according to the present invention to achieve the above object is to increase the data voltage from 0V to the highest voltage, measure the luminance and the corresponding current value, and tabulate the gray-current. step; Deriving a predicted current by analyzing input image data input at each horizontal period using data (Ldata') calculated by calculating the PLC gain of the previous frame and original image data (Ldata) and the gray-current table; Another feature is that, if the derived predicted current is higher than the threshold, the EVDD supplied to the organic light emitting device is reduced and the operation of measuring the driving characteristics or deterioration of each pixel is omitted.

The organic light emitting display device and its driving method according to the present invention having the above features have the following effects.

First, since frame memory is not used, unit cost can be reduced, PCB size and chip area can be reduced.

Second, by calculating the expected current in real time and driving by lowering the constant voltage (EVDD) when a voltage higher than a certain value is required, phenomena such as flicker and video interruption can be prevented. Therefore, image quality can be improved.

Third, when a voltage higher than a certain value is required, it is driven by lowering the constant voltage (EVDD), thereby reducing power consumption.

1 is a configuration diagram of an organic light emitting display device according to an embodiment of the present invention.
Figure 2 is a detailed configuration diagram of a timing controller of an organic light emitting display device according to an embodiment of the present invention.
3 is a gray-current table stored in the gray-current table according to an embodiment of the present invention.
Figure 4 is a timing diagram for explaining the frame and EVDD control operation of the organic light emitting display device according to the present invention.
Figure 5 is an operation flowchart of the setting step before product shipment of the organic light emitting display device according to the present invention.
6 is an operation flowchart of a method of driving an organic light emitting display device according to the present invention after product shipment.
Figure 7 is a comparative diagram of EVDD voltage and data voltage

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. Only the embodiments are intended to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

The organic light emitting display device and its driving method according to the present invention having the above features will be described in more detail with reference to the attached drawings as follows.

1 is a configuration diagram of an organic light emitting display device according to an embodiment of the present invention.

An organic light emitting display device according to an embodiment of the present invention includes a display panel 100 and a panel driver 200, as shown in FIG. 1 .

The display panel 100 emits light from the organic light emitting diode (OLED) of each pixel (P) according to the data voltage (Vdata) supplied from the panel driver 200, thereby generating a predetermined amount of light through the light emitted from each pixel (P). Displays color images. To this end, the display panel 100 includes n (where n is a natural number) data lines (DL) and m (where m is a natural number) gate lines (GL) that are formed to cross each other and define a pixel area, It is configured to include a first constant voltage line (PL1) and a second constant voltage line (PL2) formed in parallel with n data lines (DL) and connected to each pixel (P).

Each of the n data lines DL and the m gate lines GL is formed to cross each other at regular intervals. Here, each of the m gate lines GL forms m horizontal lines of the display panel 100.

The first constant voltage line PL1 is arranged in parallel adjacent to the data line DL to supply a first constant voltage ELVDD to each pixel from a power supply (not shown), and the second constant voltage line PL2 supplies a second constant voltage (ELVSS) of a low potential voltage level or a ground (or ground) voltage level lower than the first constant voltage (ELVDD) to each pixel from the power supply unit (not shown).

Each pixel (P) responds to the gate signal (GS; scan signal) supplied from the corresponding gate line (GL), and receives a predetermined data current corresponding to the data voltage (Vdata) supplied from the corresponding data line (DL). Emits monochromatic light. Each of these plurality of pixels P may be composed of one of red, green, blue, and white. Accordingly, a unit pixel displaying one color image may be composed of adjacent red pixels, green pixels, and blue pixels, or may be composed of adjacent red pixels, green pixels, blue pixels, and white pixels. To this end, each of the plurality of pixels P includes an organic light emitting device (OLED) and a pixel circuit (PC) that independently drives the organic light emitting device (OLED).

The organic light emitting device (OLED) is connected between the pixel circuit (PC) and the second constant voltage line (PL2) and emits light in proportion to the data current supplied from the pixel circuit (PC) to emit a predetermined monochromatic light. . To this end, the organic light emitting device (OLED) includes an anode electrode (or pixel electrode) connected to the pixel circuit (PC), a cathode electrode (or reflective electrode) connected to the second constant voltage line PL2, and the anode. It is comprised of an organic layer formed between an electrode and the cathode electrode.

Here, the organic layer may be formed to have a structure of a hole transport layer/organic emission layer/electron transport layer or a structure of a hole injection layer/hole transport layer/organic emission layer/electron transport layer/electron injection layer. Furthermore, a functional layer may be additionally formed on the organic layer to improve the luminous efficiency and/or lifespan of the organic light-emitting layer.

The pixel circuit (PC) receives a data voltage (Vdata) supplied from the panel driver 200 to the data line (DL) in response to the gate signal (GS) supplied from the panel driver 200 to the gate line (GL). ) Based on this, the current flowing from the corresponding first constant voltage line PL1 to the organic light emitting device (OLED) is controlled.

To this end, the pixel circuit (PC) includes a driving transistor (not shown) that controls the current flowing from the first constant voltage line (PL1) to the organic light emitting device (OLED) based on the data voltage (Vdata), the driving transistor A switching transistor (not shown) that supplies the data voltage (Vdata) to the gate electrode of the driving transistor, and a storage capacitor connected between the gate electrode and the source electrode of the driving transistor to maintain the gate-source voltage of the driving transistor for one frame. It may be configured to include (not shown).

Here, the pixel circuit (PC) is not limited to being composed of two transistors and one capacitor, and includes an internal compensation structure or a driving transistor for compensating for changes in threshold voltage/mobility of the driving transistor inside the pixel (P). It may be configured to further include a compensation circuit corresponding to an external compensation structure for sensing changes in threshold voltage/mobility and compensating outside the display panel 100 through data correction.

The panel driver 200 calculates the panel current value flowing through the display panel 100 for each horizontal period based on the current horizontal line data (Idata) input in horizontal period units, and sets the calculated panel current value below the overcurrent limit value. The current gain value for control is calculated, and the input data (Idata) is modulated according to the calculated current gain value and displayed on the display panel 100. That is, the panel driver 200 predicts the panel current value flowing through the display panel 100 for each current horizontal period based on the current horizontal line data (Idata), and based on the predicted panel current value, the current horizontal line data (Idata) By modulating Idata), the generation of overcurrent momentarily flowing through the display panel 100 is effectively controlled to prevent problems caused by overcurrent. To this end, the panel driver 200 includes a timing controller 210, a gate driver 220, and a data driver 230.

The timing control unit 210 receives timing synchronization signals (TSS) such as a vertical synchronization signal, horizontal synchronization signal, data enable signal, and main clock input from the outside, that is, the system main body (not shown) or a graphics card (not shown). Based on , a gate control signal (GCS) for controlling the gate driver 220 and a data control signal (DCS) for controlling the data driver 230 are generated, respectively.

In addition, the timing control unit 210 measures the luminance of red (R), green (G), blue (B), and white (W) and the corresponding current value, and provides a corresponding voltage for each gray, Current and luminance values are stored in a gray-current table.

Then, the PLC gain (Peak Luminance Control gain; hereinafter referred to as 'PLC gain') and the original image data (Ldata) of the previous frame are calculated (Ldata'). Using the calculated data (Ldata') and the stored gray-current table, average current luminance (ACL) is calculated and accumulated for each horizontal line, a threshold value is set for each section, and the average current luminance (ACL) is calculated and accumulated for each section. The accumulated average current luminance (ACL) value is compared with the threshold value of each section, and when the accumulated average current luminance (ACL) value exceeds the threshold value, EVDD is reduced, and the driving characteristics of each pixel (threshold of the driving transistor) are compared. Voltage or mobility) or degradation sensing is omitted.

When accumulation of one frame is completed, the timing control unit 210 derives the PLC gain value from the accumulated average current luminance (ACL) value and calculates the predicted current of the next frame.

The gate driver 220 generates a gate signal GS for data addressing in response to the gate control signal GCS supplied from the timing controller 210 and sequentially supplies the gate signal GS to the m gate lines GL. The gate driver 220 may be formed of a shift register that sequentially outputs the gate signal GS according to the gate control signal GCS.

The data driver 230 receives the data control signal (DCS) supplied from the timing controller 210 and the modulation data (Mdata) for one horizontal line, and generates a plurality of different signals from a reference gamma voltage generator (not shown). Receives the reference gamma voltage of . The data driver 230 samples modulated data (Mdata) input in units of one horizontal line according to a data control signal (DCS), and converts the sampled data based on the plurality of reference gamma voltages into an analog data voltage. (Vdata) and supplied to the data line (DL) of each pixel (P).

As such, the organic light emitting display device according to an embodiment of the present invention predicts the panel current value flowing through the display panel 100 for each current horizontal period based on the current horizontal line data (Idata) and based on the predicted panel current value. By modulating the current horizontal line data (Idata), the occurrence of overcurrent momentarily flowing through the display panel 100 can be accurately predicted and suppressed.

Figure 2 is a detailed configuration diagram of a timing control unit of an organic light emitting display device according to an embodiment of the present invention, and Figure 3 is a gray-current stored in a gray-current table (Gray-Current Table, 211) according to an embodiment of the present invention. It is a table, and FIG. 4 is a timing diagram for explaining the frame and EVDD control operation of the organic light emitting display device according to the present invention.

The specific configuration of the timing control unit 210 of the organic light emitting display device according to the present invention will be described as follows.

As shown in FIG. 2, the timing control unit 210 of the organic light emitting display device according to the present invention includes a gray-current table 211, an image processing unit 213, and a real-time prediction current deriving unit 212. ), an EVDD control unit 215, a sensing scheduler 216, and a data output and sensing unit 214.

First, using a luminance meter and a current meter, before shipping the product, increase the data voltage (Vdata) from 0V to the maximum value (corresponding to luminance Max) and measure the red (R), green (G), blue (B) and The luminance of white (W) and the corresponding current value are measured, and the corresponding voltage, current, and luminance values for each gray are stored in the gray-current table of the timing control unit 200 (211). ) to save it. The gray-current table is as shown in FIG. 3.

And, video data (gray) input from the set 300 such as a computer, laptop, TV, etc. to the display device is subjected to inverse gamma (1/2.2) processing.

Therefore, the image processing unit 213 performs gamma processing (2.2) on the image data to track a value proportional to luminance from the video data (Gray) input from the set 300 to obtain the original image data ( Restore Ldata = ^{Gray 2. 2} ). In addition, the image processing unit 213 calculates the PLC gain (Peak Luminance Control gain; hereinafter referred to as 'PLC gain') of the previous frame and the original image data (Ldata) and performs the real-time prediction using the calculated data (Ldata'). It is output to the current deriving unit 212 and the data output and sensing unit 214.

The calculated data (Ldata') is as shown in [Equation 1] below.

The real-time prediction current deriving unit 212 receives the calculated image data (Ldata') from the image processing unit 213 and uses the gray-current table 211 to calculate the average current for each horizontal line during frame driving. Luminance (Average Current Luminance (ACL)) is calculated and accumulated.

Then, one frame (1 frame) is divided into a plurality of sections and a threshold value is set for each section. That is, assuming that one frame has 100 horizontal lines and is divided into 4 sections, the first section is 1-25 horizontal lines, the second section is 26-50 horizontal lines, and the third section is 51-75 horizontal lines. Section 4 becomes the 76-100 horizontal line.

In this way, it is divided into a plurality of sections and a threshold value is set for each section. That is, the first section is 30% of the total accumulated ACL of one frame, the second section is 60% of the total accumulated ACL of one frame, the third section is 80% of the total accumulated ACL of one frame, and the fourth section is is set to 100% of the total accumulated ACL of one frame.

Then, the average current luminance (ACL) value accumulated for each section is compared with the threshold value of the section, and when the accumulated average current luminance (ACL) value exceeds the threshold value, an EVDD reduction control signal is output.

For example, if the accumulated average current luminance value (ACL) exceeds the threshold value (60%) of the second section, the EVDD control unit 215 and the sensing schedule send a control signal to reduce the EVDD voltage by about 20%. It outputs as (216).

The above process is repeated for each section, and when 1 frame accumulation is completed, the PLC gain value is derived from the accumulated average current luminance (ACL) value. The PLC gain value derived in this way is output to the image processing unit 213.

The image processing unit 213, which has received the derived PLC gain value, processes the next frame image by using it as the PLC gain of the previous frame when processing the next frame image.

When the EVDD reduction control signal is received from the real-time prediction current deriving unit 212, the EVDD control unit 215 controls the power supply unit 400 to reduce the EVDD output.

For example, if the power supply unit 400 is outputting the EVDD voltage at 24V and, as described above, the accumulated average current luminance value (ACL) exceeds the threshold value (60%) of the second section, The EVDD control unit 215 controls the power supply unit 400 to lower the EVDD voltage to 20V and output it.

In this way, when the EVDD voltage is lowered to 20V and output from the power supply unit 400, the average current luminance (ACL) margin is secured by an additional 20%, and the cumulative threshold becomes 50%.

Meanwhile, when the sensing scheduler 216 receives the EVDD reduction control signal from the real-time prediction current deriving unit 212, the data output and sensing unit 214 determines the driving characteristics of each pixel of the display panel 100. A control signal is output to stop the operation of sensing (threshold voltage or mobility of the driving transistor) and deterioration.

The data output and sensing unit 214 receives the data (Ldata') calculated by the image processing unit 213 and outputs it to the corresponding data driving IC, and displays each of the display panel 100 during the vertical blank (Vblank) period. Sensing the driving characteristics and deterioration of the pixel. At this time, if a control signal to stop the sensing operation is received from the sensing scheduler 216, sensing of the driving characteristics and deterioration of each pixel of the display panel 100 is omitted during the vertical blank (Vblank) period of the frame.

A summary of such operations is shown in Figure 4.

That is, upon receiving the N-th frame data, the image processing unit 213 calculates the PLC gain and the original image data (Ldata) of the previous frame and sends the calculated data (Ldata') to the real-time prediction current deriving unit ( 212) and output to the data output and sensing unit 214.

The real-time prediction current deriving unit 212 receives the calculated image data (Ldata') and uses the gray-current table 211 to calculate the accumulated average current luminance (ACL) value for each section of the Nth frame. The threshold value of the section is compared, and if the accumulated average current luminance (ACL) value exceeds the threshold value, an EVDD reduction control signal is output to the EVDD control unit 215 and the sensing scheduler 216. Then, when the Nth frame accumulation is completed, the PLC gain value is derived from the accumulated average current luminance (ACL) value and output to the image processing unit 213.

The image processing unit 213, which has received the derived PLC gain value, processes the image of the next frame by using it as the PLC gain of the previous frame when processing the N+1th frame image.

When the EVDD reduction control signal is output from the real-time prediction current deriving unit 212, the EVDD control unit 215 controls the power supply unit 400 to reduce the EVDD output, and the sensing scheduler 216 reduces the data. The output and sensing unit 214 outputs a control signal to stop the operation of sensing the driving characteristics (threshold voltage or mobility of the driving transistor) and deterioration of each pixel of the display panel 100. When the sensing scheduler 216 outputs a control signal to stop the operation of sensing the driving characteristics and deterioration, the EVDD voltage is restored. However, because the EVDD voltage is restored slowly, Figure 4 shows that the EVDD voltage is restored normally in the N+2th frame.

Accordingly, the sensing operation is omitted in the vertical blank section (Vblank) of the N+1th frame.

Accordingly, in the N+1th frame, the reduced EVDD voltage is output from the power supply unit 400, and the sensing operation is omitted in the vertical blank section (Vblank) of the N+1th frame.

The same process as above is performed in the N+1th frame to determine whether the accumulated average current luminance (ACL) value exceeds the threshold. If the accumulated average current luminance (ACL) value does not exceed the threshold, the EVDD voltage is restored in the N+2th frame, and the sensing operation proceeds.

When driving the N+1th frame, the EVDD voltage was reduced to 20V and an additional 20% average current luminance (ACL) margin was secured, so in the N+1th frame, the accumulated average current luminance (ACL) value exceeds the above threshold. It is very likely that it will not be exceeded.

The driving method of the organic light emitting display device according to the present invention configured as described above will be described as follows.

Figure 5 is an operation flowchart of the setting step before product shipment of the organic light emitting display device according to the present invention. As shown in Figure 5, before product shipment, the data voltage (Vdata) is increased from 0V to the highest voltage while the luminance of red (R), green (G), blue (B), and white (W) and their corresponding Measure the current value (1S). Then, the corresponding voltage, current, and luminance values for each gray are stored in the gray-current table 211 (2S).

Then, set the luminance to the desired value (2.2 gamma, FW 100 nit, APL (Average Picture Level) 400 nit) (3S) and ship the product (4S).

In this way, the method of driving the product after shipping by storing the corresponding voltage, current, and luminance values for each gray in the gray-current table 211 is as follows.

Figure 6 is an operation flowchart of a method of driving an organic light emitting display device according to the present invention after product shipment.

As shown in FIG. 6, when video data (Gray) is input to the video processing unit 213 from the set 300 (11S), the PLC gain of the previous frame and the original video data (Ldata) are input. The calculated data (Ldata') is calculated and output to the data output and sensing unit 214.

The real-time prediction current deriving unit 212 receives the calculated image data (Ldata') from the image processing unit 213 and uses the gray-current table 211 (12S) to calculate the average current luminance for each horizontal line. (ACL) is calculated and accumulated to derive the predicted current in real time (13S).

Then, the average current luminance (ACL) value accumulated for each section is compared with the threshold value of the section, and if the accumulated average current luminance (ACL) value exceeds the threshold value (14S), the amount of reduction voltage is derived. , the EVDD control unit 215 outputs an EVDD reduction control signal to reduce EVDD (15S).

Then, the sensing scheduler 216 stops sensing the driving characteristics or deterioration of each pixel (16S). At the same time, EVDD is restored (17S).

The above process is repeated for each section, and when one frame accumulation is completed, the PLC gain value is derived from the accumulated average current luminance (ACL) value and output to the image processor 213 (18S).

In step 14S, the average current luminance (ACL) value accumulated for each section is compared with the threshold value of the section, and if the accumulated average current luminance (ACL) value does not exceed the threshold value (14S), the vertical The driving characteristics or deterioration of each pixel are sensed in the blank section (19S).

As explained above, even if the EVDD voltage is reduced to a certain range, there is no visual impact.

Figure 7 is a diagram comparing EVDD voltage and data voltage.

According to the present invention, the condition for reducing the EVDD voltage due to overcurrent corresponds to a case where the ACL of the current frame is high while the ACL of the previous frame is lowest. Therefore, in the case of HDR application (pattern with many black images), the EVDD voltage reduction condition is not met. However, in case of not applying HDR, there is room to lower EVDD considering the threshold voltage (Vth) margin.

In the saturation region, the EVDD voltage is higher than the data voltage (Vdata), so there is no difference in current flowing through the OLED even if the EVDD voltage is lowered.

That is, in the saturated state (EVDD>Vdata), the current (IOLED) of the OLED is equal to [Equation 2].

Here, Vgs is the voltage between the gate and source of the driving transistor, and Vth is the threshold voltage of the driving transistor.

Therefore, even if the EVDD voltage is partially lowered in a frame where overcurrent is predicted, there is no visual impact.

As described above, the present invention can derive predicted current in real time without using frame memory, thereby reducing cost, PCB size, and chip area.

In addition, when a current higher than the threshold is required, EVDD is lowered, so image distortion can be prevented because the image is not processed as black.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 200: panel driving unit
210: Timing control unit 211: Gray-current table
212: Real-time prediction current derivation unit 213: Image processing unit
214: data output and sensing unit 215: EVDD control unit
216: Sensing scheduler 300: Set
400: power supply unit

Claims (12)

A display panel comprised of a plurality of pixels including organic light emitting elements that emit light by current corresponding to a data voltage; and
a panel driver that analyzes image data input every horizontal period to derive a predicted current of the current frame, and reduces EVDD supplied to the organic light emitting device when the predicted current of the current frame is higher than a threshold;
The panel driver senses the driving characteristics or degradation of each pixel in the vertical blank period immediately after the EVDD when there is no reduction in the EVDD, and senses the driving characteristics or degradation of each pixel in the vertical blank period immediately after the EVDD is reduced. Omitting an organic light emitting display device. delete According to claim 1,
The panel driver,
a timing controller that analyzes image data input each horizontal period to derive a predicted current, and reduces EVDD supplied to the organic light emitting device when the derived predicted current is higher than a threshold;
a gate driver sequentially supplying gate signals to a plurality of gate lines under the control of the timing controller; and
An organic light emitting display device comprising a data driver that converts image data input from the timing controller into an analog data voltage and supplies it to a corresponding data line. According to claim 3,
The timing control unit,
A gray-current table that measures the luminance and corresponding current values of red (R), green (G), blue (B), and white (W) and stores the corresponding voltage, current, and luminance values for each gray;
An image processing unit that calculates the image data input from the set with the PLC gain of the previous frame and outputs the calculated data (Ldata');
Using the image data (Ldata') calculated from the image processor and the gray-current table, the image data input for each horizontal period is analyzed to derive a predicted current, and if the derived predicted current is higher than the threshold, the An organic light emitting display device comprising a real-time prediction current derivation unit that reduces EVDD supplied to an organic light emitting device and omits sensing of driving characteristics or deterioration of each pixel. According to claim 4,
The image processing unit,
In order to track a value proportional to luminance from the image data input from the set, the original image data (Ldata) is restored, and the original image data (Ldata) is multiplied by the PLC gain value of the previous frame, and the calculated data ( An organic light emitting display device that outputs Ldata') to the real-time prediction current deriving unit and the data output and sensing unit. According to claim 4,
The real-time prediction current deriving unit,
The calculated image data (Ldata') is received from the image processor, the average current luminance is calculated and accumulated for each horizontal line using the gray-current table, and one frame is divided into a plurality of sections and a threshold value is set for each section. set,
Compares the average current luminance value accumulated for each section with the threshold value of each section, and outputs an EVDD reduction control signal when the accumulated average current luminance value exceeds the threshold value of each section,
An organic light emitting display device that repeats the above process for each section, and when one frame accumulation is completed, a PLC gain value is derived from the accumulated average current luminance value and output to the image processing unit to be used as the PLC gain of the previous frame when processing the next frame image. . According to claim 4,
The timing control unit,
an EVDD control unit that controls the power supply unit to reduce EVDD output according to the control of the real-time prediction current deriving unit;
a data output and sensing unit that outputs data (Ldata') calculated by the image processing unit to a corresponding data driving IC and senses driving characteristics or deterioration of each pixel of the display panel during the vertical blank period;
The organic light emitting display device further includes a sensing scheduler that stops sensing the driving characteristics or deterioration of each pixel of the data output and sensing unit according to the control of the real-time prediction current deriving unit. Raising the data voltage from 0V to the highest voltage, measuring the luminance and the corresponding current value and tabulating the gray-current;
A step of calculating the PLC gain and the original image data (Ldata) of the previous frame and analyzing the image data input every horizontal period using the calculated data (Ldata') and the gray-current table to derive the predicted current of the current frame. ; and
Reducing EVDD supplied to the organic light emitting device when the predicted current of the current frame is higher than a threshold,
If the EVDD is not reduced, sensing the driving characteristics or degradation of each pixel in the immediately following vertical blank period, and if the EVDD is reduced, omitting the operation of sensing the driving characteristics or degradation of each pixel in the immediately following vertical blank period. A method of driving an organic light emitting display device further comprising: According to claim 8,
The step of deriving the predicted current is,
A method of driving an organic light emitting display device in which the average current luminance is calculated and accumulated for each horizontal period using the calculated data (Ldata') and the gray-current table by calculating the PLC gain and the original image data (Ldata) of the previous frame. delete According to claim 8,
If the derived predicted current is higher than the threshold, the step of reducing the EVDD supplied to the organic light emitting device or omitting the operation of sensing the driving characteristics or deterioration of each pixel is,
Dividing one frame into a plurality of sections and setting a threshold for each section;
Comparing the average current luminance value accumulated in each section with the threshold value of each section;
A method of driving an organic light emitting display device comprising outputting an EVDD reduction control signal and a sensing operation skip signal when the accumulated average current luminance value exceeds the threshold value of each section. According to claim 11,
The step of comparing the accumulated average current luminance value for each section and the threshold value of each section is repeated, and when 1 frame accumulation is completed, the PLC gain value is derived from the accumulated average current luminance value, and when processing the next frame image, the PLC of the previous frame is used. Method of driving an organic light emitting display device using gain.