KR102619263B1 - Power amplifier module - Google Patents

Abstract

(Project) The purpose is to provide a power amplification module that can maintain linear characteristics without being affected by the characteristics of the transistor.
(Solution) A first amplifier that amplifies the first signal and outputs a second signal, a divider that distributes the second signal into a third signal and a fourth signal, and amplifies the third signal to output a fifth signal. a second amplifier, a third amplifier that amplifies the fourth signal and outputs a sixth signal, a phase shifter to which the fifth signal is input and changes the phase of the sixth signal, A synthesis unit that synthesizes the sixth signal and the fifth signal whose phase has been changed in the phase shifter and outputs an amplified signal of the second signal, and a synthesizer output from the third amplifier based on the amplitude level of the first signal and a controller that outputs a control signal that controls the power level of the sixth signal.

Description

Power amplification module {POWER AMPLIFIER MODULE}

This disclosure relates to power amplification modules.

The Doherty amplifier is a high-efficiency power amplifier. The Doherty amplifier is generally connected in parallel with a carrier amplifier that operates regardless of the power level of the input signal and a peak amplifier that turns off when the power level of the input signal is low and turns on when the power level of the input signal is large. And, when the power level of the input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. By this, the Doherty amplifier can improve efficiency compared to a normal power amplifier.

Japanese Patent Publication No. 8-330873

As described above, in the Doherty amplifier, the peak amplifier is operated at the timing when the carrier amplifier approaches saturation. The peak amplifier operates at appropriate timing by optimizing the class C bias level. The class C bias level is adjusted in the region where the idle current of the peak amplifier is zero. However, in the Doherty amplifier, the characteristics of transistors and matching circuit elements are uneven, so detailed bias level settings are required. Additionally, in Doherty amplifiers, it is necessary to introduce a pre-distortion method that compensates for deformation characteristics.

Therefore, the purpose of the present disclosure is to provide a power amplification module that reduces characteristic unevenness so that it is less affected by the characteristics of the transistor.

The power amplification module according to one aspect of the present invention includes a first amplifier that amplifies a first signal and outputs a second signal, a divider that distributes the second signal into a third signal and a fourth signal, and the third signal. a second amplifier that amplifies and outputs a fifth signal, a third amplifier that amplifies the fourth signal and outputs a sixth signal, a phase shifter that inputs the fifth signal and changes the phase of the fifth signal; , a synthesis unit that synthesizes the sixth signal and the fifth signal whose phase has been changed in the phase shifter and outputs an amplified signal of the second signal, and from the third amplifier based on the amplitude level of the first signal and a controller that outputs a control signal that controls the power level of the output sixth signal.

The power amplification module according to one aspect of the present invention includes a first amplifier that amplifies a first signal and outputs a second signal, a divider that distributes the second signal into a third signal and a fourth signal, and the third signal. a second amplifier that amplifies and outputs a fifth signal, a third amplifier that amplifies the fourth signal and outputs a sixth signal, a phase shifter that inputs the fifth signal and changes the phase of the fifth signal; , a synthesis unit that synthesizes the sixth signal and the fifth signal whose phase has been changed in the phase shifter and outputs an amplified signal of the second signal, is installed between the distributor and the third amplifier, and the fourth A signal adjusting unit for adjusting the passing amount of a signal, and an output circuit for outputting a second control signal for controlling the signal adjusting unit based on the base current of the second amplifier to the signal adjusting unit, wherein the signal adjusting unit The passing amount of the fourth signal is adjusted based on the second control signal.

According to the present disclosure, it is possible to provide a power amplification module that can maintain linear characteristics while being less affected by the characteristics of the transistor.

1 is a diagram showing a configuration example of a power amplification circuit and a control circuit according to an embodiment of the present invention.
2 is a diagram showing a configuration example of a signal generation circuit according to an embodiment of the present invention.
Figure 3 is a graph showing the relationship between the amplitude level of the signal RFin and the signal Dmod.
Figure 4 is a graph showing the relationship between gain and an amplified signal (Pout).
Figure 5 is a diagram showing an example of the configuration of a power amplification module according to the first modification.
Figure 6 is a diagram showing an example of the configuration of a drive stage amplifier of the power amplification module according to the first modification.
FIG. 7 is a diagram showing an example of the configuration of a power amplification module according to another example of the first modification.
Figure 8 is a diagram showing an example of the configuration of a power amplification module according to the second modification example.
Figure 9 is a diagram showing an example of the configuration of a power amplification module according to a third modification.
Figure 10 is a diagram showing an example of the configuration of a power amplification module according to a fourth modification.
Figure 11 is a diagram showing an example of the configuration of a power amplification module according to a comparative example.
FIG. 12 is a diagram showing an example of the configuration of a power amplification module according to the second embodiment.
Fig. 13 is a diagram showing an example of the configuration of an output circuit according to the second embodiment.
Fig. 14 is a diagram showing an example of the configuration of a signal adjustment unit according to the second embodiment.
Figure 15 is a diagram showing an example of the configuration of a signal adjustment unit according to the first modification.
Figure 16 is a diagram showing an example of the configuration of a signal adjustment unit according to the second modification.
Fig. 17 is a diagram showing an example of the configuration of a power amplification module according to the third embodiment.
Fig. 18 is a diagram showing an example of the configuration of an output circuit according to the third embodiment.
Fig. 19 is a diagram showing an example of the configuration of an output circuit according to the first modification.
Fig. 20 is a diagram showing an example of the configuration of an output circuit according to the second modification.
Fig. 21 is a diagram showing an example of the configuration of a power amplification module according to the fourth embodiment.

Hereinafter, each embodiment of the present disclosure will be described with reference to each drawing. Here, circuit elements with the same symbol represent the same circuit elements and redundant descriptions are omitted.

===Configuration of the power amplification module 100 according to this embodiment===

1 and 2 are diagrams showing configuration examples of various circuits related to the power amplification module 100, which is an embodiment of the present invention. The power amplification module 100 is mounted on, for example, a mobile phone and is used to amplify the power of a signal transmitted to a base station. The power amplification module 100 is, for example, 2G (2nd generation mobile communication system), 3G (3rd generation mobile communication system), 4G (4th generation mobile communication system), 5G (5th generation mobile communication system) , the power of signals of communication standards such as LTE (Long Term Evolution)-FDD (Frequency Division Duplex), LTE-TDD (Time Division Duplex), LTE-Advanced, and LTE-Advanced Pro can be amplified. Additionally, the communication standards of the signal amplified by the power amplification module 100 are not limited to these.

The power amplification module 100 includes, for example, a power amplification circuit 110, a control circuit 120, and a signal generation circuit 130.

<<Power amplification circuit 110>>

For example, the power amplification circuit 110 outputs a signal amplified by an input signal to a predetermined amplitude level.

As shown in FIG. 1, the power amplification circuit 110 includes, for example, a drive stage amplifier 111, a distributor 112, a carrier amplifier 113, a peak amplifier 114, a first phase phase 115, It is provided with a second phase phase 116 and a synthesis unit 117. Each component included in the power amplification circuit 110 may be formed on the same substrate or may be formed on multiple substrates. It is preferable that the phase shifter of the present invention is a line whose wiring length is intentionally adjusted.

The drive stage amplifier 111 (first amplifier), for example, amplifies an input radio-frequency (RF) signal (hereinafter referred to as “signal (RFin)”) and produces an amplified signal (hereinafter referred to as “RFin”). (referred to as “signal (RF1)”) is output. The frequency of the signal RFin is, for example, several GHz. The drive stage amplifier 111 is not particularly limited, but for example, a bipolar transistor such as a heterojunction bipolar transistor (HBT), or a field effect transistor (MOSFET: Metal oxide-semiconductor Field Effect Transistor), etc. It is composed of transistors. Additionally, the same applies to the carrier amplifier 113 and peak amplifier 114, which will be described later.

The distributor 112, the carrier amplifier 113, the peak amplifier 114, the first phase phase 115, the second phase phase 116, and the synthesis section 117 produce a signal (RF1) output from the drive stage amplifier 111. This is the second stage amplification circuit that amplifies.

For example, the distributor 112 divides the signal RF1 output from the drive amplifier 111 into a signal input to the carrier amplifier 113 (hereinafter referred to as “signal RF11”) and a peak amplifier ( 114) (hereinafter referred to as “signal RF12”). Here, the phase of the signal RF12 is delayed by approximately 90 degrees with respect to the phase of the signal RF11 through the second phase shifter 116, which will be described later. Additionally, the divider 112 may be, for example, a distributed constant circuit such as a combined line (3 dB) coupler or a Wilkinson-type divider.

For example, the carrier amplifier 113 (second amplifier) amplifies the input signal RF11 and outputs an amplified signal (hereinafter referred to as “signal RF2”). Additionally, a load (not shown) is connected to the output side of the carrier amplifier 113. When the peak amplifier is not operating, the value becomes R, and when the peak amplifier operates, the value becomes R/2. The carrier amplifier 113 is biased to, for example, class A, class AB, or class B. That is, the carrier amplifier 113 amplifies the input signal regardless of the power level of the input signal, such as a small instantaneous input power, and outputs an amplified signal.

The peak amplifier 114 (third amplifier), for example, amplifies the signal RF12 input through the switch 122 and outputs an amplified signal (hereinafter referred to as “signal RF3”). Peak amplifier 114 is biased to, for example, class A, class AB, class B, or class C. That is, the peak amplifier 114 switches the ON/OFF state of the switch 122 based on the signal Dmod (described later) output from the signal generation circuit 130, thereby generating the input signal regardless of the power level of the input signal. Amplifies the signal and outputs the amplified signal.

The first phase shifter 115 (phase shifter) is, for example, a 1/4 wavelength line connected to the output side of the carrier amplifier 113. As a result, it is possible to change the load impedance seen from the output terminal of the carrier amplifier 113 to achieve higher efficiency of the carrier amplifier 113.

The second phase shifter 116 is connected to the input side of the peak amplifier 114, for example. The second phase phase 116 is, for example, a 1/4 wavelength line.

For example, the synthesis unit 117 synthesizes the signal RF2 output from the carrier amplifier 113 and passing through the first phase phase amplifier 115 and the signal RF3 output from the peak amplifier 114 to produce a signal ( Outputs the amplified signal (Pout) of RFin).

<<Control circuit 120>>

The control circuit 120 includes, for example, a switch 122, first to third bias circuits 123 to 125, based on a control signal (signal Dmod to be described later) input from the signal generation circuit 130. The operation state of at least one of the drive stage amplifier 111, the carrier amplifier 113, and the peak amplifier 114 is switched. In addition, in this embodiment, the switch 122 is described as being built into the control circuit 120, but it may be built into the power amplification circuit 110. Alternatively, the switch 122 may be configured independently from various circuits.

As shown in FIG. 1, the control circuit 120 includes, for example, a control unit 121, a switch 122, a first bias circuit 123, a second bias circuit 124, and a third bias circuit 125. ) is provided.

For example, the control unit 121 operates the switch 122, the first bias circuit 123, and the second bias circuit based on a control signal (signal Dmod, described later) input from the signal generation circuit 130, which will be described later. (124), a control signal (hereinafter referred to as “signal (Dcont)”) for controlling at least one of the third bias circuit 125, drive stage amplifier 111, carrier amplifier 113, and peak amplifier 114. ) is output. In this embodiment, the control unit 121 controls the switch 122.

The switch 122 switches whether or not the signal RF3 is output from the peak amplifier 114, for example. The switch 122 turns on when the signal Dcont is input from the control unit 121. The switch 122 is connected in series to the base of the peak amplifier 114, for example. In this case, the switch 122 blocks the signal RF12 from being input to the peak amplifier 114 in the on state, for example, and blocks the signal RF12 from being input to the peak amplifier 114 in the off state. . Additionally, the switch 122 may be connected in series to the collector of the peak amplifier 114 so that the signal RF3 is not output from the peak amplifier 114 in the off state, for example.

The first bias circuit 123 is a circuit that supplies a bias current or voltage to the peak amplifier 114, for example.

The second bias circuit 124 is, for example, a circuit that supplies a bias current or voltage to the drive stage amplifier 111.

The third bias circuit 125 is a circuit that supplies a bias current or voltage to the carrier amplifier 113, for example.

<<Signal generation circuit 130>>

For example, the signal generation circuit 130 generates a signal (RFin) from an IQ signal and also generates a control signal (hereinafter referred to as “signal (Dmod)”) to be output to the control circuit 120. It is a circuit. Here, the IQ signal is a modulation signal obtained by modulating an input signal such as voice or data based on a modulation method such as HSUPA (High-Speed Uplink Packet Access) or LTE (Long Term Evolution). The IQ signal is, for example, a signal with a frequency of several MHz to several 100 MHz.

As shown in FIG. 2, the signal generation circuit 130 includes, for example, delay circuits 131 and 132, RF modulation unit 133, amplitude level detection unit 134, adjustment unit 135, quantizer 136, A comparison unit 137 is provided.

The delay circuits 131 and 132, for example, supply the timing at which the signal RFin is input to the power amplification circuit 110 and the power supply voltage Vcc according to the amplitude level of the signal RFin to the power amplification circuit 110. This is a circuit that delays the IQ signal for a certain period of time in order to match the timing.

The RF modulator 133 generates and outputs a signal (RFin) from, for example, an IQ signal. Specifically, the RF modulator 133 combines, for example, an I signal and a carrier signal with a multiplier, and synthesizes a Q signal and a carrier signal whose phase is 90 degrees out of phase with the Q signal with a multiplier. Then, the RF modulator 133 generates a signal (RFin) by combining each synthesized signal with a subtractor.

The amplitude level detection unit 134 detects, for example, the amplitude level of the IQ signal. That is, the amplitude level detection unit 134 detects the amplitude level of the IQ signal corresponding to the amplitude level of the signal RFin output from the RF modulator 133.

The adjustment unit 135 has a table that stores the correspondence between the amplitude level of the IQ signal and the level of the power supply voltage (Vcc) based on the gain characteristics of the transistor, for example. Then, the adjustment unit 135 outputs a signal (hereinafter referred to as a “dynamic control signal”) for adjusting the voltage level of the power supply voltage Vcc according to the amplitude level of the IQ signal based on the table above.

For example, the quantizer 136 converts a high-precision digital dynamic control signal output from the adjustment unit 135 into a low-precision digital signal (fewer bits) and discretely adjusts the power supply voltage (Vcc). A signal (hereinafter referred to as “signal Dctrl”) is output to a power supply circuit (not shown). As a result, the power amplification circuit 110 becomes capable of envelope tracking using digital signals.

The power circuit (not shown) generates a power supply voltage (Vcc) at a level according to the signal (Dctrl) and supplies it to the power amplification circuit (110). The power supply circuit (not shown) may include, for example, a DC-DC converter that generates a power supply voltage (Vcc) at a level corresponding to the signal (Dctrl) from an input voltage (eg, battery voltage, etc.).

The comparison unit 137 is a comparison circuit that outputs a signal Dmod to the control circuit 120 when, for example, the dynamic control signal output from the adjustment unit 135 is greater than or equal to a predetermined threshold.

In this way, in the power amplification module 100, by controlling the control circuit 120 based on the signal Dmod, the peak amplifier 114 can be operated at an appropriate timing without being affected by the characteristics of the transistor, etc., thereby preventing manufacturing unevenness. High efficiency is sought by realizing the suppression of .

In addition, as described above, the power amplification module 100 is not limited to performing envelope tracking using a digital signal. For example, average power tracking (APT) may be performed, and the method is not limited.

<<Power amplification module 200 according to comparative example>>

Hereinafter, with reference to FIG. 11, the power amplification module 200 according to a comparative example will be described. FIG. 11 is a diagram showing an example of the configuration of the power amplification module 200 according to a comparative example. The power amplification module 200 according to the comparative example is shown to facilitate understanding of the power amplification module 100 according to the present embodiment.

As shown in FIG. 11, the power amplification module 200 according to the comparative example includes, for example, a switch 122 and a control unit 121 for controlling the switch 122 compared to the power amplification module 100. do not have Additionally, the power amplification module 200 includes, for example, a signal generation circuit (not shown) and a strain compensation unit (not shown).

In the power amplification module 200 according to the comparative example, the carrier amplifier 213 is biased to class A, class AB, or class B, and the peak amplifier 214 is biased to class C. That is, the power amplification module 200 operates only the carrier amplifier 213 until a signal (RFin) of a predetermined amplitude level is input, and when a signal (RFin) exceeding a predetermined amplitude level is input, the peak amplifier ( 214) works.

Here, in the power amplification module 200, the operation timing varies depending on the characteristics of various elements forming the power amplification module 200.

Therefore, for example, the strain compensation unit (not shown) denies the non-linear input/output characteristics of the power amplification module 200 in advance to the IQ signal input to the signal generation circuit 130, as shown in FIG. 2. Add the reverse transformation. As a result, a transmission signal with no distortion can be obtained at the output of the power amplification module 200.

Meanwhile, in the power amplification module 100 according to the present embodiment, as described above, the peak amplifier 114 is biased to class A, class AB, or class B, and the peak amplifier 114 is biased based on the amplitude level of the IQ signal. It is provided with a switch 122 that controls. As a result, the power amplification module 100 operates the peak amplifier 114 at an appropriate timing according to the IQ signal without being influenced by the characteristics of the various elements constituting it, and thus the analog characteristics due to manufacturing unevenness of the power amplification module. It is difficult to be affected by unevenness, and highly efficient signal amplification can be realized.

===Operation of power amplification module 100===

Hereinafter, with reference to FIGS. 1 to 4, operations based on the signal Dmod in the power amplification module 100 will be described. Figure 3 is a graph showing the relationship between the amplitude level of the signal RFin and the signal Dmod. Figure 4 is a graph showing the relationship between gain and an amplified signal (Pout).

In Fig. 3(a), the horizontal axis represents the elapsed time (t), and the vertical axis represents the amplitude level (Vout) of the signal (RFin). In Figure 3(a), symbol 1000 represents the amplitude level (Vout) of the signal (RFin), and symbol 1001 represents the threshold.

In Figure 3(b), the horizontal axis represents the elapsed time (t), and the vertical axis represents the binary value of the signal (Dmod). In Fig. 3(b), the binary value of the signal Dmod represents “1”, for example, when the amplitude level of the signal RFin in Fig. 3(a) exceeds the threshold.

In Figure 4, the horizontal axis represents the amplified signal (Pout), and the vertical axis represents the gain. The symbol 1100 represents the gain characteristics of the power amplification module 100 according to this embodiment. The symbol 1101 represents the gain when only the carrier amplifier 113 operates. The symbol 1102 represents the gain when the peak amplifier 114 and the carrier amplifier 113 operate simultaneously. Reference numeral 1103 represents the operation of the power amplification module 200 according to the comparative example, and represents the process of transitioning from the independent operation of the carrier amplifier to the parallel operation of the carrier amplifier and the peak amplifier.

As shown in FIG. 2, the IQ signal is input to the signal generation circuit 130. The IQ signal is input to the comparison unit 137 as a dynamic control signal through the delay circuit 132, the amplitude level detection unit 134, and the adjustment unit 135.

When a dynamic control signal corresponding to the signal RFin shown in FIG. 2 is input, the comparison unit 137 outputs a signal Dmod when an amplitude level higher than the “threshold” shown in FIG. 3(a) is detected. That is, as shown in FIG. 3(b), the signal generation circuit 130 outputs a signal Dmod when an IQ signal with a predetermined amplitude level is input.

As shown in FIG. 1, the signal Dmod output from the comparison unit 137 is input to the control unit 121 of the control circuit 120. The control unit 121 outputs a signal (Dcont) to turn on the switch 122 based on the signal (Dmod).

And, when the switch 122 is turned on by the signal Dcont, the signal RF12 output from the distributor 112 is biased to class A, class AB, class B, or class C through the second phase shifter 116. It is input to the peak amplifier 114. The peak amplifier 114 amplifies the signal RF12 and outputs the signal RF3. As a result, the load impedance seen from the output terminal of the carrier amplifier 113 decreases, thereby increasing the saturated output power and improving the efficiency of the power amplification circuit 110.

In addition, the power amplifier circuit 110 can realize stable on-off switching control for the peak amplifier 114, and thus can output the signal RF3 at appropriate timing without being affected by the characteristics of various elements. This makes it difficult to be affected by unevenness in analog characteristics due to uneven manufacturing of the power amplification module.

The synthesis unit 117 synthesizes the signal RF3 and the signal RF2 output from the carrier amplifier 113 and outputs an amplified signal Pout of the signal RFin.

As a result, as shown in FIG. 4, in the power amplification module 100 of the present embodiment, the peak amplifier 114 is switched by the switch 122, so that linear characteristics are achieved as indicated by symbol 1100. Can be maintained (nonlinear characteristics can be suppressed). On the other hand, in the power amplification module 200 of the comparative example, since the peak amplifier 114 biased at class C is operated, nonlinearity is shown as indicated by symbol 1103.

===Power amplification module according to modification===

Referring to FIGS. 5 to 10, a power amplification module according to a modified example will be described. In this modification, description of matters common to the above-described embodiment will be omitted, and only differences will be described. In particular, the same action effects by the same composition are not mentioned sequentially.

<<First modified example>>

Referring to FIG. 5, the configuration of the power amplification module 100a according to the first modified example will be described. FIG. 5 is a diagram showing an example of the configuration of the power amplification module 100a according to the first modification example. As shown in FIG. 5, the power amplification module 100a controls the drive stage amplifier 111a by the control unit 121a of the control circuit 120a compared to the power amplification module 100.

The power amplification module 100a inputs a signal Dmod to the control unit 121a, and the control unit 121a turns on the switch 122. As a result, the power amplification module 100a operates the peak amplifier 114 in parallel with the carrier amplifier 113.

At this time, the power amplification module is operated in a state in which the power amplification circuit 110a is operating only with the carrier amplifier 113 and in a state in which the power amplification circuit 110a is operating with the carrier amplifier 113 and the peak amplifier 114. The gain of (100a) is different. That is, non-linear characteristics of the power amplification module 100a occur according to the on and off switching of the switch 122.

Therefore, in the power amplification module 100a, the control unit 121a controls the gain of the drive stage amplifier 111a at the timing when the switch 122 is turned on to suppress non-linear characteristics.

Specifically, the operation of the power amplification module 100a according to the first modified example will be described with reference to FIGS. 5 and 6. FIG. 6 is a diagram showing an example of the configuration of the drive stage amplifier 111a of the power amplification module 100a according to the first modification example.

As shown in FIG. 5, the control unit 121a turns on the switch 122 when the signal Dmod is input. When the switch 122 is turned on, the peak amplifier 114 operates in parallel with the carrier amplifier 113. As a result, in the power amplification module 100a, the load impedance seen from the output terminal of the carrier amplifier 113 decreases, and thus the gain decreases. As a result, the nonlinear characteristics of the power amplification module 100a increase.

Therefore, in order to suppress non-linear characteristics, the control unit 121a compensates the gain of the drive stage amplifier 111a when the signal Dmod is input. Hereinafter, the principle of compensating the gain of the drive stage amplifier 111a will be described.

FIG. 6 is a diagram showing an example of the configuration of the drive stage amplifier 111a of the power amplification module 100a according to the first modification example.

As shown in FIG. 6, the drive stage amplifier 111a has, for example, a transistor Q1a and a transistor Q1b connected in parallel, and signals are amplified in the second stage. The emitter of the transistor Q2b is connected to the base of the transistor Q2a through a resistor R2. A switching switch (SW) is connected in series to the base of the transistor (Q2b). The switching switch (SW) turns on when the signal (Dmod) is input. As a result, the bias control current Ibias, which controls the bias current supplied from the transistor Q2b to the base of the transistor Q2a, is supplied to the base of the transistor Q2b. That is, in the power amplification module 100a, the switch 122 is turned on by the signal Dmod and simultaneously operates the transistor Q2a to increase the total bias current of the drive stage, thereby increasing the gain of the drive stage amplifier 111a. increases.

In other words, the power amplification module 100a turns on the switch 122 and turns on the transistor Q2a based on the signal Dmod to compensate for the decrease in gain due to the decrease in load impedance seen from the output terminal of the carrier amplifier 113. ) is operated to increase the gain of the drive stage amplifier (111a).

Additionally, FIG. 7 is a diagram showing an example of the configuration of the power amplification module 100b according to another example of the first modified example. As shown in FIG. 7, the power amplification module 100b may have the control unit 121b control the gain of the carrier amplifier 113b at the timing when the switch 122 is turned on.

As a result, in the power amplification module 100a, the suppression caused by the decrease in the load impedance of the carrier amplifier 113b is negated by increasing the mutual conductance by increasing the current of the transistor constituting the carrier amplifier 113b, and the gain of Since degradation can be suppressed, nonlinear characteristics can be suppressed.

<<Second Modification>>

Referring to FIG. 8, the configuration of the power amplification module 100c according to the second modification example will be described. FIG. 8 is a diagram showing an example of the configuration of the power amplification module 100c according to the second modification example. As shown in FIG. 8, compared to the power amplification module 100, the power amplification module 100c operates the first bias circuit 123c of the peak amplifier 114 by the control unit 121c of the control circuit 120c. Control.

When the peak amplifier 114 is biased to class A, class AB, or class B by the first bias circuit 123c, current continues to flow to the peak amplifier 114 even if the switch 122 is turned off. Therefore, when the peak amplifier 114 is biased to class A, class AB, or class B, it is desirable to block the bias current from the first bias circuit 123c from the viewpoint of reducing power consumption.

Therefore, the power amplification module 100c according to the second modification reduces power consumption by turning the first bias circuit 123c on and off in accordance with the on/off of the switch 122 in the control unit 121c.

Specifically, with reference to FIG. 8, the operation of the power amplification module 100c according to the second modification example will be described.

As shown in FIG. 8, when the signal Dmod is input, the control unit 121c turns on the switch 122 and turns on the first bias circuit 123c. That is, the control unit 121c turns on the switch 122 to input the signal RF12 to the peak amplifier 114, and turns on the first bias circuit 123c to supply class A or AB to the peak amplifier 114. Apply a class or B bias.

Then, when the input of the signal Dmod disappears, the control unit 121c turns off the switch 122 and turns off the first bias circuit 123c. That is, the control unit 121c turns off the switch 122 to block the signal RF12 from being input to the peak amplifier 114, and also turns off the first bias circuit 123c to bias the peak amplifier 114. Block it from being applied.

As a result, the power amplification module 100c can reduce power consumption when the peak amplifier 114 is not operating.

<<Third modification>>

9, the configuration of the power amplification module 100 according to the third modification will be described. As shown in FIG. 9, the power amplification module 100d has a switch ( 122), the first bias circuit 123d of the peak amplifier 114 is controlled by the control unit 121d of the control circuit 120d.

When the power amplification module 100d turns the peak amplifier 114 on and off using the switch 122, the load impedance seen from the output terminal of the drive amplifier 111 changes each time. That is, in the power amplification module 100d, the change in gain increases as the switch 122 is turned on and off.

Therefore, the power amplification module 100d according to the third modification does not include the switch 122, and the control unit 121d switches the operation of the peak amplifier 114 by turning on and off the first bias circuit 123d. do. Here, the peak amplifier 114 has a deep class C bias when the first bias circuit 123d is off, and a shallow class C bias, class A, class AB, or class B when the first bias circuit 123d is on. This happens.

Specifically, with reference to FIG. 9 , the operation of the power amplification module 100d according to the third modification example will be described.

As shown in FIG. 9, when the signal Dmod is input, the control unit 121d turns on the first bias circuit 123d. That is, in the power amplification module 100d, the first bias circuit 123d is turned on to apply a bias to the peak amplifier 114. And, when the input signal Dmod disappears, the control unit 121d turns off the first bias circuit 123d. That is, in the power amplification module 100d, the first bias circuit 123d is turned off to prevent bias from being applied to the peak amplifier 114. As a result, in the power amplification module 100d, power consumption when the peak amplifier 114 is not operating can be reduced, and nonlinear characteristics due to the on/off of the switch 122 can be suppressed. .

<<Fourth Modification>>

Referring to FIG. 10, the configuration of the power amplification module 100e according to the fourth modification will be described. As shown in FIG. 10, compared to the power amplification module 100, the power amplification module 100e operates by controlling the second bias circuit 124e of the drive stage amplifier 111 by the control unit 121e of the control circuit 120e. control.

When the signal Dmod is input to the power amplification module 100e, the control unit 121e turns on the switch 122. As a result, the power amplification module 100e operates the peak amplifier 114 in parallel with the carrier amplifier 113.

At this time, power amplification occurs in a state in which the power amplification circuit 110e is operating only with the carrier amplifier 113 and a state in which the power amplification circuit 110e is operating with the carrier amplifier 113 and the peak amplifier 114. The gain of the module 100e is different. That is, the nonlinear characteristics of the power amplification module 100e increase as the switch 122 switches on and off.

Therefore, the power amplification module 100e adjusts the size of the bias current or voltage of the second bias circuit 124e so that the control unit 121e controls the gain of the drive stage amplifier 111 at the timing when the switch 122 is turned on. This suppresses nonlinear characteristics.

Specifically, with reference to FIG. 10 , the operation of the power amplification module 100e according to the fourth modification example will be described.

As shown in FIG. 10, the control unit 121e turns on the switch 122 when the signal Dmod is input. When the switch 122 is turned on, the peak amplifier 114 operates in parallel with the carrier amplifier 113. As a result, the load impedance of the carrier amplifier 113 in the power amplification module 100e decreases, and thus the gain decreases. As a result, the nonlinear characteristics of the power amplification module 100e increase.

Therefore, in order to suppress non-linear characteristics, the control unit 121e adjusts the magnitude of the bias current or voltage of the second bias circuit 124e to compensate for the gain of the drive stage amplifier 111 when the signal Dmod is input. .

As a result, the control unit 121e can compensate for the gain of the drive stage amplifier 111 and suppress nonlinear characteristics.

===Power amplification module 300 according to the second embodiment===

Referring to FIGS. 12 to 14, the power amplification module 300 according to the second embodiment will be described. FIG. 12 is a diagram showing an example of the configuration of the power amplification module 300 according to the second embodiment. FIG. 13 is a diagram showing an example of the configuration of the output circuit 324. FIG. 14 is a diagram showing an example of the configuration of the signal adjustment unit 318. In addition, in this embodiment, description of matters common to the above-described embodiment will be omitted, and only differences will be described. In particular, the same action effects by the same composition are not mentioned sequentially.

The power amplification module 300 according to the second embodiment detects saturation of the carrier amplifier 313 based on the base current of the carrier amplifier 313, for example. The power amplification module 300 operates the peak amplifier 314 upon detecting saturation of the carrier amplifier 313. As a result, the power amplification module 300 can prevent destruction of the power amplification circuit 310 due to an operation delay of the peak amplifier 314. As shown in FIG. 12, the power amplification module 300 includes an output circuit 324 and a signal adjustment unit 318. For example, compared to the power amplification module 100, the power amplification module 300 includes an output circuit 324 and a signal adjustment unit ( The peak amplifier 314 is controlled by 318). Specifically, in the power amplification module 300, for example, based on the base current of the carrier amplifier 313, the output circuit 324 generates a control signal (hereinafter referred to as “signal Dcont2”) indicating that the carrier amplifier 313 is saturated. )” is output to the signal adjustment unit 318. The signal adjustment unit 318 operates the peak amplifier 314 by passing the signal RF12 based on the signal Dcont2. In this way, the power amplification module 300 can operate the peak amplifier 314 at an appropriate timing according to the saturation of the carrier amplifier 313, thereby preventing destruction of the power amplification circuit 310.

Here, the output circuit 324 will be described with reference to FIG. 13. For example, the output circuit 324 supplies a bias current to the carrier amplifier 313 and detects the base current of the carrier amplifier 313. The output circuit 324 may or may not be included in the control circuit 320. The output circuit 324 outputs a signal Dcont2 for controlling the signal adjustment unit 318 based on the base current of the carrier amplifier 313. As shown in FIG. 13, the output circuit 324 includes, for example, an input terminal 324a, an output terminal 323b, a transistor Q11, a transistor Q12, a resistor R11, and Includes resistor (R12). The input terminal 324a is a terminal to which a control signal for controlling the bias current is supplied. The output terminal 323b is a terminal for outputting the signal Dcont2. The transistor Q11 is a transistor that supplies bias current to the carrier amplifier 313. For example, the collector of the transistor Q11 is connected to the power supply Vcc1, and the emitter is connected to the base of the carrier amplifier 313 through a resistor. A control signal for controlling the bias current is supplied to the base of the transistor Q11 through, for example, a resistor R11. The collector of the transistor Q12 is connected to the base of the transistor Q11, the base is connected to the emitter of the transistor Q11 through a resistor R12, and the emitter is connected to ground. The output terminal 323b is connected to the node between the base of the transistor Q12 and the resistor R12.

Next, the signal adjustment unit 318 will be described with reference to FIG. 14. The signal adjustment unit 318 is connected in series to the base of the peak amplifier 314. The signal adjustment unit 318 controls whether or not to pass the signal RF12 based on the signal Dcont2, for example. The signal adjusting unit 318 is, for example, a variable attenuator that changes the passing characteristics of the signal RF12 based on the signal Dcont2. By this, the signal adjustment unit 318 can easily control the operating point of the peak amplifier 314. As shown in FIG. 14, the signal adjustment unit 318 includes, for example, an input terminal 318a, an output terminal 318b, a control terminal 318c, a transistor Q21, a resistor R21, and , a resistor (R22), a capacitor (C21), and an inductor (L21). The input terminal 318a is a terminal to which the signal RF12 is supplied. The output terminal 318b outputs a signal RF12 from the emitter of the transistor Q21 according to the signal Dcont2. The control terminal 317d is a terminal to which the signal Dcont2 is supplied. The transistor Q21 has its collector connected to the input terminal 318a through a capacitor C21, its emitter connected to the output terminal 318b, and its base connected to the control terminal 317d through a resistor R21. . Additionally, the collector of the transistor (Q21) is connected to the power supply (Vcc2) through a resistor (R42). The capacitor C21 is a capacitor for blocking the direct current component of the signal RF12. One end of the inductor L21 is connected to the emitter of the transistor Q21, and the other end is connected to ground. The inductor (L2) is an inductor for sending the direct current component of the signal (RF12) to the ground. In addition, here, the output 324b of the output circuit 324 shown in FIG. 13 is directly connected to the control terminal 318c shown in FIG. 14, but a level shift circuit may be inserted as appropriate. Additionally, the transistor Q21 shown in FIG. 14 is described as a bipolar transistor, but may be an FET.

Additionally, the signal adjustment unit 318 is not limited to the variable attenuator described above. The signal adjustment unit 318 may be, for example, a switch that switches whether or not to input the signal RF12 to the peak amplifier 314. The switch is connected in series to the base of the peak amplifier 314, for example. The switch turns on when the signal Dcont2 is input from the output circuit 324. That is, for example, the switch is switched so that the signal RF12 is input to the peak amplifier 314 in the on state, and the signal RF12 is not input to the peak amplifier 314 in the off state. As a result, the signal adjustment unit 318 can control the operating point of the peak amplifier 314 with a simple configuration.

In addition, although the power amplification circuit 310 is shown in FIG. 12 as consisting of only one carrier amplifier and one peak amplifier, it is not limited to this. For example, the power amplification circuit 310 may be configured to include a plurality of carrier amplifiers connected in series and a plurality of peak amplifiers connected in series. In this case, the output circuit 324 is preferably formed to detect, for example, the base current of the carrier amplifier on the most output side. Additionally, the signal adjustment unit 318 may be connected in series to, for example, the base of any one peak amplifier among a plurality of peak amplifiers.

Here, with reference to FIG. 15, a first modified example of the signal adjustment unit 318 will be described. FIG. 15 is a diagram showing an example of the configuration of the signal adjustment unit 1318 according to the first modification. Description of matters common to the signal adjustment unit 318 according to the above-described embodiment will be omitted, and only differences will be described. As shown in FIG. 15, the signal adjustment unit 1318 includes, for example, a transistor Q22, a resistor R23, and , This is a circuit that adds a resistor (R24) and a capacitor (C22). Transistor Q22 has its collector connected to the output terminal 1318b through a capacitor C22, its emitter connected to ground through an inductor L41, and its base connected to the control terminal 318c through a resistor R43. Connected. Additionally, the emitter of transistor Q22 is connected to the emitter of transistor Q21. And, the collector of the transistor Q22 is connected to the power supply Vcc3 through the resistor R24. In addition, here, the output 324b of the output circuit 324 shown in FIG. 13 is directly connected to the control terminal 1318c shown in FIG. 15, but a level shift circuit may be inserted as appropriate. Additionally, the transistors Q21 and Q22 shown in FIG. 15 are described as bipolar transistors, but may be FETs.

Also, referring to FIG. 16, a second modification of the signal adjustment unit 318 will be described. FIG. 16 is a diagram showing an example of the configuration of the signal adjustment unit 2318 according to the second modification example. As shown in FIG. 16, the signal adjustment unit 2318 includes, for example, an input terminal 2318a, an output terminal 2318b, a control terminal 2318c, a diode D31, and a diode D32. , inductor (L31), inductor (L32), capacitor (C31), capacitor (C32), inductors (L33, L34) constituting a 90 degree hybrid circuit, and capacitors (C33, C34, C35, C36, C37). The input terminal 2318a is a terminal to which the signal RF12 is supplied. The output terminal 2318b is a terminal through which the signal RF12 according to the signal Dcont2 is output. The control terminal 2318c is connected to the anode of the diode D31 through the inductor L31 and to the anode of the diode D32 through the inductor L32. The cathodes of diode D31 and diode D32 are connected to ground. The capacitor C31 is a capacitor for blocking direct current components, and one end is connected to the anode of the diode D31, and the other end is connected to a 90-degree hybrid circuit. The capacitor C32 is a capacitor for blocking direct current components, and one end is connected to the anode of the diode D32, and the other end is connected to a 90-degree hybrid circuit. In addition, here, the output 324b of the output circuit 324 shown in FIG. 13 is directly connected to the control terminal 2318c shown in FIG. 16, but a level shift circuit may be inserted as appropriate. Also, instead of the diodes D31 and D32 shown in FIG. 16, a FET with a drain and a gate connected may be used.

===Operation of the power amplification module 300 according to the second embodiment===

Hereinafter, the operation of the power amplification module 300 will be described with reference to FIGS. 12 to 14. First, in the power amplification module 300, when the carrier amplifier 313 is saturated, the base-collector diode turns on. As a result, the base current of the carrier amplifier 313 increases, and the current flowing from the emitter of the transistor Q11 of the output circuit 324 shown in FIG. 13 to the carrier amplifier 313 increases. At this time, as the current supplied from the emitter of the transistor Q11 increases, the potential of the emitter of the transistor Q11 decreases. Then, the current supplied from the emitter of the transistor Q11 is supplied to the base of the transistor Q12 through the resistor R12. However, since the signal RF11 is not input to the transistor Q12, the entire current supplied from the transistor Q11 is not supplied to the base of the transistor Q12. For this reason, part of the current supplied from the emitter of the transistor Q11 is supplied to the output terminal 323b. The output circuit 324 outputs the current supplied to the output terminal 323b as a signal Dcont2. Accordingly, the output circuit 324 can output the signal Dcont2 based on the base current of the carrier amplifier 313.

Next, the signal adjustment unit 318 shown in FIG. 14 supplies the control signal Dcont2 to the base of the transistor Q21 through the resistor R21. When the control signal Dcont2 exceeds a predetermined current value, the transistor Q21 passes the signal RF12 to the output terminal 318b. Then, the peak amplifier 314 amplifies the signal RF12 and outputs the signal RF3. As a result, the peak amplifier 314 can be operated without an operation delay when the carrier amplifier 313 is saturated, thereby preventing damage to the power amplification circuit 310.

===Power amplification module 400 according to the third embodiment===

17 and 18, the power amplification module 400 according to the third embodiment will be described. FIG. 17 is a diagram showing an example of the configuration of the power amplification module 400 according to the third embodiment. FIG. 18 is a diagram showing an example of the configuration of the output circuit 424. Additionally, since the signal adjustment unit 418 is the same as the signal adjustment unit 318 in the second embodiment, its description is omitted. That is, in this embodiment, description of matters common to the above embodiment will be omitted, and only differences will be described. In particular, the same action effects by the same composition are not mentioned sequentially.

The power amplification module 400 according to the third embodiment detects saturation of the carrier amplifier 413 based on the collector voltage amplitude that changes depending on the base current of the carrier amplifier 413, for example. The power amplification module 400 operates the peak amplifier 414 based on detection of saturation of the carrier amplifier 413. By this, the power amplification module 400 can prevent destruction of the power amplification circuit 410 due to an operation delay of the peak amplifier 414. As shown in FIG. 17, the power amplification module 400 includes an output circuit 424 and a signal adjustment unit 418. That is, for example, compared to the power amplification module 100, the power amplification module 400 uses the output circuit 424 and the signal instead of controlling the peak amplifier 114 by the control unit 121 and the switch 122. The peak amplifier 414 is controlled by the adjustment unit 418. Specifically, the power amplification module 400 sends a signal (Dcon2) indicating that the carrier amplifier 413 is saturated from the output circuit 424 based on the voltage amplitude of the collector of the carrier amplifier 413 to the signal adjustment unit. Printed at (418). The signal adjustment unit 418 operates the peak amplifier 414 based on the signal Dcont2. As a result, the power amplification module 400 can operate the peak amplifier 414 at an appropriate timing as the carrier amplifier 413 saturates, thereby preventing damage to the power amplification circuit 410.

Here, an example of the configuration of the output circuit 424 will be described with reference to FIG. 18. The output circuit 424 detects the voltage amplitude of the collector of the carrier amplifier 313. The output circuit 424 outputs a signal (Dcont2) for controlling the signal adjustment unit 418 based on the voltage amplitude of the collector. As shown in FIG. 18, the output circuit 424 includes, for example, an input terminal 424a, an output terminal 424b, a transistor Q41, a transistor Q42, a resistor R41, It includes a resistor (R42), a resistor (R43), a resistor (R44), and a capacitor (C41). The input terminal 424a is a terminal into which the voltage of the collector of the carrier amplifier 413 is input. The output terminal 424b is a terminal for outputting the signal Dcont2. The collector of the transistor Q41 is connected to the power source Vbat through a resistor R43, the base is connected to a node between the resistors R41 and R42, and the emitter is connected to ground. Additionally, the base of the transistor Q41 is connected to the base of the transistor Q42 through a resistor R41, and the collector of the transistor Q41 is connected to the base of the transistor Q42. That is, a constant voltage circuit is formed by the transistor Q41, resistor R41, and resistor R42. Therefore, the base potential of the transistor Q42 is made constant by the constant voltage circuit. The base of the transistor Q42 is connected to a constant voltage circuit, the collector is connected to the power source Vbat through a resistor R44, and the emitter is connected to the input terminal 424a. Additionally, the collector of transistor Q42 is connected to the output terminal 424b. The capacitor C41 is a capacitor for smoothing the signal Dcont2. One end of the capacitor C41 is connected to the node between the collector of the transistor Q42 and the output terminal 424b, and the other end is connected to ground.

Next, referring to FIG. 19, a first modification of the output circuit 424 will be described. FIG. 19 is a diagram showing an example of the configuration of the output circuit 1424 according to the first modification. As shown in FIG. 19, the output circuit 1424 includes, for example, an input terminal 1424a, an output terminal 1424b, a transistor Q51, a transistor Q52, and a transistor Q53. It includes a diode (D51), a diode (D52), a resistor (R51), a resistor (R52), a resistor (R53), a capacitor (C51), and a current source (Is1). The input terminal 1424a is a terminal into which the collector voltage of the carrier amplifier 413 is input. The output terminal 1424b is a terminal for outputting the signal Dcont2. The transistor Q51 has its collector connected to the input terminal 1424a, its emitter connected to the anode of the diode D51, and its base connected to a predetermined reference potential B1. The cathode of diode D51 is connected to output terminal 1424b through resistor R51. The collector of the transistor Q52 is connected to the power source Vcc4 through the current source Is1, the emitter is connected to the anode of the diode D52, and the base is connected to a predetermined reference potential B1. Transistor Q53 has its collector connected to the cathode of diode D52 through resistor R52, its emitter connected to ground, and its base connected to power source Vcc4 through resistor R53. The capacitor C51 has one end connected to a predetermined reference potential B1 and the other end connected to ground.

Also, referring to Fig. 20, a second modification of the output circuit 424 will be described. FIG. 20 is a diagram showing an example of the configuration of the output circuit 2424 according to the second modification. Descriptions of common points with the output circuit 1424 according to the first modification described above will be omitted, and only differences will be described. As shown in FIG. 20, the output circuit 2424 according to the first modification includes an input terminal 2424c, a transistor Q54, a diode D53, and a resistor R54. This is a circuit with added . The input terminal 2424a is, for example, a terminal into which the voltage of the collector of the peak amplifier 414 is input. The transistor Q54 has its collector connected to the input terminal 2424c, its emitter connected to the anode of the diode D53, and its base connected to a predetermined reference potential B1. The cathode of diode D53 is connected to output terminal 2424b through resistor R34.

===Operation of the power amplification module 400 according to the third embodiment===

Hereinafter, the operation of the power amplification module 400 will be described with reference to FIGS. 17 and 18. First, in the power amplification module 400, when the carrier amplifier 413 is saturated, the amplitude of the collector voltage of the carrier amplifier 413 increases. The amplitude of the emitter voltage of the transistor Q42 of the output circuit 424 shown in FIG. 18 increases according to the amplitude of the collector voltage of the carrier amplifier 413. Depending on the amplitude of the emitter voltage of the transistor (Q42), the potential of the emitter becomes lower than that of the base. At this time, current flows through the emitter of the transistor (Q42). As a result, current flows through the collector of the transistor Q42. That is, when the potential of the emitter of the transistor Q42 decreases, a current flows through the collector of the transistor Q42. Current in the collector of transistor (Q42) flows from the power supply (Vbat) through resistor (R44). As a result, the voltage equal to the product of the collector current of the transistor Q42 and the resistor R44 drops, thereby lowering the potential of the node between the resistor R44 and the output terminal 424b. That is, the potential of the output terminal 424b decreases. The output circuit 424 outputs the voltage drop of the output terminal 424b as a signal Dcont2.

In addition, since the signal adjustment section 418 is the same as the signal adjustment section 318 of the second embodiment, for example, by forming an inverting amplification circuit (not shown) or a digital circuit on the output side of the output circuit 324, the signal (Dcont2) ) is desirable to invert. The signal adjusting unit 418 passes the signal RF12 according to the signal Dcont2. As a result, the peak amplifier 414 can be operated without an operation delay when the carrier amplifier 413 is saturated, thereby preventing damage to the power amplification circuit 410.

===Power amplification module 500 according to the fourth embodiment===

Referring to FIG. 21, the power amplification module 500 according to the fourth embodiment will be described. FIG. 21 is a diagram showing an example of the configuration of the power amplification module 500 according to the fourth embodiment. In addition, in this embodiment, description of matters common to the above embodiment will be omitted, and only differences will be described. In particular, the same action effects by the same composition are not mentioned sequentially.

The power amplification module 500 according to the fourth embodiment detects saturation of the carrier amplifier 513 based on the base current of the carrier amplifier 513, for example. The power amplification module 500 outputs a signal (Dcont2) indicating that the carrier amplifier 513 is saturated to the control unit 524. The control unit 524 outputs a control signal (hereinafter referred to as signal Dcont3) for operating the signal adjustment unit 518 based on the signal Dcont2. The control unit 524 may output the signal Dcont3 based on the signal Dmod and the signal Dcont2 in the power amplification module 100 of the first embodiment. The signal adjustment unit 518 operates the peak amplifier 514 by passing the signal RF12 based on the signal Dcont3. In this way, the power amplification module 500 can operate the peak amplifier 514 at an appropriate timing as the carrier amplifier 513 is saturated, thereby preventing destruction of the power amplification circuit 510.

===Summary===

The power amplification module 100 according to an exemplary embodiment of the present disclosure includes a drive stage amplifier 111 (first amplifier) that amplifies the signal RFin (first signal) and outputs the signal RF1 (second signal). ) and a distributor 112 for distributing the signal RF1 (second signal) into signal RF12 (third signal) and signal RF12 (fourth signal), and signal RF11 (third signal) A carrier amplifier 113 (second amplifier) amplifies and outputs the signal RF2 (the fifth signal), and amplifies the signal RF12 (the fourth signal) and outputs the signal RF3 (the sixth signal). A peak amplifier 114 (third amplifier) that inputs the signal RF2 (fifth signal), and a first phase shifter 115 (phase shifter) that changes the phase of the signal RF2 (fifth signal) , combining the signal RF3 (sixth signal) and the signal RF2 whose phase has been changed in the first phase shifter 115, and outputting an amplified signal (Pout) of the signal RF1 (second signal) A signal for controlling the power level of the signal RF3 (sixth signal) output from the peak amplifier 114 (third amplifier) based on the amplitude level of the unit 117 and the signal RFin (first signal) It is provided with a control unit 121 (controller) that outputs (Dcont) (first control signal). As a result, it is possible to provide a power amplification module 100 that reduces variation in characteristics so that it is less affected by the characteristics of the transistor.

In addition, the control unit 121 (controller) of the power amplification module 100 is provided with a switch 122 for switching whether or not the signal RF3 (sixth signal) is output from the peak amplifier 114 (third amplifier). , the switch 122 is controlled to turn on and off based on the signal Dcont (first control signal). As a result, stable control of the peak amplifier 114 becomes possible, and a highly efficient power amplification module 100 that is less susceptible to the characteristics of various elements can be realized.

Additionally, the gain of the drive stage amplifier 111a of the power amplification module 100a is controlled based on the signal Dcont (first control signal). As a result, nonlinear characteristics when the peak amplifier 114 operates can be suppressed.

In addition, the power amplification module 100c further includes a first bias circuit 123c that supplies a bias current or voltage to the third amplifier, and the first bias circuit 123c is connected to the signal Dcont (first control signal). Based on this, the bias current or voltage to the peak amplifier 114 (third amplifier) is controlled. As a result, when the peak amplifier 114 is stopped, the bias current does not flow to the peak amplifier 114, so the power amplification module 100c can realize low power consumption.

In addition, the power amplification module 100e further includes a second bias circuit 124e that supplies a bias current or voltage to the drive amplifier 111 (first amplifier), and the second bias circuit 124e supplies a signal (Dcont) ) (first control signal), the bias current or voltage to the drive stage amplifier 111 (first amplifier) is controlled. As a result, nonlinear characteristics when the peak amplifier 114 operates can be suppressed.

In addition, the carrier amplifier 113 (second amplifier) of the power amplification module 100d amplifies the signal RF11 (third signal) in a region where the power level of the signal RF1 (second signal) is above the first level. The signal RF2 (fifth signal) is amplified, and the peak amplifier 114 (third amplifier) outputs the signal RF1 (second signal) in an area above the second level where the power level of the signal RF1 (second signal) is greater than the first level. In this way, the signal RF12 (the fourth signal) is amplified and the signal RF3 (the sixth signal) is output. As a result, in the power amplification module 100d, power consumption when the peak amplifier 114 is not operating can be reduced.

Additionally, the gain of the carrier amplifier 113b (second amplifier) of the power amplification module 100b is controlled based on the signal Dcont (first control signal). As a result, in the power amplification module 100b, a decrease in the load impedance of the carrier amplifier 113b can be suppressed, a decrease in gain can be suppressed, and nonlinear characteristics can be suppressed.

In addition, the power amplification modules 300, 400, and 500 include a drive amplifier 311 (first amplifier) that amplifies the signal RFin (first signal) and outputs the signal RF1 (second signal), and a signal RF1 ( A divider 312 that distributes the second signal) into the signal RF12 (third signal) and the signal RF12 (fourth signal), and amplifies the signal RF12 (third signal) to produce a signal RF2 ( A carrier amplifier 313 (second amplifier) that outputs the fifth signal) and a peak amplifier 314 (the second amplifier) that amplifies the signal RF12 (the fourth signal) and outputs the signal RF3 (the sixth signal). 3 amplifier), a first phase shifter 315 (phase shifter) to which the signal RF2 (fifth signal) is input and changes the phase of the signal RF2 (fifth signal), and a signal RF3 (sixth signal) signal) and a signal RF2 (fifth signal) whose phase has been changed in the phase shifter, and output an amplified signal Pout of the signal RF1 (second signal), and a distributor 312 ) and the peak amplifier 314 (third amplifier), the signal adjustment unit 318 that adjusts the passing amount of the signal RF12 (fourth signal), and the carrier amplifier 313 (second amplifier) It is provided with an output circuit 324 that outputs a signal Dcont2 (second control signal) for controlling the signal adjustment unit 318 based on the base current to the signal adjustment section 318, and the signal adjustment section 318 outputs a signal ( The passing amount of the signal RF12 (the fourth signal) is adjusted based on Dcont2) (the second control signal). As a result, in the power amplification modules 300, 400, and 500, power consumption when the peak amplifiers 314, 414, and 514 are not operating can be reduced, and as the carrier amplifiers 313, 413, and 513 are saturated, the peak amplifiers 314, 414, and 513 are saturated. Since the amplifiers 314, 414, and 514 can be operated, damage to the power amplification circuits 310, 410, and 510 can be prevented.

Additionally, the output circuit 324 of the power amplification module 300 outputs a signal Dcont2 (second control signal) based on the bias current supplied to the base of the carrier amplifier 313 (second amplifier). As a result, in the power amplification module 300, power consumption when the peak amplifier 314 is not operating can be reduced, and as the carrier amplifier 313 saturates, the peak amplifier 314 can be reached at an appropriate timing. Since the amplifier 314 can be operated, damage to the power amplification circuit 310 can be prevented.

In addition, the output circuit 424 of the power amplification module 400 outputs a signal Dcont2 (second signal) based on the signal RF2 (fifth signal) that changes according to the base current of the carrier amplifier 413 (second amplifier). control signal) is output. As a result, in the power amplification module 400, power consumption when the peak amplifier 414 is not operating can be reduced, and as the carrier amplifier 413 saturates, the peak amplifier 414 can be reached at an appropriate timing. Since the amplifier 414 can be operated, damage to the power amplification circuit 410 can be prevented.

Additionally, the signal adjustment units 318, 418, and 518 of the power amplification modules 300, 400, and 500 are variable attenuators that change the characteristics of current passing according to the signal Dcont2 (second control signal). As a result, the variable attenuator can easily control the operating points of the peak amplifiers 314, 414, and 514, and thus can easily prevent damage to the power amplification circuits 310, 410, and 510.

Additionally, the signal adjustment units 318, 418, and 518 of the power amplification modules 300, 400, and 500 are switches that switch whether to supply the fourth signal to the third amplifier or not according to the signal Dcont2 (second control signal). As a result, the operating points of the peak amplifiers 314, 414, and 514 can be easily controlled with a simple configuration.

The embodiments described above are intended to facilitate understanding of the present disclosure, and are not intended to limit the present disclosure. This disclosure may be changed or improved without departing from its spirit, and equivalents thereof are also included in this disclosure. In other words, appropriate design changes added by those skilled in the art to the embodiments are included in the scope of the present disclosure as long as they retain the features of the present disclosure. The elements provided in the embodiment, their arrangement, etc. are not limited to those illustrated and can be changed as appropriate.

100… Power amplification module, 110… Power amplification circuit, 111… Drive stage amplifier, 112… Distributor, 113… Carrier Amplifier, 114... Peak Amp, 115… 1st Lee Sang-gi, 116… 2nd Lee Sang-gi, 117… Synthesis section, 120… Control circuit, 121… Control unit, 122… Switch, 123… First bias circuit, 124... Second bias circuit, 125... Third bias circuit.

Claims (12)

a first amplifier that amplifies the first signal and outputs a second signal;
a distributor that distributes the second signal into a third signal and a fourth signal;
a second amplifier that amplifies the third signal and outputs a fifth signal;
a third amplifier that amplifies the fourth signal and outputs a sixth signal;
a phase shifter to which the fifth signal is input and to change the phase of the fifth signal;
a synthesis unit that synthesizes the sixth signal and the fifth signal whose phase has been changed in the phase shifter and outputs an amplified signal of the second signal;
A controller that outputs a first control signal that controls the power level of the sixth signal output from the third amplifier,
The gain of the first amplifier is controlled based on the first control signal,
The first control signal is a power amplification module output based on a signal having a value of 0 or 1 depending on the amplitude level of the first signal. According to claim 1,
The controller has a switch for switching whether or not the sixth signal is output from the third amplifier,
A power amplification module wherein the switch is controlled to turn on and off based on the first control signal. delete The method of claim 1 or 2,
Further comprising a first bias circuit that supplies a bias current or voltage to the third amplifier,
The first bias circuit is a power amplification module in which the bias current or voltage to the third amplifier is controlled based on the first control signal. The method of claim 1 or 2,
Further comprising a second bias circuit that supplies a bias current or voltage to the first amplifier,
The second bias circuit is a power amplification module in which the bias current or voltage to the first amplifier is controlled based on the first control signal. The method of claim 1 or 2,
The second amplifier amplifies the third signal and outputs the fifth signal in a region where the power level of the second signal is higher than the first level,
The third amplifier is a power amplification module that amplifies the fourth signal and outputs the sixth signal in a region above the second level where the power level of the second signal is greater than the first level. The method of claim 1 or 2,
A power amplification module in which the gain of the second amplifier is controlled based on the first control signal. a first amplifier that amplifies the first signal and outputs a second signal;
a distributor that distributes the second signal into a third signal and a fourth signal;
a second amplifier that amplifies the third signal and outputs a fifth signal;
a third amplifier that amplifies the fourth signal and outputs a sixth signal;
a phase shifter to which the fifth signal is input and to change the phase of the fifth signal;
a synthesis unit that synthesizes the sixth signal and the fifth signal whose phase has been changed by the phase shifter and outputs an amplified signal of the second signal;
a signal adjustment unit installed between the distributor and the third amplifier and adjusting a passing amount of the fourth signal;
An output circuit for outputting a second control signal for controlling the signal adjustment unit to the signal adjustment unit based on the base current of the second amplifier,
The signal adjustment unit is a power amplification module that adjusts the passing amount of the fourth signal based on the second control signal. According to claim 8,
The output circuit is a power amplification module that outputs the second control signal based on a bias current supplied to the base of the second amplifier. According to claim 8,
The output circuit is a power amplification module that outputs the second control signal based on the fifth signal that changes depending on the base current of the second amplifier. The method according to any one of claims 8 to 10,
The signal adjusting unit is a power amplification module that is a variable attenuator that changes the characteristics of current passing according to the second control signal. The method according to any one of claims 8 to 10,
The signal adjusting unit is a power amplification module that switches whether or not to supply the fourth signal to the third amplifier according to the second control signal.