CN215072332U

CN215072332U - Power amplifying module

Info

Publication number: CN215072332U
Application number: CN202120635997.3U
Authority: CN
Inventors: 田中聪; 祐森义明; 小暮武
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2020-04-07
Filing date: 2021-03-29
Publication date: 2021-12-07
Anticipated expiration: 2031-03-29
Also published as: KR20210124902A; JP2021166376A; KR102619263B1

Abstract

Provided is a power amplification module which is not affected by the characteristics of a transistor and can maintain linear characteristics. The power amplification module includes: a first amplifier that amplifies the first signal and outputs a second signal; a distributor that distributes the second signal into a third signal and a fourth signal; a second amplifier that amplifies the third signal and outputs a fifth signal; a third amplifier that amplifies the fourth signal and outputs a sixth signal; a phase shifter to which the fifth signal is input and which changes a phase of the fifth signal; a combining unit that combines the sixth signal and the fifth signal whose phase has been changed by the phase shifter, and outputs an amplified signal of the second signal; and a controller that outputs a control signal that controls a power level of the sixth signal output from the third amplifier based on an amplitude level of the first signal.

Description

Power amplifying module

Technical Field

The present disclosure relates to a power amplification module.

Background

Doherty amplifiers are power amplifiers (power amplifiers) that are highly efficient. The doherty amplifier is generally connected in parallel with a carrier amplifier that operates regardless of the power level of an input signal, and a peak amplifier that is turned off when the power level of the input signal is small and turned on when the power level of the input signal is large. When the power level of the input signal is high, the carrier amplifier operates while maintaining saturation at the saturation output power level. Thus, the doherty amplifier can improve efficiency as compared with a normal power amplifier.

Prior art documents

Patent document

Patent document 1: japanese laid-open patent publication No. 8-330873

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

As described above, in the doherty amplifier, the peak amplifier is operated at a timing (timing) at which the carrier amplifier is close to saturation. The peak amplifier operates at an appropriate timing by optimizing the class C bias level. The class C bias level is adjusted in the region where the idle current of the peak amplifier is zero. However, in the doherty amplifier, since characteristics of transistors and characteristics of elements of a matching circuit vary, it is necessary to set the bias level in detail. In addition, the doherty amplifier needs to introduce a predistortion method for compensating for distortion characteristics.

In view of the above, an object of the present disclosure is to provide a power amplifier module that is less affected by characteristics of transistors and reduces variations in characteristics.

Means for solving the problems

The utility model discloses a power amplification module of an aspect possesses: a first amplifier that amplifies the first signal and outputs a second signal; a distributor that distributes the second signal into a third signal and a fourth signal; a second amplifier that amplifies the third signal and outputs a fifth signal; a third amplifier that amplifies the fourth signal and outputs a sixth signal; a phase shifter to which the fifth signal is input and which changes a phase of the fifth signal; a combining unit that combines the sixth signal and the fifth signal whose phase has been changed by the phase shifter, and outputs an amplified signal of the second signal; and a controller that outputs a control signal that controls a power level of the sixth signal output from the third amplifier based on an amplitude level of the first signal.

The utility model discloses a power amplification module of an aspect possesses: a first amplifier that amplifies the first signal and outputs a second signal; a distributor that distributes the second signal into a third signal and a fourth signal; a second amplifier that amplifies the third signal and outputs a fifth signal; a third amplifier that amplifies the fourth signal and outputs a sixth signal; a phase shifter to which the fifth signal is input and which changes a phase of the fifth signal; a combining unit that combines the sixth signal and the fifth signal whose phase has been changed by the phase shifter, and outputs an amplified signal of the second signal; a signal adjustment unit provided between the distributor and the third amplifier, for adjusting a throughput of the fourth signal; and an output circuit that outputs a second control signal for controlling the signal adjustment section to the signal adjustment section based on the base current of the second amplifier, wherein the signal adjustment section adjusts the throughput of the fourth signal based on the second control signal.

Effect of the utility model

According to the present disclosure, a power amplification module that is less susceptible to the characteristics of a transistor and can maintain linear characteristics can be provided.

Drawings

Fig. 1 is a diagram showing an example of the configuration of a power amplifier circuit and a control circuit according to an embodiment of the present invention.

Fig. 2 is a diagram showing a configuration example of a signal generation circuit according to an embodiment of the present invention.

Fig. 3 is a graph showing the relationship between the amplitude level of signal RFin and signal Dmod.

Fig. 4 is a graph showing the relationship of the gain to the amplified signal Pout.

Fig. 5 is a diagram showing an example of the configuration of the power amplification module according to the first modification.

Fig. 6 is a diagram showing an example of the configuration of the drive-stage amplifier of the power amplification module according to the first modification.

Fig. 7 is a diagram showing an example of the configuration of a power amplification module according to another example of the first modification.

Fig. 8 is a diagram showing an example of the configuration of a power amplification module according to a second modification.

Fig. 9 is a diagram showing an example of the configuration of a power amplification module according to a third modification.

Fig. 10 is a diagram showing an example of the configuration of a power amplification module according to a fourth modification.

Fig. 11 is a diagram showing an example of the configuration of a power amplification module of a comparative example.

Fig. 12 is a diagram showing an example of the configuration of a power amplification module according to the second embodiment.

Fig. 13 is a diagram showing an example of the configuration of the output circuit according to the second embodiment.

Fig. 14 is a diagram showing an example of the configuration of the signal adjustment unit according to the second embodiment.

Fig. 15 is a diagram showing an example of the configuration of the signal adjustment unit according to the first modification.

Fig. 16 is a diagram showing an example of the configuration of the signal adjustment unit according to the second modification.

Fig. 17 is a diagram showing an example of the configuration of a power amplification module according to the third embodiment.

Fig. 18 is a diagram showing an example of the configuration of the output circuit according to the third embodiment.

Fig. 19 is a diagram showing an example of the configuration of the output circuit of the first modification.

Fig. 20 is a diagram showing an example of the configuration of an output circuit according to a second modification.

Fig. 21 is a diagram showing an example of the configuration of a power amplification module according to the fourth embodiment.

Description of the reference numerals

A power amplification module, 110.. power amplification circuitry, 111.. drive stage amplifier, 112.. divider, 113.. carrier amplifier, 114.. peak amplifier, 115.. first phase shifter, 116.. second phase shifter, 117.. combiner, 120.. control circuitry, 121.. control circuitry, 122.. switch, 123.. first bias circuitry, 124.. second bias circuitry, 125.. third bias circuitry.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Here, the same reference numerals denote the same circuit elements, and redundant description is omitted.

The power amplification module 100 of the present embodiment has a configuration

Fig. 1 and 2 are diagrams showing configuration examples of various circuits related to a power amplification module 100 according to an embodiment of the present invention. The power amplification module 100 is mounted on, for example, a mobile phone, and amplifies power of a signal transmitted to a base station. The power amplification module 100 can amplify power of signals of communication standards such as 2G (second generation mobile communication system), 3G (third generation mobile communication system), 4G (fourth generation mobile communication system), 5G (fifth generation mobile communication system), LTE (Long Term Evolution ) -FDD (Frequency Division Duplex), LTE-TDD (Time Division Duplex), LTE-Advanced, and LTE-Advanced Pro, for example. It should be noted that the communication standard of the signal amplified by the power amplification module 100 is not limited to this.

The power amplification module 100 includes, for example, a power amplification circuit 110, a control circuit 120, and a signal generation circuit 130.

< < Power amplifying Circuit 110 >)

The power amplifier circuit 110 outputs a signal obtained by amplifying an input signal to a predetermined amplitude level, for example.

As shown in fig. 1, the power amplification circuit 110 includes, for example, a driver-stage amplifier 111, a divider 112, a carrier amplifier 113, a peak amplifier 114, a first phase shifter 115, a second phase shifter 116, and a combining unit 117. Each of the components included in the power amplifier circuit 110 may be formed on the same substrate, or may be formed on a plurality of substrates. The phase shifter of the present invention is preferably a line in which the length of wiring is intentionally adjusted.

The driver-stage amplifier 111 (first amplifier) amplifies, for example, an input Radio-Frequency (RF) signal (hereinafter referred to as "signal RFin") and outputs an amplified signal (hereinafter referred to as "signal RF 1"). The frequency of signal RFin is, for example, about several GHz. The driver stage amplifier 111 is not particularly limited, but includes, for example, a Bipolar Transistor such as a Heterojunction Bipolar Transistor (HBT) or a Transistor such as a Field Effect Transistor (MOSFET). The same applies to the carrier amplifier 113 and the peak amplifier 114, which will be described later.

The distributor 112, the carrier amplifier 113, the peak amplifier 114, the first phase shifter 115, the second phase shifter 116, and the combining unit 117 are second-stage amplification circuits that amplify the signal RF1 output from the driver-stage amplifier 111.

The distributor 112 distributes the signal RF1 output from the driver-stage amplifier 111, for example, into a signal input to the carrier amplifier 113 (hereinafter referred to as "signal RF 11") and a signal input to the peak amplifier 114 (hereinafter referred to as "signal RF 12"). Here, the phase of the signal RF12 is delayed by substantially 90 degrees from the phase of the signal RF11 by the second phase shifter 116 described later. The divider 112 may be a distributed constant circuit such as a coupled line 3dB coupler, or a Wilkinson divider, for example.

The carrier amplifier 113 (second amplifier) amplifies, for example, the input signal RF11 and outputs an amplified signal (hereinafter referred to as "signal RF 2"). A load (not shown) is connected to the output side of the carrier amplifier 113, and the value of R is obtained when the peak amplifier is not operating, and the value of R/2 is obtained when the peak amplifier is operating. The carrier amplifier 113 is biased, for example, to class a, class AB, or class B. That is, the carrier amplifier 113 amplifies an input signal and outputs the amplified signal regardless of the power level of the input signal such as a small instantaneous input power.

The peak amplifier 114 (third amplifier) amplifies, for example, the signal RF12 input through the switch 122 and outputs an amplified signal (hereinafter referred to as "signal RF 3"). The peak amplifier 114 is biased, for example, to class a, AB, B, or C. That is, the peak amplifier 114 amplifies an input signal and outputs the amplified signal regardless of the power level of the input signal by switching the on/off state of the switch 122 based on a signal Dmod (described later) output from the signal generation circuit 130.

The first phase shifter 115 (phase shifter) is, for example, an 1/4 wavelength line connected to the output side of the carrier amplifier 113. By this means, the load impedance observed at the output terminal of the carrier amplifier 113 is changed, whereby the carrier amplifier 113 can be made more efficient.

The second phase shifter 116 is connected to the input side of the peak amplifier 114, for example. The second phase shifter 116 is, for example, an 1/4 wavelength line.

The combining section 117 combines the signal RF2 output from the carrier amplifier 113 and passed through the first phase shifter 115 with the signal RF3 output from the peak amplifier 114, and outputs the amplified signal Pout of the signal RFin.

< < control Circuit 120 >)

The control circuit 120 switches the state of operation of at least one of the switch 122, the first to third bias circuits 123 to 125, the driver-stage amplifier 111, the carrier amplifier 113, and the peak amplifier 114, for example, based on a control signal (signal Dmod described later) input from the signal generation circuit 130. In the present embodiment, the mode in which the switch 122 is incorporated in the control circuit 120 is described, but the switch may be incorporated in the power amplifier circuit 110. Alternatively, the switch 122 may be configured independently of various circuits.

As shown in fig. 1, the control circuit 120 includes, for example, a control unit 121, a switch 122, a first bias circuit 123, a second bias circuit 124, and a third bias circuit 125.

The control unit 121 outputs a control signal (hereinafter referred to as "signal Dcont") for controlling at least one of the switch 122, the first bias circuit 123, the second bias circuit 124, the third bias circuit 125, the driver-stage amplifier 111, the carrier amplifier 113, and the peak amplifier 114, based on a control signal (signal Dmod) input from a signal generation circuit 130 described later, for example. In the present embodiment, the controller 121 controls the switch 122.

The switch 122 switches whether or not the signal RF3 is output from the peak amplifier 114, for example. The switch 122 is turned on when the signal Dcont is input from the control unit 121. The switch 122 is connected in series with the base of the peak amplifier 114, for example. In this case, the switch 122 is turned on to input the signal RF12 to the peak amplifier 114, and turned off to not input the signal RF12 to the peak amplifier 114, for example. The switch 122 may be connected in series with the collector of the peak amplifier 114, for example, so that the signal RF3 is not output from the peak amplifier 114 in the off state

The first bias circuit 123 is a circuit that supplies a bias current or voltage to the peak amplifier 114, for example.

The second bias circuit 124 is a circuit that supplies a bias current or voltage to the driver stage amplifier 111, for example.

The third bias circuit 125 is a circuit that supplies a bias current or voltage to the carrier amplifier 113, for example.

< < Signal Generation Circuit 130 >)

The signal generation circuit 130 is a circuit that generates a signal RFin from the IQ signal and generates a control signal (hereinafter referred to as "signal Dmod") to be output to the control circuit 120, for example. Here, the IQ signal is a modulation signal obtained by modulating an input signal such as voice or data based on a modulation scheme such as HSUPA (High-Speed Uplink Packet Access) or LTE (Long Term Evolution). The IQ signal is, for example, a signal of a frequency of the order of several MHz to several hundred MHz.

As shown in fig. 2, the signal generation circuit 130 includes, for example, delay

circuits

131 and 132, an RF modulation unit 133, an amplitude level detection unit 134, an adjustment unit 135, a quantizer 136, and a comparison unit 137.

The

delay circuits

131 and 132 are circuits that delay the IQ signal by a predetermined time in order to match the timing of inputting the signal RFin to the power amplifier circuit 110 with the timing of supplying the power supply voltage Vcc corresponding to the amplitude level of the signal RFin to the power amplifier circuit 110, for example.

The RF modulation unit 133 generates and outputs a signal RFin from the IQ signal, for example. Specifically, the RF modulation unit 133 combines the I signal and the carrier signal by a multiplier, for example, and combines the Q signal and the carrier signal whose phase is shifted by 90 degrees from the Q signal by a multiplier. Then, the RF modulation unit 133 combines the respective signals thus combined by a subtractor to generate a signal RFin.

The amplitude level detection unit 134 detects, for example, the amplitude level of the IQ signal. That is, the amplitude level detection unit 134 detects the amplitude level of the IQ signal corresponding to the amplitude level of the signal RFin output from the RF modulation unit 133.

The adjustment unit 135 has a table storing a correspondence relationship between the amplitude level of the IQ signal and the level of the power supply voltage Vcc, for example, based on the gain characteristics of the transistors. Based on the table, the adjustment unit 135 outputs a signal (hereinafter referred to as "dynamic control signal") for adjusting the voltage level of the power supply voltage Vcc in accordance with the amplitude level of the IQ signal.

The quantizer 136 converts the digital dynamic control signal with high accuracy output from the adjustment unit 135 into a digital signal with low accuracy (with a small number of bits), for example, and outputs a control signal (hereinafter referred to as "signal Dctrl") for discretely adjusting the power supply voltage Vcc to a power supply circuit (not shown). Thus, the power amplifier circuit 110 can perform envelope tracking based on the digital signal.

A power supply circuit (not shown) generates a power supply voltage Vcc of a level corresponding to the signal Dctrl and supplies the power supply voltage Vcc to the power amplifier circuit 110. The power supply circuit (not shown) may include, for example, a DC-DC converter that generates the power supply voltage Vcc of a level corresponding to the signal Dctrl from an input voltage (for example, a battery voltage).

The comparison unit 137 is, for example, a comparison circuit that outputs a signal Dmod to the control circuit 120 when the dynamic control signal output from the adjustment unit 135 is equal to or greater than a predetermined threshold value.

In this way, in the power amplification module 100, by controlling the control circuit 120 based on the signal Dmod, the peak amplifier 114 can be operated at an appropriate timing without being affected by the characteristics of transistors and the like, and therefore, high efficiency can be achieved while suppressing manufacturing variations.

As described above, the power amplification module 100 is not limited to performing envelope tracking based on a digital signal, and may perform Average Power Tracking (APT), for example, in a manner not limited thereto.

< < Power amplification Module of comparative example 200 >)

Hereinafter, the power amplification module 200 of the comparative example will be described with reference to fig. 11. Fig. 11 is a diagram showing an example of the configuration of a power amplification module 200 of a comparative example. The power amplification module 200 of the comparative example is shown to help understand the power amplification module 100 of the present embodiment.

As shown in fig. 11, the power amplification module 200 of the comparative example does not include the switch 122 and the controller 121 for controlling the switch 122, for example, as compared with the power amplification module 100. The power amplification module 200 includes a distortion compensation unit (not shown) in a signal generation circuit (not shown), for example.

In the power amplification module 200 of the comparative example, the carrier amplifier 213 is biased in class a, class AB, or class B, and the peak amplifier 214 is biased in class C. That is, the power amplification module 200 operates only the carrier amplifier 213 before the signal RFin of the predetermined amplitude level is input, and operates the peak amplifier 214 when the signal RFin exceeding the predetermined amplitude level is input.

Here, in the power amplification module 200, the operation timing thereof varies depending on the characteristics of the various elements constituting the module.

On the other hand, as illustrated in fig. 2, for example, a distortion compensation unit (not shown) applies inverse distortion, which is obtained by eliminating the nonlinear input/output characteristics of the power amplification module 200 in advance, to the IQ signal input to the signal generation circuit 130. Thus, a transmission signal from which distortion is removed can be obtained at the output of the power amplification module 200.

On the other hand, in the power amplification module 100 of the present embodiment, as described above, the peak amplifier 114 is biased in class a, class AB, or class B, and the power amplification module 100 includes the switch 122 that controls the peak amplifier 114 based on the amplitude level of the IQ signal. Thus, the power amplification module 100 is not affected by the characteristics of the various elements constituting the power amplification module 100, and the peak amplifier 114 is operated at an appropriate timing in accordance with the IQ signal, so that it is less affected by variations in analog characteristics due to variations in manufacturing of the power amplification module, and efficient signal amplification can be achieved.

The operation of the power amplification module 100 is equal to

The operation of the power amplification module 100 based on the signal Dmod will be described below with reference to fig. 1 to 4. Fig. 3 is a graph showing the relationship between the amplitude level of signal RFin and signal Dmod. Fig. 4 is a graph showing the relationship of the gain to the amplified signal Pout.

In fig. 3 (a), the horizontal axis represents elapsed time t, and the vertical axis represents amplitude level Vout of signal RFin. Reference numeral 1000 in fig. 3 (a) denotes the amplitude level Vout of the signal RFin, and reference numeral 1001 denotes a threshold value.

In fig. 3 (b), the horizontal axis represents elapsed time t, and the vertical axis represents a binary value of signal Dmod. In fig. 3 (b), the binary value of signal Dmod indicates "1" when the amplitude level of signal RFin in fig. 3 (a) exceeds a threshold value, for example.

In fig. 4, the horizontal axis represents the amplified signal Pout, and the vertical axis represents the gain. Reference numeral 1100 denotes the characteristics of the gain of the power amplification module 100 of the present embodiment. Reference numeral 1101 denotes a gain when only the carrier amplifier 113 is operated. Reference numeral 1102 denotes a gain when the peak amplifier 114 and the carrier amplifier 113 are operated simultaneously. Reference numeral 1103 denotes a process of shifting from the single operation of the carrier amplifier to the parallel operation of the carrier amplifier and the peak amplifier in the operation of the power amplification module 200 of the comparative example.

As shown in fig. 2, an IQ signal is input to the signal generation circuit 130. The IQ signal is input as a dynamic control signal to the comparison unit 137 via the delay circuit 132, the amplitude level detection unit 134, and the adjustment unit 135.

When the dynamic control signal corresponding to the signal RFin shown in fig. 2 is input, the comparing unit 137 outputs a signal Dmod when the amplitude level equal to or higher than the "threshold" shown in fig. 3 (a) is detected. That is, as shown in fig. 3 (b), when an IQ signal having an amplitude level of a predetermined magnitude is input, the signal generation circuit 130 outputs a signal Dmod.

As shown in fig. 1, the signal Dmod output from the comparison section 137 is input to the control section 121 of the control circuit 120. Based on signal Dmod, control unit 121 outputs signal Dcont for turning on switch 122.

Then, when the switch 122 is turned on by the signal Dcont, the signal RF12 output from the divider 112 is input to the peak amplifier 114 biased to class a, class AB, class B, or class C through the second phase shifter 116. The peak amplifier 114 amplifies the signal RF12 and outputs a signal RF 3. This reduces the load impedance seen from the output terminal of the carrier amplifier 113, thereby increasing the saturated output power and improving the efficiency of the power amplifier circuit 110.

Further, since the power amplifier circuit 110 can realize switching control of on/off with respect to the peak amplifier 114 in a stable manner, the signal RF3 can be output at an appropriate timing without being affected by the characteristics of various elements. This makes it difficult to be affected by variations in analog characteristics due to variations in manufacturing of the power amplifier module.

The combining unit 117 combines the signal RF3 with the signal RF2 output from the carrier amplifier 113, and outputs an amplified signal (Pout) of the signal RFin.

Thus, as shown in fig. 4, in the power amplification module 100 of the present embodiment, since the peak amplifier 114 is switched by the switch 122, the linear characteristic can be maintained (the nonlinear characteristic can be suppressed) as shown by reference numeral 1100. On the other hand, in the power amplification module 200 of the comparative example, the peak amplifier 114 biased in the class C is operated, and therefore, nonlinearity is shown as indicated by a reference numeral 1103.

Power amplifying module of the variation

A power amplification module according to a modification will be described with reference to fig. 5 to 10. In this modification, descriptions of common matters with the above-described embodiment are omitted, and only differences will be described. In particular, the same effects due to the same structures are not mentioned in sequence.

< first modification >

The configuration of the power amplification module 100a according to the first modification will be described with reference to fig. 5. Fig. 5 is a diagram showing an example of the configuration of the power amplification module 100a according to the first modification. As shown in fig. 5, in the power amplification module 100a, the driver-stage amplifier 111a is controlled by the control unit 121a of the control circuit 120a, compared to the power amplification module 100.

The power amplification module 100a inputs the signal Dmod to the control unit 121a, and the control unit 121a turns on the switch 122. Thus, the power amplification module 100a operates the peak amplifier 114 in parallel with the carrier amplifier 113.

At this time, the gain of the power amplification module 100a differs between a state in which the power amplification circuit 110a operates only by the carrier amplifier 113 and a state in which the power amplification circuit 110a operates by the carrier amplifier 113 and the peak amplifier 114. That is, the nonlinear characteristic of the power amplification module 100a occurs with the switching of the on and off of the switch 122.

In contrast, in the power amplification module 100a, the gain of the driver stage amplifier 111a is controlled by the control unit 121a at the timing when the switch 122 is turned on, thereby suppressing the nonlinear characteristic.

Specifically, the operation of the power amplifier module 100a according to the first modification will be described with reference to fig. 5 and 6. Fig. 6 is a diagram showing an example of the configuration of the driver-stage amplifier 111a of the power amplification module 100a according to the first modification.

As shown in fig. 5, the control unit 121a turns on the switch 122 when a signal Dmod is input. When the switch 122 is turned on, the peak amplifier 114 operates in parallel with the carrier amplifier 113. As a result, in the power amplification module 100a, the load impedance viewed from the output terminal of the carrier amplifier 113 decreases, and therefore, the gain decreases. This increases the nonlinear characteristics of the power amplification module 100 a.

On the other hand, in order to suppress the nonlinear characteristic, the control unit 121a compensates the gain of the driver stage amplifier 111a when the signal Dmod is input. The principle of compensating the gain of the driver stage amplifier 111a will be described below.

Fig. 6 is a diagram showing an example of the configuration of the driver-stage amplifier 111a of the power amplification module 100a according to the first modification.

As shown in fig. 6, in the driver-stage amplifier 111a, for example, a transistor Q1a is connected in parallel with a transistor Q1b to amplify a signal in 2 stages. The emitter of the transistor Q2b is connected to the base of the transistor Q2a through a resistor R2. A changeover switch SW is connected in series to the base of the transistor Q2 b. The changeover switch SW is turned on when a signal Dmod is input. Thereby, a bias control current Ibias that controls the bias current supplied from the transistor Q2b to the base of the transistor Q2a is supplied to the base of the transistor Q2 b. That is, in the power amplification module 100a, the transistor Q2a is operated while the switch 122 is turned on by the signal Dmod, and the gain of the driver stage amplifier 111a is increased by increasing the total bias current of the driver stage.

In other words, in order to compensate for the decrease in gain due to the decrease in load impedance observed from the output terminal of the carrier amplifier 113 when the switch 122 is turned on, the power amplification module 100a operates the transistor Q2a based on the signal Dmod, and increases the gain of the driver-stage amplifier 111 a.

Fig. 7 is a diagram showing an example of the configuration of a power amplification module 100b according to another example of the first modification. As shown in fig. 7, in the power amplification module 100b, the gain of the carrier amplifier 113b may be controlled by the control unit 121b at the timing when the switch 122 is turned on.

Thus, in the power amplification module 100a, the current of the transistor constituting the carrier amplifier 113b is increased to increase the transconductance, so that the suppression due to the decrease in the load impedance of the carrier amplifier 113b is cancelled, and the decrease in the gain can be suppressed.

< second modification >

The configuration of a power amplifier module 100c according to a second modification will be described with reference to fig. 8. Fig. 8 is a diagram showing an example of the configuration of a power amplification module 100c according to a second modification. As shown in fig. 8, in the power amplification module 100c, the first bias circuit 123c of the peak amplifier 114 is controlled by the controller 121c of the control circuit 120c, compared to the power amplification module 100.

When the peak amplifier 114 is biased in class a, class AB, or class B by the first bias circuit 123c, current continues to flow to the peak amplifier 114 even if the switch 122 is off. Therefore, when the peak amplifier 114 is biased in class a, class AB, or class B, it is preferable to cut off the bias current from the first bias circuit 123c from the viewpoint of reducing power consumption.

In contrast, in the power amplification module 100c of the second modification, the controller 121c turns on and off the first bias circuit 123c in response to the on and off of the switch 122, thereby reducing power consumption.

Specifically, the operation of the power amplifier module 100c according to the second modification will be described with reference to fig. 8.

As shown in fig. 8, when a signal Dmod is input, the control unit 121c turns on the switch 122 and also turns on the first bias circuit 123 c. That is, the control unit 121c turns on the switch 122 to input the signal RF12 to the peak amplifier 114, and turns on the first bias circuit 123c to apply a class a, class AB, or class B bias to the peak amplifier 114.

Then, the control section 121c turns off the switch 122 and turns off the first bias circuit 123c after the input of the signal Dmod disappears. That is, the control unit 121c turns off the switch 122 so that the signal RF12 is not input to the peak amplifier 114, and turns off the first bias circuit 123c so that a bias is not applied to the peak amplifier 114.

Thus, the power amplification module 100c can reduce power consumption when the peak amplifier 114 is not operating.

< third modification >

The configuration of a power amplifier module 100d according to a third modification will be described with reference to fig. 9. As shown in fig. 9, the power amplification module 100d does not include the switch 122 as compared with the power amplification module 100, and the control unit 121d of the control circuit 120d controls the first bias circuit 123d of the peak amplifier 114.

When the power amplification module 100d turns on and off the peak amplifier 114 via the switch 122, the load impedance viewed from the output terminal of the driver-stage amplifier 111 fluctuates each time. That is, in the power amplification module 100d, the gain is changed greatly by turning on and off the switch 122.

In contrast, the power amplification module 100d of the third modification does not include the switch 122, and the control unit 121d switches the operation of the peak amplifier 114 by turning on and off the first bias circuit 123 d. Here, the peak amplifier 114 becomes a deep class C bias when the first bias circuit 123d is off, and becomes a shallow class C bias, class a, class AB, or class B when the first bias circuit 123d is on.

Specifically, the operation of the power amplifier module 100d according to the third modification will be described with reference to fig. 9.

As shown in fig. 9, the control unit 121d turns on the first bias circuit 123d when the signal Dmod is input. That is, in the power amplification module 100d, the first bias circuit 123d is turned on to apply a bias to the peak amplifier 114. Then, the control unit 121d turns off the first bias circuit 123d after the input of the signal Dmod disappears. That is, in the power amplification module 100d, the first bias circuit 123d is turned off and turned off so that no bias is applied to the peak amplifier 114. Thus, in the power amplification module 100d, the power consumption when the peak amplifier 114 is not operating can be reduced, and the nonlinear characteristic due to the on/off of the switch 122 can be suppressed.

< fourth modification >

The configuration of a power amplifier module 100e according to a fourth modification will be described with reference to fig. 10. As shown in fig. 10, in the power amplification module 100e, the second bias circuit 124e of the driver stage amplifier 111 is controlled by the control unit 121e of the control circuit 120e, compared to the power amplification module 100.

In the power amplification module 100e, when the signal Dmod is input to the control unit 121e, the control unit 121e turns on the switch 122. Thus, the power amplification module 100e operates the peak amplifier 114 in parallel with the carrier amplifier 113.

At this time, the gain of the power amplification module 100e differs between a state in which the power amplification circuit 110e operates only by the carrier amplifier 113 and a state in which the power amplification circuit 110e operates by the carrier amplifier 113 and the peak amplifier 114. That is, the nonlinear characteristic of the power amplification module 100e increases with the switching of the on and off of the switch 122.

In contrast, in the power amplification module 100e, the control unit 121e adjusts the magnitude of the bias current or voltage of the second bias circuit 124e at the timing when the switch 122 is turned on, so that the gain of the driver stage amplifier 111 is controlled, thereby suppressing the nonlinear characteristic.

Specifically, the operation of the power amplifier module 100e according to the fourth modification will be described with reference to fig. 10.

As shown in fig. 10, the control unit 121e turns on the switch 122 when a signal Dmod is input. When the switch 122 is turned on, the peak amplifier 114 operates in parallel with the carrier amplifier 113. As a result, in the power amplification module 100e, the load impedance of the carrier amplifier 113 decreases, and therefore, the gain decreases. This increases the nonlinear characteristics of the power amplification module 100 e.

In order to suppress the nonlinear characteristic, the control unit 121e adjusts the magnitude of the bias current or voltage of the second bias circuit 124e to compensate for the gain of the driver stage amplifier 111 when the signal Dmod is input.

Thus, the control unit 121e can compensate the gain of the driver stage amplifier 111 to suppress the nonlinear characteristic.

The power amplification module 300 of the second embodiment

A power amplification module 300 according to a second embodiment will be described with reference to fig. 12 to 14. Fig. 12 is a diagram showing an example of the configuration of a power amplification module 300 according to the second embodiment. Fig. 13 is a diagram showing an example of the configuration of the output circuit 324. Fig. 14 is a diagram showing an example of the configuration of the signal adjustment section 318. In the present embodiment, descriptions of common matters with the above-described embodiments are omitted, and only differences will be described. In particular, the same effects due to the same structures are not mentioned in sequence.

The power amplification module 300 of the second embodiment detects saturation of the carrier amplifier 313 based on, for example, the base current of the carrier amplifier 313. The power amplification module 300 operates the peak amplifier 314 in response to detection of saturation of the carrier amplifier 313. Thus, the power amplifier module 300 can prevent the power amplifier circuit 310 from being destroyed due to the operation delay of the peak amplifier 314. As shown in fig. 12, the power amplification module 300 includes an output circuit 324 and a signal adjustment section 318. For example, in comparison with the power amplification module 100, the power amplification module 300 controls the peak amplifier 314 through the output circuit 324 and the signal adjustment unit 318, instead of controlling the peak amplifier 114 through the control unit 121 and the switch 122. Specifically, in the power amplification module 300, for example, based on the base current of the carrier amplifier 313, the output circuit 324 outputs a control signal (hereinafter referred to as "signal Dcont 2") indicating that the carrier amplifier 313 is saturated to the signal adjustment unit 318. The signal adjustment unit 318 operates the peak amplifier 314 by passing the signal RF12 based on the signal Dcont 2. In this way, the power amplification module 300 can operate the peak amplifier 314 at an appropriate timing in accordance with the saturation of the carrier amplifier 313, and thus can prevent the destruction of the power amplification circuit 310.

Here, the output circuit 324 will be described with reference to fig. 13. The output circuit 324 supplies a bias current to the carrier amplifier 313, for example, and detects a base current of the carrier amplifier 313. The output circuit 324 may be included in the control circuit 320 or may not be included in the control circuit 320. The output circuit 324 outputs a signal Dcont2 for controlling the signal adjustment section 318 based on the base current of the carrier amplifier 313. As shown in fig. 13, the output circuit 324 includes, for example, an input terminal 324a, an output terminal 323b, a transistor Q11, a transistor Q12, a resistor R11, and a resistor R12. The input terminal 324a is a terminal to which a control signal for controlling the bias current is supplied. The output terminal 323b is a terminal for outputting a signal Dcont 2. The transistor Q11 is a transistor that supplies a bias current to the carrier amplifier 313. The transistor Q11 has a collector connected to the power supply Vcc1 and an emitter connected to the base of the carrier amplifier 313 via a resistor. The base of transistor Q11 is supplied with a control signal for controlling the bias current, for example, through resistor R11. The transistor Q12 has a collector connected to the base of the transistor Q11, a base connected to the emitter of the transistor Q11 through a resistor R12, and an emitter connected to ground. The output terminal 323b is connected to a node between the base of the transistor Q12 and the resistor R12.

Next, the signal adjustment unit 318 will be described with reference to fig. 14. The signal adjustment section 318 is connected in series to the base of the peak amplifier 314. The signal adjustment unit 318 controls whether or not to pass the signal RF12, for example, based on the signal Dcont 2. The signal adjustment unit 318 is, for example, a variable attenuator that changes the transmission characteristics with respect to the signal RF12 based on the signal Dcont 2. Thus, the signal adjustment unit 318 can easily control the operating point of the peak amplifier 314. As shown in fig. 14, the signal adjustment section 318 includes, for example, an input terminal 318a, an output terminal 318b, a control terminal 318C, a transistor Q21, a resistor R21, a resistor R22, a capacitor C21, and an inductor L21. The input terminal 318a is a terminal to which the signal RF12 is supplied. The output terminal 318b outputs the signal RF12 from the emitter of the transistor Q21 in accordance with the signal Dcont 2. The control terminal 317d is a terminal to which a signal Dcont2 is supplied. The transistor Q21 has a collector connected to the input terminal 318a via a capacitor C21, an emitter connected to the output terminal 318b, and a base connected to the control terminal 317d via a resistor R21. In addition, the collector of the transistor Q21 is connected to the power supply Vcc2 through a resistor R42. The capacitor C21 is a capacitor for cutting off the dc component of the signal RF 12. The inductor L21 has one end connected to the emitter of the transistor Q21 and the other end connected to ground. Inductor L2 is an inductor for flowing the dc component of signal RF12 to ground. Here, the output 324b of the output circuit 324 shown in fig. 13 is directly connected to the control terminal 318c shown in fig. 14, but a level shift circuit may be appropriately inserted. The transistor Q21 shown in fig. 14 is described as a bipolar transistor, but may be an FET.

The signal adjustment unit 318 is not limited to the variable attenuator described above. The signal adjustment unit 318 may be a switch that switches whether or not the signal RF12 is input to the peak amplifier 314, for example. The switch is connected in series with the base of the peak amplifier 314, for example. The switch is turned on when the signal Dcont2 is input from the output circuit 324. That is, the switch is switched such that, for example, the signal RF12 is input to the peak amplifier 314 in the on state, and the signal RF12 is not input to the peak amplifier 314 in the off state. Thus, the signal adjustment unit 318 can control the operating point of the peak amplifier 314 with a simple configuration.

In addition, in fig. 12, it is shown that the power amplification circuit 310 includes only one carrier amplifier and one peak amplifier, but is not limited thereto. For example, the power amplifier circuit 310 may be configured to include a plurality of carrier amplifiers connected in series and a plurality of peak amplifiers connected in series. In this case, the output circuit 324 is preferably provided to detect the base current of the carrier amplifier closest to the output side, for example. The signal adjustment unit 318 may be connected in series to the base of any one of the plurality of peak amplifiers, for example.

Here, a first modification of the signal adjustment unit 318 will be described with reference to fig. 15. Fig. 15 is a diagram showing an example of the configuration of the signal adjustment section 1318 according to the first modification. Description of common matters with the signal adjustment unit 318 of the above-described embodiment is omitted, and only different points will be described. As shown in fig. 15, the signal adjustment section 1318 is a circuit in which, for example, a transistor Q22, a resistor R23, a resistor R24, and a capacitor C22 are added between the input terminal 1318a and the output terminal 1318b with respect to the signal adjustment section 318. The transistor Q22 has a collector connected to the output terminal 1318b via a capacitor C22, an emitter connected to ground via an inductor L41, and a base connected to the control terminal 318C via a resistor R43. The emitter of the transistor Q22 is connected to the emitter of the transistor Q21. Further, the collector of the transistor Q22 is connected to the power supply Vcc3 through a resistor R24. Here, the output 324b of the output circuit 324 shown in fig. 13 is directly connected to the control terminal 1318c shown in fig. 15, but a level shift circuit may be appropriately inserted. The transistors Q21 and Q22 shown in fig. 15 are described as bipolar transistors, but may be FETs.

A second modification of the signal adjustment unit 318 will be described with reference to fig. 16. Fig. 16 is a diagram showing an example of the configuration of the signal adjustment section 2318 according to the second modification. As shown in fig. 16, the signal adjustment section 2318 includes, for example, an input terminal 2318a, an output terminal 2318b, a control terminal 2318C, a diode D31, a diode D32, an inductor L31, an inductor L32, a capacitor C31, a capacitor C32, inductors L33 and L34 constituting a 90-degree hybrid circuit, and capacitors C33, C34, C35, C36, and C37. The input terminal 2318a is a terminal to which the signal RF12 is supplied. The output terminal 2318b is a terminal for outputting a signal RF12 corresponding to the signal Dcont 2. The control terminal 2318c is connected to the anode of the diode D31 through the inductor L31, and to the anode of the diode D32 through the inductor L32. The cathodes of diode D31 and diode D32 are connected to ground. The capacitor C31 is a capacitor for cutting off a dc component, and has one end connected to the anode of the diode D31 and the other end connected to the 90-degree hybrid circuit. The capacitor C32 is a capacitor for cutting off a dc component, and has one end connected to the anode of the diode D32 and the other end connected to the 90-degree hybrid circuit. Here, the output 324b of the output circuit 324 shown in fig. 13 is directly connected to the control terminal 2318c shown in fig. 16, but a level shift circuit may be appropriately inserted. Further, instead of the diodes D31 and D32 shown in fig. 16, an FET having a drain and a gate connected to each other may be applied.

The operation of the power amplification module 300 according to the second embodiment is equal to

The operation of the power amplifier module 300 will be described below with reference to fig. 12 to 14. First, in the power amplification module 300, when the carrier amplifier 313 is saturated, the base-collector diode becomes on-state. This increases the base current of the carrier amplifier 313, and increases the current flowing from the emitter of the transistor Q11 of the output circuit 324 to the carrier amplifier 313 shown in fig. 13. At this time, as the current supplied from the emitter of the transistor Q11 increases, the potential of the emitter of the transistor Q11 decreases. Further, the current supplied from the emitter of the transistor Q11 is supplied to the base of the transistor Q12 through the resistor R12. However, since the signal RF11 is not input to the transistor Q12, the entire current supplied from the transistor Q11 is not supplied to the base of the transistor Q12. Therefore, a part of the current supplied from the emitter of the transistor Q11 is supplied to the output terminal 323 b. The output circuit 324 outputs the current supplied to the output terminal 323b as a signal Dcont 2. Therefore, the output circuit 324 can output the signal Dcont2 based on the base current of the carrier amplifier 313.

Next, the signal adjustment section 318 shown in fig. 14 supplies the control signal Dcont2 to the base of the transistor Q21 through the resistor R21. When the control signal Dcont2 exceeds a predetermined current value, the transistor Q21 passes the signal RF12 through the output terminal 318 b. Then, the peak amplifier 314 amplifies the signal RF12 and outputs a signal RF 3. This makes it possible to operate peak amplifier 314 without an operation delay when carrier amplifier 313 is saturated, and thus, breakage of power amplifier circuit 310 can be prevented.

The power amplification module 400 of the third embodiment

A power amplification module 400 according to a third embodiment will be described with reference to fig. 17 and 18. Fig. 17 is a diagram showing an example of the configuration of a power amplification module 400 according to the third embodiment. Fig. 18 is a diagram showing an example of the configuration of the output circuit 424. The signal adjustment unit 418 is the same as the signal adjustment unit 318 in the second embodiment, and therefore, the description thereof is omitted. That is, in the present embodiment, descriptions of common matters with the above-described embodiments are omitted, and only differences will be described. In particular, the same effects caused by the same structure are not mentioned in sequence.

The third embodiment power amplification module 400 detects saturation of the carrier amplifier 413, for example, based on the voltage amplitude of the collector that varies according to the base current of the carrier amplifier 413. The power amplification module 400 operates the peak amplifier 414 based on the detection of saturation of the carrier amplifier 413. Thus, the power amplifier module 400 can prevent the power amplifier circuit 410 from being destroyed due to the operation delay of the peak amplifier 414. As shown in fig. 17, the power amplification module 400 includes an output circuit 424 and a signal adjustment section 418. That is, in the power amplification module 400, for example, in comparison with the power amplification module 100, the peak amplifier 414 is controlled by the output circuit 424 and the signal adjustment unit 418 instead of controlling the peak amplifier 114 by the control unit 121 and the switch 122. Specifically, the power amplification module 400 outputs a signal Dcont2 indicating saturation of the carrier amplifier 413 from the output circuit 424 to the signal adjustment unit 418, for example, based on the voltage amplitude of the collector of the carrier amplifier 413. The signal adjustment unit 418 operates the peak amplifier 414 based on the signal Dcont 2. Accordingly, the power amplification module 400 can operate the peak amplifier 414 at an appropriate timing in accordance with the saturation of the carrier amplifier 413, and thus can prevent the destruction of the power amplification circuit 410.

Here, an example of the configuration of the output circuit 424 will be described with reference to fig. 18. The output circuit 424 detects the voltage amplitude of the collector of the carrier amplifier 313. The output circuit 424 outputs a signal Dcont2 for controlling the signal adjustment unit 418 based on the voltage amplitude of the collector. As shown in fig. 18, the output circuit 424 includes, for example, an input terminal 424a, an output terminal 424b, a transistor Q41, a transistor Q42, a resistor R41, a resistor R42, a resistor R43, a resistor R44, and a capacitor C41. The input terminal 424a is a terminal to which the voltage of the collector of the carrier amplifier 413 is input. The output terminal 424b is a terminal for outputting a signal Dcont 2. The transistor Q41 has a collector connected to the power supply Vbat through a resistor R43, a base connected to a node between the resistor R41 and the resistor R42, and an emitter connected to ground. The base of the transistor Q41 is connected to the base of the transistor Q42 via a resistor R41, and the collector of the transistor Q41 is connected to the base of the transistor Q42. That is, a constant voltage circuit is formed by the transistor Q41, the resistor R41, and the resistor R42. Therefore, the base potential of the transistor Q42 is fixed by the constant voltage circuit. The transistor Q42 has a base connected to the constant voltage circuit, a collector connected to the power supply Vbat via a resistor R44, and an emitter connected to the input terminal 424 a. The collector of the transistor Q42 is connected to the output terminal 424 b. The capacitor C41 is a capacitor for smoothing the signal Dcont 2. The capacitor C41 has one end connected to a node between the collector of the transistor Q42 and the output terminal 424b, and the other end connected to ground.

Next, a first modification of the output circuit 424 will be described with reference to fig. 19. Fig. 19 is a diagram showing an example of the configuration of the output circuit 1424 according to the first modification. As shown in fig. 19, the output circuit 1424 includes, for example, an input terminal 1424a, an output terminal 1424b, a transistor Q51, a transistor Q52, a transistor Q53, a diode D51, a diode D52, a resistor R51, a resistor R52, a resistor R53, a capacitor C51, and a current source Is 1. The input terminal 1424a is a terminal to which the voltage of the collector of the carrier amplifier 413 is input. The output terminal 1424b is a terminal for outputting the signal Dcont 2. The transistor Q51 has a collector connected to the input terminal 1424a, an emitter connected to the anode of the diode D51, and a base connected to a predetermined reference potential B1. The cathode of the diode D51 is connected to the output terminal 1424b through the resistor R51. The transistor Q52 has a collector connected to the power supply Vcc4 via the current source Is1, an emitter connected to the anode of the diode D52, and a base connected to a predetermined reference potential B1. The transistor Q53 has a collector connected to the cathode of the diode D52 through a resistor R52, an emitter connected to ground, and a base connected to the power supply Vcc4 through a resistor R53. The capacitor C51 has one end connected to a predetermined reference potential B1 and the other end connected to ground.

A second modification of the output circuit 424 will be described with reference to fig. 20. Fig. 20 is a diagram showing an example of the configuration of the output circuit 2424 according to the second modification. Descriptions of common matters with the output circuit 1424 of the first modification described above are omitted, and only differences will be described. As shown in fig. 20, the output circuit 2424 is a circuit in which an input terminal 2424c, a transistor Q54, a diode D53, and a resistor R54 are added to the output circuit 1424 of the first modification. The input terminal 2424a is a terminal to which a voltage of the collector of the peak amplifier 414 is input, for example. The transistor Q54 has a collector connected to the input terminal 2424c, an emitter connected to the anode of the diode D53, and a base connected to a predetermined reference potential B1. The cathode of the diode D53 is connected to the output terminal 2424b through the resistor R34.

The operation of the power amplification module 400 according to the third embodiment is as follows

The operation of the power amplifier module 400 will be described below with reference to fig. 17 and 18. First, in the power amplification module 400, when the carrier amplifier 413 is saturated, the amplitude of the collector voltage of the carrier amplifier 413 becomes large. The amplitude of the emitter voltage of the transistor Q42 of the output circuit 424 shown in fig. 18 becomes large in accordance with the amplitude of the collector voltage of the carrier amplifier 413. By the amplitude of the emitter voltage of the transistor Q42, the potential of the emitter becomes lower than the potential of the base. At this time, a current flows to the emitter of the transistor Q42. Thereby, a current flows to the collector of the transistor Q42. That is, when the potential of the emitter of the transistor Q42 becomes low, a current flows to the collector of the transistor Q42. The current at the collector of transistor Q42 flows from the power supply Vbat through resistor R44. Thereby, a voltage equal to the product of the current of the collector of the transistor Q42 and the resistor R44 drops, and therefore, the potential of the node between the resistor R44 and the output terminal 424b becomes low. That is, the potential of the output terminal 424b becomes low. The output circuit 424 outputs the voltage drop at the output terminal 424b as a signal Dcont 2.

Since the signal adjustment section 418 is similar to the signal adjustment section 318 of the second embodiment, it is preferable to invert the signal Dcont2 by providing an inverting amplifier circuit (not shown) or a digital circuit on the output side of the output circuit 324, for example. The signal adjustment unit 418 passes the signal RF12 in accordance with the signal Dcont 2. This makes it possible to operate the peak amplifier 414 without an operation delay when the carrier amplifier 413 is saturated, and thus, breakage of the power amplifier circuit 410 can be prevented.

The power amplification module 500 of the fourth embodiment

A power amplification module 500 according to a fourth embodiment is described with reference to fig. 21. Fig. 21 is a diagram showing an example of the configuration of a power amplification module 500 according to the fourth embodiment. In the present embodiment, descriptions of common matters with the above-described embodiments are omitted, and only differences will be described. In particular, the same effects due to the same structures are not mentioned in sequence.

The power amplification module 500 of the fourth embodiment detects saturation of the carrier amplifier 513 based on, for example, the base current of the carrier amplifier 513. The power amplification module 500 outputs a signal Dcont2 indicating saturation of the carrier amplifier 513 to the control unit 524. The controller 524 outputs a control signal (hereinafter referred to as a signal Dcont3) for operating the signal adjuster 518 based on the signal Dcont 2. The control unit 524 may output a signal Dcont3 based on the signal Dmod and the signal Dcont2 in the power amplification module 100 according to the first embodiment. The signal adjustment unit 518 operates the peak amplifier 514 by passing the signal RF12 based on the signal Dcont 3. In this way, the power amplification module 500 can operate the peak amplifier 514 at an appropriate timing in accordance with the saturation of the carrier amplifier 513, and thus can prevent the destruction of the power amplification circuit 510.

The term "summary" means that

The power amplification module 100 according to the exemplary embodiment of the present disclosure includes: a driver-stage amplifier 111 (first amplifier) that amplifies the signal RFin (first signal) and outputs a signal RF1 (second signal); a distributor 112 that distributes the signal RF1 (second signal) into a signal RF12 (third signal) and a signal RF12 (fourth signal); a carrier amplifier 113 (second amplifier) that amplifies the signal RF11 (third signal) and outputs a signal RF2 (fifth signal); a peak amplifier 114 (third amplifier) that amplifies the signal RF12 (fourth signal) and outputs a signal RF3 (sixth signal); a first phase shifter 115 (phase shifter) to which the signal RF2 (fifth signal) is input and which changes the phase of the signal RF2 (fifth signal); a combining unit 117 that combines the signal RF3 (sixth signal) and the signal RF2 whose phase has been changed by the first phase shifter 115, and outputs an amplified signal Pout of the signal RF1 (second signal); and a control unit 121 (controller) that outputs a signal Dcont (first control signal) that controls the power level of the signal RF3 (sixth signal) output from the peak amplifier 114 (third amplifier) based on the amplitude level of the signal RFin (first signal). This makes it possible to provide the power amplification module 100 that is less affected by the characteristics of the transistor and reduces variations in the characteristics.

The control unit 121 (controller) of the power amplification module 100 includes a switch 122 that switches whether or not the signal RF3 (sixth signal) is output from the peak amplifier 114 (third amplifier), and controls the on/off of the switch 122 based on the signal Dcont (first control signal). This enables stable control of the peak amplifier 114, and enables realization of the efficient power amplification module 100 that is less susceptible to the characteristics of various elements.

In addition, the gain of the driver-stage amplifier 111a of the power amplification module 100a is controlled based on the signal Dcont (first control signal). This can suppress the nonlinear characteristic of the peak amplifier 114 when it is operated.

The power amplification module 100c further includes a first bias circuit 123c that supplies a bias current or voltage to the third amplifier, and the first bias circuit 123c controls the bias current or voltage supplied to the peak amplifier 114 (third amplifier) based on the signal Dcont (first control signal). Thus, when the peak amplifier 114 is stopped, the bias current does not flow to the peak amplifier 114, and therefore, the power amplification module 100c can realize low power consumption.

The power amplification module 100e further includes a second bias circuit 124e that supplies a bias current or voltage to the driver stage amplifier 111 (first amplifier), and the second bias circuit 124e controls the bias current or voltage supplied to the driver stage amplifier 111 (first amplifier) based on the signal Dcont (first control signal). This can suppress the nonlinear characteristic of the peak amplifier 114 when it is operated.

The carrier amplifier 113 (second amplifier) of the power amplification module 100d amplifies the signal RF11 (third signal) and outputs the signal RF2 (fifth signal) in a region where the power level of the signal RF1 (second signal) is equal to or higher than the first level, and the peak amplifier 114 (third amplifier) amplifies the signal RF12 (fourth signal) and outputs the signal RF3 (sixth signal) in a region where the power level of the signal RF1 (second signal) is equal to or higher than the second level which is higher than the first level. Thus, in the power amplification module 100d, the power consumption when the peak amplifier 114 is not operating can be reduced.

In addition, the gain of the carrier amplifier 113b (second amplifier) of the power amplification module 100b is controlled based on the signal Dcont (first control signal). Thus, in the power amplification module 100b, the decrease in the load impedance of the carrier amplifier 113b and the decrease in the gain can be suppressed, and thus the nonlinear characteristic can be suppressed.

The power amplification modules 300, 400, and 500 include: a drive stage amplifier 311 (first amplifier) which amplifies the signal RFin (first signal) and outputs a signal RF1 (second signal); a distributor 312 that distributes the signal RF1 (second signal) into a signal RF12 (third signal) and a signal RF12 (fourth signal); a carrier amplifier 313 (second amplifier) that amplifies the signal RF12 (third signal) and outputs a signal RF2 (fifth signal); a peak amplifier 314 (third amplifier) which amplifies the signal RF12 (fourth signal) and outputs a signal RF3 (sixth signal); a first phase shifter 315 (phase shifter) to which the signal RF2 (fifth signal) is input and which changes the phase of the signal RF2 (fifth signal); a combining unit 317 that combines the signal RF3 (sixth signal) and the signal RF2 (fifth signal) whose phase has been changed by the phase shifter, and outputs an amplified signal Pout of the signal RF1 (second signal); a signal adjustment unit 318 provided between the distributor 312 and the peak amplifier 314 (third amplifier) and adjusting the throughput of the signal RF12 (fourth signal); and an output circuit 324 that outputs a signal Dcont2 (second control signal) for controlling the signal adjustment section 318 to the signal adjustment section 318 based on the base current of the carrier amplifier 313 (second amplifier), and the signal adjustment section 318 adjusts the throughput of the signal RF12 (fourth signal) based on the signal Dcont2 (second control signal). Accordingly, in the

power amplification modules

300, 400, and 500, the power consumption when the

peak amplifiers

314, 414, and 514 are not operated can be reduced, and the

peak amplifiers

314, 414, and 514 can be operated at an appropriate timing in accordance with the saturation of the

carrier amplifiers

313, 413, and 513, so that the

power amplification circuits

310, 410, and 510 can be prevented from being destroyed.

The output circuit 324 of the power amplification module 300 outputs a signal Dcont2 (second control signal) based on the bias current supplied to the base of the carrier amplifier 313 (second amplifier). Thus, in the power amplification module 300, the power consumption when the peak amplifier 314 is not operating can be reduced, and the peak amplifier 314 can be operated at an appropriate timing in accordance with the saturation of the carrier amplifier 313, so that the destruction of the power amplification circuit 310 can be prevented.

In addition, the output circuit 424 of the power amplification module 400 outputs a signal Dcont2 (second control signal) based on a signal RF2 (fifth signal) that varies according to the base current of the carrier amplifier 413 (second amplifier). Thus, in the power amplification module 400, the power consumption when the peak amplifier 414 is not operating can be reduced, and the peak amplifier 414 can be operated at an appropriate timing in accordance with the saturation of the carrier amplifier 413, so that the destruction of the power amplification circuit 410 can be prevented.

The

signal adjustment units

318, 418, and 518 of the

power amplification modules

300, 400, and 500 are variable attenuators that change characteristics of passing a current in accordance with the signal Dcont2 (second control signal). This makes it easy for the variable attenuator to control the operating point of the

peak amplifiers

314, 414, 514, and therefore, the

power amplifier circuits

310, 410, 510 can be prevented from being destroyed easily.

The

signal adjustment units

318, 418, and 518 of the

power amplification modules

300, 400, and 500 are switches that switch whether or not to supply the fourth signal to the third amplifier in accordance with the signal Dcont2 (second control signal). This makes it possible to easily control the operating points of the

peak amplifiers

314, 414, and 514 with a simple configuration.

The above-described embodiments are provided for easy understanding of the present disclosure, and are not intended to be restrictive in interpretation. The present disclosure can be modified or improved within a range not departing from the gist thereof, and equivalents thereof are also included in the present disclosure. That is, the embodiment appropriately modified by design by those skilled in the art is included in the scope of the present disclosure as long as the embodiment has the features of the present disclosure. The elements and their arrangement provided in the embodiments are not limited to those exemplified, and can be appropriately modified.

Claims

1. A power amplification module, characterized in that,

the power amplification module includes:

a first amplifier that amplifies the first signal and outputs a second signal;

a distributor that distributes the second signal into a third signal and a fourth signal;

a second amplifier that amplifies the third signal and outputs a fifth signal;

a third amplifier that amplifies the fourth signal and outputs a sixth signal;

a phase shifter to which the fifth signal is input and which changes a phase of the fifth signal;

a combining unit that combines the sixth signal and the fifth signal whose phase has been changed by the phase shifter, and outputs an amplified signal of the second signal; and

a controller outputting a first control signal that controls a power level of the sixth signal output from the third amplifier based on an amplitude level of the first signal.

2. The power amplification module of claim 1,

the controller is provided with a switch that switches whether or not the sixth signal is output from the third amplifier,

the switch is controlled to be turned on and off based on the first control signal.

3. The power amplification module of claim 2,

the gain of the first amplifier is controlled based on the first control signal.

4. The power amplification module of any one of claims 1 to 3,

the power amplification module further includes a first bias circuit that supplies a bias current or voltage to the third amplifier,

the first bias circuit controls the bias current or voltage supplied to the third amplifier based on the first control signal.

5. The power amplification module of any one of claims 1 to 3,

the power amplification module further includes a second bias circuit that supplies a bias current or voltage to the first amplifier,

the second bias circuit controls the bias current or voltage supplied to the first amplifier based on the first control signal.

6. The power amplification module of any one of claims 1 to 3,

a second amplifier that amplifies the third signal and outputs the fifth signal in a region where the power level of the second signal is equal to or higher than a first level,

the third amplifier amplifies the fourth signal and outputs the sixth signal in a region where the power level of the second signal is equal to or higher than a second level that is higher than the first level.

7. The power amplification module of any one of claims 1 to 3,

the gain of the second amplifier is controlled based on the first control signal.

8. A power amplification module, characterized in that,

the power amplification module includes:

a first amplifier that amplifies the first signal and outputs a second signal;

a second amplifier that amplifies the third signal and outputs a fifth signal;

a third amplifier that amplifies the fourth signal and outputs a sixth signal;

a combining unit that combines the sixth signal and the fifth signal whose phase has been changed by the phase shifter, and outputs an amplified signal of the second signal;

a signal adjustment unit provided between the distributor and the third amplifier, for adjusting a throughput of the fourth signal; and

an output circuit that outputs a second control signal for controlling the signal adjustment section to the signal adjustment section based on the base current of the second amplifier,

the signal adjustment section adjusts the throughput of the fourth signal based on the second control signal.

9. The power amplification module of claim 8,

the output circuit outputs the second control signal based on a bias current supplied to a base of the second amplifier.

10. The power amplification module of claim 8,

the output circuit outputs the second control signal based on the fifth signal that varies in accordance with the base current of the second amplifier.

11. The power amplification module of any one of claims 8 to 10,

the signal adjustment unit is a variable attenuator that changes a characteristic of passing a current according to the second control signal.

12. The power amplification module of any one of claims 8 to 10,

the signal adjustment unit is a switch that switches whether or not to supply the fourth signal to the third amplifier in accordance with the second control signal.