KR102596760B1 - Semiconductor package - Google Patents

Abstract

One embodiment of the present invention includes a base connection member having a redistribution layer, a first semiconductor chip having a plurality of first connection pads connected to the redistribution layer, and a semiconductor chip disposed on the base connection member and covering the first semiconductor chip. A package structure including an encapsulant and a backside connection member disposed on the encapsulant and having a backside wiring layer electrically connected to the redistribution layer, and disposed on the package structure and connected to one of the redistribution layer and the backside wiring layer. a second semiconductor chip having a plurality of second connection pads, the second semiconductor chip including a logic unit, the first semiconductor chip including a logic input/output unit for the logic unit, and the logic input/output unit Provides a semiconductor package connected to the logic unit through at least one of the redistribution layer and the backside wiring layer.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

This disclosure relates to semiconductor packages.

As smart electronic devices have recently developed, the specifications of the components used in them are also increasing. For example, the specifications of the application processor (AP), a core chip of smart electronic devices, are rapidly evolving. Accordingly, major processor units that can drive various functions are integrated into one chip.

One of the several purposes of the present disclosure is to provide a semiconductor package that can have an appropriate package size while enhancing package performance.

One of several solutions proposed through this disclosure is to separate a specific existing semiconductor chip, for example, an application processor chip, into a plurality of semiconductor chips and arrange them vertically. In addition, power transmission characteristics, etc. are improved by forming electronic components embedded in the lower semiconductor chip to be connected to the through-via and/or through-via penetrating the lower semiconductor chip on the semiconductor chip designed and placed separately on the lower side.

For example, one embodiment according to the present disclosure includes a base connection member having a redistribution layer, a first semiconductor chip having a plurality of first connection pads connected to the redistribution layer, and disposed on the base connection member, A package structure including an encapsulant covering a first semiconductor chip and a backside connection member disposed on the encapsulant and having a backside wiring layer electrically connected to the redistribution layer, and disposed on the connection member or the backside connection member, A second semiconductor chip having a plurality of second connection pads connected to a redistribution layer or the backside wiring layer, the second semiconductor chip including a logic unit, and the first semiconductor chip providing logic input and output for the logic unit. It includes a unit, and the logic input/output unit provides a semiconductor package connected to the logic unit through at least one of the redistribution layer and the backside wiring layer.

In addition, a first connection member having a first redistribution layer, a first semiconductor chip having a plurality of first connection pads connected to the first redistribution layer, and a first semiconductor chip disposed on the first connection member and including the first semiconductor chip. A first package structure including a first encapsulant covering the first encapsulant, a backside connection member disposed on the first encapsulant and having a backside wiring layer electrically connected to the first redistribution layer, and disposed on the first package structure, the first package structure comprising: a second connecting member having a second rewiring layer connected to one of a first rewiring layer and the backside wiring layer, a second semiconductor chip having a plurality of second connection pads connected to the second rewiring layer, and the second connecting member It is disposed on the second semiconductor chip and includes a second package structure including a second encapsulant covering the second semiconductor chip, wherein the second semiconductor chip includes a logic unit, and the first semiconductor chip is a logic input and output for the logic unit. It includes a unit, and the logic input/output unit provides a semiconductor package connected to the logic unit through at least one of the first redistribution layer, the backside wiring layer, and the second redistribution layer.

In addition, a first connection member having a first redistribution layer, a first semiconductor chip having a plurality of first connection pads connected to the first redistribution layer, and a first semiconductor chip disposed on the first connection member and including the first semiconductor chip. A backside connecting member having a first encapsulating material covering the first encapsulating material and a backside wiring layer electrically connected to the first redistribution layer, disposed between the first connecting member and the backside connecting member, and A first package structure including an interconnection member that electrically connects a redistribution layer and the backside wiring layer, a plurality of devices disposed on the first connection member or the backside connection member and connected to the first redistribution layer or the backside wiring layer. a second semiconductor chip having a second connection pad and a third connection member disposed on the first package structure and the second semiconductor chip, a third semiconductor chip disposed on the third connection member, and the third A third package structure is disposed on a connection member and includes a molding material covering the third semiconductor chip, wherein the third semiconductor chip includes a memory unit, and the second semiconductor chip includes a logic unit and the memory unit. and a memory input/output unit for, wherein the first semiconductor chip includes a logic input/output unit for the logic unit, and the logic input/output unit is connected to the logic unit through at least one of the first redistribution layer and the backside wiring layer. and the memory input/output unit is connected to the memory unit through at least one of the first redistribution layer and the backside wiring layer.

As one of the many effects of the present disclosure, it is possible to provide a semiconductor package that can have an appropriate package size while enhancing package performance.

1 is a block diagram schematically showing an example of an electronic device system.
Figure 2 is a perspective view schematically showing an example of an electronic device.
3A and 3B are cross-sectional views schematically showing before and after packaging a fan-in semiconductor package.
Figure 4 is a cross-sectional view schematically showing the packaging process of a fan-in semiconductor package.
Figure 5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.
Figure 6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.
Figure 7 is a cross-sectional view schematically showing a fan-out semiconductor package.
Figure 8 is a cross-sectional view schematically showing a case where a fan-out semiconductor package is mounted on the main board of an electronic device.
Figure 9 is a cross-sectional view schematically showing an example of a semiconductor package.
Figure 10 is a cross-sectional view schematically showing another example of a semiconductor package.
Figure 11 is a cross-sectional view schematically showing another example of a semiconductor package.
Figure 12 is a cross-sectional view schematically showing another example of a semiconductor package.
Figure 13 is a cross-sectional view schematically showing another example of a semiconductor package.
Figure 14 is a cross-sectional view schematically showing another example of a semiconductor package.

Hereinafter, the present disclosure will be described with reference to the attached drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. The motherboard 1010 is physically and/or electrically connected to chip set-related components 1020, network-related components 1030, and other components 1040. These are combined with other components described later to form various signal lines 1090.

Chip set-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPU), graphics processors (eg, GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; Logic chips such as analog-digital converters and ASICs (application-specific ICs) are included, but are not limited to these, and of course other types of chip-related components may also be included. Additionally, of course, these components 1020 can be combined with each other.

Network-related parts (1030) include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such, but are not limited to, and many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, of course, the network-related components 1030 can be combined with the chip set-related components 1020.

Other parts (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. , but is not limited to this, and may include passive parts used for various other purposes. In addition, of course, the other components 1040 can be combined with the chip set-related components 1020 and/or the network-related components 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other components include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), and a compass ( (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (e.g., hard disk drive) (not shown), compact disk (CD) (not shown), and DVD (digital versatile disk) (not shown), etc. However, it is not limited thereto, and of course, other parts used for various purposes may be included depending on the type of electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Figure 2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, semiconductor packages are applied to various electronic devices as described above for various purposes. For example, a printed circuit board 1110 such as a motherboard is accommodated inside the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically installed on the printed circuit board 1110. It is connected to. Additionally, other components, such as the camera 1130, which may or may not be physically and/or electrically connected to the printed circuit board 1110, are accommodated within the body 1101. Some of the components 1120 may be chip set-related components, for example, the semiconductor package 1121, but are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, and of course, it may be other electronic devices as described above.

semiconductor package

In general, a semiconductor chip integrates numerous microscopic electrical circuits, but it cannot function as a finished semiconductor product by itself, and there is a possibility that it may be damaged by external physical or chemical shock. Therefore, rather than using the semiconductor chip itself, the semiconductor chip is packaged and used in electronic devices as a package.

The reason why semiconductor packaging is necessary is because, from the perspective of electrical connection, there is a difference in circuit width between the semiconductor chip and the main board of electronic devices. Specifically, in the case of semiconductor chips, the size of the connection pads and the spacing between the connection pads are very small, whereas in the case of motherboards used in electronic devices, the size of the component mounting pads and the spacing between the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a motherboard, and packaging technology that can buffer the difference in circuit width between them is required.

Semiconductor packages manufactured using this packaging technology can be divided into fan-in semiconductor packages and fan-out semiconductor packages depending on their structure and use.

Below, we will look at the fan-in semiconductor package and fan-out semiconductor package in more detail with reference to the drawings.

(Fan-in semiconductor package)

3A and 3B are cross-sectional views schematically showing before and after packaging a fan-in semiconductor package.

Figure 4 is a cross-sectional view schematically showing the packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor chip 2220 includes a body 2221 containing silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc., and aluminum (Al) formed on one surface of the body 2221. A connection pad 2222 containing a metal material, and a passivation film 2223 such as an oxide or nitride film formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222, for example, It may be an integrated circuit (IC) in a bare state. At this time, because the connection pad 2222 is very small, it is difficult for an integrated circuit (IC) to be mounted on a mid-level printed circuit board (PCB) as well as a main board of an electronic device.

Accordingly, in order to rewire the connection pad 2222, a connection member 2240 is formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220. The connecting member 2240 forms an insulating layer 2241 with an insulating material such as photosensitive insulating resin (PID: Photo Image-able Dielectric) on the semiconductor chip 2220, and forms a via hole 2243h that opens the connection pad 2222. ) can be formed by forming the wiring pattern 2242 and the via 2243. After that, a passivation layer 2250 is formed to protect the connecting member 2240, an opening 2251 is formed, and then an underbump metal 2260 and the like are formed. That is, through a series of processes, for example, a fan-in semiconductor package 2200 including a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an underbump metal 2260 is manufactured. do.

As such, the fan-in semiconductor package is a package type in which the connection pads of the semiconductor chip, such as I/O (Input/Output) terminals, are all placed inside the device. The fan-in semiconductor package has good electrical characteristics and can be produced inexpensively. there is. Accordingly, many devices used in smartphones are manufactured in the form of fan-in semiconductor packages, and specifically, development is being carried out in the direction of realizing small size and fast signal transmission.

However, fan-in semiconductor packages have many space limitations as all I/O terminals must be placed inside the semiconductor chip. Therefore, it is difficult to apply this structure to semiconductor chips with a large number of I/O terminals or to semiconductor chips of small size. Additionally, due to this vulnerability, the fan-in semiconductor package cannot be directly mounted and used on the main board of an electronic device. Even if the size and spacing of the I/O terminals of a semiconductor chip are expanded through a rewiring process, the size and spacing are not large enough to be directly mounted on the main board of an electronic device.

Figure 5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.

Figure 6 is a cross-sectional view schematically showing the case where the fan-in semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 of the semiconductor chip 2220, that is, the I/O terminals, are rewired again through the printed circuit board 2301, and finally, Can be mounted on the main board 2500 of an electronic device with the fan-in semiconductor package 2200 mounted on the printed circuit board 2301. At this time, the solder ball 2270, etc. may be fixed with an underfill resin 2280, etc., and the outside may be covered with a molding material 2290, etc. Alternatively, the fan-in semiconductor package 2200 may be embedded within a separate printed circuit board 2302, and the connection pads of the semiconductor chip 2220 may be connected by the printed circuit board 2302 in an embedded state. (2222), that is, the I/O terminals can be rewired once again and finally mounted on the main board 2500 of the electronic device.

As such, since it is difficult to use the fan-in semiconductor package by directly mounting it on the main board of an electronic device, it is mounted on a separate printed circuit board and then goes through a packaging process and is then mounted on the main board of the electronic device, or as a printed circuit board. It is used by being embedded within a circuit board and mounted on the main board of an electronic device.

(Fan-out semiconductor package)

Figure 7 is a cross-sectional view schematically showing a fan-out semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected with an encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 is a connecting member. By 2140, the wiring is rewired to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connecting member 2140, and an underbump metal 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the underbump metal 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121 and a connection pad 2122. The connection member 2140 may include an insulating layer 2141, a wiring layer 2142 formed on the insulating layer 2241, and a via 2143 that electrically connects the connection pad 2122 and the wiring layer 2142. .

In this way, the fan-out semiconductor package is a type in which I/O terminals are rewired and arranged to the outside of the semiconductor chip through connection members formed on the semiconductor chip. As described above, the fan-in semiconductor package requires all I/O terminals of the semiconductor chip to be placed inside the semiconductor chip, and as the device size decreases, the ball size and pitch must be reduced, so a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a type in which the I/O terminals are rewired and arranged to the outside of the semiconductor chip through the connecting members formed on the semiconductor chip, so even if the size of the semiconductor chip is reduced, a standardized ball layout is maintained. It can be used as is, and as described later, it can be mounted on the main board of an electronic device without a separate printed circuit board.

Figure 8 is a cross-sectional view schematically showing a case where a fan-out semiconductor package is mounted on the main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on the main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 is a connection member that can rewire the connection pad 2122 on the semiconductor chip 2120 to a fan-out area that exceeds the size of the semiconductor chip 2120. Since it forms (2140), a standardized ball layout can be used as is, and as a result, it can be mounted on the main board 2500 of an electronic device without a separate printed circuit board.

In this way, since the fan-out semiconductor package can be mounted on the main board of an electronic device without a separate printed circuit board, it can be implemented with a thinner thickness than the fan-in semiconductor package using a printed circuit board, enabling miniaturization and thinning. do. Additionally, it has excellent thermal and electrical properties, making it particularly suitable for mobile products. In addition, it can be implemented more compactly than the typical POP (Package on Package) type that uses a printed circuit board (PCB), and problems caused by bending can be solved.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on the motherboard of an electronic device, etc., and for protecting the semiconductor chip from external shock. It is different from this in scale, purpose, etc. It is a different concept from a printed circuit board (PCB), such as a printed circuit board in which a fan-in semiconductor package is built.

Hereinafter, a semiconductor package that can have an appropriate package size while enhancing package performance will be described with reference to the drawings.

Figure 9 is a cross-sectional view schematically showing an example of a semiconductor package.

Referring to the drawings, a semiconductor package 500A according to an example includes a first package structure 100A including a first semiconductor chip 120, and a second semiconductor chip disposed on the first package structure 100A ( 220). The second semiconductor chip 220 may be surface mounted on the first package structure 100A using a connection bump 220B, etc. If necessary, the semiconductor package 500A according to the example may further include a third package structure 300A disposed on the first package structure 100A with the second semiconductor chip 220 interposed therebetween. The third package structure 300A may be mounted in a package-on-package (POP) form on the first package structure 100A using a third electrical connection metal 340, etc. The electrical connection path of power and signals is, for example, as shown in the drawing.

The first package structure 100A includes a first semiconductor chip 120 having a plurality of first connection pads 120P, a first encapsulant 130 covering at least a portion of the first semiconductor chip 120, and a first seal. It is disposed below each of the material 130 and the first semiconductor chip 120 and above the first connection member 140 including one or more first redistribution layers 142 and the first encapsulating material 130, It includes a backside connection member 150 including one or more backside wiring layers 152. In addition, a first interconnection member 110 is disposed between the first connection member 140 and the backside connection member 150 and electrically connects the first redistribution layer 142 and the backside wiring layer 152. may further include. If necessary, a first passivation layer 160 and a first electrical connection metal 170 may be further disposed on the lower side of the first connection member 140. Additionally, a cover layer 180 may be further disposed on the backside connection member 150.

The first semiconductor chip 120 may include a through via (120V) that penetrates the first semiconductor chip 120. The through via (120V) may be electrically connected to the first redistribution layer 142 of the first connection member 140 and the backside wiring layer 152 of the backside connection member 150, respectively. The second semiconductor chip 220 may be arranged to overlap the first semiconductor chip 120 on a plane (or vertically), and therefore, at least one of the plurality of second connection pads 220P of the second semiconductor chip 220 Some may be electrically connected to the first electrical connection metal 170 through the backside wiring layer 152, the through via (120V), and the first redistribution layer 142 in a substantially vertical path. As a result, the transmission path of power, etc. can be minimized.

The first semiconductor chip 120 may include an electronic component 120C disposed inside the first semiconductor chip 120 and electrically connected to a through via (120V). The electronic component 120C may be a capacitor, for example, a MIM (Metal-Insulator-Metal) type capacitor. Through this, power characteristics can be improved more effectively. If necessary, the electronic component 120C may be a specific memory unit, for example, SRAM. Through this, the size of the second semiconductor chip 220 can be reduced by omitting or reducing the SRAM inside the second semiconductor chip 220. If necessary, the electronic component 120C may include both the capacitor and memory unit described above. In other words, it may include both.

The first and second semiconductor chips 120 and 220 may function together as a specific semiconductor chip. For example, the first and second semiconductor chips 120 and 220 may implement the functions of at least one application processor chip. That is, the first and second semiconductor chips 120 and 220 may be designed to separate a specific semiconductor chip, for example, an application processor chip, into a plurality of semiconductor chips 120 and 220. Through this separation design, performance can be optimized while reducing the size of the second semiconductor chip 220 including the core unit, as will be described later. In addition, by separately designing the parts that require high-level design and parts that require relatively less sophisticated design into the first and second semiconductor chips (120, 220), defects in the manufacturing process between the two do not affect the chip, improving yield and reducing costs. It can also be promoted.

For example, the first semiconductor chip 120 may include an input/output unit of an application processor. At this time, the plurality of first connection pads 120P may include a plurality of pads for input/output (I/O) of the application processor. In addition, the second semiconductor chip 220 includes a central processing unit (CPU: Central Processing Unit), a graphics processing unit (GPU: Graphics Processing Unit), a neural processing unit (NPU: Neural Processing Unit), and a digital signal processor. It may include core units such as a digital signal processor unit (DSPU) and an image signal processing unit (ISPU: image signal processor unit). At this time, the plurality of second connection pads 220P may include a first group G1 for these core units. Meanwhile, the second semiconductor chip 220 may further include an input/output (I/O) unit for electrical connection with the memory. At this time, the plurality of second connection pads 220P may include a second group G2 for input/output (I/O) with the memory. Here, the memory may be DRAM, which may be the third semiconductor chip 320 of the third package structure 300A.

Hereinafter, each configuration of the semiconductor package 500A according to an example will be described in more detail with reference to the drawings.

First, the first package structure 100A includes a first connection member 140 having a first redistribution layer 142, and a plurality of first connection pads 120P connected to the first redistribution layer 142. 1 semiconductor chip 120, a first encapsulant 130 disposed on the first connecting member 140 and covering the first semiconductor chip 120, and disposed on the first encapsulant 130. and a backside connection member 150 having a backside wiring layer 152 electrically connected to the first redistribution layer 142, and disposed between the first connection member 140 and the backside connection member 150. It may include an interconnection member 110 that electrically connects the first redistribution layer 142 and the backside wiring layer 152. If necessary, a first passivation layer 160 and a first electrical connection metal 170 may be further disposed on the lower side of the first connection member 140. Additionally, a cover layer 180 may be further disposed on the backside connection member 150.

The interconnection member 110 is disposed between the first connection member 140 and the backside connection member 150 and penetrates the first encapsulant 130 to connect the first rewiring layer 142 and the backside wiring layer. (152) can be electrically connected. The interconnection member 110 is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these. It may contain metal substances such as alloys. The interconnection member 110 may have a post shape penetrating the first encapsulant 130. For example, the interconnection member 110 may be formed by sealing a post containing a conductive material with the first semiconductor chip 120 with a first encapsulant 130. Through the planarization process, the top surface of the interconnection member 110 may be substantially coplanar with the top surface of the first encapsulant 130 and the top surface of the first semiconductor chip 120. However, the present invention is not limited to this, and for example, unlike what is shown in FIG. 9, the upper surface of the interconnection member 110 may be covered with the first encapsulant 130, and in this case, the interconnection The member 110 may be connected to the backside wiring layer 152 through a backside via 153 penetrating the first encapsulant 130.

The first semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of elements are integrated into one chip. At this time, the integrated circuit constituting the first semiconductor chip 120 may be, for example, an application processor chip with some units separated and omitted, as described above. The first semiconductor chip 120 may be a bare integrated circuit in which no separate bumps or wiring layers are formed. However, it is not limited to this, and may be a packaged type integrated circuit if necessary. Integrated circuits can be formed based on active wafers. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material forming the body of the first semiconductor chip 120. Various circuits may be formed in the body. The first connection pad 120P is used to electrically connect the first semiconductor chip 120 to other components, and metal materials such as copper (Cu) and aluminum (Al) can be used as forming materials without particular restrictions. there is. A passivation film that opens the first connection pad 120P may be formed on the body. The passivation film may be an oxide film, a nitride film, or a double layer of an oxide film and a nitride film. Additional insulating films, etc. may be disposed at other necessary positions.

The first encapsulant 130 covers at least a portion of the first semiconductor chip 120 and the interconnection member 110. The first encapsulant 130 includes an insulating material, and the insulating material includes a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin, such as a thermosetting resin such as an epoxy resin, and polyimide. Thermoplastic resins such as, or resins containing reinforcing materials such as inorganic fillers, specifically non-photosensitive insulating materials such as ABF or EMC, can be used. If necessary, a material in which an insulating resin such as a thermosetting resin or thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber may be used. Through this, voiding and undulation problems can be improved, and warpage control can also be made easier. If necessary, PIE (Photo Image-able Encapsulant) can be used.

The first connection member 140 can rewire the first and/or second connection pads 120P and 220P. A plurality of first and/or second connection pads (120P, 220P) with various functions can be rewired through the first connection member 140, respectively, and their functions can be connected through the first electrical connection metal 170. It can be physically and/or electrically connected to the outside as appropriate. The first connection member 140 penetrates the first insulating layer 141, the first redistribution layer 142 disposed on the lower surface of the first insulating layer 141, and the first insulating layer 141, and is connected to the first insulating layer 141. It includes a first connection via 143 connected to the wiring layer 142. The first insulating layer 141, the first redistribution layer 142, and the first connection via 143 may be more or less than what is shown in the drawing. In other words, the number of layers may vary depending on the design.

An insulating material may be used as the material for the first insulating layer 141. In this case, a photosensitive insulating material (PID) may be used as the insulating material. In this case, it is possible to introduce a fine pitch through a photo via, so fine pitch can be used. It is advantageous for circuit and high-density design, and the plurality of first and/or second connection pads 120P and 220P can be rewired very effectively. The boundaries of the first insulating layer 141 may be distinct from each other, or the boundaries may be unclear.

The first rewiring layer 142 may be electrically connected to the first electrical connection metal 170 by rewiring the plurality of first and/or second connection pads 120P and 220P. The forming material of the first redistribution layer 142 is also copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). Metal materials such as , or alloys thereof can be used. The first redistribution layer 142 can also perform various functions depending on the design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, the first redistribution layer 142 may include various types of via pads, electrical connection metal pads, etc. The first redistribution layer 142 may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The first connection via 143 electrically connects the first redistribution layer 142 formed in different layers. Additionally, the first connection pad 120P and the first interconnection member 110 of the first semiconductor chip 120 are electrically connected to the first redistribution layer 142. The first connection via 143 may be in physical contact with the first connection pad 120P when the first semiconductor chip 120 is a bare die. The forming materials of the first connection via 143 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium ( Metal materials such as Ti) or alloys thereof can be used. The first connection via 143 may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The first connection vias 143 may also be field-type vias each filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. Additionally, it may have a tapered shape in the opposite direction to the first wiring vias 113a and 113b. The first connection via 143 may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The backside connection member 150 can rewire the second connection pad 220P. A plurality of second connection pads 220P having various functions can each be rewired through the second backside connection member 150. The backside connection member 150 includes a backside insulating layer 151, a backside wiring layer 152 disposed on the top of the backside insulating layer 151, and a backside via that penetrates the backside insulating layer 151 and is connected to the backside wiring layer 152. Includes (153). The number of layers of the backside insulating layer 151, the backside wiring layer 152, and the backside via 153 may vary depending on the design.

The backside insulating layer 151 may include thermosetting resin. For example, the backside insulating layer 151 may be ABF. However, it is not limited to this, and like the first insulating layer 141, it may include a PID. The boundaries of the plurality of backside insulating layers 151 may be distinct from each other, or the boundaries may be unclear.

The backside wiring layer 152 is disposed on the first encapsulant 130 and provides a backside circuit to the first package structure 100A together with the backside via 153. The backside wiring layer 152 is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. It may include metal substances such as: The backside wiring layer 152 may perform various functions in the design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern includes various signals, for example, data signals, etc., excluding the ground (GND) pattern, power (PWR) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. The backside wiring layer 152 may also be formed through a known plating process and may be composed of a seed layer and a conductor layer.

The backside via 153 penetrates the first encapsulant 130 and/or the backside insulating layer 151. The backside via 153 electrically connects the backside wiring layer 152 to the first to third wiring layers 112c. Additionally, the backside via 153 electrically connects the backside wiring layers 152 arranged at different levels. The backside via 153 is also made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. It may include metal substances such as: The backside via 153 may also be a field-type via filled with a metal material, or it may be a conformal-type via in which a metal material is formed along the wall of the via hole. Additionally, it may have a tapered shape in the same direction as the first wiring vias 113a and 113b. The backside via 153 may also include a signal via, a ground via, a power via, etc., and the power via and the ground via may be the same via. The backside via 153 may also be formed through a known plating process and may be composed of a seed layer and a conductor layer.

The first passivation layer 160 is an additional component to protect the first connection member 140 from external physical and chemical damage. The first passivation layer 160 may include a thermosetting resin. For example, the first passivation layer 160 may be ABF, but is not limited thereto. The first passivation layer 160 may have an opening that opens at least a portion of the lowermost first redistribution layer 142. There may be tens to millions of openings, and the number may be more or less. Each opening may be composed of a plurality of holes. If necessary, surface-mounted components such as capacitors may be disposed on the lower surface of the first passivation layer 160 to be electrically connected to the first redistribution layer 142 and, as a result, may be electrically connected to the first semiconductor chip 120. You can.

The first electrical connection metal 170 is also an additional component and is configured to physically and/or electrically connect the semiconductor package 500A according to one example to the outside. For example, the semiconductor package 500A according to one example may be mounted on the main board of an electronic device through the first electrical connection metal 170. The first electrical connection metal 170 may be disposed on each opening of the first passivation layer 160. The first electrical connection metal 170 may be made of a low melting point metal, for example, tin (Sn) or an alloy containing tin (Sn). For example, the first electrical connection metal 170 may be formed of solder, etc., but this is only an example and the material is not particularly limited thereto.

The first electrical connection metal 170 may be a land, ball, pin, etc. The first electrical connection metal 170 may be formed as a multi-layer or a single layer. When formed in multiple layers, it may include copper pillars and solder, and when formed as a single layer, it may include tin-silver solder or copper, but this is only an example and is not limited thereto. . The number, spacing, arrangement form, etc. of the first electrical connection metal 170 are not particularly limited, and can be sufficiently modified according to design details by a person skilled in the art. For example, the number of first electrical connection metals 170 may be tens to millions, and may be more or less, depending on the number of first and/or second connection pads 120P and 220P.

At least one of the first electrical connection metals 170 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the first and second semiconductor chips 120 and 220 are disposed. Fan-out packages have superior reliability compared to fan-in packages, enable the implementation of multiple I/O terminals, and facilitate 3D interconnection. In addition, compared to BGA (Ball Grid Array) packages and LGA (Land Grid Array) packages, the package thickness can be manufactured thinner and its price competitiveness is excellent.

The first electrical connection metal 170 may be connected to the lowermost first redistribution layer 142 through an underbump metal as needed. In this case, the connection reliability of the first electrical connection metal 170 is improved, and the connection reliability of the first electrical connection metal 170 is improved. As a result, the board level reliability of the first semiconductor package 100A can be improved. The underbump metal can be formed using metal using a known metallization method, but is not limited to this.

The cover layer 180 is an additional component to protect the backside connection member 150 from external physical or chemical damage. The cover layer 180 may include a thermosetting resin. For example, the cover layer 180 may be ABF, but is not limited thereto. The cover layer 180 may have an opening that opens at least a portion of the uppermost backside wiring layer 152. There may be tens to millions of openings, and the number may be more or less. Each opening may be composed of a plurality of holes.

Next, the second semiconductor chip 220 is placed on the first package structure 100A (first connection member 140 or backside connection member 150). For example, the second semiconductor chip 220 may be surface mounted on the backside connection member 150 of the first package structure 100A using a connection bump 220B. The second semiconductor chip 220 may be fixed on the first package structure 100A through the underfill resin 225.

The second semiconductor chip 220 may also be an integrated circuit (IC) in which hundreds to millions of elements are integrated into one chip. At this time, the integrated circuit constituting the second semiconductor chip 220 may be, for example, an application processor chip with some units separated and omitted, as described above. The second semiconductor chip 220 may be a bare integrated circuit in which no separate bumps or wiring layers are formed. However, it is not limited to this, and may be a packaged type integrated circuit if necessary. Integrated circuits can be formed based on active wafers. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material forming the body of the second semiconductor chip 220. Various circuits may be formed in the body. The second connection pad 220P is used to electrically connect the second semiconductor chip 220 to other components, and metal materials such as copper (Cu) and aluminum (Al) can be used as forming materials without particular restrictions. there is. A passivation film that opens the second connection pad 220P may be formed on the body, and the passivation film may be an oxide film or a nitride film, or a double layer of an oxide film and a nitride film. Additional insulating films, etc. may be disposed at other necessary positions.

The connection bump 220B can surface mount the second semiconductor chip 220 on the first package structure 100A, for example, on the cover layer 180. The connection bumps 220B may each be connected to the uppermost backside wiring layer 152 exposed through the opening of the cover layer 180. The connection bump 220B may be made of a low melting point metal, for example, tin (Sn) or an alloy containing tin (Sn). For example, the connection bump 220B may be a solder bump formed of solder paste, etc., but is not limited thereto.

The underfill resin 225 may fix the second semiconductor chip 220 by filling the space between the second semiconductor chip 220 and the cover layer 190. The underfill resin 225 may cover at least a portion of each connection bump 220B. The underfill resin 225 may cover at least a portion of the side surface of the second semiconductor chip 220 . The underfill resin 225 may include epoxy, but its material is not necessarily limited thereto.

Next, the third package structure 300A is disposed on the first package structure 100A with the second semiconductor chip 220 interposed therebetween. The third package structure 300A may be mounted in a POP form on the first package structure 100A using the third electrical connection metal 340, etc. The third package structure 300A is disposed in a stack on the printed circuit board (or may be referred to as a “third connection member”) 310 and the printed circuit board 310 through wire bonding 320W, respectively. A plurality of third semiconductor chips 320 electrically connected to the printed circuit board 310, a molding material 330 disposed on the upper side of the printed circuit board 310 and covering the third semiconductor chip 320, and a printed circuit board. It is disposed on the lower side of 310 and includes a third electrical connection metal 340 connecting the first and third package structures 100A and 300A. Each of the plurality of third semiconductor chips 320 may be a memory chip, for example, DRAM. That is, the third package structure 300A may be a DRAM package.

Figure 10 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in another example of a semiconductor package 500B, the interconnection member 110 may be a first frame 110 having a first penetration portion 110H on which the first semiconductor chip 120 is disposed. . For example, the first package structure 110B includes a first frame 110 that has a first through portion 110H and includes one or more first wiring layers 112a, 112b, and 112c, and the first through portion 110H. is disposed in and covers at least a portion of each of the first semiconductor chip 120, the first frame 110, and the first semiconductor chip 120 having a plurality of first connection pads 120P, and a first penetrating portion 110H. A first connection member ( 140), and a backside connection member 150 disposed above the first encapsulant 130 and including one or more backside wiring layers 152. If necessary, a first passivation layer 160 and a first electrical connection metal 170 may be further disposed on the lower side of the first connection member 140. Additionally, a cover layer 180 may be further disposed on the backside connection member 150. The interconnection member 110 of FIG. 9 may be a frame 110 including an insulating layer, a wiring layer on the insulating layer, and a wiring via that penetrates the insulating layer and is connected to the wiring layer.

The first frame 110 can further improve the rigidity of the first package structure 100A depending on the specific material of the first insulating layer 111a and 111b, and ensure thickness uniformity of the first encapsulant 130, etc. can perform the role of The first frame 110 may have a first penetration portion 110H that penetrates the first insulating layers 111a and 111b. The first semiconductor chip 120 is disposed in the first penetration portion 110H, and if necessary, passive components may be disposed together. The first penetrating portion 110H may have a wall that surrounds the first semiconductor chip 120, but is not limited thereto. The first frame 110 includes first wiring layers (112a, 112b, 112c) and first wiring vias (113a, 113b) in addition to the first insulating layers (111a, 111b), and thus provides an electrical connection path between the upper and lower sides. It can function as a connecting member. If necessary, an electrical connection member capable of providing another type of upper and lower electrical connection path, such as a metal post, may be introduced into the first frame 110.

In one example, the first frame 110 is in contact with the 1-1 insulating layer 111a and the first connection member 140, and the 1-1 wiring layer 112a is embedded in the 1-1 insulating layer 111a. , the 1-2 wiring layer 112b disposed on the opposite side of the 1-1 insulating layer 111a from the side where the 1-1 wiring layer 112a is buried, the first wiring layer 112b of the 1-1 insulating layer 111a. - a 1-2 insulating layer 111b disposed on the opposite side of the side where the 1st wiring layer 112a is buried and covering at least a portion of the 1-2 wiring layer 112b, and a 1-2 insulating layer 111b ) includes a 1-3 wiring layer 112c disposed on the opposite side of the side where the 1-2 wiring layer 112b is buried. The 1-1 and 1-2 wiring layers (112a, 112b) and the 1-2 and 1-3 wiring layers (112b, 112c) have 1-1 and 1-2 insulating layers (111a, 111b), respectively. They are electrically connected through the 1-1 and 1-2 wiring vias 113a and 113b. The 1-1st to 1-3rd wiring layers 112a, 112b, and 112c may be electrically connected to a plurality of first and/or second connection pads 120P and 220P.

The material of the first insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used, in which case the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build-ABF). up Film), etc. may be used. Alternatively, a material in which the core material such as glass fiber (glass fiber, glass cloth, glass fabric) is impregnated with the above-described resin along with an inorganic filler, for example, prepreg, etc. may be used.

The first wiring layers (112a, 112b, 112c) together with the first wiring vias (113a, 113b) may provide an electrical connection path for the top and bottom of the package, and the first and/or second connection pads (120P, 220P) It can play a role in rewiring. Materials forming the first wiring layers 112a, 112b, and 112c include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), Metal materials such as titanium (Ti) or alloys thereof can be used. The first wiring layers 112a, 112b, and 112c can perform various functions depending on the design of the corresponding layer. For example, it may include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern includes various signals, for example, data signals, etc., excluding the ground (GND) pattern, power (PWR) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, the first wiring layers 112a, 112b, and 112c may each include various types of via pads. The first wiring layers 112a, 112b, and 112c may be formed through a known plating process and may include a seed layer and a plating layer, respectively.

The thickness of each of the first wiring layers 112a, 112b, and 112c may be thicker than the thickness of each of the first redistribution layers 142. Specifically, the first frame 110 may have a thickness equal to or greater than that of the first semiconductor chip 120, and in order to maintain rigidity, the material of the first insulating layers 111a and 111b is selected such as prepreg, and is formed accordingly. The thickness of the first wiring layers 112a, 112b, and 112c may also be relatively thick. On the other hand, the first connection member 140 requires a fine circuit and high-density design, and therefore the material of the first insulating layer 141 is selected as a photosensitive insulating material (PID), and the first rewiring layer ( 142) may also be relatively thin.

The 1-1 wiring layer 112a may be recessed into the interior of the 1-1 insulating layer 111a. In this way, the 1-1 wiring layer 112a is recessed into the 1-1 insulating layer 111a, and the lower surface in contact with the first connection member 140 of the 1-1 insulating layer 111a and the 1-1 When the lower surface of the first wiring layer 112a in contact with the first connection member 140 has a step, it is formed when encapsulating the first semiconductor chip 120 and the first frame 110 with the first encapsulant 130. It is possible to prevent material from bleeding and contaminating the lower surface of the 1-1 wiring layer 112a.

The first wiring vias 113a and 113b electrically connect the first wiring layers 112a, 112b, and 112c formed in different layers, and as a result, form an electrical path within the first frame 110. The forming materials of the first wiring vias 113a and 113b include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium. Metal materials such as (Ti) or alloys thereof can be used. The first wiring vias 113a and 113b may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The first wiring vias 113a and 113b may be field-type vias filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. Additionally, each may have a tapered shape. The first wiring vias 113a and 113b may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

When forming a hole for the 1-1 wiring via 113a, some pads of the 1-1 wiring layer 112a may serve as a stopper, and the 1-1 wiring via 113a is It may be advantageous in the process to have a tapered shape where the width of the upper surface is larger than the width of the lower surface. In this case, the 1-1 wiring via 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, when forming a hole for the 1-2 wiring via 113b, some pads of the 1-2 wiring layer 112b may serve as a stopper, and the 1-2 wiring via 113b is formed on the upper surface. It may be advantageous in the process to have a tapered shape where the width of the surface is larger than the width of the lower surface. In this case, the 1-2 wiring via 113b may be integrated with the pad pattern of the 1-3 wiring layer 112c.

Meanwhile, if necessary, a metal layer may be disposed on the inner wall of the first penetration portion 110H of the first frame 110 for the purpose of electromagnetic wave shielding or heat dissipation, and the metal layer may be formed on the first semiconductor chip 120. can surround.

The first encapsulant 130 covers at least a portion of the first semiconductor chip 120 and the first frame 110, and fills at least a portion of the first penetration portion 110H. The first encapsulant 130 includes an insulating material, and the insulating material includes a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin, such as a thermosetting resin such as an epoxy resin, and polyimide. Thermoplastic resins such as, or resins containing reinforcing materials such as inorganic fillers, specifically non-photosensitive insulating materials such as ABF or EMC, can be used. If necessary, a material in which an insulating resin such as a thermosetting resin or thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber may be used. Through this, voiding and undulation problems can be improved, and warpage control can also be made easier. If necessary, PIE (Photo Image-able Encapsulant) can be used.

Meanwhile, in FIG. 10, the 1st-3rd wiring layer 112c of the first frame 110 is covered with the first encapsulant 130, and the backside via 153 penetrates the first encapsulant 130 to form the first encapsulant 130. The first to third wiring layers 112c are connected to the backside wiring layer 152. However, the present invention is not limited to this. For example, the top surface of the 1-3 wiring layer 112c is in direct contact with the backside insulating layer 151, and the backside via 153 is in direct contact with the 1-3 wiring layer. The first to third wiring layers 112c may be connected to the backside wiring layer 152 by penetrating the backside insulating layer 151, which is in direct contact with the upper surface of 112c.

Other contents are substantially the same as those described in the semiconductor package 500A according to the above-described example, and detailed descriptions will be omitted.

Figure 11 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawing, in another example, the semiconductor package 500C has the first package structure 100C flipped upside down compared to the above-described first package structure 100A so that the first semiconductor chip 120 is arranged in a face-up shape. has the form For example, the second semiconductor chip 220 may be surface mounted on the first connection member 140 of the first package structure 100C using a connection bump 220B. The second semiconductor chip 220 may be fixed on the first package structure 100C through the underfill resin 225. In this case, the electrical connection path between the first and second semiconductor chips 120 and 220 may be shorter. The second semiconductor chip 220 is disposed on the first passivation layer 160, and the third package structure 300C is disposed on the first passivation layer 160 with the second semiconductor chip 220 interposed therebetween. . The electrical connection path of power and signals is, for example, as shown in the drawing.

Other contents are substantially the same as those described in the semiconductor package 500A according to the above-described example, and detailed descriptions will be omitted.

Figure 12 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in a semiconductor package 500D according to another example, a second package structure 200D is disposed between the first and third package structures 100D and 300D. The first and second package structures (100D, 200D) are connected in a POP form through the second electrical connection metal (270). The second and third package structures (200D, 300D) are connected in a POP form through the third electrical connection metal 340. The second package structure (200D) is connected to the first connection member 140 or the backside connection member ( 150) and a second connection member 240 having a second redistribution layer 242 connected to the first redistribution layer 142 or the backside wiring layer 152, and the second redistribution layer 242 A second semiconductor chip 220 having a plurality of second connection pads 220P connected to, and a second encapsulant 230 disposed on the second connection member 240 and covering the second semiconductor chip 220. ) may include. In addition, it may further include a second interconnection member 210 disposed on the second connection member 240 and electrically connected to the second redistribution layer 242. The second interconnection member 210 may electrically connect the second redistribution layer 242 and the third electrical connection metal 340. For example, the second connection member 240 may be mounted on the backside connection member 150 through the second electrical connection metal 270.

The second encapsulant 230 covers at least a portion of the second semiconductor chip 220 and the second interconnection member 210. The second encapsulant 230 includes an insulating material, and the insulating material includes a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin, such as a thermosetting resin such as an epoxy resin, and polyimide. Thermoplastic resins such as, or resins containing reinforcing materials such as inorganic fillers, specifically non-photosensitive insulating materials such as ABF or EMC, can be used. If necessary, a material in which an insulating resin such as a thermosetting resin or thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber may be used. Through this, voiding and undulation problems can be improved, and warpage control can also be made easier. If necessary, PIE can also be used.

The second connection member 240 can rewire the second connection pad 220P. Through the second connection member 240, a plurality of second connection pads 220P with various functions can each be rewired, and through the second electrical connection metal 270, they can be physically and/or externally connected according to their functions. Can be electrically connected. The second connection member 240 penetrates the second insulating layer 241, the second rewiring layer 242 disposed on the lower surface of the second insulating layer 241, and the second insulating layer 241, and is connected to the second insulating layer 241. It includes a second connection via 243 connected to the wiring layer 242. The second insulating layer 241, the second redistribution layer 242, and the second connection via 243 may be more or less than what is shown in the drawing. In other words, the number of layers may vary depending on the design.

An insulating material may be used as the material for the second insulating layer 241. In this case, a photosensitive insulating material (PID) may be used as the insulating material. In this case, it is possible to introduce a fine pitch through a photo via, so fine pitch can be used. It is advantageous for circuit and high-density design, and the plurality of second connection pads 220P can be rewired very effectively. The boundaries of the second insulating layer 241 may be distinct from each other, or the boundaries may be unclear.

The second rewiring layer 242 can be electrically connected to the second electrical connection metal 270 by rewiring the plurality of second connection pads 220P. The forming material of the second redistribution layer 242 is also copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). Metal materials such as , or alloys thereof can be used. The second redistribution layer 242 can also perform various functions depending on the design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, the second redistribution layer 242 may include various types of via pads, electrical connection metal pads, etc. The second redistribution layer 242 may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The second connection via 243 electrically connects the second redistribution layer 242 formed in different layers. Additionally, the second connection pad 220P and the second interconnection member 210 of the second semiconductor chip 220 are electrically connected to the second redistribution layer 242. The second connection via 243 may be in physical contact with the second connection pad 220P when the second semiconductor chip 220 is a bare die. The forming materials of the second connection via 243 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium ( Metal materials such as Ti) or alloys thereof can be used. The second connection via 243 may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The second connection vias 243 may also be field-type vias each filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. Additionally, it may have a tapered shape in the opposite direction to the second wiring vias 213a and 213b. The second connection via 243 may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The second passivation layer 260 is an additional component to protect the second connection member 240 from external physical and chemical damage. The second passivation layer 260 may include a thermosetting resin. For example, the second passivation layer 260 may be ABF, but is not limited thereto. The second passivation layer 260 may have an opening that opens at least a portion of the lowermost second redistribution layer 242. There may be tens to millions of openings, and the number may be more or less. Each opening may be composed of a plurality of holes. If necessary, surface-mounted components such as capacitors may be placed on the lower surface of the second passivation layer 250 to be electrically connected to the second redistribution layer 242 and, as a result, to be electrically connected to the second semiconductor chip 220. You can.

The second electrical connection metal 270 is configured to physically and/or electrically connect the first and second package structures 100D and 200D. The second electrical connection metal 270 may be disposed on each opening of the second passivation layer 250. Each of the second electrical connection metals 270 may be made of a low melting point metal, for example, tin (Sn) or an alloy containing tin (Sn). For example, the second electrical connection metal 270 may be formed of solder, etc., but this is only an example and the material is not particularly limited thereto.

The second electrical connection metal 270 may be a land, ball, pin, etc. The second electrical connection metal 270 may be formed as a multi-layer or a single layer. When formed in multiple layers, it may include copper pillars and solder, and when formed as a single layer, it may include tin-silver solder or copper, but this is only an example and is not limited thereto. . The number, spacing, arrangement form, etc. of the second electrical connection metal 270 are not particularly limited, and can be sufficiently modified according to design details by a person skilled in the art. For example, the number of second electrical connection metals 270 may be tens to millions depending on the number of second connection pads 220P, and may be more or less.

At least one of the second electrical connection metals 270 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the second semiconductor chip 220 is placed. Fan-out packages have superior reliability compared to fan-in packages, enable the implementation of multiple I/O terminals, and facilitate 3D interconnection. In addition, compared to BGA (Ball Grid Array) packages and LGA (Land Grid Array) packages, the package thickness can be manufactured thinner and its price competitiveness is excellent.

The second electrical connection metal 270 may be connected to the lowermost second redistribution layer 242 through an underbump metal as needed. In this case, the connection reliability of the second electrical connection metal 270 is improved, and the connection reliability of the second electrical connection metal 270 is improved. As a result, the board level reliability of the second semiconductor package 200D can be improved. The underbump metal can be formed using metal using a known metallization method, but is not limited to this.

Other contents are substantially the same as those described in the semiconductor package 500A according to the above-described example, and detailed descriptions will be omitted.

Figure 13 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in the semiconductor package 500E according to another example, the second interconnection member 210 is a second frame 210 having a second penetration portion 210H on which the second semiconductor chip 220 is disposed. You can. For example, a second frame 210 having a second penetrating portion 210H and including one or more second wiring layers 212a, 212b, and 212c, is disposed on the second penetrating portion 210H and includes a plurality of second connections. A second seal covering at least a portion of each of the second semiconductor chip 220, the second frame 210, and the second semiconductor chip 220 having the pad 220P, and filling at least a portion of the second penetration portion 210H. It may include material 230 and a second connection member 240 disposed below each of the second frame 210 and the second semiconductor chip 220 and including one or more second redistribution layers 242. . If necessary, a second passivation layer 260 and a second electrical connection metal 270 may be further disposed on the lower side of the second connection member 240. In this case, because the second frame 210, which will be described later, can compensate for the height of the third electrical connection metal 340, the third electrical connection metal 340 between the second and third package structures 200E and 300E ) can reduce the pitch. Accordingly, the number of input/output (I/O) of the third package structure 300C, for example, the number of input/output (I/O) of memory can be increased. The electrical connection path of power and signals is, for example, as shown in the drawing.

The second package structure 200E is disposed on the second frame 210, which has a second penetrating portion 210H and includes one or more second wiring layers 212a, 212b, and 212c, and the second penetrating portion 210H, and includes a plurality of second penetrating portions 210H. It covers at least a portion of each of the second semiconductor chip 220, the second frame 210, and the second semiconductor chip 220 having the second connection pad 220P, and covers at least a portion of the second penetration portion 210H. A second sealing material 230 to be filled, and a second connection member 240 disposed below each of the second frame 210 and the second semiconductor chip 220 and including one or more second redistribution layers 242. Includes. If necessary, a second passivation layer 260 and a second electrical connection metal 270 may be further disposed on the lower side of the second connection member 240.

The second frame 210 can further improve the rigidity of the second package structure 200E depending on the specific material of the second insulating layer 211a and 211b, and ensure thickness uniformity of the second encapsulant 230, etc. can perform the role of The second frame 210 may have a second penetrating portion 210H that penetrates the second insulating layers 211a and 211b. A second semiconductor chip 220 is disposed in the second penetrating portion 210H, and passive components may be disposed together as needed. The second penetrating portion 210H may have a wall surrounding the second semiconductor chip 220, but is not limited thereto. The second frame 210 includes second wiring layers (212a, 212b, 212c) and second wiring vias (213a, 213b) in addition to the second insulating layers (211a, 211b), and thus provides an electrical connection path for upper and lower electrical connections. It can function as a connecting member. If necessary, an electrical connection member capable of providing another type of upper and lower electrical connection path, such as a metal post, may be introduced into the second frame 210.

In one example, the second frame 210 is in contact with the 2-1 insulating layer 211a and the second connection member 240, and the 2-1 wiring layer 212a is embedded in the 2-1 insulating layer 211a. , a 2-2 wiring layer 212b disposed on the opposite side of the 2-1 insulating layer 211a from the side where the 2-1 wiring layer 212a is buried, and a second wiring layer 212b of the 2-1 insulating layer 211a. - a 2-2 insulating layer 211b disposed on the opposite side of the side where the 1st wiring layer 212a is buried and covering at least a part of the 2-2 wiring layer 212b, and a 2-2 insulating layer 211b ) includes a 2-3 wiring layer 212c disposed on the opposite side of the side where the 2-2 wiring layer 212b is buried. The 2-1 and 2-2 wiring layers (212a, 212b) and the 2-2 and 2-3 wiring layers (212b, 212c) include the 2-1 and 2-2 insulating layers (211a, 211b), respectively. They are electrically connected through 2-1 and 2-2 wiring vias 213a and 213b. The 2-1st to 2-3rd wiring layers 212a, 212b, and 212c may be electrically connected to a plurality of second connection pads 220P.

The material of the second insulating layers 211a and 211b is not particularly limited. For example, an insulating material may be used, and in this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, such as ABF. there is. Alternatively, a material in which the above-described resin is impregnated with a core material such as glass fiber along with an inorganic filler, for example, prepreg, etc. may be used.

The second wiring layers (212a, 212b, 212c) together with the second wiring vias (213a, 213b) can provide an electrical connection path for the top and bottom of the package and serve to rewire the second connection pad (220P). can do. Materials forming the second wiring layers 212a, 212b, and 212c include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), Metal materials such as titanium (Ti) or alloys thereof can be used. The second wiring layers 212a, 212b, and 212c can perform various functions depending on the design of the corresponding layer. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern includes various signals, for example, data signals, etc., excluding the ground (GND) pattern, power (PWR) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, the second wiring layers 212a, 212b, and 212c may each include various types of via pads. The second wiring layers 212a, 212b, and 212c may be formed using a known plating process and may include a seed layer and a plating layer, respectively.

The thickness of each of the second wiring layers 212a, 212b, and 212c may be thicker than the thickness of each of the second redistribution layers 242. Specifically, the second frame 210 may have a thickness greater than that of the second semiconductor chip 220, and to maintain rigidity, the material of the second insulating layers 211a and 211b is selected from prepreg, etc., and is formed accordingly. The thickness of the second wiring layers 212a, 212b, and 212c may also be relatively thick. On the other hand, the second connection member 240 requires a fine circuit and high-density design, and therefore the material of the second insulating layer 241 is selected as a photosensitive insulating material (PID), and the second rewiring layer ( 242) may also be relatively thin.

The 2-1 wiring layer 212a may be recessed into the interior of the 2-1 insulating layer 211a. In this way, the 2-1 wiring layer 212a is recessed into the 2-1 insulating layer 211a, and the lower surface in contact with the second connection member 240 of the 2-1 insulating layer 211a and the 2- When the lower surface of the first wiring layer 212a in contact with the second connection member 240 has a step, it is formed when encapsulating the second semiconductor chip 220 and the second frame 210 with the second encapsulant 230. It is possible to prevent material from bleeding and contaminating the lower surface of the 2-1 wiring layer 212a.

The second wiring vias 213a and 213b electrically connect the second wiring layers 212a, 212b, and 212c formed in different layers, and as a result, form an electrical path within the second frame 210. Forming materials for the second wiring vias 213a and 213b include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium. Metal materials such as (Ti) or alloys thereof can be used. The second wiring vias 213a and 213b may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The second wiring vias 213a and 213b may be field-type vias filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. Additionally, each may have a tapered shape. The second wiring vias 213a and 213b may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

When forming a hole for the 2-1 wiring via 213a, some pads of the 2-1 wiring layer 212a can serve as a stopper, and the 2-1 wiring via 213a has a width of the upper surface. It may be advantageous in the process to have a tapered shape larger than the width of the lower surface. In this case, the 2-1 wiring via 213a may be integrated with the pad pattern of the second wiring layer 212b. In addition, when forming a hole for the 2-2 wiring via 213b, some pads of the 2-2 wiring layer 212b can serve as a stopper, and the 2-2 wiring via 213b is formed on the upper surface. It may be advantageous in the process to have a tapered shape where the width of the surface is larger than the width of the lower surface. In this case, the 2-2 wiring via 213b may be integrated with the pad pattern of the 2-3 wiring layer 212c.

Meanwhile, if necessary, a metal layer may be disposed on the inner wall of the second penetration portion 210H of the second frame 210 for the purpose of electromagnetic wave shielding or heat dissipation, and the metal layer may be formed on the second semiconductor chip 220. can surround.

The second encapsulant 230 covers at least a portion of the second semiconductor chip 220 and the second frame 210, and fills at least a portion of the second penetration portion 210H. The second encapsulant 230 includes an insulating material, and the insulating material includes a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin, such as a thermosetting resin such as an epoxy resin, and polyimide. Thermoplastic resins such as, or resins containing reinforcing materials such as inorganic fillers, specifically non-photosensitive insulating materials such as ABF or EMC, can be used. If necessary, a material in which an insulating resin such as a thermosetting resin or thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber may be used. Through this, voiding and undulation problems can be improved, and warpage control can also be made easier. If necessary, PIE can also be used.

Figure 14 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawing, in a semiconductor package 500F according to another example, the first package structure 100F is vertically inverted compared to the above-described first package structure 100A so that the first semiconductor chip 120 is arranged in a face-up shape. has the form For example, the second semiconductor chip 220 may be surface mounted on the first connection member 140 of the first package structure 100F using a connection bump 220B. The second semiconductor chip 220 may be fixed on the first package structure 100F through the underfill resin 225. Additionally, the second package structure 200F is disposed between the first and third package structures 100F and 300F. The first and second package structures (100F, 200F) are connected in a POP form through the second electrical connection metal (270). The second and third package structures (200F, 300F) are connected in a POP form through the third electrical connection metal 340. The electrical connection path of power and signals is, for example, as shown in the drawing.

The second package structure 200F is disposed on the second frame 210, which has a second penetrating portion 210H and includes one or more second wiring layers 212a, 212b, and 212c, and the second penetrating portion 210H, and includes a plurality of second penetrating portions 210H. It covers at least a portion of each of the second semiconductor chip 220, the second frame 210, and the second semiconductor chip 220 having the second connection pad 220P, and covers at least a portion of the second penetration portion 210H. A second sealing material 230 to be filled, and a second connection member 240 disposed below each of the second frame 210 and the second semiconductor chip 220 and including one or more second redistribution layers 242. Includes. If necessary, a second passivation layer 260 and a second electrical connection metal 270 may be further disposed on the lower side of the second connection member 240.

Other contents are substantially the same as those described in the semiconductor package 500A according to the above-described example and the semiconductor packages 500B and 500C according to the other example above, and detailed descriptions will be omitted.

In the present disclosure, lower, lower, bottom, etc. are used for convenience to mean a downward direction based on the cross section of the drawing, and upper, upper, upper, etc. are used to mean the opposite direction. However, this direction is defined for convenience of explanation, and the scope of the patent claims is not particularly limited by the description of this direction, and the concept of top/bottom can change at any time.

In the present disclosure, the meaning of connected is a concept that includes not only directly connected, but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both cases where it is physically connected and cases where it is not connected. Additionally, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and/or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of rights.

The expression 'example' used in the present disclosure does not mean identical embodiments, but is provided to emphasize and explain different unique features. However, the examples presented above do not exclude being implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, it can be understood as an explanation related to the other example, as long as there is no explanation contrary to or contradictory to the matter in the other example.

The terminology used in this disclosure is used to describe examples only and is not intended to limit the disclosure. At this time, singular expressions include plural expressions, unless the context clearly indicates otherwise.

500A, 500B, 500C, 500D: Semiconductor package
100A, 100B, 100C, 100D: first package structure
110: Interconnection member, frame 110H: First penetration portion
112a, 112b, 112c: first wiring layer 120: first semiconductor chip
120V: Through via 120P: 1st connection pad
130: first suture material 140: first connecting member
142: First redistribution layer 150: Backside connection member
152: backside wiring layer
200C, 200D: 2nd package structure
210: 2nd frame 210H: 2nd penetration part
212a, 212b, 212c: second wiring layer 220: second semiconductor chip
230: second suture material 240: second connecting member
300A, 300B, 300C, 300D: Third package structure
310: printed circuit board 320: third semiconductor chip
320W: Wire bonding 330: Molding material
340: Third electrical connection metal

Claims (20)

A base connection member having a redistribution layer, a first semiconductor chip having a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering the first semiconductor chip, and the encapsulant. a package structure including a backside connection member disposed on the backside wiring layer and having a backside wiring layer electrically connected to the redistribution layer; and
A second semiconductor chip disposed on the base connection member or the backside connection member and having a plurality of second connection pads connected to the redistribution layer or the backside wiring layer,
The second semiconductor chip includes a logic unit, the first semiconductor chip includes a logic input/output unit for the logic unit, and the logic input/output unit is connected to the logic unit through at least one of the redistribution layer and the backside wiring layer. A semiconductor package connected to.
According to paragraph 1,
The package structure is disposed between the base connection member and the backside connection member, and further includes an interconnection member electrically connecting the redistribution layer and the backside wiring layer.
According to paragraph 1,
The plurality of second connection pads are divided into at least first and second groups of second connection pads, and the second connection pads of the first group are connected to the logic unit,
A semiconductor package wherein the plurality of first connection pads include input/output pads connected to the logic input/output unit.
According to paragraph 1,
The logic unit is a semiconductor package including a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor unit (DSPU), and an image signal processing unit (ISPU).
According to paragraph 1,
The first semiconductor chip further includes a through via penetrating the interior,
The through via connects the redistribution layer and the backside wiring layer.
According to clause 5,
The second semiconductor chip is arranged to vertically overlap the first semiconductor chip,
A semiconductor package wherein at least some of the plurality of second connection pads are electrically connected to one of the backside wiring layer and the redistribution layer through the through via.
According to clause 5,
A semiconductor package disposed inside the first semiconductor chip and further comprising an electronic component electrically connected to the through via.
According to paragraph 1,
A third connecting member disposed on the upper side of the second semiconductor chip, a third semiconductor chip disposed on the third connecting member, a molding material disposed on the third connecting member and covering the third semiconductor chip, and A semiconductor package further comprising a third package structure including a third electrical connection metal connecting a third connection member and one of the base connection member and the backside connection member.
According to clause 8,
The third semiconductor chip includes a memory unit,
The second semiconductor chip further includes a memory input/output unit for the memory unit,
The plurality of second connection pads are divided into at least first and second groups of second connection pads, the second connection pad of the first group is connected to the logic unit, and the second connection pad of the second group is connected to the logic unit. is connected to the memory input/output unit,
A semiconductor package wherein the plurality of first connection pads include input/output pads connected to the logic input/output unit.
According to paragraph 1,
A semiconductor package disposed between the package structure and the second semiconductor chip, further comprising a plurality of connection bumps connecting the plurality of second connection pads to one of the redistribution layer and the backside wiring layer.
a first connection member having a first rewiring layer, a first semiconductor chip having a plurality of first connection pads connected to the first rewiring layer, and a first semiconductor chip disposed on the first connection member and covering the first semiconductor chip. A first package structure including a first encapsulant and a backside connection member disposed on the first encapsulant and having a backside wiring layer electrically connected to the first redistribution layer; and
A second connecting member disposed on the first connecting member or the backside connecting member and having a second rewiring layer connected to the first rewiring layer or the backside wiring layer, and a plurality of second connections connected to the second rewiring layer. A second package structure comprising a second semiconductor chip having a pad and a second encapsulant disposed on the second connection member and covering the second semiconductor chip,
The second semiconductor chip includes a logic unit, the first semiconductor chip includes a logic input/output unit for the logic unit, and the logic input/output unit includes the first rewiring layer, the backside wiring layer, and the second redistribution layer. A semiconductor package connected to the logic unit through at least one of.
According to clause 11,
The first package structure is disposed between the first connection member and the backside connection member and includes a first interconnection member electrically connecting the first redistribution layer and the backside wiring layer,
The second package structure is disposed on the second connection member and includes a second interconnection member electrically connected to the second redistribution layer.
According to clause 11,
The first semiconductor chip further includes a through via therein,
The through via connects the first redistribution layer and the backside wiring layer.
According to clause 13,
The second semiconductor chip is arranged to vertically overlap the first semiconductor chip,
A semiconductor package wherein at least some of the plurality of second connection pads are electrically connected to one of the backside wiring layer and the first redistribution layer through the through via.
According to clause 13,
A semiconductor package disposed inside the first semiconductor chip and further comprising an electronic component electrically connected to the through via.
According to clause 11,
A semiconductor package further comprising a second electrical connection metal disposed between the first package structure and the second package structure and connecting the second redistribution layer to one of the first redistribution layer and the backside wiring layer.
According to clause 11,
A third connection member disposed on the upper side of the second package structure, a third semiconductor chip disposed on the third connection member, a molding material disposed on the third connection member and covering the third semiconductor chip, and A semiconductor package further comprising a third package structure including a third electrical connection metal that electrically connects the third connection member and the second redistribution layer.
According to clause 11,
The first package structure further includes a cover layer disposed on the backside connection member.
According to clause 11,
The first package structure is a semiconductor package further comprising a passivation layer disposed on the first connection member and a first electrical connection metal penetrating the passivation layer and connected to the first redistribution layer.
a first connection member having a first rewiring layer, a first semiconductor chip having a plurality of first connection pads connected to the first rewiring layer, and a first semiconductor chip disposed on the first connection member and covering the first semiconductor chip. A backside connecting member having a first encapsulating material and a backside wiring layer disposed on the first encapsulating material and electrically connected to the first redistribution layer, and disposed between the first connecting member and the backside connecting member and the first material a first package structure including an interconnection member electrically connecting a wiring layer and the backside wiring layer;
a second semiconductor chip disposed on the first connection member or the backside connection member and having a plurality of second connection pads connected to the first redistribution layer or the backside wiring layer; and
A third connection member disposed on the first package structure and the second semiconductor chip, a third semiconductor chip disposed on the third connection member, and a third semiconductor chip disposed on the third connection member. A third package structure including a covering molding material,
The third semiconductor chip includes a memory unit,
The second semiconductor chip includes a logic unit and a memory input/output unit for the memory unit,
The first semiconductor chip includes a logic input/output unit for the logic unit,
The logic input/output unit is connected to the logic unit through at least one of the first redistribution layer and the backside wiring layer,
The semiconductor package wherein the memory input/output unit is connected to the memory unit through at least one of the first redistribution layer and the backside wiring layer.

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