KR102595282B1 - Organic Light Emitting Diode display device - Google Patents

Abstract

The present invention exchanges sensing data and gain information between each timing controller and processes them to generate boundary bands at the boundaries of divided areas, generate luminance differences for each divided area, and generate imbalance of synchronization signals between divided areas. An OLED display device capable of preventing etc., comprising: first and second active areas divided on a screen where a plurality of pixels are arranged by crossing a plurality of data lines and a plurality of gate lines; a first driving circuit that writes pixel data to pixels in the first active area; A first device that senses the degree of deterioration of pixels in the first active area through the first driving circuit, compensates and transmits pixel data of the first active area to be displayed in the first active area, and controls the first driving circuit. timing controller; a second driving circuit that writes pixel data to pixels in the second active area; A second device that senses the degree of deterioration of pixels in the second active area through the second driving circuit, compensates and transmits pixel data of the second active area to be displayed in the second active area, and controls the second driving circuit. Equipped with a timing controller, the first and second timing controllers share the sensing data of the degree of deterioration of pixels corresponding to the boundary between the first and second active areas and perform average filtering to compensate for the pixel data of each active area. will be.

Description

OLED display device {Organic Light Emitting Diode display device}

The present invention relates to an OLED display device, and more particularly to an OLED display device and a method of driving the same for compensating for afterimages caused by deterioration of each pixel of an OLED display panel.

As the information society develops and various portable electronic devices such as mobile communication terminals and laptop computers develop, the demand for flat panel display devices applicable to them is gradually increasing.

As such flat display devices, liquid crystal displays (LCDs) using liquid crystals and OLED displays using organic light emitting diodes (OLEDs) are used.

These flat panel display devices consist of a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the above display devices, the display panel of the OLED display device has subpixels defined by the intersection of the plurality of gate lines and the plurality of data lines, and each subpixel has an anode and a cathode and an anode and a cathode between the anode and the cathode. It is provided with an OLED composed of an organic light-emitting layer and a pixel circuit that independently drives the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to the scan pulse. The driving TFT adjusts the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

The driving circuit for driving the display panel includes a gate driving circuit that sequentially supplies gate pulses (or scan pulses) to the plurality of gate lines of the display panel, and a gate driving circuit that sequentially supplies gate pulses (or scan pulses) to the plurality of data lines of the display panel. It consists of a data driving circuit that supplies a data voltage, a timing controller that supplies image data and various control signals to the gate driving circuit and the data driving circuit.

The electrical characteristics of the OLED and driving TFT of the above OLED display device change depending on temperature or deterioration. If the electrical characteristics of the OLED and/or the driving TFT vary for each pixel, the luminance between pixels for the same image data varies, making it difficult to realize a desired image.

External compensation technology is known to compensate for luminance deviation due to changes in electrical characteristics of the OLED and driving TFT.

The external compensation technology senses the electrical characteristics of the OLED or driving TFT and modulates digital video data to compensate for the luminance deviation based on the sensed value.

Meanwhile, recent technological issues in OLED display devices include realizing high resolution and large areas. In particular, technology research to realize high resolution is shifting from the currently commercialized 4K (3840*2160) resolution to 8K (7680x4320) resolution.

In order to achieve this high resolution, the panel was divided into at least two regions, and each divided region was driven using at least two timing controllers.

However, since the panel is divided into at least two areas and each divided area is driven using a separate timing controller, a border band occurs at the border of each divided area, a luminance difference occurs for each divided area, and synchronization occurs. Problems such as signal imbalance occurred.

The present invention is intended to solve the above-described conventional problems, by exchanging sensing data and gain information between each timing controller and processing this to generate a border band at the border of the divided areas and a luminance difference for each divided area. The purpose is to provide an OLED display device that can prevent the occurrence of synchronization signal imbalance between divided areas.

An OLED display device according to the present invention for achieving the above object includes first and second active areas divided on a screen where a plurality of pixels are arranged by crossing a plurality of data lines and a plurality of gate lines; a first driving circuit that writes pixel data to pixels in the first active area; A first device that senses the degree of deterioration of pixels in the first active area through the first driving circuit, compensates and transmits pixel data of the first active area to be displayed in the first active area, and controls the first driving circuit. timing controller; a second driving circuit that writes pixel data to pixels in the second active area; A second device that senses the degree of deterioration of pixels in the second active area through the second driving circuit, compensates and transmits pixel data of the second active area to be displayed in the second active area, and controls the second driving circuit. Equipped with a timing controller, the first and second timing controllers share the sensing data of the degree of deterioration of pixels corresponding to the boundary between the first and second active areas and perform average filter processing to compensate for the pixel data of each active area. It has that characteristic.

Here, the first and second timing controllers each include a communication unit for transmitting and receiving data for sensing the degree of deterioration of pixels corresponding to the boundary between the first and second active areas, and a communication unit for transmitting and receiving data sensing the degree of deterioration of pixels corresponding to the boundary between the first and second active areas. It is characterized by having an internal logic unit that performs average filter processing by sharing the sensing data of the degree of deterioration of the corresponding pixels.

Each of the first and second timing controllers shares one of the average gain value (a) of the first active area and the average gain value (b) of the second active area, or applies a maximum value, a minimum value, or a weight. It is characterized by being driven by sharing matching values.

Each of the first and second timing controllers includes a communication unit for transmitting and receiving an average gain value (a) of the first active area and an average gain value (b) of the second active area, and the first timing controller It is characterized by having an internal logic unit that calculates the average gain value ((a+b)/2)a) of the first and second active areas and transmits it to the second timing controller through the communication unit.

The first timing controller receives sensing data of the first boundary portion from the second timing controller, outputs the average filtered sensing data of the second boundary portion to the second timing controller, and sends the average gain value to the second timing controller. A communication unit that transmits and receives data, an average gain value calculation unit that calculates an average gain value when the power is turned on, and sensing data received through the first driving circuit and a first boundary portion received by the second timing controller through the communication unit. Receives data, processes an average filter, transmits sensing data of a second boundary portion among the average filter-processed sensing data to the second timing controller through the communication unit, and sets a gain value according to the average filter-processed sensing data. It is characterized by having a sensing/average filter/gain calculation unit that derives and outputs the output.

The first timing controller obtains an average gain value ((a+b)/2) of the calculated average gain value (a) and the average gain value (b) of the second timing controller and transmits the average gain value ((a+b)/2) to the calculated average gain value (a) and the average gain value (b) of the second timing controller. It is characterized by further comprising a gain merge unit provided to the second timing controller.

The first timing controller includes an overflow check unit that counts a gain value under an overflow condition among the gain values derived from the sensing/average filter/gain operation unit and activates an interrupt processing unit when the counting value exceeds a certain value; an interrupt handler that transmits an interrupt signal (Interrupt_M) when activated by the overflow check unit and receives an interrupt signal (Interrupt_S) generated from the second timing controller; the first timing controller and the second timing controller; A synchronization signal transceiver for transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) between controllers, and when all synchronization matching signals (Sync Match_S, Sync Match_M) are activated through the synchronization signal transceiving unit, a data sensing enable signal is sent to the gate and Outputs data to the data driver and the sensing/average filter/gain calculation unit, updates the gain value derived from the sensing/average filter/gain calculation unit to the memory, and receives an interrupt signal (Interrupt_M) or Interrupt_S from the interrupt handler. It is characterized in that it further includes a scheduler that disables the gain value update and data sensing.

The second timing controller transmits the sensing data of the first boundary portion to the first timing controller, receives the average filtered second boundary portion sensing data from the first timing controller, and sets the average gain value to the first timing controller. A communication unit that transmits and receives data to and from the controller, an average gain value calculation unit that calculates the average gain value when the power is turned on, and a first boundary unit that processes the sensing data received through the second driving circuit and the average filter received from the first timing controller. It is characterized by a sensing/average filter/gain operation unit that receives sensing data, processes the average filter, and derives and outputs a gain value according to the average filter-processed sensing data.

The second timing controller stores an average gain value ((a+b)/2) of the average gain value (a) of the first timing controller and the average gain value (b) of the second timing controller. It is characterized by further comprising a merge part.

The second timing controller includes an overflow check unit that counts a gain value under an overflow condition among the gain values derived from the sensing/average filter/gain operation unit and activates an interrupt processing unit when the counting value exceeds a certain value; an interrupt handler that transmits an interrupt signal (Interrupt_M) when activated by the overflow check unit and receives an interrupt signal (Interrupt_S) generated from the first timing controller; the first timing controller and the second timing controller; A synchronization signal transceiver for transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) between controllers, and when all synchronization matching signals (Sync Match_S, Sync Match_M) are activated through the synchronization signal transceiving unit, a data sensing enable signal is sent to the gate and Outputs data to the data driver and the sensing/average filter/gain calculation unit, updates the gain value derived from the sensing/average filter/gain calculation unit to the memory, and receives an interrupt signal (Interrupt_M) or Interrupt_S from the interrupt handler. It is characterized in that it further includes a scheduler that disables the gain value update and data sensing.

The sensing/average filter/gain calculation unit includes a buffer unit that receives sensing data through a first or second data driver and temporarily stores the sensing data, and the sensing data output from the buffer unit includes the sensing data of the first boundary unit or the average. It is characterized by comprising a data expansion unit that expands and outputs the sensing data of the filtered second boundary part, and an average filter unit that performs an average filtering process on the sensing data output from the data expansion unit.

The OLED display device according to the present invention having the above characteristics has the following effects.

First, since the first and second timing controllers share the sensing data at the boundary and perform average filter processing, image data is displayed at the boundary and the tee effect at the boundary can be prevented.

Second, the first timing controller and the second timing controller drive the display panel by sharing the average gain value of the first active area and the second active area, thereby preventing a luminance difference between the first active area and the second active area. Therefore, no step occurs between the first active area and the second active area.

Third, the higher the average gain value, the lower the overall luminance, thereby slowing down the acceleration of deterioration of the display panel.

Fourth, since the first and second timing controllers drive the display panel by transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M), synchronization imbalance between the first and second timing controllers can be prevented.

Fifth, when an interrupt signal is generated due to gain overflow in any one of the first and second timing controllers, each of the first and second timing controllers 111 and 112 stops updating the gain value and sensing data, so that the accurate gain Video data can be modulated with values.

1 is a block diagram schematically showing an electroluminescent display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing in detail the timing controller, data driving circuit, and inter-pixel connection structure.
Figures 3 and 4 are diagrams explaining the principle of the pixel driving characteristic sensing method
Figure 5 is a diagram explaining the principle of the pixel OLED deterioration sensing method
6 is a configuration diagram of a data driving circuit, a display panel, and a gate driving circuit according to the present invention.
Figure 7 is a configuration diagram of a timing controller of an OLED display device according to the present invention.
8 is a detailed configuration diagram of the first and second timing controllers of the OLED display device according to the present invention.
Figure 9 is a block diagram of the average filter processing unit in the sensing/average filter/gain operation unit according to the present invention.
Figure 10 is a timing diagram of synchronization matching signals (Sync Match_S, Sync Match_M) according to the present invention.
Figure 11 is a timing diagram of interrupt signals (Interrupt_S, Interrupt_M) according to the present invention.
12 is a flowchart of interrupt signal generation and operation of the first or second timing controllers 111 and 112 according to the present invention.
Figure 13 is a flowchart of the average gain value calculation operation of the first or second timing controllers 111 and 112 according to the present invention.

Each pixel of the OLED display device of the present invention includes a driving element that controls the current flowing to the OLED in each pixel. The driving element may be implemented as a transistor. It is desirable that the driving characteristics of the pixels, such as threshold voltage and mobility, are designed to be the same for all pixels, but the electrical characteristics of the driving elements are not uniform due to uneven manufacturing processes, driving environments, etc. OLED and driving elements experience more stress as the driving time increases, and there is a difference in stress depending on the data voltage. The electrical characteristics of the driving element are affected by stress. Pixels deteriorate as the operating time increases, and the level of deterioration varies between pixels, which may cause image quality deterioration to be visible on the screen. Accordingly, the organic light emitting display device compensates for the deterioration in the driving characteristics of the pixels using an internal compensation method and an external compensation method in order to make the driving characteristics uniform.

The internal compensation method automatically compensates for threshold voltage differences between driving elements inside the pixel circuit. For internal compensation, an internal compensation circuit is added to the pixel that compensates the data voltage within the pixel by the threshold voltage of the OLED and driving elements so that the current flowing through the OLED is not affected by the threshold voltage of the OLED and driving elements.

The external compensation method senses the driving characteristics of the pixels (threshold voltage, mobility, etc.) and modulates the pixel data of the input image in a compensation circuit outside the display panel based on the sensing results to determine the driving characteristics of each pixel. Compensate for change.

The external compensation method senses the voltage or current of the pixel through a sensing circuit connected to the pixels on the display panel, and converts the sensing result into digital using an analog-to-digital converter (hereinafter referred to as "ADC"). It is converted into data and transmitted to the timing controller. The timing controller modulates digital video data of the input image based on pixel sensing results to compensate for changes in pixel driving characteristics.

In the following embodiments, the pixel circuit is not shown as an example connected to a sensing circuit for external compensation, but the present invention is not limited thereto. For example, the pixel circuit of the present invention may further include an internal compensation circuit.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, the algorithm refers to a data operation processing method that modulates pixel data using a preset operation method to improve image quality, improve power consumption, improve lifespan, etc. The compensation value used or calculated in the algorithm is multiplied or added to the pixel data, and the result may vary for each timing controller depending on the image and external conditions, causing luminance deviation at the boundary. The compensation value includes gain, offset, etc. in the following embodiments.

Like reference numerals refer to like elements throughout the specification.

Each of the features of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a block diagram schematically showing an electroluminescence display device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing in detail a timing controller, a data driving circuit, and a connection structure between pixels.

1 and 2, the OLED display device of the present invention includes an OLED display panel 10 in which pixels are arranged in a matrix type, and writing pixel data of an input image to the pixels of the OLED display panel 10. A display panel driving circuit is provided for the display panel.

In the OLED display panel 10, a plurality of data lines 14 and a plurality of gate lines 16 intersect, and pixels are arranged in a matrix form. The OLED display panel 10 further includes sensing lines 16, a power wiring 17 for supplying a high-potential pixel driving power supply voltage (EVDD), and an electrode for supplying a low-potential power supply voltage (EVSS). . The reference voltage Vpre is supplied to the pixels P through the sensing lines 16.

The pixels P may include red (R), green (G), and blue (B) subpixels to implement color. Each of the pixels may further include a white (W) subpixel in addition to the RGB subpixels. Each of the subpixels may include a pixel circuit 20 as shown in FIG. 2 . Figure 2 shows an example of a pixel circuit, but the pixel circuit 20 of the present invention is not limited thereto.

Each of the subpixels receives a pixel driving power supply voltage (EVDD) and a low potential power supply voltage (EVSS) from a power circuit. The subpixel may include an OLED, a driving TFT, first and second switch TFTs, and a storage capacitor (Cst). The TFTs that make up the subpixel may be implemented as a p-type or an n-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The semiconductor layer of the TFTs may include amorphous silicon, polysilicon, or oxide.

Each of the subpixels is connected to one of the data lines 14, one of the sensing lines 15, and the first scan lines 16A and the second scan lines 16B.

The display panel driving circuit includes a data driver 12 that supplies a data signal to the data lines 14, and a gate pulse (or scan pulse) synchronized with the data signal to the gate lines (or scan lines) of the pixel array. It includes a gate driver 13 that sequentially supplies power to the gate driver 13, and a timing controller 11 that controls the data driver 12 and the gate driver 13.

The gate driver 13 sequentially supplies scan pulses for image display during the image display period under the control of the timing controller 11, and the gate line 16 connected to the pixels P of the sensing target line during the vertical blank period. Supply scan pulses for sensing.

The image display scan pulse is a first image display scan pulse (SCAN) sequentially supplied to the first gate line 16A, and a second image display scan pulse sequentially supplied to the second gate line 16B. Includes (SEN). The first scanning pulse for sensing (SCAN) is supplied to the first gate line (16A) connected to the pixels of the sensing target line, and the second gate line (16B) is supplied to the pixels of the sensing target line. It includes a second sensing scan pulse (SEN). The gate driver 13 may be formed in a non-display area of the OLED display panel 10 through the pixel array forming process.

The data driver 12 supplies a data voltage (Vdata) to the data lines 14 and a reference voltage to the sensing lines 15 under the control of the timing controller 11. In addition, the data driver 12 converts the sensing voltage received from the pixels P through the sensing lines 15 into digital data through an ADC and outputs sensing data SD. ) is transmitted to the timing controller 11. The data voltage may be divided into a data voltage for image display, a data voltage for sensing, etc., but is not limited thereto.

The data driver 12 supplies the data voltage for image display of the input image to the data lines 14 in synchronization with the scan pulse for image display, and supplies the data voltage for sensing to the data lines 14 in synchronization with the scan pulse for sensing. 14) is supplied. The data voltage for image display reflects a compensation value to compensate for changes in driving characteristics based on the results of sensing the driving characteristics of the pixel. The compensation value may include, but is not limited to, an offset value and a gain value. The data driver 12 may be integrated into a source drive integrated circuit (IC) (SIC) and connected to data lines 14. In FIG. 2, the sensing circuit includes a sensing line 15, a sensing capacitor (Cx), switch elements (SW1, SW2), an ADC, etc.

The timing controller 11 operates the data driver 12 based on timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a main clock signal (MCLK), and a data enable signal (DE). ), the gate driver 13, and timing control signals (SDC, GDC) for controlling the operation timing of the sensing circuit. The timing controller 11 provides digital data for image display to be supplied to the pixels as a compensation value during the image display period to compensate for changes in driving characteristics of the pixels based on the sensing data (SD) supplied from the data driver 12. falsify In FIG. 2, “MDATA” represents image display data modulated by the timing controller 11 and transmitted to the data driver 12.

The timing controller 11 can modulate the pixel data of the input image with a compensation value derived using various image improvement algorithms as well as an external compensation algorithm. Information related to image quality improvement from the timing controller 11 may be transmitted to another timing controller by a method described later.

In the example of Figure 2, the pixel circuit 20 includes an OLED, a driving TFT (DT), a storage capacitor (Cst), a first switch TFT (ST1), and a second switch TFT (ST2).

OLED includes an organic compound layer (HIL, HTL, EML, ETL, EIL) disposed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included, but is not limited thereto. OLED emits light due to excitons generated by holes and electrons moving to the light emitting layer (EML) when a voltage higher than its threshold voltage is applied between the anode and cathode.

The driving TFT (DT) includes a gate electrode connected to a first node (N1), a drain electrode connected to a high potential power source (EVDD), and a source electrode connected to a second node (N2). The driving TFT (DT) controls the driving current (Ioled) flowing through the OLED according to the potential difference (Vgs) between the gate and source. The driving TFT (DT) is turned on when the potential difference (Vgs) between the gate and source is greater than the threshold voltage (Vth), and the larger the potential difference (Vgs) between the gate and source, the more energy flows between the source and drain of the driving TFT (DT). Current (Ids) increases. When the source potential of the driving TFT (DT) becomes greater than the threshold voltage of the OLED, the source-drain current (Ids) of the driving TFT (DT) flows through the OLED as a driving current (Ioled). As the driving current (Ioled) increases, the amount of light emitted by the OLED increases, and through this, the desired grayscale is realized.

The storage capacitor Cst is connected between the first node N1 and the second node N2.

The first switch TFT (ST1) includes a gate electrode connected to the first gate line (16A), a drain electrode connected to the data line 14, and a source electrode connected to the first node (N1). The first switch TFT (ST1) is switched in response to the first scan pulse (SCAN), thereby applying the data voltage (Vdata) charged in the data line 14 to the first node (N1).

The gate electrode of the second switch TFT (ST2) is connected to the second gate line (16B). The drain electrode of the second switch TFT (ST2) is connected to the second node (N2), and the source electrode of the second switch TFT (ST2) is connected to the sensing line (15). The second switch TFT (ST2) switches in response to the second scan pulse (SEN), thereby electrically connecting the second node (N2) and the sensing line 15.

The data driver 12 is connected to pixels through a data line 14 and a sensing line 15. The data driver 12 includes a digital-to-analog converter (hereinafter referred to as “DAC”), an ADC, an initialization switch (SW1), and a sampling switch (SW2). A sensing capacitor (Cx) that samples and stores the source voltage of the second node (N2) is connected to the sensing line (15).

The DAC receives digital data, generates a data voltage (Vdata) required for driving, that is, a data voltage for image display and a data voltage for sensing, and outputs them to the data line 14.

The sensing capacitor Cx may be created as a separate capacitor or may be implemented as a parasitic capacitor connected to the sensing line 15. Charges from the pixel (P) are stored in the sensing capacitor (Cx).

The initialization switch (SW1) switches in response to the initialization control signal (SPRE) and outputs the reference voltage (Vpre) to the sensing line (15). The sampling switch SW2 is switched in response to the sampling control signal SSAM, thereby supplying the sensing voltage stored in the sensing capacitor Cx of the sensing line 15 to the ADC for a certain period of time. The ADC converts the sensing voltage sampled at the sensing capacitor (Cx) into digital data and transmits it to the timing controller (11).

FIG. 3 is a diagram showing a method for sensing the threshold voltage of a driving TFT, FIG. 4 is a diagram showing a method for sensing the mobility of a driving TFT, and FIG. 5 is a diagram explaining the principle of a method for sensing deterioration of an OLED.

As shown in FIG. 3, the method of sensing the threshold voltage of the driving TFT involves supplying a sensing data voltage (Vdata) to the gate of the driving TFT (DT) and using the driving TFT (DT) as a source follower method. After operation, the source voltage (Vs) of the driving TFT (DT) is input as a sensing voltage (Vsen A), and the threshold voltage (Vth) of the driving TFT (DT) is sensed based on this sensing voltage (Vsen A). . A capacitor (Cst) that stores the gate-source voltage of the driving TFT is connected between the gate and source of the driving TFT. The source voltage (Vs) is Vs = Vdata - Vth = Vsen A. The threshold voltage of the driving TFT can be known based on the level of the sensing voltage (Vsen A), and an offset value to compensate for the change in the threshold voltage of the driving TFT can be determined. An offset value is added to the data of the input image to compensate for the change in threshold voltage of the driving TFT. The method of sensing the threshold voltage of the driving TFT is that after the gate-source voltage (Vgs) of the driving TFT (DT) operating as a source follower reaches the saturation state, the threshold voltage of the driving TFT (DT) is Because it must be sensed, the time required for sensing is relatively long. When the voltage (Vgs) between the gate and source of the driving TFT (DT) is saturated, the current between the drain and source of the driving TFT (DT) is zero.

As shown in Figure 4, the method of sensing the mobility (μ) of the driving TFT is to apply a voltage higher than the threshold voltage of the driving TFT (DT) to the gate of the driving TFT (DT) (Vdata + voltage) is applied to turn on the driving TFT (DT), and the source voltage (Vs) of the driving TFT (DT) charged for a certain period of time is input as the sensing voltage (Vsen B). The mobility of the driving TFT is determined according to the size of the sensing voltage (Vsen B), and a gain value for data compensation is obtained through this. The mobility (μ) sensing method of the driving TFT senses the mobility of the driving TFT (DT) when the driving TFT (DT) operates in the active section. While the driving TFT (DT) is active, the source voltage (Vgs) rises along with the gate voltage (Vg). The data of the input image is multiplied by a gain value to compensate for the change in mobility of the driving TFT. In the method for sensing the mobility (μ) of the driving TFT, the time required for sensing is short because the mobility is sensed in the active section of the driving TFT.

As shown in FIG. 5, the OLED deterioration sensing method supplies a sensing data voltage (Vdata) to the gate of the driving TFT (DT) to turn on the driving TFT (DT) and applies a constant voltage (EVDD, about 12V) to the OLED. After supplying the OLED, the parasitic capacitor (C _OLED ) connected to the OLED is sensed. Depending on the degree of deterioration of the OLED, a parasitic capacitor (COLED) connected to the OLED varies, and OLED deterioration is sensed as the parasitic capacitance (C _OLED ) decreases due to the deterioration of the OLED.

The external compensation method according to the present invention can compensate for the characteristics and deterioration of each pixel within a predetermined time, for example, a few seconds, in the power on sequence when power to the OLED display device begins to be input. In addition, the external compensation method according to the present invention is a power off sequence in which the OLED display device is turned off by turning off the power of the OLED display device, and pixels that have relatively deteriorated within a predetermined period of time, for example, a few minutes, Compensation may be provided to them. In addition, in the external compensation method according to the present invention, the driving characteristics of pixels arranged on the sensing target line can be sensed and compensated in real time during a vertical blank period (VB) excluding the image display section in one frame period.

FIG. 6 is a configuration diagram of a data driving circuit, a display panel, and a gate driving circuit according to the present invention, and FIG. 7 is a configuration diagram of a timing controller of an OLED display device according to the present invention.

As shown in FIGS. 6 and 7, an OLED display device according to an embodiment of the present invention includes an OLED display panel (PNL) and a display panel driving circuit for writing data of an input image into the OLED display panel (PNL). Provide a furnace.

The screen of the OLED display panel (PNL) is divided into two active areas. The first active area (L) is placed on the left side of the screen and controlled by the first timing controller (TCON1) 111, and the second active area (R) is placed on the right side of the screen and controlled by the second timing controller (TCON2). It is controlled by (112).

The data driver 12 in FIG. 1 may be integrated into the source drive IC (SIC) in FIG. 6 and connected to the data lines 14 and sensing lines 15. The gate driver 13 in FIG. 1 represents a Gate In Panel (GIP) formed directly on the substrate of the display panel (PNL) in FIG. 6 .

In Figure 6, “LRB” is the boundary line between the left active area (L) and the right active area (R). The boundary line LRB does not mean that the substrate of the display panel PNL is physically divided, but rather a boundary line over which control rights of different timing controllers 111 to 112 are exercised.

A chip on film (COF) on which source drive ICs (SICs) are mounted is connected between the display panel (PNL) and the source printed circuit board (PCB). Gate timing control signals and gate driving voltage for controlling the gate driver (GIP) may be transmitted to the gate driver (GIP) on the display panel through the COF.

The first and second timing controllers 111 to 112 may be mounted on a control board (CPCB). The first and second timing controllers 111 to 112 may be implemented as application-specific integrated circuits (ASICs).

When the power of the OLED display device is input, each of the first and first timing controllers 111 to 112 receives parameters from the flash memory 113 to 114 and a compensation value (gain) for external compensation. , opsen), the grayscale-luminance-voltage-current table is loaded into the internal memory (SRAM).

The grayscale-brightness-voltage-current table is created based on the luminance measurement results for each grayscale before product shipment and is stored in the flash memories 113 to 114.

The host system transmits the video signal of the input image to the first and second timing controllers 111 and 112 through a high-speed transmission interface.

That is, when the OLED display panel (PNL) has a resolution of 8K (7680x4320), the host system transmits 1 to 3840 pixel image data to the first timing controller 111 and transmits 3841 to 7680 pixel image data to the first timing controller 111. It is transmitted to the second timing controllers 112.

Each of the first and second timing controllers 111 and 112 transmits the received input image data to the source drive IC (SIC) in charge of the input image data, as well as control data, clock, etc., together with the pixel data of the input image. Transfer to source drive IC (SIC).

Each of the first and second timing controllers 111 to 112 extracts timing signals such as vertical/horizontal synchronization signals, data enable, and main clock signals from the received input video signal, and uses these timing signals to operate the source drive. Timing control signals are generated to control the operation timing of the IC (SIC) and the gate driver (GIP).

In addition, each of the first and second timing controllers 111 to 112 displays an image to compensate for changes in pixel driving characteristics based on the sensing data (SD) supplied from the data driver, as described in FIG. 2. During the section, the image data to be supplied to the pixels is modulated as a compensation value and transmitted to the source drive IC (SIC) in charge.

That is, the first timing controller 111 receives image data (1 to 3840) input from the host system, and senses the degree of deterioration of each pixel of the OLED display panel (threshold voltage and movement of the driving TFT). (sensing light, OLED deterioration, etc.), compensates the image data with the corresponding compensation value for each pixel according to the sensed value, and provides it to the source drive IC (SIC) in charge.

Likewise, the second timing controller 112 receives image data (38411 to 7680) input from the host system and senses the degree of deterioration of each pixel of the OLED display panel (threshold voltage of the driving TFT). and mobility, OLED deterioration, etc.), compensates the image data with the corresponding compensation value for each pixel according to the sensed value, and provides it to the source drive IC (SIC) in charge.

At this time, each of the first and second timing controllers 111 to 112 uses an average filter to reduce sensing noise. For example, if the size of the average filter mask is 25, the average of the sensing data of 12 pixels on the left and 12 pixels on the right is calculated and considered the sensing data of the corresponding pixel. That is, in the case of the 25th pixel, the sensing data of the 13th to 37th pixels (12 pixels to the left and 12 pixels to the right of the 25th pixel) are averaged and used as the 25th sensing data.

However, in this way, the screen of the OLED display panel (PNL) is divided into a first active area (L) and a second active area (R), and pixels of the first active area (L) are connected to the first data driving circuit. and a first timing controller (TCON1) (111), and the pixels of the second active area (R) are controlled by a second data driving circuit and a second timing controller (TCON1) (112) to deteriorate the pixels. And because an average filter is used to compensate for driving characteristics and reduce sensing noise, a border band may occur at the boundary between the first active area (L) and the second active area (R).

That is, in order to average filter the 3840th pixel of the first active area (L) controlled by the first timing controller 111, the sensing data of the 3841st to 3852nd pixels is required, but the first timing controller 111 requires 3841 pixels. Since the sensing data of the ~3852nd pixel is not recognized, average filter processing is not possible, so a border band may occur at the border.

In addition, the pixels of the first active area (L) and the pixels of the second active area (R) are separately compensated for deterioration and driving characteristics by the first timing controller 111 and the second timing controller 112, respectively. Since the luminance is adjusted according to the average gain value, a luminance difference occurs between the first active area (L) and the second active area (R), which causes the first active area (L) and the second active area ( R) A step may occur between

In addition, the pixels of the first active area (L) and the pixels of the second active area (R) are separately compensated for deterioration and driving characteristics by the first timing controller 111 and the second timing controller 112, respectively. Therefore, if the operation is stopped due to gain overflow, synchronization imbalance occurs between the first timing controller 111 and the second timing controller 112, and a difference occurs in whether or not the gain value is updated, resulting in deterioration of image quality. You can.

In order to solve this problem, the present invention processes the average filter by sharing the sensing data of the boundary between the first timing controller 111 and the second timing controller 112, and the first timing controller 111 ) and the second timing controller 112 share a gain value, and the interrupt generated when an overflow occurs is transmitted to the first timing controller 111 and the second timing controller 112. Let's share to keep in sync.

That is, each of the first timing controller 111 and the second timing controller 112 shares the sensing data corresponding to the boundary area with a communication unit (M2S, 115) for sharing the sensing data of the boundary area, respectively, to obtain an average It is composed of an internal logic unit 116 that processes an average filter, performs afterimage compensation, and improves image quality by transmitting and receiving synchronization matching and interrupt signals.

Here, assuming the mask size of the average filter is 25 (12 pixels on the left and right), the sensing data at the border corresponds to 24 pixel data.

Assuming that the first timing controller 111 is a master and the second timing controller 112 is a slave, the average filter processing is performed in the first timing controller 111. 2 It proceeds to the timing controller 112.

Therefore, the first timing controller 111 transmits the average filtered boundary sensing data (3817 to 3840) to the communication unit of the second timing controller 112 through the communication unit 115, and the second timing controller 115 (112) transmits the boundary sensing data (3841 to 3864) to the communication unit of the first timing controller 111 through the communication unit 115.

The first and second timing controllers 111 and 112 according to the present invention, which operate as described above, will be described in more detail as follows.

Figure 8 is a detailed configuration diagram of the first and second timing controllers of the OLED display device according to the present invention.

Since the first and second timing controllers 111 and 112 have the same configuration, they are described by assigning the same numbers.

First, the first timing controller 111 receives boundary sensing data (3841 to 3864) from the second timing controller 112, and average filtered sensing data (AF sensing data (3817 to 3840)) to the second timing controller 112. The average gain value is output from the communication unit 115 that outputs to the timing controller 112 and transmits and receives the gain average value to the second timing controller 112, and the memory (DDR, 121) when the power is turned on. An average gain value calculation unit 123 that receives the gain value (3840 * 4320, meaning that the gate line is 4320) before being obtained line by line and calculates the average gain value, and Through a gain merge unit 122 that calculates the average of the average gain value and the average gain value of the second timing controller 112 received from the second timing controller 112 through the communication unit 115, and a data driver. The received sensing data (1 to 3840) and the boundary sensing data (3841 to 3864) received from the second timing controller 112 through the communication unit 115 are received, an average filter is performed (processed), and the average Sensing data (3817 to 3840) of the boundary portion among the filtered sensing data is transmitted to the second timing controller 112 through the communication unit 115, and internal calculation and lookup table ( A sensing/average filter/gain calculation unit 125 that derives and outputs a gain value using a LUT), and a gain value of an overflow condition among the gain values derived from the sensing/average filter/gain calculation unit 125 in real time. An overflow check unit 124 that counts and activates the interrupt processing unit 126 when the counting value (deterioration degree) exceeds a certain value, and an interrupt signal ( An interrupt handler that transmits Interrupt_M) to the scheduler 127 and the second timing controller 112, and receives the interrupt signal (Interrupt_S) generated from the second timing controller 112 and transmits it to the scheduler 127. (126), a synchronization signal transceiving unit 128 for transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) between the first timing controller 111 and the second timing controller 112, and the synchronization signal transceiving unit When all synchronization matching signals (Sync Match_S, Sync Match_M) are activated through (128), a data sensing enable signal is output to the gate and data driver (GIP, SIC) and the sensing/average filter/gain operation unit 125, The gain value derived from the sensing/average filter/gain calculation unit 125 is updated in the memory (NAND) 129 so that the image data (1 to 3840) received from the host system is compensated, and the inter It is configured to include a scheduler (Scheduler) 127 that disables the gain value update and data sensing when an interrupt signal is received from the loop handler 126.

In addition, the second timing controller 112 receives the average filtered boundary sensing data (3817 to 3840) from the first timing controller 111, and transmits the boundary sensing data (3841 to 3864) to the first timing controller ( 111) until the average gain value is obtained from the communication unit 115, which transmits and receives the gain average to and from the first timing controller 111, and the memory (DDR, 121) when the power is turned on. An average gain value calculation unit 123 that receives the gain value (7680 * 4320) in line units and calculates the average gain value, and the first signal received from the first timing controller 111 through the communication unit 115. and a gain merge unit 122 that stores the average gain values of the second timing controllers 111 and 112, and sensing data 3841 to 3864 of the boundary portion among the sensing data 3841 to 7680 received through the data driver. Sensing data (3841 to 7680) is transmitted to the first timing controller 111 through the communication unit 115 and received from the first timing controller 111 through the communication unit 115. Receives the average filtered boundary portion sensing data (3817 to 3840), performs (processes) an average filter, and derives a gain value using internal calculation and a lookup table (LUT) according to the average filtered sensing data. Among the gain values derived from the sensing/average filter/gain operation unit 125 and the sensing/average filter/gain operation unit 125, the gain value of the overflow condition is counted in real time to calculate the counting value (deterioration). an overflow check unit 124 that activates the interrupt processing unit 126 when the degree) exceeds a certain value, and an interrupt signal (Interrupt_M) when activated by the overflow check unit 124 to the scheduler 127 and An interrupt handler 126 that transmits the interrupt signal (Interrupt_M) generated from the first timing controller 111 to the first timing controller 111 and transmits it to the scheduler 127, and the first A synchronization signal transceiver 128 for transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) between the timing controller 111 and the second timing controller 112, and a synchronization matching signal through the synchronization signal transceiving unit 128. When (Sync Match_S, Sync Match_M) are all activated, a data sensing enable signal is output to the gate and data driver (GIP, SIC) and the sensing/average filter/gain operation unit 125, and the sensing/average filter/gain operation unit The gain value derived at (125) is updated in the memory (NAND) 129 so that the image data (3841 to 7680) received from the host system is compensated, and the interrupt handler (126) It is configured to include a scheduler 127 that disables the gain value update and data sensing when a signal is received.

Here, the gain merge unit 122 of the first timing controller 111 calculates the average gain value (a) of the first active area driven by the first timing controller 111 and the second timing controller 112. The average gain value ((a+b)/2) of the average gain value (b) of the second active area driven by is calculated and provided to the second timing controller 112 through the communication unit 115. Therefore, since the first timing controller 111 and the second timing controller 112 drive by sharing the average gain value ((a+b)/2), the first active area L and the second active area L There is no difference in luminance between regions (R), and as a result, no step difference occurs between the first active region (L) and the second active region (R).

In addition, the higher the average gain value ((a+b)/2), the more the pixels are deteriorated, so the overall luminance can be lowered to slow down the acceleration of deterioration.

In the above, the first timing controller 111 and the second timing controller 112 do not drive by sharing the average gain value ((a+b)/2), but drive in a different way to generate the first active area ( It is possible to prevent a step from occurring between L) and the second active area (R).

That is, the first timing controller 111 or the second timing controller 112 is driven by sharing one of the average gain value (a) of the first active area and the average gain value (b) of the second active area. Therefore, it is possible to prevent a luminance difference between the first active area (L) and the second active area (R).

In addition, the first timing controller 111 or the second timing controller 112 is configured to control the maximum, minimum, or Since the two timing controllers 111 or 112 are driven by sharing a value calculated with a matching value, such as using a weighted value, the distance between the first active area (L) and the second active area (R) It is possible to prevent a difference in luminance from occurring. In the explanation below, for convenience of explanation, the average gain value ((a+b)/2) is used. Therefore, the average gain value calculation unit 123 is not necessarily necessary.

Meanwhile, the first and second timing controllers 111 and 112 are driven by transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) through the synchronization signal transmitting and receiving unit 128, so that when data is sensed, they are synchronized with each other for each line. , They are synchronized with each other even when switching from sensing mode to driving mode.

In addition, the first and second timing controllers 111 and 112 share the sensing data at the boundary and perform average filter processing, so that accurately compensated image data is displayed at the boundary, thereby preventing the tee phenomenon at the boundary.

Figure 9 is a block diagram of the average filter processing unit in the sensing/average filter/gain operation unit according to the present invention.

The average filter processing unit of the sensing/average filter/gain operation unit 125A of the first timing controller 111 includes a buffer unit 131 that receives and temporarily stores the sensing data (1 to 3840) through the data driver, and the buffer A data expansion unit ( 132), the sensing data (1 to 3864) output from the data expansion unit 132 is processed through an average filter, and the sensing data (3817 to 3840) of the boundary portion among the average filtered sensing data are processed by the communication unit 115. It is configured to include an average filter unit 133 that outputs output to the second timing controller 112 through .

The average filter processing unit of the sensing/average filter/gain operation unit 125B of the second timing controller 112 includes a buffer unit 131 that receives and temporarily stores the sensing data (3841 to 7680) through the data driver, and the buffer Data that outputs sensing data (3817 to 7680) by expanding the average filtered boundary portion sensing data (3817 to 3840) received through the communication unit 115 to the sensing data (3841 to 7680) output from the unit 131. It is comprised of an expansion unit 132 and an average filter unit 133 that performs average filter processing on the sensing data (3817 to 7680) output from the data expansion unit 132.

A method of driving an OLED display device according to the present invention configured as described above will be described as follows.

Figure 10 is a timing diagram of synchronization matching signals (Sync Match_S, Sync Match_M) according to the present invention.

As shown in FIG. 10, when the second timing controller 112 (Slave) is ready, the scheduler 127 of the second timing controller 112 transmits a synchronization matching signal (Sync) through the synchronization signal transmitting and receiving unit 128. Match_S) is provided to the synchronization signal transceiver 128 of the first timing controller 111.

Then, when the first timing controller (111, Master) is prepared and the synchronization matching signal (Sync Match_S) is received, the scheduler 127 of the first timing controller 111 sends and receives the synchronization signal transceiver 128. A synchronization matching signal (Sync Match_M) is provided to the synchronization signal transceiving unit 128 of the second timing controller 112.

In this way, when the other party's synchronization matching signal (Sync Match_S, Sync Match_M) is received, each line is synchronized during data sensing.

Figure 11 is a timing diagram of interrupt signals (Interrupt_S, Interrupt_M) according to the present invention.

When an interrupt signal occurs in sensing mode, the other party's timing controller recognizes that an overflow has occurred.

FIG. 11(A) indicates that an overflow occurred first in the second timing controller 112, and the first timing controller 111 recognizes that an overflow occurred in the second timing controller 112.

That is, as shown in FIG. 11(A), the overflow check unit 124 of the second timing controller 112 counts the gain value derived from the sensing/average filter/gain calculation unit 125 and calculates the gain value ( When the degree of deterioration exceeds a certain value, the interrupt processing unit 126 is activated and the interrupt processing unit 126 provides an interrupt signal (Interrupt_S) to the first timing controller 111. Then, the interrupt processing unit 126 of the first timing controller 111 recognizes that an overflow has occurred in the second timing controller 112 and provides an interrupt signal (Interrupt_M) to the second timing controller 112. .

In this way, when an interrupt signal is received from either the first or second timing controllers 111 and 112, the scheduler 127 of each of the first and second timing controllers 111 and 112 updates the gain value and performs data sensing. stop.

Meanwhile, as shown in FIG. 11(B), the overflow check unit 124 of the first timing controller 111 counts the gain value derived from the sensing/average filter/gain calculation unit 125 and calculates the gain value ( When the degree of deterioration exceeds a certain value, the interrupt processing unit 126 is activated and the interrupt processing unit 126 provides an interrupt signal (Interrupt_M) to the second timing controller 111. Then, the interrupt processing unit 126 of the second timing controller 112 recognizes that an overflow has occurred in the first timing controller 111 and provides an interrupt signal (Interrupt_S) to the first timing controller 111. .

In this way, when the interrupt signal of the first or second timing controller is received, the scheduler 127 of each of the first and second timing controllers 111 and 112 stops the gain value update and data sensing.

Figure 12 is a flowchart of interrupt signal generation and operation of the first or second timing controllers 111 and 112 according to the present invention.

An 8K display panel has 7680 data lines and 4320 gate lines. Therefore, the sensing/average filter/gain operation unit 125 of each timing controller 111 or 112 receives sensing data in units of 1 horizontal line (gate line) starting from the first horizontal line, processes the average filter, and processes the average filter. According to the filtered sensing data, the gain value is derived and output using internal calculation and a look-up table (LUT) (3S).

And the overflow check unit 124 counts in real time (4S) the gain value corresponding to the overflow condition among the gain values derived from the sensing/average filter/gain calculation unit 125 and calculates the gain value (deterioration). When the degree (degree) exceeds a certain value (threshold) (5S), the interrupt processor 126 is activated to generate and output an interrupt signal (Interrupt_S or Interrupt_M) to the relative timing controller (111 or 112) (7S).

If the interrupt signal (Interrupt_M) is output from the first timing controller 111, the second timing controller 112 outputs an interrupt signal (Interrupt_S) indicating that the interrupt signal (Interrupt_M) has been received. Conversely, if the interrupt signal (Interrupt_S) is output from the second timing controller 112, the first timing controller 111 outputs an interrupt signal (Interrupt_M) indicating receipt of the interrupt signal (Interrupt_S) (8S ).

In this way, when an interrupt signal (Interrupt_M or Interrupt_S) is generated from the relative timing controller, an interrupt signal (Interrupt_S or Interrupt_M) that recognizes this is provided to the relative timing controller (8S), and the first and second timing controllers (111) , 112) each stops the gain value update and data sensing (9S).

In step 5S, if the counting value of the gain value corresponding to the overflow condition is less than a specific value (threshold), the gain value corresponding to the overflow condition of the next horizontal line is counted and the counting value of the gain value is set to a specific value. By repeating the comparison with (threshold), the gain value corresponding to the overflow condition of the final (4320) horizontal line is counted, and the counting value of the gain value is compared with a specific value (threshold) (2S to 6S).

And, if the counting value of the gain value corresponding to the overflow condition up to the last (4320) horizontal line is less than a certain value (threshold), the sensing mode is terminated and converted to the driving mode (10S).

Meanwhile, Figure 13 is a flowchart of the average gain value calculation operation of the first or second timing controllers 111 and 112 according to the present invention.

When the power is turned on (11S), the average gain value calculation unit 123 of each timing controller (111 or 112) calculates the gain value (3840 * 4320 or 7680 * 4320) before the average gain value is obtained from the memory (DDR, 121). ) is read in units of 1 horizontal line from 1 to 4320 horizontal lines and calculate the average gain value (12S~14S).

Then, the second timing controller 112 transmits the calculated average gain value to the first timing controller 111 (15S), and the first timing controller 111 transmits the average gain value calculated by the first timing controller 111. Add the gain value and the average gain value calculated by the second timing controller 112 and divide by 2 to obtain the average gain value (Master+Slave)/2) of the first and second timing controllers 111 and 112 ( 16S), the average gain value (Master+Slave)/2) of the first and second timing controllers 111 and 112 is provided to the second timing controller 112 (17S).

In this way, the average gain value (Master+Slave)/2) of the first and second timing controllers 111 and 112 is shared, and the first and second timing controllers 111 and 112 share the shared first gain value (Master+Slave)/2). The brightness is adjusted according to the average gain value (Master+Slave)/2) of the first and second timing controllers 111 and 112 (18S).

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

111, 112: Timing controller 115, 117: Communication unit
116, 118: internal logic unit 121: memory unit
122: Gain merge unit 123: Average gain value calculation unit
124: Overflow check unit 125: Sensing/average filter/gain calculation unit
126: Interrupt handler 127: Scheduler
128: Synchronization signal transceiver 129: Memory
131: buffer 132: data extension unit
133: average filter unit

Claims (12)

First and second active areas divided on a screen where a plurality of pixels are arranged by crossing a plurality of data lines and a plurality of gate lines;
a first driving circuit that writes pixel data to pixels in the first active area;
A first timing controller that senses the degree of deterioration of pixels in the first active area through the first driving circuit, compensates for pixel data of the first active area to be displayed in the first active area, and controls the first driving circuit. ;
a second driving circuit that writes pixel data to pixels in the second active area;
A second timing controller that senses the degree of deterioration of pixels in the second active area through the second driving circuit, compensates for pixel data of the second active area to be displayed in the second active area, and controls the second driving circuit. Equipped with
The first and second timing controllers share deterioration degree sensing data of pixels corresponding to the boundary between the first and second active areas and perform average filter processing to compensate for pixel data in each active area,
The first and second timing controllers share a gain value for compensating pixel data to be written in the first and second active areas, and update the gain value and sense pixel deterioration in an overflow condition for the gain value. OLED display device that makes you stop. According to claim 1,
An OLED display device in which each pixel further includes a sensing circuit for sensing driving characteristics. According to claim 1,
Each of the first and second timing controllers,
a communication unit for transmitting and receiving data sensing the degree of deterioration of pixels corresponding to the boundary between the first and second active areas;
An OLED display device comprising an internal logic unit that performs average filter processing by sharing deterioration degree sensing data of pixels corresponding to the boundary between the first and second active areas. According to claim 1,
Each of the first and second timing controllers,
Driving by sharing one of the average gain value (a) of the first active area and the average gain value (b) of the second active area, or by sharing a value that matches the maximum value, minimum value, or weighting. OLED display device. According to claim 1,
Each of the first and second timing controllers,
A communication unit for transmitting and receiving an average gain value (a) of the first active area and an average gain value (b) of the second active area,
The first timing controller is an OLED display device including an internal logic unit that calculates the average gain value ((a+b)/2)) of the first and second active areas and transmits the average gain value ((a+b)/2)) to the second timing controller through the communication unit. . According to claim 1,
The first timing controller,
a communication unit that receives sensing data of a first boundary portion from the second timing controller, outputs the average filtered sensing data of the second boundary portion to the second timing controller, and transmits and receives an average gain value to and from the second timing controller;
An average gain value calculation unit that calculates the average gain value when the power is turned on,
The sensing data received through the first driving circuit and the sensing data of the first boundary portion received through the communication unit from the second timing controller are received, processed with an average filter, and a second boundary portion of the average filter-processed sensing data is received. An OLED display device comprising a sensing/average filter/gain calculation unit that transmits sensing data to the second timing controller through the communication unit and derives and outputs a gain value according to the average filter-processed sensing data. According to claim 6,
An average gain value ((a+b)/2) of the calculated average gain value (a) and the average gain value (b) of the second timing timing controller is calculated and provided to the second timing controller through the communication unit. An OLED display device further comprising a gain merge unit. According to claim 6,
The first timing controller,
An overflow check unit that counts the gain value of the overflow condition among the gain values derived from the sensing/average filter/gain operation unit and activates the interrupt processing unit when the counting value exceeds a certain value;
an interrupt handler that transmits an interrupt signal (Interrupt_M) when activated by the overflow check unit and receives an interrupt signal (Interrupt_S) generated from the second timing controller;
a synchronization signal transceiver for transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) between the first timing controller and the second timing controller;
When all synchronization matching signals (Sync Match_S, Sync Match_M) are activated through the synchronization signal transceiver, a data sensing enable signal is output to the gate and data driver and the sensing/average filter/gain operation unit, and the sensing/average filter/gain operation unit is output. An OLED display device further comprising a scheduler that updates the gain value derived from the calculation unit in memory and disables the gain value update and the pixel deterioration sensing when an interrupt signal (Interrupt_M or Interrupt_S) is received from the interrupt handler. According to claim 1,
The second timing controller,
a communication unit that transmits sensing data of a first boundary portion to the first timing controller, receives sensing data of a second boundary portion that has been average filtered from the first timing controller, and transmits and receives an average gain value to and from the first timing controller;
An average gain value calculation unit that calculates the average gain value when the power is turned on,
Receives the sensing data received through the second driving circuit and the average filtered first boundary portion sensing data received from the first timing controller, processes the average filter, and sets a gain value according to the average filtered sensing data. An OLED display device including a sensing/average filter/gain calculation unit that derives and outputs . According to clause 9,
The second timing controller,
An OLED display further comprising a gain merge unit storing an average gain value ((a+b)/2) of the average gain value (a) of the first timing controller and the average gain value (b) of the second timing controller. Device. According to clause 9,
An overflow check unit that counts the gain value of the overflow condition among the gain values derived from the sensing/average filter/gain operation unit and activates the interrupt processing unit when the counting value exceeds a certain value;
an interrupt handler that transmits an interrupt signal (Interrupt_M) when activated by the overflow check unit and receives an interrupt signal (Interrupt_S) generated from the first timing controller;
a synchronization signal transceiver for transmitting and receiving synchronization matching signals (Sync Match_S, Sync Match_M) between the first timing controller and the second timing controller;
When all synchronization matching signals (Sync Match_S, Sync Match_M) are activated through the synchronization signal transceiver, a data sensing enable signal is output to the gate and data driver and the sensing/average filter/gain operation unit, and the sensing/average filter/gain operation unit is output. An OLED display device further comprising a scheduler that updates the gain value derived from the calculation unit in memory and disables the gain value update and the pixel deterioration sensing when an interrupt signal (Interrupt_M or Interrupt_S) is received from the interrupt handler. According to claim 6 or 9,
The sensing/average filter/gain calculation unit is,
A buffer unit that receives sensing data through the first or second data driver and temporarily stores it,
a data expansion unit that expands the sensing data of the first border or the average filtered second border to the sensing data output from the buffer;
An OLED display device including an average filter unit that performs average filter processing on the sensing data output from the data expansion unit.

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