KR102587962B1 - Search circuit, hammer address management circuit and memory system including the same - Google Patents

Abstract

The search circuit includes a content addressable memory (CAM) and a cam controller. The content addressable memory includes a plurality of CAM cells storing a plurality of entry data each including K bits corresponding to the Kth bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, and the plurality of CAM cells Provides a plurality of matching signals indicating whether the entry data matches the search data. In order to search for target entry data among the plurality of entry data based on the plurality of matching signals, the cam controller uses comparison target bits corresponding to some of the first to Kth bits as the search data. The content is applied to the addressable memory to perform a partial search operation to determine whether bits of the plurality of entry data corresponding to the bits to be compared match the bits to be compared.

Description

Search circuit, hammer address management circuit and memory system including the same {Search circuit, hammer address management circuit and memory system including the same}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a search circuit, a hammer address management circuit including the same, and a memory system.

Content addressable memory (CAM) is a type of memory that enables high-speed parallel search of memory for entry data stored in it. Content-addressable memory is memory that can implement lookup-table functions in one clock cycle using a dedicated comparison circuit. In particular, content addressable memory is used in a variety of fields that require high-speed parallel search, such as network routers for packet forwarding. However, a typical content-addressable memory is used to determine whether a plurality of stored entry data matches externally input search data, and the fields in which the comparison function inherent in the content-addressable memory can be utilized are limited. .

One purpose of the present invention to solve the above problems is to provide a search circuit that can efficiently search for data that satisfies specific conditions using a content addressable memory.

Another object of the present invention is to provide a hammer address management circuit and memory system including the search circuit.

To achieve the above object, the search circuit according to embodiments of the present invention includes a content addressable memory (CAM) and a CAM controller. The content addressable memory includes a plurality of CAM cells storing a plurality of entry data each including K bits corresponding to the Kth bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, and the plurality of CAM cells Provides a plurality of matching signals indicating whether the entry data matches the search data. In order to search for target entry data among the plurality of entry data based on the plurality of matching signals, the cam controller uses comparison target bits corresponding to some of the first to Kth bits as the search data. The content is applied to the addressable memory to perform a partial search operation to determine whether bits of the plurality of entry data corresponding to the bits to be compared match the bits to be compared.

To achieve the above object, a memory system according to embodiments of the present invention includes a memory cell array including a plurality of memory cells, a hammer address management circuit that determines and provides an intensively accessed hammer address, and the hammer It includes a refresh controller that performs a hammer refresh operation on the row corresponding to the address and the row physically adjacent to it. The hammer address management circuit includes an address storage unit that stores a plurality of row addresses based on an access address signal, K bits corresponding to the K bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, respectively. and a plurality of CAM cells storing access count data respectively indicating access numbers of the plurality of row addresses, and providing a plurality of matching signals indicating whether the plurality of access count data matches search data. memory, in order to search for target count data among the plurality of access count data based on the plurality of matching signals, bits to be compared corresponding to some of the first to Kth bits are used as the search data. A cam controller that performs a partial search operation to apply content to an addressable memory to determine whether bits of the plurality of access count data corresponding to the bits to be compared match the bits to be compared, and the target count data. and an address controller that provides the hammer address from among the plurality of row addresses stored in the address storage unit based on the search result.

To achieve the above object, the hammer address management circuit according to embodiments of the present invention includes an address storage unit, a content addressing circuit, a cam controller, and an address controller. The address storage unit stores a plurality of row addresses based on an address signal provided to a memory device. The content addressable memory includes K bits corresponding to the K bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, and stores access count data respectively indicating the number of accesses of the plurality of row addresses. It includes a plurality of CAM (content addressable memory) cells and provides a plurality of matching signals indicating whether the plurality of access count data matches search data. In order to search for target count data among the plurality of access count data based on the plurality of matching signals, the cam controller uses comparison target bits corresponding to some of the first to Kth bits as the search data. It is applied to the content addressable memory to perform a partial search operation to determine whether bits of the plurality of access count data corresponding to the bits to be compared match the bits to be compared. The address controller includes an address controller that provides a hammer address that is accessed intensively among the plurality of row addresses stored in the address storage unit based on a search result of the target count data.

The search circuit according to embodiments of the present invention can replace additional circuits such as comparators for determining the various conditions by searching for data that satisfies various conditions using a partial search operation for the content addressable memory. and can reduce the size of various integrated circuits.

Additionally, the hammer address management circuit and memory system according to embodiments of the present invention can reduce the size of the circuit for the hammer refresh operation by using the search circuit.

1 is a block diagram showing a search circuit according to embodiments of the present invention.
FIG. 2 is a diagram showing a schematic structure of a content addressable memory included in the search circuit of FIG. 1.
3A, 3B, 4A, and 4B are diagrams showing examples of partial search operations of a search circuit according to embodiments of the present invention.
Figure 5 is a circuit diagram showing an embodiment of a CAM cell included in a content addressable memory.
Figures 6a, 6b, 7a, 7b, 8a, and 8b are diagrams for explaining bit values of search data applied to the content addressable memory.
Figure 9 is a flowchart illustrating an example of a maximum entry search operation of a search circuit according to embodiments of the present invention.
Figures 10a and 11b are diagrams showing examples of the maximum entry search operation of Figure 9.
Figure 12 is a flowchart showing an example of a minimum entry search operation of a search circuit according to embodiments of the present invention.
Figures 13a and 14b are diagrams showing examples of the minimum entry search operation of Figure 12.
15 and 16 are diagrams showing memory systems according to embodiments of the present invention.
Figure 17 is a block diagram showing a hammer address management circuit according to embodiments of the present invention.
FIG. 18 is a block diagram illustrating an example of a refresh controller included in a memory device according to embodiments of the present invention.
FIG. 19 is a diagram showing a portion of a memory cell array to explain data damage caused by coupling between word lines.
20A, 20B, and 20C are timing diagrams showing examples of operations of a refresh controller included in a memory device according to embodiments of the present invention.
Figure 21 is a block diagram showing a mobile system including a memory device according to embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

1 is a block diagram showing a search circuit according to embodiments of the present invention.

Referring to FIG. 1, the search circuit 1000 includes a content addressable memory (CAM) 1010 and a CAM controller 1020.

The content addressable memory 1010 can store a plurality of entry data (ENT1 to ENTN). As will be described later with reference to FIG. 2, the content addressable memory 1010 stores a plurality of entry data each including K bits corresponding to the K bit corresponding to the most significant bit to the first bit corresponding to the least significant bit. It may include a plurality of cam cells.

The content addressable memory 1010 receives search data (SDT) from the cam controller 1020 and provides a plurality of matching signals indicating whether a plurality of entry data (ENT1 to ENTN) matches the search data (SDT). (MAT1~MATN) can be provided.

The cam controller 1020 may search for target entry data among the plurality of entry data ENT1 to ENTN based on the plurality of matching signals MAT1 to MATN. The cam controller 1020 may perform a partial search operation to search for the target entry data. The partial search operation applies bits to be compared, corresponding to some of the first to K bits (B1 to BK), as search data (SDT) to the content addressable memory 1010 to search for bits corresponding to the bits to be compared. This refers to determining whether bits of a plurality of entry data (ENT1 to ENTN) match the comparison target bits. Examples of partial search operations will be described later with reference to FIGS. 3A to 4B.

The cam controller 1020 may include a seek data driver (SDD), a read-write circuit (RWC), and control logic (CLG).

The read-write circuit (RWC) is connected to the content-addressable memory 1010 through a plurality of bit lines (BLS) and a plurality of word lines (WLS), and writes entry data to the content-addressable memory 1010. Alternatively, the entry data stored in the content addressable memory 1010 can be read. The cam cells included in the content-addressable memory 1010 may have various configurations, and the read-write circuit (RWC) may have various configurations to suit the configuration of the content-addressable memory 1010.

Control logic (CLG) can control the partial search operation. The control logic (CLG) determines comparison target bits for a partial search operation based on the target entry data to be searched and provides search data (SDT) corresponding to the comparison target bits to the search data driver (SDD). there is. The control logic (CLG) is connected to the content addressable memory 1010 through a plurality of matching lines (ML1 to MLN), and a plurality of matching signals (MAT1) provided through a plurality of matching lines (ML1 to MLN). Based on ~MATN), target entry data can be searched among a plurality of entry data (ENT1~ENTN). Those skilled in the art will understand that control logic (CLG) may be implemented in hardware, software, or a combination of hardware and software.

The search data driver (SDD) may be connected to the content addressable memory 1010 through a plurality of search lines (SL1 to SLK). The search data driver (SDD) may latch the search data (SDT) provided from the control logic (CLG) and apply it to the content addressable memory 1010 through a plurality of search lines (SL1 to SLK).

Using this partial search operation, target entry data that satisfies various conditions can be searched among the plurality of entry data (ENT1 to ENTN) stored in the content addressable memory 1010. The cam controller 1020 may repeatedly perform the partial search operation while changing the bits to be compared until the target entry data is determined. In this specification, searching for target entry data refers to detecting the target location of the content addressable memory 1010 where the target entry data is stored. The target location may be expressed in the form of an address or pointer. Information about the target location may be provided to a read-write circuit (RWC), and the read-write circuit (RWC) may read target entry data from the content addressable memory 1010 based on the provided target location information. there is.

In one embodiment, the cam controller 1020 may repeatedly perform the partial search operation while sequentially increasing the bits to be compared by one in the direction from the Kth bit to the lower bit. This sequential and repetitive partial search operation may be referred to as a 1-bit cumulative search operation. As will be described later with reference to FIGS. 9 to 14B, the 1-bit cumulative search operation may be performed to determine the maximum or minimum entry data among the plurality of entry data ENT1 to ENTN as the target entry data.

As such, the search circuit according to embodiments of the present invention searches for data that satisfies a specific condition using a partial search operation for the content addressable memory, thereby installing additional circuits such as comparators to determine the specific condition. It can replace and reduce the size of various integrated circuits.

FIG. 2 is a diagram showing a schematic structure of a content addressable memory included in the search circuit of FIG. 1.

Referring to FIG. 2, the content addressable memory 1010 may include a plurality of cam cells (C11 to CNK), a precharge circuit (TP), and a plurality of sense amplifiers (SA1 to SAN).

A plurality of cam cells (C11 to CNK) may be arranged in a matrix of N rows and K columns, and K cam cells corresponding to one row are configured to select the Kth bit corresponding to the most significant bit to the first bit corresponding to the least significant bit. One entry data containing each K bits corresponding to can be stored. That is, the cam cells (C11 to C1K) in the first row store first entry data (ENT1) containing K bits, and the cam cells (C21 to C2K) in the second row store second entry data (ENT1) containing K bits. Entry data ENT2 is stored, and in this manner, the N-th row cam cells CN1 to CNK can store N-th entry data ENTN including K bits.

Cam cells in the same row may be commonly connected to the same matching line. That is, the cam cells (C11 to C1K) in the first row are commonly connected to the first matching line (ML1), and the cam cells (C21 to C2K) in the second row are commonly connected to the second matching line (ML2). , In this way, the N-th row cam cells (CN1 to CNK) can be commonly connected to the N-th matching line (MLN).

Cam cells in the same row may be commonly connected to the same search line. That is, the cam cells C11 to CN1 in the first row are commonly connected to the first search line SL1, and the cam cells C12 to CN2 in the second row are commonly connected to the second search line SL2. In the same way, the cam cells (C1K to CNK) of the Kth row can be commonly connected to the Kth search line (SLK).

The plurality of sense amplifiers (SA1 to SAN) may respectively sense the voltages of the plurality of matching lines (ML1 to MLN) and provide a plurality of matching signals (MAT1 to MATN). Depending on the embodiment, the sense amplifiers (SA1 to SAN) may be omitted or may be included in the control logic (CLG) of FIG. 1.

The precharge circuit TP may precharge the plurality of matching lines ML1 to MLN with the precharge voltage VPR in response to the precharge signal PRCH. FIG. 2 shows a configuration in which one precharge circuit TP implemented with a PMOS transistor commonly precharges a plurality of matching lines ML1 to MLN, but the configuration is not limited thereto. For example, one precharge circuit may be placed for each matching line. The configuration of the precharge circuit (TP) can be implemented in various ways.

Figure 2 shows a simplified configuration of content addressable memory 1010. Search data (SDT) including the first to Kth bits (B1 to BK) is broadcast through the first to Kth search lines (SL1 to SLK), and is transmitted to a plurality of cam cells (C11 to CNK). The comparison results between the stored entry data (ENT1 to ENN) and the search data (SDT) are provided to the sense amplifiers (SA1 to SAN) through the matching lines (ML1 to MLN).

The comparison result is that when the comparison target bits of the search data (SDT) match the corresponding bits of each entry data (ENTi), each matching signal (MATi) has a first logic level indicating a match case ( For example, when there is a mismatch, each matching signal MATi may have a second logic level (for example, a logic low level) indicating a mismatch case. In the present disclosure, a logic high level may be used to have the same meaning as a value of 1, and a logic low level may be used to have the same meaning as a value of 0.

The search operation of the content addressable memory 1010 may include a search line precharge operation, a matching line precharge operation, and a comparison operation. For example, when the cam cells have the NOR type configuration shown in FIG. 5, the pull-down paths included in each cam cell are first disabled to set the search lines to a logic low level so that the search lines are not connected to ground. Free charge. In this state, with the pull-down paths disabled, the matching lines are precharged to a logic high level using a precharge circuit. Finally, a comparison operation is performed by applying bit values of search data to the search lines.

In the case of a match, the pull-down paths of all cam cells connected to the matching line are disabled and the match line maintains the precharged logic high level. That is, the matching signal has a logic high level or a value of 1.

In the case of mismatch, the pull-down path of at least one of the cam cells connected to the matching line is enabled and the match line is discharged to the ground voltage level. That is, the matching signal has a logic low level or a value of 0.

3A, 3B, 4A, and 4B are diagrams showing examples of partial search operations of a search circuit according to embodiments of the present invention.

3A, 3B, 4A, and 4B show a 6-bit configuration corresponding to one row for convenience of illustration and explanation, but it will be understood that the number of bits can be varied.

The first to sixth bits of the entry data ENT are stored in the first to sixth cam cells C1 to C6, and the first to sixth bits B1 to B6 of the search data SDT are stored in the first to sixth cam cells C1 to C6. The first to sixth bits are applied to the first to sixth cam cells C1 to C6 through the sixth search lines SL1 to SL6, respectively. Exemplarily, the sixth to first cam cells C6 to C1 are shown to sequentially have values of 0, 1, 1, 0, 1, and 0.

Among the first to sixth bits of the search data (SDT), the remaining bits excluding the above-described comparison target bits may be referred to as comparison-excluded bits. A value of 0 or 1 may be applied to the bits to be compared, depending on the search condition, and a don't care value (DCV) may be applied to the bits excluded from comparison. Here, the doncare value (DCV) represents a value that can disable the pull-down path of the cam cell regardless of the bit value stored in the cam cell, and the doncare value (DCV) can be implemented in various ways depending on the configuration of the cam cell. You can.

Figures 3a and 3b show partial search operations corresponding to the match case.

Referring to Figure 3a, the 6th bit (B6) and the 5th bit (B5) of the search data (SDT) correspond to the bits to be compared, and the 4th bit (B4), the 3rd bit (B3), and the 2nd bit Bit (B2) and first bit (B1) correspond to bits excluded from comparison. The comparison exclusion bits (B4, B3, B2, B1) do not affect the comparison result, that is, the logic level or value of the matching signal (MAT). As a result, the compared bits B6 and B5 of the search data SDT each match the corresponding bits of the entry data ENT, so the matching signal MAT has a value of 1, indicating a match.

Referring to Figure 3b, the fifth bit (B5), third bit (B3), and second bit (B2) of the search data (SDT) correspond to bits to be compared, and the sixth bit (B6), fourth bit Bit (B4) and the first bit (B1) correspond to bits excluded from comparison. Comparison exclusion bits (B6, B4, B1) do not affect the value of the matching signal (MAT). As a result, the comparison target bits (B5, B3, B2) of the search data (SDT) each match the corresponding bits of the entry data (ENT), so the matching signal (MAT) has a value of 1, indicating a match case. .

Figures 4a and 4b show partial search operations corresponding to the mismatch case.

Referring to Figure 4a, the sixth bit (B6), the fifth bit (B5), the fourth bit (B4), and the third bit (B3) of the search data (SDT) correspond to bits to be compared, and the second Bit (B2) and first bit (B1) correspond to bits excluded from comparison. The comparison exclusion bits (B2, B1) do not affect the logic level or value of the matching signal (MAT). As a result, at least one bit, that is, the third bit (B3), among the comparison target bits (B6, B5, B4, B3) of the search data (SDT) does not match the third bit of the entry data (ENT), so matching Signal MAT has a value of 0, indicating a mismatch case.

Referring to Figure 4b, the fourth bit (B4) and the second bit (B2) of the search data (SDT) correspond to the bits to be compared, and the sixth bit (B6), the fifth bit (B5), and the third bit (B2) correspond to the bits to be compared. Bit (B3) and the first bit (B1) correspond to bits excluded from comparison. Comparison exclusion bits (B6, B5, B3, B1) do not affect the value of the matching signal (MAT). As a result, at least one bit, that is, the fourth bit B4, among the comparison target bits B4 and B2 of the search data SDT does not match the fourth bit of the entry data ENT, so the matching signal MAT has a value of 0, indicating a mismatch case.

Various search conditions can be implemented through each partial search operation or a combination or sequence of a plurality of partial search operations as shown in FIGS. 3A to 4B.

Figure 5 is a circuit diagram showing an embodiment of a CAM cell included in a content addressable memory.

Figure 5 shows a NOR type cam cell that is a modified static random access memory (SRAM) cell. Embodiments of the present invention are not limited to the configuration shown in FIG. 5.

Referring to FIG. 5, the cam cell may be implemented including first and second inverters (INV1, INV2) and first to sixth NMOS transistors (T1 to T6) forming a latch.

The fifth and sixth transistors (T5, T6) are related to the read and write operations of the cam cell, and are normal based on the voltage of the word line (WL) driven by the read-write circuit (RWC) of FIG. 1. The bit line (BL) and the complementary bit line (/BL) are electrically connected to the latch node (N) and the inverting node (/N), respectively. In a read operation, the normal bit value (D) and the invert bit value (/D) of the latch node (N) and inversion node (/N) are read and written through the normal bit line (BL) and the complementary bit line (/BL). It can be provided as a circuit (RWC). In a write operation, the normal bit value (D) and the inverted bit value (/D) loaded into the normal bit line (BL) and the complementary bit line (/BL) by the read-write circuit (RWC) are connected to the latch node (N) and Each can be stored in the inversion node (/N). The write operation and the read operation are the same as those of a general SRAM cell, and details regarding the general configuration and operation of the SRAM cell will be omitted from illustration and description below.

The first transistor (T1) is turned on in response to the inverted bit value (/D) stored in the inverting node (/N), and the second transistor (T2) responds to the normal bit value (D) stored in the latch node (N). It turns on. The third transistor T3 is turned on in response to the bit value applied to the normal search line (SL), and the fourth transistor T4 is turned on in response to the bit value applied to the complementary search line (/SL).

The NOR type cam cell in FIG. 5 has a first pull-down path including a first transistor (T1) and a third transistor (T3) and a second pull-down path including a second transistor (T2) and a fourth transistor (T4). Includes. As described above, the matching line ML is precharged to a logic high level. Afterwards, the first pull-down path (T1, T2) and the second pull-down path (T2, When at least one of T4) is enabled, the matching line (ML) is discharged to the ground voltage (VSS), and as a result, the voltage of the matching line (ML) corresponds to a value of 0 from a logic high level corresponding to a value of 1. transitions to the logic low level. When both the first pull-down paths (T1, T2) and the second pull-down paths (T2, T4) are disabled, the matching line (ML) maintains a logic high level corresponding to the precharged value of 1.

Figures 6a, 6b, 7a, 7b, 8a, and 8b are diagrams for explaining bit values of search data applied to the content addressable memory.

One bit value of search data can be expressed as a combination of the bit value of the normal search line (SL) and the bit value of the complementary search line (/SL), that is, (SL, /SL). Additionally, one bit value of the entry data stored in the cam cell is a combination of the bit value (D) of the latch node (N) and the inversion bit value (/D) of the inversion node (/N), that is, (D, /D). can be expressed.

6A and 6B show a case where one bit of entry data has a combination corresponding to a value of 0, that is, (D, /D)=(0, 1).

Referring to FIG. 6A, when one bit of search data is applied with a combination corresponding to the value of 0, that is, (SL, /SL) = (0, 1), the first transistor (T1) and the fourth transistor ( T4) is turned on, and the second transistor (T2) and third transistor (T3) are turned off. As a result, both the first pull-down paths (T1, T3) and the second pull-down paths (T2, T4) are disabled, and the matching signal (MAT) maintains the precharged value of 1, indicating a match case.

Referring to Figure 6b, when one bit of search data is applied to a combination corresponding to the value of 1, that is, (SL, /SL) = (1, 0), the first transistor (T1) and the third transistor ( T3) is turned on, and the second transistor T2 and the fourth transistor T4 are turned off. As a result, the second pull-down paths (T2, T4) are disabled, but the first pull-down paths (T1, T3) are enabled, and the matching signal (MAT) is discharged to a value of 0, indicating a mismatch case.

7A and 7B show a case where one bit of entry data has a combination corresponding to the value of 1, that is, (D, /D)=(1, 0).

Referring to FIG. 7A, when one bit of search data is applied with a combination corresponding to the value of 1, that is, (SL, /SL) = (1, 0), the first transistor (T1) and the fourth transistor ( T4) is turned off, and the second transistor (T2) and third transistor (T3) are turned on. As a result, both the first pull-down paths (T1, T3) and the second pull-down paths (T2, T4) are disabled, and the matching signal (MAT) maintains the precharged value of 1, indicating a match case.

Referring to FIG. 7b, when one bit of search data is applied with a combination corresponding to the value of 0, that is, (SL, /SL) = (0, 1), the first transistor (T1) and the third transistor ( T3) is turned off, and the second transistor T2 and the fourth transistor T4 are turned on. As a result, the first pull-down path (T1, T3) is disabled, but the second pull-down path (T2, T4) is enabled, and the matching signal (MAT) is discharged to a value of 0, indicating a mismatch case.

Figures 8a and 8b illustrate the case where one bit of search data has a corresponding doncare value combination, that is, (SL, /SL)=(0, 0). Figure 8a shows a case where one bit of entry data has a combination corresponding to a value of 0, that is, (D, /D) = (0, 1), and Figure 8b shows a case where one bit of entry data has a value of 1. It represents the case of having the corresponding combination, that is, (D, /D)=(1, 0).

Referring to FIGS. 8A and 8B, since a value of 0 is applied to both the normal search line (SL) and the complementary search line (/SL), the third transistor (T2) and the fourth transistor (T4) apply the bit value of the stored entry data. Regardless, it is always turned off. Therefore, when the combination (SL, /SL) = (0, 0) corresponding to the doncare value is applied, the first pull-down path (T1, T3) and the second pull-down path regardless of the bit value of the stored entry data (T2, T4) are all disabled and the matching signal (MAT) maintains the value of 1.

In this way, for the bits to be compared among the bits of the search data, as described with reference to FIGS. 6a, 6b, 7a, and 7b, one of the normal search line (SL) and the complementary search line (/SL) contains 0. You can apply a value to one and a value of 1 to the other. Meanwhile, among the bits of the search data, bits excluded from comparison other than the comparison target bits are the same as the normal search line (SL) and the complementary search line (/SL), as described with reference to FIGS. 8A and 8B. A value of 0 can be applied. Depending on the configuration of the cam cell, a value of 1 may be equally applied to the normal search line (SL) and the complementary search line (/SL) for comparison exclusion bits. For example, if the cam cell has a structure that precharges the matching line to a value of 0 and enables the pull-up paths in case of a mismatch, the same value of 1 is applied to the normal search line (SL) and the complementary search line (/SL). By applying a value, the pull-up paths can be disabled regardless of the bit value stored in the cam cell.

Hereinafter, with reference to FIGS. 9 to 14B, a 1-bit cumulative search operation according to embodiments of the present invention will be described. The 1-bit cumulative search operation refers to repeatedly performing the partial search operation as described above while sequentially increasing the comparison target bits of the search data by one in the direction from the Kth bit corresponding to the most significant bit to the lower bit. Through the 1-bit cumulative search operation, the maximum entry data or minimum entry data among the plurality of entry data stored in the content addressable memory can be determined as the target entry data.

Figure 9 is a flow chart illustrating an example of a maximum entry search operation of a search circuit according to embodiments of the present invention.

Referring to FIG. 9, first, the value of i is initialized to 1 (S101). The (K-i+1)th bit of the search data is set to the value of 1, and the first to (K-i)th bits of the search data are set to the don care value (DCV) (S102). After setting the comparison target bits and comparison exclusion bits of the search data in this way, the i-th partial search operation (PCOi) is performed (S103).

As a result, in the case where the value of i is 1, the Kth bit with a value of 1 is applied to the content addressable memory as the comparison target bit to perform the first partial search operation (OPR1) (S103).

When at least one matching signal (MAT) among the matching signals is activated (e.g., has a value of 1 indicating a match case) (S104: YES), the (K-i+1)th bit of the search data Set to a value of 1 (S105). If all matching signals are deactivated (e.g., have a value of 0 indicating a mismatch case) (S104: NO), the (K-i+1)th bit of the search data is set to the value of 0 ( S106). Afterwards, i is increased by 1 (S109) and these steps (S102 to S106) are repeated.

In this way, based on the matching signals by the ith partial search operation (PCOi) corresponding to i, the number of bits to be compared is (i+1), which is (i+1). The values of bits to be compared in the th partial search operation (PCO(i+1)) can be determined.

In other words, if the target entry data corresponds to the maximum entry data, and at least one of the plurality of matching signals is activated in the ith partial search operation (PCOi), the (K-i+1)th bit is selected according to step S105. It is set to a value of 1, and when all the plurality of matching signals are deactivated in the ith partial search operation (PCOi), the (K-i+1)th bit can be set to a value of 0 according to step S106. Meanwhile, after i is increased by 1, the (K-i)th bit can be set to the value of 1 according to step S102. In this way, the (i+1)th partial search operation (PCO(i+1)) is performed by applying comparison target bits corresponding to the Kth to (K-i+1)th bits to the content addressable memory. You can sequentially perform the second and subsequent partial search operations.

These cyclical steps (S102 to S106, S109) may be repeatedly performed until only one of the matching signals is activated (S107: NO). If only one matching signal among the plurality of matching signals is activated in the ith partial search operation (PCOi) (S107: YES), the part after the (i+1)th partial search operation (PCO(i+1)) Search operations can be omitted.

When only one matching signal among the matching signals is activated (S107: YES), the entry data corresponding to the one matching signal is determined as the maximum entry data, and the result of the maximum entry search operation can be output ( S108). The result may include maximum entry data and/or location information of the maximum entry data.

FIGS. 10A and 10B are diagrams illustrating an example of the maximum entry search operation of FIG. 9.

FIG. 10A shows an example of first to fifth entry data ENT1 to ENT5 stored in a content addressable memory. Each of the first to fifth entry data (ENT1 to ENT5) may include six bits corresponding to the sixth bit (B6) corresponding to the most significant bit to the first bit (B1) corresponding to the least significant bit. . The number of entry data and the number of bits shown in FIG. 10A are exemplary for convenience of illustration and description, and embodiments of the present invention are not limited thereto.

Figure 10b shows the maximum entry search operation corresponding to the data in Figure 10a.

Referring to FIGS. 10A and 10B, the sixth bit (B6) with a value of 1 is applied to the content addressable memory as a comparison target bit to perform the first partial search operation (PCO1). Since the sixth bit (B6) of the first to fifth entry data (ENT1 to ENT5) is all 0, the first to fifth matching signals (MAT1 to MAT5) all have a value of 0, indicating a mismatch.

As a result of the first partial search operation (PCO1), all matching signals are deactivated, so the 6th bit (B6) is set to the value of 0, the 5th bit (B5) is set to the value of 1, and then the 6th and 5th bits are set to the value of 1. The second partial search operation (PCO2) is performed by applying 5 bits (B6, B5) as two comparison target bits to the content addressable memory.

As a result of the second partial search operation (PCO2), only the second matching signal (MAT2) was activated with a value of 1 indicating a match case, so the second entry data (ENT2) corresponding to the second matching signal (MAT2) was set to the maximum entry data ( MAXENT).

FIGS. 11A and 11B are diagrams showing another example of the maximum entry search operation of FIG. 9.

FIG. 11A shows an example of first to fifth entry data ENT1 to ENT5 stored in the content addressable memory, and FIG. 11B shows a maximum entry search operation corresponding to the data in FIG. 11A.

Referring to FIGS. 11A and 11B, the sixth bit (B6) with a value of 1 is applied to the content addressable memory as a comparison target bit to perform the first partial search operation (PCO1). Since the sixth bit (B6) of the first to fifth entry data (ENT1 to ENT5) is all 0, the first to fifth matching signals (MAT1 to MAT5) all have a value of 0, indicating a mismatch.

As a result of the first partial search operation (PCO1), all matching signals are deactivated, so the 6th bit (B6) is set to the value of 0, the 5th bit (B5) is set to the value of 1, and then the 6th and 5th bits are set to the value of 1. The second partial search operation (PCO2) is performed by applying 5 bits (B6, B5) as two comparison target bits to the content addressable memory.

As a result of the second partial search operation (PCO2), the second matching signal (MAT2) and the fourth matching signal (MAT4) are activated with a value of 1 indicating a match case, so the fifth bit (B5) is set to a value of 1, After setting the fourth bit (B4) to the value of 1, the sixth, fifth and fourth bits (B6, B5, B4) are applied to the content addressable memory as three comparison target bits to perform the third partial search operation ( Perform PCO3).

As a result of the third partial search operation (PCO3), all matching signals are deactivated, so the fourth bit (B4) is set to the value of 0, the third bit is set to the value of 1, and then the sixth to third bits are set. (B6 to B3) are applied to the content addressable memory as four comparison target bits to perform the fourth partial search operation (PCO4).

As a result of the fourth partial search operation (PCO4), only the second matching signal (MAT2) was activated with a value of 1 indicating a match case, so the second entry data (ENT2) corresponding to the second matching signal (MAT2) was set to the maximum entry data ( MAXENT).

Figure 12 is a flowchart showing an example of a minimum entry search operation of a search circuit according to embodiments of the present invention.

Referring to FIG. 12, first, the value of i is initialized to 1 (S201). The (K-i+1)th bit of the search data is set to a value of 0, and the first to (K-i)th bits of the search data are set to the don care value (DCV) (S202). After setting the comparison target bits and comparison exclusion bits of the search data in this way, the ith partial search operation (PCOi) is performed (S203).

As a result, when the value of i is 1, the Kth bit with a value of 0 is applied to the content addressable memory as the comparison target bit to perform the first partial search operation (OPR1) (S203).

If at least one matching signal (MAT) among the matching signals is activated (e.g., has a value of 1 indicating a match case) (S204: YES), the (K-i+1)th bit of the search data Set to a value of 0 (S205). If all matching signals are deactivated (e.g., have a value of 0 indicating a mismatch case) (S204: NO), the (K-i+1)th bit of the search data is set to the value of 1 ( S206). Afterwards, i is increased by 1 (S209) and the same steps (202 to 206) are repeated.

In this way, based on the matching signals by the ith partial search operation (PCOi) corresponding to i, the number of bits to be compared is (i+1), which is (i+1). The values of bits to be compared in the th partial search operation (PCO(i+1)) can be determined.

In other words, if the target entry data corresponds to the maximum entry data, and at least one of the plurality of matching signals is activated in the ith partial search operation (PCOi), the (K-i+1)th bit is selected according to step S205. The value is set to 0, and when all the plurality of matching signals are deactivated in the ith partial search operation (PCOi), the (K-i+1)th bit can be set to the value of 1 according to step S206. Meanwhile, after i is increased by 1, the (K-i)th bit can be set to the value of 0 according to step S202. In this way, the (i+1)th partial search operation (PCO(i+1)) is performed by applying comparison target bits corresponding to the Kth to (K-i+1)th bits to the content addressable memory. You can sequentially perform the second and subsequent partial search operations.

These cyclical steps (S202 to S206, S209) may be repeatedly performed until only one of the matching signals is activated (S207: NO). If only one matching signal among the plurality of matching signals is activated in the ith partial search operation (PCOi), partial search operations after the (i+1)th partial search operation (PCO(i+1)) can be omitted. You can.

When only one matching signal among the matching signals is activated (S207: YES), the entry data corresponding to the one matching signal is determined as the minimum entry data, and the result of the minimum entry search operation can be output ( S208). The result may include minimum entry data and/or location information of the minimum entry data.

FIGS. 13A and 13B are diagrams illustrating an example of the maximum entry search operation of FIG. 12.

FIG. 13A shows an example of first to fifth entry data ENT1 to ENT5 stored in a content addressable memory, and FIG. 13B shows a minimum entry search operation corresponding to the data of FIG. 13A.

Referring to FIGS. 13A and 13B, the sixth bit (B6) with a value of 0 is applied to the content addressable memory as a comparison target bit to perform the first partial search operation (PCO1). Since the sixth bit (B6) of the first to fifth entry data (ENT1 to ENT5) is all 0, the first to fifth matching signals (MAT1 to MAT5) all have a value of 1 indicating a match case.

As a result of the first partial search operation (PCO1), at least one matching signal is activated, so the 6th bit (B6) is set to the value of 0, the 5th bit is set to the value of 0, and then the 6th and 5th bits are set to the value of 0. The second partial search operation (PCO2) is performed by applying the bits (B6, B5) as two comparison target bits to the content addressable memory.

Since at least one matching signal is activated as a result of the second partial search operation (PCO2) and the third partial search operation (PCO3), all sixth to third bits (B6 to B3) are set to the value of 0, and Perform the fourth partial search operation (PCO4).

As a result of the fourth partial search operation (PCO4), only the first matching signal (MAT1) was activated with a value of 1 indicating a match case, so the first entry data (ENT1) corresponding to the first matching signal (MAT1) was set to the minimum entry data ( MINENT).

FIGS. 14A and 14B are diagrams showing another example of the minimum entry search operation of FIG. 12.

FIG. 14A shows an example of first to fifth entry data ENT1 to ENT5 stored in a content addressable memory, and FIG. 14B shows a minimum entry search operation corresponding to the data of FIG. 14A.

Referring to Figures 14a and 14b, the sixth bit (B6) with a value of 0 is applied to the content addressable memory as a comparison target bit to perform the first partial search operation (PCO1). Since the sixth bit (B6) of the first to fifth entry data (ENT1 to ENT5) is all 0, the first to fifth matching signals (MAT1 to MAT5) all have a value of 1 indicating a match case.

As a result of the first partial search operation (PCO1), at least one matching signal is activated, so the 6th bit (B6) is set to the value of 0, the 5th bit is set to the value of 0, and then the 6th and 5th bits are set to the value of 0. The second partial search operation (PCO2) is performed by applying the bits (B6, B5) as two comparison target bits to the content addressable memory.

Since at least one matching signal is activated as a result of the second partial search operation (PCO2) and the third partial search operation (PCO3), all sixth to third bits (B6 to B3) are set to the value of 0, and Perform the fourth partial search operation (PCO4).

As a result of the fourth partial search operation (PCO4), the first to fifth matching signals (MAT1 to MAT5) were all deactivated with a value of 0 indicating a mismatch case, so the third bit (B3) was set to a value of 1 and the third bit (B3) was set to a value of 1. 2 After setting bit (B2) to the value of 0, perform the fifth partial search operation (PCO5).

As a result of the fifth partial search operation (PCO5), only the third matching signal (MAT3) was activated with a value of 1 indicating a match case, so the third entry data (ENT3) corresponding to the third matching signal (MAT3) was set to the minimum entry data. Decide on (MINENT).

15 and 16 are diagrams showing memory systems according to embodiments of the present invention.

Referring to FIG. 15 , the memory system 10 includes a memory controller 100 and a memory device 200. Each of the memory controller 100 and the memory device 200 includes an interface for mutual communication. The interfaces can be connected through a control bus 21 for transmitting commands (CMD), access addresses (ADDR), clock signals (CLK), hammer addresses (HADD), etc., and a data bus 22 for transmitting data. there is. The command (CMD) may be considered to include an address (ADDR). The memory controller 100 generates a command signal (CMD) for controlling the memory device 200, and data (DATA) is written to the memory device 200 or the memory device 200 according to the control of the memory controller 100. ) Data (DATA) can be read from.

The memory device 200 includes a hammer address management circuit (HMMAG) 300 that provides a hammer address (HADD) and a refresh controller (RFCON) 400 that performs a hammer refresh operation based on the provided hammer address (HADD). can do.

Referring to FIG. 16, the memory system 11 includes a memory controller 101 and a memory device 201 connected through a control bus 23 and a data bus 24.

Compared to the memory system 10 of FIG. 15, the memory system 11 of FIG. 16 includes a hammer address management circuit (HMMAG) 301 in which the memory controller 101 provides a hammer address (HADD) and a memory device. 201 includes a refresh controller (RFCON) 401 that performs a hammer refresh operation based on the provided hammer address (HADD). In this case, detection and refresh of the hammer address (HADD) are performed in the memory controller 101 and the memory device 201, respectively, to distribute the burden related to the hammer refresh operation, thereby reducing the size of the memory device 201. And the overall performance of the system 11 can be improved.

Figure 17 is a block diagram showing a hammer address management circuit according to embodiments of the present invention.

Referring to FIG. 17, the hammer address management circuit 300 includes a content addressable memory 1010, a content addressable memory (CAM) controller (CAMCON) 1020, an address storage unit 2010, and an address controller (ADDCON). (2020).

The address storage unit 2020 stores a plurality of row addresses (ADD1 to ADDN) based on the access address signal (ADDR). The content addressable memory 1010 includes K bits corresponding to the Kth bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, respectively, and records the access counts of the plurality of row addresses ADD1 to ADDN, respectively. It includes a plurality of CAM cells that store the access count data (ENT1 to ENTN). The content addressable memory 1010 provides a plurality of matching signals indicating whether a plurality of access count data (ENT1 to ENTN) matches search data.

The cam controller 1020 compares some of the first to Kth bits to search for target count data among the plurality of access count data (ENT1 to ENTN) based on the plurality of matching signals. A partial search operation of applying target bits as the search data to the content addressable memory 1010 to determine whether bits of the plurality of access count data corresponding to the comparison target bits match the comparison target bits. Perform.

The address controller 2020 provides a hammer address (HADD) from among a plurality of row addresses (ADD1 to ADDN) stored in the address storage unit 2010 based on a search result of the target count data.

The cam controller 1020 repeatedly performs a partial search operation, that is, performs the maximum entry search operation as described above with reference to FIGS. 9 to 11B to select the maximum count data among the plurality of access count data (ENT1 to ENTN). is determined as the target count data. The address controller 2020 selects the maximum count data from among a plurality of row addresses ADD1 to ADDN stored in the address storage unit 2010 based on the position information MAXPT of the maximum count data provided from the cam controller 1020. The corresponding row address is provided as a hammer address (HADD).

Meanwhile, the cam controller 1020 repeatedly performs a partial search operation, that is, performs the minimum entry search operation as described above with reference to FIGS. 12 to 14B to find the minimum entry number among the plurality of access count data ENT1 to ENTN. Count data is determined as the target count data. The address controller 2020 may replace the row address corresponding to the minimum count data among the plurality of row addresses ADD1 to ADDN stored in the address storage unit 2010 with a new row address. That is, the row address corresponding to the minimum count data can be judged to have a low possibility of being an intensively accessed hammer address and excluded from management.

Meanwhile, the cam controller 1020 may increase or initialize the values of the access count data ENT1 to ENTN based on the access information ADDPT and NEWADD provided from the address controller 2020.

Conventionally, it includes counter circuits for storing access count data values and comparators for determining the maximum and/or minimum value among the access count data values. As the degree of integration of a memory device increases, the number and bits of access count data to be stored increase, and counter circuits and comparators of a large number and size are required. Circuits like these increase the size of the memory device and reduce design margin.

The hammer address management circuit according to embodiments of the present invention reduces the size of the memory device and refreshes the memory device by replacing the comparison function between stored data with a partial search operation for the content addressable memory and a combination of a plurality of partial search operations. The efficiency of operation can be improved.

FIG. 18 is a block diagram illustrating an example of a refresh controller included in a memory device according to embodiments of the present invention.

Referring to FIG. 18, the refresh controller 400 may include a timing controller 410, a refresh counter 420, and an address generator 430.

The timing controller 410 generates a counter refresh signal (CREF) indicating the timing of the normal refresh operation and a hammer refresh signal (HREF) indicating the timing of the hammer refresh operation. As shown in FIGS. 20A, 20B, and 20C, the timing controller 410 can selectively activate the counter refresh signal (CREF) and the hammer refresh signal (HREF). The operation of the timing controller 410 will be described later with reference to FIGS. 20A, 20B, and 20C. The refresh counter 420 generates a counter refresh address signal (CRFADD) indicating an address that changes sequentially in synchronization with the counter refresh signal (CREF). For example, the refresh counter 420 may increase the value of the counter refresh address signal CRFADD by 1 each time the counter refresh signal CREF is activated. In this way, word lines for the normal refresh operation can be sequentially selected one by one by increasing the value of the counter refresh address signal CRFADD by 1.

The address generator 430 stores the hammer address (HADD) provided from the hammer address management circuit 300, and generates a row physically adjacent to the row corresponding to the hammer address (HADD) in synchronization with the hammer refresh signal (HREF). Generates a hammer refresh address signal (HRFADD) indicating the address. The address generator 430 may include a hammer address storage 440 and a mapper 450. The hammer address storage unit 440 stores the hammer address (HADD) provided from the hammer address management circuit 300.

The mapping unit 450 generates a hammer refresh address signal (HRFADD) based on the hammer address (HADD) provided from the hammer address storage unit 440. As described with reference to FIG. 19, the hammer refresh address signal (HRFADD) represents the address of a row that is physically adjacent to the row corresponding to the hammer address (HADD).

FIG. 19 is a diagram showing a portion of a memory cell array to explain data damage caused by coupling between word lines.

In Figure 19, three word lines (WLs-1, WLs, WLs+1) are extended in the row direction (X) and sequentially arranged adjacent to each other in the column direction (Y) within the memory cell array. , three bit lines (BLp-1, BLp, BLp+1) extending in the column direction (Y) and sequentially arranged adjacent to each other in the row direction (X) and memory cells (MC) respectively coupled to them are shown. It is done.

For example, the middle word lines (WLs) may correspond to hammer addresses (HADD) that are intensively accessed. Here, intensive access means that the number of word lines is active is high or the frequency of activation is high. When the hammer word line (WLs) is accessed and active and precharged, that is, when the voltage of the hammer word line (WLs) rises and falls, a coupling phenomenon that occurs between adjacent word lines (WLs-1, WLs+1) As a result, the voltage of adjacent word lines (WLs-1, WLs+1) rises and falls together, affecting the cell charges charged in the memory cells (MC) connected to adjacent word lines (WLs-1, WLs+1). It's crazy. The more frequently the hammer word line (WLs) is accessed, the more likely it is that the cell charges of the memory cells (MC) connected to the adjacent word lines (WLs-1, WLs+1) will be lost and the stored data will be damaged.

The address generator 430 of FIG. 18 generates a hammer refresh address signal indicating the addresses (HRFADD1, HRFADD2) of the row (WLs) corresponding to the hammer address (HADD) and the physically adjacent rows (WLs-1, WLs+1). (HRFADD) and additionally performs a hammer refresh operation on adjacent word lines (WLs-1, WLs+1) based on the hammer refresh address signal (HRFADD) to prevent data damage in memory cells due to intensive access. can be prevented.

20A, 20B, and 20C are timing diagrams showing examples of operations of a refresh controller included in a memory device according to embodiments of the present invention.

20A, 20B, and 20C show the counter refresh signal (CREF), hammer refresh signal (HREF), counter refresh address signal (CRFADD), and hammer refresh address for the refresh signal (IREF) activated in pulse form from t1 to t19. Embodiments regarding the generation of signal HRFADD are shown.

Referring to FIGS. 18 and 20A, the timing controller 410 is synchronized to some (t1 to t4, t6 to t10, t12 to t16, and t18 to t19) of the activation points (t1 to t19) of the refresh signal (IREF). Thus, the counter refresh signal CREF can be activated and the hammer refresh signal HREF can be activated in synchronization with the remaining portions (t5, t11, and t17) of the activation points (t1 to T19) of the refresh signal (IREF).

The refresh counter 420 has addresses (X+1 to Generates a counter refresh address signal (CRFADD) indicating . The address generator 430 generates addresses (Ha, Hb, A hammer refresh address signal (HRFADD) representing Hc) is generated.

As shown in FIG. 20A, the mapping unit 450 of the address generator 430 may provide an address corresponding to one of two adjacent rows. For example, Ha is an address that is 1 smaller than the hammer address at time t5, and Hb is an address that is 1 larger than the hammer address at time t11, such that the hammer address is provided every time the hammer address (MXADD) is activated. Larger addresses and smaller addresses can be provided alternatively.

Hereinafter, the timing diagrams of FIGS. 20B and 20C are similar to those of FIG. 20A, so duplicate descriptions will be omitted. In the case of FIG. 20A, the counter refresh signal (CREF) is deactivated at the point when the hammer refresh signal (HREF) is activated, but as shown in FIG. 20B, the counter refresh signal (CREF) is periodically activated regardless of the hammer refresh signal (HREF). It can be activated with .

Meanwhile, as shown in FIG. 20C, the mapping unit 450 of the address generator 430 may sequentially provide addresses corresponding to two adjacent rows. For example, Ha1 is an address smaller by 1 than the hammer address at time t5, and Ha2 is an address larger than the hammer address at time t5 by 1, such that the hammer address is provided each time the hammer address (MXADD) is activated. Larger addresses and smaller addresses can be provided sequentially.

Figure 21 is a block diagram showing a mobile system including a memory device according to embodiments of the present invention.

Referring to FIG. 21, the mobile system 1200 includes an application processor 1210, a communication unit 1220, a memory device 1230, a non-volatile memory device 1240, a user interface 1250, and a power supply ( 1260).

The application processor 1210 can execute applications that provide Internet browsers, games, videos, etc. The communication unit 1220 may perform wireless or wired communication with an external device. The memory device 1230 may store data processed by the application processor 1210 or operate as a working memory. The non-volatile memory device 1240 may store a boot image for booting the mobile system 1200. User interface 1250 may include one or more input devices, such as a keypad or touch screen, and/or one or more output devices, such as speakers or a display device. Power supply 1260 may supply the operating voltage of mobile system 1200.

In one embodiment, as described with reference to FIG. 15 , the memory device 1230 may include a hammer address management circuit 300 and a refresh controller 400. In another embodiment, as described with reference to FIG. 16 , the application processor 1210 may include a hammer address management circuit 300 and the memory device 1230 may include a refresh controller 400 .

The hammer address management circuit 300 can efficiently search for the maximum and minimum values among the access count values using the search circuit described with reference to FIGS. 1 to 14b and reduce the size of the hammer address management circuit 300. .

Embodiments of the present invention can be usefully used in devices requiring a data search function and systems including the same. In particular, embodiments of the present invention are used in memory cards, solid state drives (SSD), embedded multimedia cards (eMMC), universal flash storage (UFS), computers, and laptops ( Laptop, cellular phone, smart phone, MP3 player, Personal Digital Assistants (PDA), Portable Multimedia Player (PMP), digital TV, digital camera, portable game console ), navigation devices, wearable devices, IoT (internet of things) devices, IoE (internet of everything:) devices, e-books, VR (virtual reality) devices, AR ( It can be more usefully applied to electronic devices such as augmented reality devices.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that you can.

Claims (20)

A plurality of CAM (content addressable memory) cells storing a plurality of entry data each containing K bits corresponding to the Kth bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, a content addressing memory that provides a plurality of matching signals indicating whether a plurality of entry data matches search data; and
In order to search for target entry data among the plurality of entry data based on the plurality of matching signals, comparison target bits corresponding to some of the first to Kth bits are used as the search data in the content addressable memory. and a cam controller that performs a partial search operation to determine whether bits of the plurality of entry data corresponding to the bits to be compared match the bits to be compared,
The cam controller is,
By repeatedly performing the partial search operation while sequentially increasing the bits to be compared by one in the direction from the Kth bit to the lower bit, determining the maximum entry data or minimum entry data among the plurality of entry data as the target entry data. navigation circuit. delete delete According to claim 1,
The cam controller is,
Search for the (i+1)th part where the number of bits to be compared is (i+1) based on the matching signals by the ith partial search operation where the number of bits to be compared is (i+1). A search circuit, characterized in that determining the values of the bits to be compared for operation. According to clause 4,
The cam controller is,
A search circuit, wherein when only one matching signal among the plurality of matching signals is activated in the i-th partial search operation, partial search operations after the (i+1)-th partial search operation are omitted. According to claim 1,
The cam controller is,
When the target entry data corresponds to the maximum entry data, the K-th bit with a value of 1 is applied to the content addressable memory as the comparison target bit to perform a first partial search operation. . According to clause 6,
The cam controller is,
If the target entry data corresponds to the maximum entry data, and if at least one of the plurality of matching signals is activated in the ith partial search operation, set the (K-i+1)th bit to the value of 1, When all of the plurality of matching signals are deactivated in the ith partial search operation, the (K-i+1)th bit is set to a value of 0, and the (Ki)th bit is set to a value of 1 to The second and subsequent partial search operations are sequentially performed by applying the comparison target bits corresponding to the (K-i+1)th to (K-i+1)th bits to the content addressable memory to perform the (i+1)th partial search operation. A search circuit characterized in that it is performed by. According to clause 7,
The cam controller is,
When only one matching signal among the plurality of matching signals is activated, the search circuit determines entry data corresponding to the activated matching signal as the maximum entry data. According to claim 1,
The cam controller is,
When the target entry data corresponds to the minimum entry data, the K-th bit with a value of 0 is applied to the content addressable memory as the comparison target bit to perform a first partial search operation. . According to clause 9,
The cam controller is,
If the target entry data corresponds to the minimum entry data, and if at least one of the plurality of matching signals is activated in the ith partial search operation, set the (K-i+1)th bit to a value of 0, When all of the plurality of matching signals are deactivated in the ith partial search operation, the (K-i+1)th bit is set to a value of 1, and the (Ki)th bit is set to a value of 0 to The second and subsequent partial search operations are sequentially performed by applying the comparison target bits corresponding to the (K-i+1)th to (K-i+1)th bits to the content addressable memory to perform the (i+1)th partial search operation. A search circuit characterized in that it is performed by. According to claim 10,
The cam controller is,
When only one matching signal among the plurality of matching signals is activated, the search circuit determines entry data corresponding to the activated matching signal as the minimum entry data. delete delete delete a memory cell array including a plurality of memory cells;
a hammer address management circuit that determines and provides hammer addresses that are accessed intensively; and
A refresh controller that performs a hammer refresh operation on a row corresponding to the hammer address and a row physically adjacent to the hammer address,
The hammer address management circuit is:
an address storage unit that stores a plurality of row addresses based on an access address signal;
A plurality of CAMs, each including K bits corresponding to the K bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, and storing access count data respectively indicating the number of accesses of the plurality of row addresses. a content addressable memory) comprising cells and providing a plurality of matching signals indicating whether the plurality of access count data matches search data;
In order to search for target count data among the plurality of access count data based on the plurality of matching signals, the comparison target bits corresponding to some of the first to Kth bits are addressed as the search data. a cam controller that applies a partial search operation to a memory to determine whether bits of the plurality of access count data corresponding to the bits to be compared match the bits to be compared; and
A memory system comprising an address controller providing the hammer address from among the plurality of row addresses stored in the address storage unit based on a search result of the target count data. According to claim 15,
The cam controller is,
By repeatedly performing the partial search operation while sequentially increasing the bits to be compared by one in the direction from the Kth bit to the lower bit, the maximum count data or minimum count data among the plurality of access count data is converted to the target count data. A memory system characterized by determining as . According to claim 15,
The cam controller repeatedly performs the partial search operation to determine the maximum count data among the plurality of access count data as the target count data,
The address controller provides a row address corresponding to the maximum count data among the plurality of row addresses stored in the address storage unit as the hammer address. According to claim 15,
The cam controller repeatedly performs the partial search operation to determine minimum count data among the plurality of access count data as the target count data,
The address controller replaces the row address corresponding to the minimum count data among the plurality of row addresses stored in the address storage unit with a new row address. According to claim 15,
The content addressable memory is a binary content addressable memory (BCAM, binary CAM) that stores a value of 0 or a value of 1 in each of the first to Kth bits of the plurality of access count data. system, an address storage unit that stores a plurality of row addresses based on an address signal provided to a memory device;
A plurality of CAMs, each including K bits corresponding to the K bit corresponding to the most significant bit to the first bit corresponding to the least significant bit, and storing access count data respectively indicating the number of accesses of the plurality of row addresses. a content addressable memory) comprising cells and providing a plurality of matching signals indicating whether the plurality of access count data matches search data; and
In order to search for target count data among the plurality of access count data based on the plurality of matching signals, the comparison target bits corresponding to some of the first to Kth bits are addressed as the search data. a cam controller that applies a partial search operation to a memory to determine whether bits of the plurality of access count data corresponding to the bits to be compared match the bits to be compared; and
A hammer address management circuit of a memory system including an address controller that provides a hammer address to be accessed intensively among the plurality of row addresses stored in the address storage unit based on a search result of the target count data.

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