JP5632797B2 - Associative memory and network address search device - Google Patents

Description

  The present invention relates to an associative memory and a network address search device, and more particularly to an associative memory and a network address search device having a configuration for reducing power consumption.

  The content addressable memory (CAM) has a search operation function for determining whether or not the search data matches the stored data in addition to the data read / write function. One entry of search data is composed of a plurality of CAM cells (CAM array), and the CAM cell stores search candidate word bits (stored data). Each entry is provided with a match line to which corresponding CAM cells are coupled in parallel. When the search data matches the stored data, the value of the corresponding match line is maintained in the “1” state, and when the search data does not match, the value of the corresponding match line is in the “0” state.

  The content addressable memory determines whether or not the data corresponding to the search data is stored in the CAM cell by identifying the voltage level of the match line. By using the associative memory as, for example, a table, the associative memory can determine whether or not the search data is stored in the table, and can read the contents corresponding to the table at high speed. Therefore, the associative memory is used, for example, for determination of cache miss / hit in a router and a cache memory for communication use.

  Further, the associative memory pipelines the search operation as disclosed in Patent Documents 1 and 2 in order to perform the search operation at higher speed. In the associative memory disclosed in Patent Document 1, a CAM cell configured by a DRAM (Dynamic Random Access Memory) is used, a clamp circuit is provided in the match line ML, and a search operation is pipelined. In the associative memory disclosed in Patent Document 2, whether or not the remaining search data and the remaining storage data are compared based on the result of comparing a part of the search data and the part of the storage data. A control circuit for controlling is provided, and the search operation is pipelined.

JP 2008-10144 A JP 2005-228461 A

  However, the associative memory disclosed in Patent Document 1 divides a CAM array into a plurality of CAM subarrays, and transmits a result of executing a search operation between the divided CAM subarrays. A circuit is used. Since the flip-flop circuit is composed of a large number of transistors, if a flip-flop circuit is used between each CAM subarray, the content addressable memory has a problem that the layout area of the circuit to be configured becomes large. In addition, the associative memory disclosed in Patent Document 1 uses a large number of flip-flop circuits that consume a large amount of power during operation.

  Furthermore, the associative memory disclosed in Patent Document 2 has a circuit configuration in which a through current flows from the power supply terminal to the ground terminal every time a search operation is executed, and thus there is a problem that power consumption increases. It was.

  Therefore, the present invention has been made to solve the above problems, and in an associative memory in which the search operation is pipelined, the layout area of the circuit to be configured is small, and the consumption when the search operation is executed. An object of the present invention is to provide an associative memory and a network address search device capable of reducing power.

  In order to solve the above-described problem, the present invention divides a memory array having a plurality of memory cells arranged along the match line and connected to the match line into a plurality of sub-arrays. This is an associative memory that sequentially executes a search operation toward the subarray. The subarray performs a search operation on a plurality of memory cells connected to the match line, a match line control unit that controls the match line to a precharge state or a discharge state on the preceding stage of the memory cell, and a subsequent stage on the memory cell. A half latch circuit that transmits the result to the lower sub-array and a full latch circuit that transmits the result of the search operation to the encoder section in the lowermost sub-array. The lowermost sub-array is a full latch instead of the half latch circuit. A circuit is provided, and after the operation of the upper subarray is completed, the match line control unit of the lower subarray controls the match line to a precharge state or a discharge state.

  According to the content addressable memory according to the present invention, after the operation of the upper subarray is completed, the match line control unit of the lower subarray controls the match line to the precharge state or the discharge state, thereby executing the search operation result. Instead of a full latch circuit (for example, a flip-flop circuit), a half latch circuit can be used as a circuit that transmits to a lower subarray. The subarray can use a half latch circuit composed of almost half of the transistors of a full latch circuit (for example, a flip-flop circuit) as a circuit that transmits the result of executing the search operation to the lower subarray. The layout area can be reduced. In addition, since the subarray uses a half latch circuit that consumes less power than the flip-flop circuit, power consumption can be reduced.

It is a block diagram which shows the whole structure of the content addressable memory which concerns on Embodiment 1 of this invention. It is a figure which shows an example of a structure of the CAM cell arranged in the CAM array shown in FIG. It is a block diagram which shows in detail the structure of a part of content addressable memory which concerns on Embodiment 1 of this invention. It is a schematic diagram which shows the structure which divided | segmented the CAM array which concerns on Embodiment 1 of this invention into the some CAM subarray. It is a circuit diagram which shows the detailed structure of the CAM subarray which concerns on Embodiment 1 of this invention. 3 is a timing chart for explaining the operation of the associative memory according to the first embodiment of the present invention. It is a schematic diagram which shows the structure which divided | segmented the CAM array which concerns on Embodiment 2 of this invention into the some CAM subarray. It is a circuit diagram which shows the detailed structure of the CAM subarray which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the system LSI which functions as a network address search apparatus concerning Embodiment 3 of this invention.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing an overall configuration of an associative memory 100 according to Embodiment 1 of the present invention.

  An associative memory 100 shown in FIG. 1 includes a CAM array 10 formed on a semiconductor substrate SUB, a coincidence detection unit 20, a search data transfer unit 30, a search control circuit 40 (control unit), a priority encoder 70, A search result output buffer 81, an address / data buffer 74, an instruction code buffer 75, a clock buffer 76, an instruction code decoder 77, an address decoder 78, and a sense amplifier 79 are included.

  The associative memory 100 includes word lines (word lines WL_X and WL_Y shown in FIG. 2) provided corresponding to each row of the CAM array 10 for normal data writing and data reading, and each column of the CAM array 10. Corresponding bit line pairs (bit line pairs BL and BL_N shown in FIG. 2). Further, the associative memory 100 includes a match line ML (match line) provided corresponding to each row of the CAM array 10 and a search line pair SL provided corresponding to each column of the CAM array 10 for a search operation. , SL_N (search line pair). In this specification, “_N” is added to the end of the reference symbol to indicate a complementary reference symbol in which the logic level is inverted (for example, “0” is inverted to “1”). is there.

  The CAM array 10 includes a plurality of CAM cells (memory cells) arranged in a matrix. Each memory cell stores 1-bit data and has a function of comparing search data with previously stored data.

  The match detector 20 (match amplifier) detects the value (“1” or “0”) of each match line ML. Thereby, the coincidence detection unit 20 detects whether or not the search data matches the data stored in advance (stored data) in each memory cell connected to each match line ML.

  The search data transfer unit 30 (search line pair driver) transfers search data to each memory cell of the CAM array 10 via the search line pair SL, SL_N during a search operation.

  The search control circuit 40 controls the operation timing of the search data transfer unit 30 and the match detection unit 20 based on the input clock signal CLK.

  Based on the detection result of the match detection unit 20, the priority encoder 70 outputs an address where the search data matches the stored data as a search result according to a predetermined priority.

  The search result output buffer 81 outputs the search result received from the priority encoder 70 to the outside via the search result output terminal 82.

  Address / data buffer 74 outputs the address or data received via address / data input terminal 71 to address decoder 78 and sense amplifier 79. Further, the address / data buffer 74 receives multi-bit search data SD and SD_N necessary for the search operation via the address / data input terminal 71 and outputs them to the search data transfer unit 30.

  The instruction code buffer 75 outputs the instruction code received via the instruction code input terminal 72 to the instruction code decoder 77. The instruction code includes an instruction code representing data writing and an instruction code representing a retrieval operation.

  The instruction code decoder 77 decodes the instruction code received from the instruction code buffer 75 and generates a signal corresponding to the instruction content. For example, instruction code decoder 77 generates search signal SCM when it receives an instruction code representing a search operation. The instruction code decoder 77 generates a reset signal RST when receiving an instruction code representing a reset instruction.

  The clock buffer 76 receives a clock signal CLK from the outside via the clock input terminal 73 and outputs it to each part of the associative memory 100.

  Based on the address received from address / data buffer 74, address decoder 78 selects a memory cell group to be written at the time of data writing, and selects a memory cell group to be read at the time of data reading.

  The sense amplifier 79 detects the logic level of the bit line pair BL, BL_N to which the memory cell to be read is connected during data reading.

  FIG. 2 is a diagram showing an example of the configuration of the CAM cells CC arranged in the CAM array 10 shown in FIG. In FIG. 2, a CAM cell CC compares a data storage unit 22 for storing stored data with the stored data and the data of the search line pair SL, SL_N, and a search unit 24 for driving the match line ML according to the comparison result. Including.

  The data storage unit 22 includes two memory cells (X cell and Y cell). These X cell and Y cell have the structure of an SRAM (Static Random Access Memory) cell. Since both the X cell and the Y cell have the same structure, the same reference numerals are assigned to the corresponding portions in the X cell and the Y cell in FIG.

  Each of the X cell and the Y cell couples inverters IV1 and IV2 connected in antiparallel to form a latch circuit for holding data, and storage nodes ND1 and ND2 to bit lines / BLL and BLL, respectively, when conductive. Access transistors TR1 and TR2 are included.

  The access transistors TR1 and TR2 of the X cell become conductive according to the drive signal of the word line WL_X. The access transistors TR1 and TR2 of the Y cell become conductive according to the drive signal for the word line WL_Y. The drive signal for the word line WL_X and the drive signal for the word line WL_Y are generated by a row drive circuit (not shown) at the time of writing and reading data of the CAM cell CC.

  Complementary data BL and BL_N are transmitted to bit lines BLL and / BLL by a write circuit (not shown). Therefore, in each of the X cell and the Y cell, complementary data is stored in storage nodes ND1 and ND2. Data stored in each of the X cell and the Y cell is set according to the stored data. In the CAM cell CC, ternary data can be stored by using two memory cells.

  Search unit 24 includes MOS transistors (insulated gate field effect transistors) TQ1 and TQ2 provided for the X cell, and MOS transistors TQ3 and TQ4 provided corresponding to the Y cell. MOS transistors TQ1 and TQ2 are connected in series between match line ML and the ground node. MOS transistor TQ1 has its gate coupled to storage node ND2 of the cell. MOS transistor TQ2 receives data on search line SL at its gate. MOS transistor TQ3 has its gate coupled to storage node ND2 of the Y cell. MOS transistor TQ4 receives data on search line SL_N at its gate.

  The X cell and the Y cell can individually set storage data in accordance with the drive signal for the word line WL_X and the drive signal for the word line WL_Y. The CAM cell CC realizes a ternary state as described below.

(I) When the storage node ND2 of the X cell is “1” (logic high level) and the storage node ND2 of the Y cell is “0” (logic low level):
In this case, if the data on the search line SL is “1”, both the MOS transistors TQ1 and TQ2 are turned on, and the match line ML is discharged. Therefore, in this state, it is a miss state. On the other hand, if the data on the search line SL is “0”, the MOS transistor TQ2 is off, and the MOS transistor TQ3 is also off. Therefore, in this state, match line ML is not discharged and is maintained at the precharge voltage level. This state is a hit state in which the search data matches the stored data.

(Ii) When the storage node ND2 of the X cell is “0” and the storage node ND2 of the Y cell is “1”:
In this case, if the data on the search line SL is “0”, the data on the search line SL_N is “1”. Therefore, MOS transistors TQ3 and TQ4 are both turned on, and match line ML is discharged. Therefore, this state is a miss state. On the other hand, if the data on the search line SL is “1”, the data on the search line SL_N is “0”. Therefore, MOS transistor TQ4 is turned off, and MOS transistor TQ1 is turned off. Therefore, match line ML is maintained in the precharge voltage state. Therefore, this state is a hit state.

(Iii) When storage node ND2 of both X cell and Y cell is "0":
In this state, MOS transistors TQ1 and TQ3 are both non-conductive. Therefore, match line ML is maintained at the precharge voltage level regardless of data on search line SL. Therefore, in this state, the “don't care state (X state)” can be realized for the search line SL.

(Iv) When the storage node ND2 of both the X cell and the Y cell is “1”:
In this state, according to the data on search line SL, one of the paths of MOS transistors TQ1 and TQ2 and the paths of MOS transistors TQ3 and TQ4 is rendered conductive, and match line ML is discharged. Therefore, since a miss state is always designated regardless of search data, this state is normally a prohibited state.

  As described above, the CAM cell CC has a state in which “0” is stored as the storage data in the state (i), a state in which “1” is stored as the storage data in the state (ii), and a don't care in the state (iii). Three-value data including the state can be stored. However, the CAM cell CC may be a CAM cell that stores binary data. As a CAM cell for storing binary data, the data storage unit may be composed of one SRAM cell. Complementary storage nodes of one SRAM cell are coupled to the respective gates of transistors TQ1 and TQ3 of the search unit.

Hereinafter, the components related to the search operation will be described in more detail.
FIG. 3 is a block diagram showing in detail the configuration of a part of the associative memory 100 according to Embodiment 1 of the present invention. In the associative memory 100 shown in FIG. 3, a case where the search operation is not pipelined will be described for the sake of simplicity. FIG. 3 shows the CAM array 10, the match detection unit 20, the search data transfer unit 30, and the search control circuit 40 that are necessary for explaining the search operation.

  The CAM array 10 includes a plurality of memory cells (CAM cells) arranged in a matrix of n rows and m columns. In FIG. 3, m = 80. Hereinafter, a CAM cell in the i-th row and j-th column (i is an integer of 1 to n-1 and j is an integer of 1 to m-1) is referred to as a CAM cell CC [i-1, j-1]. , When referring generically to CAM cells or indicating unspecified CAM cells, it is described as CAM cell CC. Further, the row direction of the CAM array 10 is referred to as an X direction, and the column direction is referred to as a Y direction. When distinguishing the direction in the X direction, it is described with a reference numeral such as + X direction and -X direction. The same applies to the Y direction.

  The associative memory 100 shown in FIG. 3 is provided corresponding to the row of the CAM array 10 and includes n match lines ML [0] to ML [n−1] extending in the X direction. Furthermore, the associative memory 100 is provided corresponding to the column of the CAM array 10, and m pairs of search lines SL [0], SL_N [0] to SL [m−1], SL_N [m−] extending in the Y direction. 1]. The match lines ML [0] to ML [n−1] and the search line pairs SL [0], SL_N [0] to SL [79], SL_N [79] are collectively or unspecified match lines and search lines. When indicating a pair, they are described as a match line ML and a search line pair SL, SL_N, respectively. Each CAM cell CC is provided corresponding to each intersection of n match lines ML and m pairs of search lines SL, SL_N. Each CAM cell CC is connected to a corresponding match line ML and a corresponding search line pair SL, SL_N.

  The associative memory 100 further includes precharge units PC [0] to PC [n−1] connected to n match lines ML [0] to ML [n−1], respectively. The precharge units PC [0] to PC [n−1] are also referred to as a precharge unit PC when collectively referring to an unspecified precharge unit. When the match line precharge signal MLPRE_N received from the search control circuit 40 becomes active (“0”), each precharge unit PC sets the corresponding match line ML to a predetermined voltage (in the case of FIG. 3, the power supply voltage ) To precharge. Each precharge unit PC is provided at the end of the corresponding match line ML on the −X direction side, that is, close to the match detection unit 20 (match amplifiers MA [0] to MA [n−1]).

  The associative memory 100 compares multi-bit search data (search word) with stored data (storage word) stored in advance for each entry configured by a plurality of CAM cells CC. In the associative memory 100 shown in FIG. 3, one entry is configured by one row (80 cells) of CAM cells CC connected to each match line ML. That is, the entry bit width is 80 bits. The search word is input to each entry of the CAM array 10 through 80 search line pairs SL and SL_N. The associative memory 100 compares the input search word and storage word for each CAM cell CC (bit unit).

  The search operation will be briefly described. First, the value of each match line ML is precharged to “1” by the precharge unit PC. Next, search data is input to each CAM cell CC via the corresponding search line pair SL, SL_N. The associative memory 100 compares the input search data with 1-bit stored data stored in advance in each CAM cell CC, and discharges the corresponding match line ML in the precharged state when they do not match. Then, the logic level of the corresponding match line ML is changed.

  Accordingly, when all the stored data of the plurality of CAM cells CC connected to each match line ML match the search data (hit: HIT), that is, when the search word and the storage word match, the match line ML The value of is maintained at “1”. When the storage data of at least one CAM cell CC connected to each match line ML does not match the search data (miss: MISS), that is, when the search word does not match the storage word, the match line ML is precharged. The charged charges are discharged, and the value of the match line ML changes to “0”.

  In the search operation, the value of the match line ML is precharged to “0” and charged to “1” when the stored data matches the search data, or the value of the match line ML is set to “1”. A case where precharge is performed and the stored data and the search data coincide with each other and discharged to “0” can be considered. In the present application, the search operation is not particularly limited.

  Next, the content addressable memory 100 when the search operation is pipelined will be described. The associative memory 100 divides the CAM array 10 shown in FIG. 3 into a plurality of subarrays, and sequentially executes a search operation from the upper CAM subarray toward the lower CAM subarray.

  FIG. 4 is a schematic diagram showing a configuration in which the CAM array 10 according to Embodiment 1 of the present invention is divided into a plurality of CAM subarrays. The CAM array 10 shown in FIG. 4 is divided into four CAM subarrays 10a to 10d. VB (valid bit) data is input to the CAM sub-array 10 a, and the CAM sub-array 10 d outputs the result (ZMAT signal) of the search operation to the priority encoder 70. As shown in FIG. 3, when CAM cells CC are arranged in 80 columns (m = 80), the CAM sub-arrays 10a to 10d are divided into 20 columns, each including a 20-bit CAM cell CC.

  The CAM subarrays 10a to 10c include a match line control unit 11 that controls the match line ML in a precharge state or a discharge state, a 20-bit CAM cell CC, and a half for sending a result of executing a search operation to a lower CAM subarray. A latch circuit 12 is included. In addition to the configuration of the CAM subarrays 10a to 10c, the CAM subarray 10d includes a slave latch circuit 13 that transmits the result of executing the search operation to the priority encoder 70. The half latch circuit 12 and the slave latch circuit 13 of the CAM sub-array 10d constitute a master-slave type D-FF (FlipFlop) circuit that is a full latch circuit.

  The match line control unit 11 controls the match line ML to a precharge state or a discharge state before the CAM cell CC. The half latch circuit 12 transmits the result of the search operation to the lower CAM sub-array after the CAM cell CC. The CAM subarray including the match line control unit 11, the CAM cell CC, and the half latch circuit 12 constitutes one stage in the pipeline. The CAM array 10 shown in FIG. 4 is divided into four CAM sub-arrays 10a to 10d and described as a pipeline configuration having four stages, but the number of divisions may be any even odd number.

  The CAM array 10 performs a search operation sequentially from the left CAM sub-array 10a in the drawing, and transmits the result of executing the search operation to the priority encoder 70 through four stages leading to the right CAM sub-array 10d in the drawing. For example, in the first stage, when the CAM subarray 10a does not match the stored data of the at least one CAM cell CC and the search data (miss: MISS), the CAM subarrays 10b to 10d are connected to the match line ML in the second stage and thereafter. Is not put into the precharge state, but is controlled to the discharge state. Therefore, the CAM array 10 can transmit the result of executing the search operation (miss information) to the priority encoder 70. In all stages, when the stored data and the search data of all the CAM cells CC match (hit: HIT), the CAM array 10 uses the priority encoder to obtain the result of the search operation (hit information). 70 can be transmitted.

  In the case of the conventional associative memory, in the first stage, even when the storage data and the search data of at least one CAM cell CC do not match (miss: MISS), in the first stage, the CAM subarray Match line ML is set to a precharge state. For this reason, the conventional associative memory puts the match line ML in a precharge state unnecessarily, so that the power consumed by the match line control unit is large. Therefore, associative memory 100 according to the present embodiment reduces the power consumed by the match line control unit by executing the search operation without using match line ML unnecessarily as described above.

  FIG. 5 is a circuit diagram showing a detailed configuration of the CAM subarray according to Embodiment 1 of the present invention. The CAM array 10 shown in FIG. 5 is a circuit diagram of the CAM subarray 10a and the CAM subarray 10d. Note that the CAM subarray 10b and the CAM subarray 10c have the same circuit configuration as that of the CAM subarray 10a, and thus the illustration thereof will not be repeated.

  The CAM sub-array 10 a includes a match line control unit 11, a 20-bit CAM cell CC, and a half latch circuit 12. The match line control unit 11 includes two p-type transistors 11a and 11b connected in series between the match line ML and the power supply terminal, and two n connected in series between the match line ML and the ground terminal. Type transistors 11c and 11d. When the value of the PRE_N [0] line for the p-type transistor 11a and the value of the PRE_ENA_N [0] line for the p-type transistor 11b are “0”, the match line control unit 11 sets the match line ML to the precharged state. To do. When the value of the n-type transistor 11c is MAN_N [0] line and the value of the PRE_ENA_N [0] line is “1”, the n-type transistor 11d is turned on, and the match line control unit 11 puts the match line ML into a discharge state. . The half latch circuit 12 includes a two-input NAND circuit 12a and inverters 12b to 12d. The numbers in [0] represent the numbers of wirings connected to the CAM subarray, [0] is the number of wirings connected to the CAM subarray 10a, [1] is the number of wirings connected to the CAM subarray 10b, [ 2] represents the number of the wiring connected to the CAM subarray 10c, and [3] represents the number of the wiring connected to the CAM subarray 10d.

  The CAM subarray 10d includes a slave latch circuit 13 in addition to the configuration of the CAM subarrays 10a to 10c. The half latch circuit 12 and the slave latch circuit 13 of the CAM sub-array 10d constitute a master-slave type D-FF circuit that is a full latch circuit, and includes a two-input NAND circuit 12a, inverters 12b to 12d, and inverters 13b to 13d. .

  The half latch circuit 12 can be configured by substantially half an inverter (transistor) compared to a master-slave type D-FF circuit which is a full latch circuit. For this reason, the content addressable memory 100 can reduce the layout area of the circuit to be configured. Further, since the half latch circuit 12 only needs to drive approximately half of the inverter in comparison with the master-slave type D-FF circuit which is a full latch circuit, the associative memory 100 can reduce power consumption. it can.

  Next, the operation of the content addressable memory 100 according to Embodiment 1 of the present invention will be described. FIG. 6 is a timing chart for explaining the operation of the associative memory 100 according to the first embodiment of the present invention. Hereinafter, in order to explain the operation of the associative memory 100 in an easy-to-understand manner, a case where VB data is valid will be described. That is, in the first stage [stage1], the match line control unit 11 of the CAM sub-array 10a always sets the match line ML to the precharge state. When the VB data is invalid (entry invalid), the match line control unit 11 of the CAM array 10 does not put the match lines ML for one entry (four CAM subarrays 10a to 10d) in a precharged state. That is, the value of the match line ML for one entry is always “0”.

  First, in the first stage, when the value of the PRE_N [0] line becomes “0”, the CAM sub-array 10a sets the match line ML to the precharge state. As shown in FIG. 6, the value of the PRE_ENA_N [0] line is also “0”. After the match line ML is set to the precharge state, in the first stage, the CAM sub-array 10a executes a search operation. When the search operation is executed, the match line ML is discharged, so that the value of the match line ML changes from “1” to “0”. A two-input NAND circuit 12a is provided so that a through current does not flow through a CMOS transistor located at a later stage due to a slow transition time in which the value of the match line ML changes from “1” to “0”. When a low amplitude value is adopted as the value of the match line ML, a sense amplifier is used instead of the 2-input NAND circuit 12a.

  Next, the 2-input NAND circuit 12a inputs the value of the match line ML to the inverter 12b of the half latch circuit 12 when the value of the MAE [0] line is “1”. That is, the two-input NAND circuit 12a determines that the result of the search operation of the CAM subarray 10a is “0” if the hit information is “1”, and “1” if the miss information is “0”. It outputs to the inverter 12b. When the value of the LAT [0] line is “1”, the half latch circuit 12 transmits the value of the match line ML to the CAM subarray 10b of the second stage [stage2].

  As shown in FIG. 6, the value of the LAT [0] line becomes “1” when the CAM sub-array 10a is operating (first stage), and therefore, the match line ML when the CAM sub-array 10a is operating (first stage). Is transmitted to the CAM sub-array 10b. However, the match line control unit 11 in the second stage controls the match line ML to the precharge state or the discharge state after the operation of the CAM subarray 10a (first stage) is completed, so that the CAM subarray 10a is in operation ( Even if the value of the match line ML is transmitted to the CAM sub-array 10b in the first stage), no malfunction occurs.

  That is, the value of the match line ML is transmitted to the CAM subarray 10b of the second stage while the CAM subarray 10a is operating (first stage) using the D-FF circuit instead of the half latch circuit as in the conventional associative memory. It is not necessary to have a configuration that is not performed. Therefore, the content addressable memory 100 according to the present embodiment can reduce the layout area of the circuit to be configured by using the half latch circuit 12 instead of the D-FF circuit.

  Next, when the value of the LAT [0] line becomes “0”, the CAM_CLK signal becomes “1”, and the CAM sub-array 10b starts operating in the second stage. One cycle of the CAM_CLK signal corresponds to the operation of the CAM subarray in each stage. When the value of the LAT [0] line becomes “0”, the operation of the CAM subarray 10a in the first stage and the operation of the CAM subarray 10b in the second stage are completely separated. Can operate completely independently. Further, as shown in FIG. 5, the half latch circuit 12 does not have a circuit configuration in which a through current flows from the power supply terminal to the ground terminal every time the search operation is performed. Therefore, the content addressable memory 100 can reduce power consumption. it can.

  Next, in the second stage, when the result of executing the search operation of the upper CAM subarray 10a (first stage) is the hit information “1” (at the time of the upper hit), the CAM subarray 10b Since the value of the match line ML output from the (first stage) half latch circuit 12 is “0” (previous value (PRE_ENA_N [1])), the value of the PRE_ENA_N [0] line becomes “0”. , The match line ML is set to the precharge state. The CAM sub-array 10b sets the match line ML to the precharged state, thereby obtaining the hit information “1” as a result of executing the search operation of the upper CAM sub-array 10a (first stage). 2 stage) search operation.

  In the second stage, when the result of executing the search operation of the upper CAM subarray 10a (first stage) is miss information “0” (at the time of the upper miss), the CAM subarray 10b Since the value of the match line ML output from the half latch circuit 12 of the stage) is “1” (previous value (PRE_ENA_N [1])), the value of the PRE_ENA_N [0] line becomes “0”. The match line ML is not put in the precharge state. The CAM sub-array 10b has a period in which the value of the MAE_N [1] line is “1” longer than the period in which the match line ML is in the precharge state (the period in which the value of the MAE [1] line is “0” in FIG. 6). ), The match line ML is set to a discharge state. The CAM sub-array 10b sets the match line ML to the discharge state, and thereby, information on the error “0” as a result of executing the search operation of the upper CAM sub-array 10a (first stage) is transferred to the lower CAM sub-array 10b (second Stage) search operation. Note that if the result of executing the search operation of the CAM subarray in any stage is misinformation, the CAM subarrays subsequent to that stage did not set the match line ML to the precharged state and executed the search operation. The result is information about a mistake.

  In the third and fourth stages ([stage3], [stage4]), the CAM subarrays 10c and 10d perform the same operation as the second stage CAM subarray 10b, and thus the same description will not be repeated.

  Since the fourth stage CAM sub-array 10d includes the slave latch circuit 13, the half latch circuit 12 and the slave latch circuit 13 constitute a master-slave D-FF circuit that is a full latch circuit. . The CAM subarray 10d transmits the result of executing the search operation to the priority encoder 70 at the timing when the value of the MAT_CLK line becomes “1” (fifth stage [stage5]). That is, the CAM sub-array 10d transmits the result of executing the search operation to the priority encoder 70 using the D-FF circuit as in the conventional associative memory.

  As described above, in the content addressable memory 100 according to the first exemplary embodiment, the match line control unit 11 of the lower CAM subarray controls the match line ML to the precharge state or the discharge state after the operation of the upper CAM subarray is finished. Thus, the half latch circuit 12 can be used instead of the full latch circuit (for example, flip-flop circuit) for the circuit that transmits the result of executing the search operation to the lower CAM subarray. The CAM subarray uses the half latch circuit 12 composed of substantially half of the transistors of the full latch circuit (for example, flip-flop circuit) as a circuit that transmits the result of executing the search operation to the lower CAM subarray. The layout area can be reduced. Further, since the CAM subarray uses a half latch circuit that consumes less power than the flip-flop circuit, power consumption can be reduced.

  In addition, the content addressable memory 100 according to the first exemplary embodiment pipelines the search operation, and if the result of executing the search operation of the CAM subarray in a certain stage becomes information on a mistake, Since the match line ML is not put in the precharge state, the power consumed by the match line control unit is reduced without wastefully putting the match line ML in the precharge state.

  In the conventional associative memory, when the result of executing the search operation is consecutively miss-miss-miss-miss, the power required to put the match line ML into the precharge state four times becomes the worst case of power consumption. . However, the content addressable memory 100 according to the first exemplary embodiment requires the power required to put the match line ML in the precharge state twice when the result of executing the search operation is continuous with hit-miss-hit-miss. Is the worst case of power consumption. Therefore, the worst-case power consumption of the associative memory 100 according to the first embodiment is approximately half that of the conventional associative memory.

  Further, the content addressable memory 100 according to the first exemplary embodiment completely stops the control for setting the match line ML in the entry to the precharge state by inputting the VB data to the match line control unit 11 in the first stage. Therefore, the power consumption when the entry is invalid can be suppressed.

  Further, associative memory 100 according to the first embodiment, as shown in FIG. 5, half latch circuit 12 is not a circuit configuration in which a through current flows from a power supply terminal to a ground terminal every time a search operation is performed. The associative memory 100 can reduce power consumption.

  Furthermore, in the associative memory 100 according to the first embodiment, the match line control unit 11 can set the match line ML to the discharge state, so that the match line ML becomes an intermediate potential or the like according to the result of executing the search operation. It is possible to suppress a through current from flowing through the transistors of the lower CAM subarray.

  The match line control unit 11 includes p-type transistors 11a and 11b for setting the match line ML in a precharge state, and n-type transistors 11c and 11d for setting the match line ML in a discharge state. As shown in FIG. 6, since the period during which the match line ML is in the discharge state can be made longer than the period during which the match line ML is in the precharge state, the n-type transistors 11c and 11d are connected to the p-type transistor 11a. , 11b may have a smaller driving capability. Therefore, the n-type transistors 11c and 11d can be reduced in size compared to the p-type transistors 11a and 11b.

  In addition, since the associative memory 100 according to the first embodiment divides the match line ML into a plurality of lines in order to form a pipeline, the charge / discharge capacity of the match line ML is reduced, and the search operation speed ( The frequency of the search operation can be increased.

  In the match line control unit 11 according to the first embodiment, the gate of the p-type transistor 11a is connected to the PRE_N line, and the gate of the p-type transistor 11b is connected to the PRE_ENA_N line. In the match line control unit 11 according to the first embodiment, the gate of the n-type transistor 11c is connected to the MAN_N line, and the gate of the n-type transistor 11d is connected to the PRE_ENA_N line.

  However, in the match line control unit 11 according to the first embodiment, the gate of the p-type transistor 11a is on the PRE_ENA_N line, the gate of the p-type transistor 11b is on the PRE_N line, the gate of the n-type transistor 11c is on the PRE_ENA_N line, and n The gate of the type transistor 11d may be connected to the MAN_N line. By changing to such a connection, the match line control unit 11 can speed up the operation when the match line ML is set to the precharge state or the discharge state.

(Embodiment 2)
FIG. 7 is a schematic diagram showing a configuration in which the CAM array 10 according to Embodiment 2 of the present invention is divided into a plurality of CAM subarrays. The associative memory 100 according to the second embodiment of the present invention has the same configuration as that of the associative memory 100 according to the first embodiment.

  The CAM array 10 shown in FIG. 7 is divided into four CAM subarrays 10a to 10d. VB (valid bit) data is input to the CAM sub-array 10 a, and the CAM sub-array 10 d outputs the result (ZMAT signal) of the search operation to the priority encoder 70. As shown in FIG. 3, when CAM cells CC are arranged in 80 columns (m = 80), the CAM sub-arrays 10a to 10d are divided into 20 columns, each including a 20-bit CAM cell CC.

  The CAM subarrays 10 a to 10 c include a 20-bit CAM cell CC and a control circuit 15. The control circuit 15 includes a match line control unit that controls the match line ML in a precharge state or a discharge state, and a half latch circuit for sending a result of executing a search operation to a lower CAM subarray. In addition to the configuration of the CAM subarrays 10a to 10c, the CAM subarray 10d includes a slave latch circuit 13 that transmits the result of executing the search operation to the priority encoder 70. The half latch circuit and slave latch circuit 13 included in the control circuit 15 constitute a master-slave type D-FF circuit which is a full latch circuit.

  The CAM array 10 shown in FIG. 7 supplies control signals to the CAM subarray 10a and the CAM subarray 10b through the same wiring 16, and to the CAM subarray 10c and the CAM subarray 10d through the same wiring 17. . The CAM array 10 shown in FIG. 7 is divided into four CAM sub-arrays 10a to 10d and described as a pipeline configuration having four stages. However, the number of divisions may be any even odd number.

  The CAM array 10 performs a search operation sequentially from the left CAM sub-array 10a in the drawing, and transmits the result of executing the search operation to the priority encoder 70 through four stages leading to the right CAM sub-array 10d in the drawing.

  FIG. 8 is a circuit diagram showing a detailed configuration of the CAM subarray according to Embodiment 2 of the present invention. The CAM subarray 10 a shown in FIG. 8 includes a 20-bit CAM cell CC and a control circuit 15. The control circuit 15 includes a match line control unit 11 and a half latch circuit 12 having the same circuit configuration as that shown in FIG. The CAM subarray 10d includes a slave latch circuit 13 in addition to the configuration of the CAM subarrays 10a to 10c.

  The CAM subarray 10a and the CAM subarray 10b are commonly connected to the MAE [0] line, the MAE_N [0] line, the LAT [0] line, the LAT_N [0] line, and the PRE_N [0] line. The CAM subarray 10c and the CAM subarray 10d are commonly connected to the MAE [1] line, the MAE_N [1] line, the LAT [1] line, the LAT_N [1] line, and the PRE_N [1] line. The numbers in [0] represent the numbers of wirings connected to the CAM subarrays, [0] represents the numbers of wirings connected to the CAM subarrays 10a and 10b, and [1] represents the wirings connected to the CAM subarrays 10c and 10d. Each number is represented.

  Since the operation of the content addressable memory 100 according to Embodiment 2 of the present invention is also the same as that of the content addressable memory 100 according to Embodiment 1, the description thereof will not be repeated.

  As described above, in the content addressable memory 100 according to the second exemplary embodiment of the present invention, the wiring connected to the CAM subarray is common to the two adjacent CAM subarrays, so that the control signal supplied to the wiring is reduced. Power consumption can be reduced. Further, the content addressable memory 100 according to the second exemplary embodiment of the present invention can reduce the layout area of the circuit to be configured by reducing the number of wirings.

  Furthermore, the content addressable memory 100 according to the second exemplary embodiment of the present invention reduces the layout area of the circuit to be configured by arranging the match line control unit 11 and the half latch circuit 12 together as one control circuit 15. Can do.

(Embodiment 3)
FIG. 9 is a block diagram showing a configuration of a system LSI that functions as a network address search apparatus according to Embodiment 3 of the present invention.

  A system LSI 130 shown in FIG. 9 includes a TCAM cell array 131 using a content addressable memory 100 according to the first embodiment (FIGS. 4 and 5) or a content addressable memory 100 according to the second embodiment (FIGS. 7 and 8), a priority control unit ( Priority encoder) 132 and action memory 133.

  As described above, the network address search apparatus according to the third embodiment of the present invention uses the associative memory 100 according to the first embodiment or the associative memory 100 according to the second embodiment for the TCAM cell array 131. Electric power can be reduced. In addition, the network address search device according to Embodiment 3 of the present invention can reduce the layout area of the circuits constituting the TCAM cell array 131.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 array, 10a to 10d subarray, 11 match line control unit, 11a, 11b p-type transistor, 11c, 11d n-type transistor, 12 half latch circuit, 13 slave latch circuit, 15 control circuit, 16, 17 wiring, 20 coincidence detection Unit, 22 data storage unit, 24 search unit, 30 search data transfer unit, 40 search control circuit, 70 priority encoder, 71 data input terminal, 72 instruction code input terminal, 73 clock input terminal, 74 data buffer, 75 instruction code buffer 76 clock buffer, 77 instruction code decoder, 78 address decoder, 79 sense amplifier, 81 search result output buffer, 82 search result output terminal, 100 content addressable memory, 131 cell array, 133 action memory.

Claims (8)

A memory array having a plurality of memory cells arranged along the match line and each connected to the match line is divided into a plurality of subarrays, and search operations are executed in order from the upper subarray to the lower subarray. Associative memory
The subarray is
A plurality of the memory cells connected to the match line;
A match line control unit for controlling the match line to a precharge state or a discharge state in a previous stage of the memory cell;
A half latch circuit that transmits a result of executing a search operation to the lower subarray after the memory cell;
The lowermost subarray includes a full latch circuit that transmits a result of executing a search operation to the encoder unit, and
An associative memory in which the match line control unit of the lower subarray controls the match line to a precharge state or a discharge state after the operation of the upper subarray.   The match line control unit includes a p-type transistor connected between the match line and a power supply terminal, and an n-type transistor connected between the match line and a ground terminal. Associative memory.   3. The content addressable memory according to claim 2, wherein the match line control unit turns on the p-type transistor or the n-type transistor after the operation of the upper subarray.   The content addressable memory according to claim 2 or 3, wherein the n-type transistor is smaller in size than the p-type transistor.   The full latch circuit is a flip-flop circuit having a master latch circuit that holds a result transmitted from the sub-array and a slave latch circuit that transmits a result held by the master latch circuit to the encoder unit. The associative memory according to claim 4.   The content addressable memory according to claim 5, wherein the master latch circuit has the same circuit configuration as the half latch circuit.   The content addressable memory according to any one of claims 1 to 6, wherein a wiring connected to the subarray is common to two adjacent subarrays. A network address search device for searching whether an input network address matches stored data,
An associative memory according to any one of claims 1 to 7,
A network address search device comprising: a control unit that controls the associative memory.

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