KR102581094B1 - Plasma treatment method - Google Patents

Abstract

A plasma treatment method is provided that can improve the etching selectivity of the etching material to the mask material and reduce the roughness of the sidewall of the mask pattern.
A plasma processing method for selectively depositing a deposition film on a mask material with respect to an etching material controls etching parameters so that the incubation time of the mask material is shorter than the incubation time of the etching material.

Description

Plasma treatment method

The present invention relates to a plasma treatment method.

In the manufacturing process of semiconductor devices and devices such as MEMS (Micro Electro Mechanical Systems), response to miniaturization and integration of components included in semiconductor devices, etc. is required. For example, in integrated circuits and MEMS systems, nanoscale structures are being promoted further.

Typically, in the manufacturing process of semiconductor devices, lithography technology is used to form fine patterns. This technology applies a photoresist material onto a laminated thin film formed on a semiconductor substrate, irradiates it with ultraviolet rays or the like using an exposure device, transfers the circuit pattern of the photomask to the photoresist material, and performs development. By doing this further, a fine pattern of photoresist is formed. Thereafter, the photoresist pattern is used as an etching mask and an etching process using plasma is performed to selectively remove the thin film, thereby realizing a pattern similar to the photomask as a three-dimensional object.

Recently, in order to cope with the acceleration of miniaturization of LSI (Large Scale Integration), the resolution of the exposure device has been improved in the pattern transfer process using the exposure device. In general, in order to advance miniaturization, it is necessary to improve the exposure wavelength (λ), lens numerical aperture (NA), and process constant (k1) determined by resist performance or transfer process. Recently, the exposure wavelength has been shortened by adoption of an ArF laser (wavelength 193 nm), and NA has been improved by immersion exposure technology.

Double patterning technology is also being adopted to improve k1 by further dividing the circuit pattern mask into two masks and enlarging the minimum pitch of the exposure pattern. Regarding double patterning technology, various methods have been proposed for exposure and development. For example, a double exposure method in which exposure is continuously performed once, an etching process is performed after the first exposure and then a second exposure is performed, or a spacer is deposited after pattern formation and the spacer is used as a mask pattern. There are self-alignment methods, etc.

However, when using these techniques for performing exposure multiple times, problems such as an increase in the number of steps, a decrease in throughput, and an increase in manufacturing cost arise. Therefore, patterning methods using EUV (Extreme ultraviolet) lithography technology using extreme ultraviolet rays with a wavelength of 13.5 nm or DSA (Directed self assembly) lithography technology using self-organizing materials are also beginning to be adopted.

EUV lithography technology can achieve resolution finer than 20 nm half pitch in a single exposure by using extreme ultraviolet rays with a wavelength of 13.5 nm, and is therefore being adopted as an exposure technology responsible for the next generation of ArF immersion lithography. Since EUV lithography technology uses extremely short wavelengths, the biggest advantage is that high resolution can be obtained even with low NA according to Rayleigh's equation.

In theory, resolution finer than a line width of 10 nm can be obtained when the line width is 22 to 32 nm at NA = 0.25, the line width is 16 nm at NA = 0.35, and the line width is 10 nm or more at NA = 0.4, so EUV lithography technology is expected to be an ultra-fine pattern exposure technology. is rising. The resist used in EUV lithography technology (hereinafter referred to as “EUV resist”) is, for example, SiARC (Silicon Anti Reflection Coating), which is an anti-reflection coating of Si-containing material, or SOG (Spin) based on hydroxysilsesquioxane. A patterning structure on glass is generally adopted.

On the other hand, DSA lithography technology performs pattern formation using phase separation of the material itself without requiring a special exposure device. As self-assembling materials, diblock polymers composed of hydrophilic and hydrophobic polymers are standardly used, and representative examples include diblocks of polystyrene (hereinafter abbreviated as “PS”) and polymethacrylic acid (hereinafter abbreviated as “PMMA”). There are polymers. The patterning process of DSA lithography technology is extremely simple, requiring only the creation of a guide pattern before applying the diblock polymer, the formation of a neutral film (hereinafter abbreviated as “NUL”), and the baking after application.

Pattern formation using DSA lithography technology is also called a dry development process because after pattern formation, PMMA is dry-etched with plasma and developed. Afterwards, PS formed by PMMA etching is used as a mask material, and the etching material is Etch NUL.

In this way, a characteristic of the mask patterned by EUV lithography technology and DSA lithography technology is that it is a thin film with a very low mask height. In the case of EUV lithography technology, taking into account the resolution of the resist and pattern collapse during development, the mask height is generally set to 30 nm or less. Meanwhile, in the case of DSA lithography technology, the mask height is generally 30 nm or less, which is the same as the pitch width (PS width + PMMA width).

In the case of a thin film mask with a very low mask height, it is very important to selectively etch the etching target film with respect to the mask material. In addition, with miniaturization, reduction of pattern edge roughness is becoming important, and in particular, reduction of LER (Line Edge Roughness) and LWR (Line Width Roughness) of line patterns is required. .

The reason is that the width of the gate pattern, that is, the gate length, greatly affects transistor performance. Specifically, LWR, whose period is shorter than the transistor width Wg, causes a short channel effect in which the gate length is locally shortened, thereby increasing the leak current and lowering the threshold voltage. On the other hand, LWR, which has a period longer than the transistor width Wg, causes fluctuations in the gate length across a plurality of transistors, causing unevenness in transistor performance.

In this way, in recent years, with the miniaturization of semiconductor devices, the complexity of their structures, and the diversification of their materials, there has been a demand for additional improvements in the etching selectivity between mask materials and etching materials and reduction of roughness. As a technique for improving the etching selectivity, for example, Patent Document 1 describes a method of improving the selectivity between the mask material and the etching material by using a gas that can generate a deposited film containing the same components as the mask material. It has been disclosed.

Japanese Patent Application Publication No. 2013-118359

According to the technology in Patent Document 1, as a combination of a mask material and an etching material, the mask material is SiO and the etching material is SiN, or the mask material is TaN or WN and the etching material is Poly-Si, or the mask material is Poly-Si and the etching material is In the case of SiN, a deposited film containing the same components as the mask material is created on the mask material, and the etching material on one side is selected and used as a gas for etching, thereby etching the mask material. Selectivity can be improved.

In the case of a limited combination of mask material and etching material as described above, selective etching as described above becomes possible by selecting the gas to be used. However, in recent years, with the diversification of materials and the complexity of structures, it has become very difficult to produce a deposited film containing the same components as the mask material and to select a gas for etching one of the etching materials. there is.

When the etching selectivity is improved, a deposition film is created on the mask material and etching progresses on the etching material. However, it is sufficient for a deposition film to be created on the mask material and no deposition film being created on the etching material. do. This means that if a deposition film is selectively created only on the mask material, the height of the mask increases as a result, and when etching the material to be etched in the next process, it is possible to sufficiently secure the remaining amount of mask height even if the selectivity of the material to be etched is low. Because it becomes.

In the case of EUV lithography technology, as described above, the structure of patterning EUV resist on SiARC or SOG is common, and SiARC or SOG, which is an etching material, is etched using the EUV resist as a mask material. However, it is very difficult to select a gas that generates a deposited film containing the same components as the resist, which is a mask material according to the technology in Patent Document 1, and does not cause etching or generate a deposited film on SiARC or SOG, which is an etching material. There is a task.

On the other hand, in the case of DSA lithography technology, there is only a slight difference in composition between the film structures of PS, PMMA, and NUL. In particular, NUL has a neutral film structure, such as a diblock polymer of about 50% PMMA and about 50% PS, and has only a slight difference in composition. In the case of DSA lithography technology, as described above, PMMA or NUL, which is a material to be etched, is etched using PS as a mask material. However, it is very difficult to select a gas that generates a deposited film containing the same components as PS, which is a mask material, using the technology of Patent Document 1, and does not cause etching or generate a deposited film on PMMA or NUL, which is an etching material. There is a task to do.

Therefore, when etching a material to be etched using a pattern formed by EUV lithography technology or DSA lithography technology as a mask material, a technology for improving the selectivity is needed regardless of the gas. In addition, reduction of LER and LWR roughness is an important issue in EUV lithography technology and DSA lithography technology, but Patent Document 1 does not mention roughness reduction and countermeasures therefor have not been examined. For this reason, with the diversification of materials and the complexity of structures, there has been a demand for technology to improve selectivity regardless of gas and reduce roughness.

The present invention was made in view of these problems, and its purpose is to provide a plasma treatment method that can improve the etching selectivity of the etching material to the mask material and reduce the roughness of the sidewall of the mask pattern.

In order to solve the above problems, one of the representative plasma treatment methods according to the present invention is,

In a plasma treatment method for selectively depositing a deposition film on a mask material with respect to an etching material,

This is achieved by controlling the etching parameters so that the incubation time of the mask material is shorter than the incubation time of the etching material and using a gas that deposits a deposited film on the etching material and the mask material.

According to the present invention, a plasma treatment method is provided that can improve the etching selectivity of the etching material to the mask material and reduce the roughness of the sidewall of the mask pattern.

Problems, configurations, and effects other than those described above will become clear from the description of the embodiments below.

1 is a diagram showing the configuration of a microwave plasma etching device applied to the present invention.
Figure 2 is a diagram showing the etching process when a resist formed by EUV lithography is used as a mask material.
3 is a diagram showing EUV resist etch rate, SiARC etch rate and selectivity.
Figure 4 is a diagram showing EUV resist width and LWR value.
Fig. 5 is a diagram showing the etching parameter adjustment procedure leading to the embodiment.
Fig. 6 is a diagram showing the microwave power source power dependency in the first step of the condition adjustment procedure leading to Example 1.
Fig. 7 is a diagram showing the high-frequency bias power supply power dependence of the second stage of the condition adjustment procedure leading to Example 1.
Fig. 8 is a diagram showing the deposition rate of the deposited film on the EUV resist and SiARC in the third step of the condition adjustment procedure leading to Example 1.
FIG. 9 is a diagram showing the transition of the deposition amount of the EUV resist and SiARC deposited film, which can be estimated from the results of FIG. 8, and the transition of the microwave power supply power and high-frequency bias power supply power output at that time.
FIG. 10 is a diagram showing an explanation of the incubation time in Example 1 by extracting the time of 0 to 0.5 msec for the deposition amount transition of the deposited film shown in FIG. 9.
Figure 11 is a diagram showing the etching process when formed by DSA lithography.
12 is a diagram showing the PS etching rate, NUL etching rate, and selectivity.
Figure 13 is a diagram showing PS width and LWR values.

Each embodiment of the present invention will be described below with reference to the drawings.

In this embodiment, as a technology to improve the selectivity regardless of the gas and reduce roughness, paying attention to the difference in incubation time that occurs even if there is a slight difference in the structure of the mask material and the etching material, Controls the film thickness of the deposited film formed. The incubation time is the time from the start of film formation until the generated film tumor expands to the size of the critical nucleus and appears as a film. Additionally, this time changes even when there is only a slight difference in composition between the film structures of the mask material and the etching material. In other words, it becomes possible to selectively deposit a deposited film by using the difference in incubation time.

In this embodiment, in the plasma processing method of selectively depositing a deposition film on a mask material for an etching material, a plasma etching parameter (also simply referred to as an etching parameter) is set so that the incubation time of the mask material is shorter than the incubation time of the etching material. control).

In addition, in the plasma treatment method for selectively depositing a deposition film on a mask material for an etching material, the incubation time of the mask material is shorter than the incubation time of the etching material, and the deposition film is not deposited on the etching material. , it is desirable to control the plasma etching parameters.

In addition, in the plasma treatment method for selectively depositing a deposition film on a mask material for an etching material, the incubation time of the mask material is shorter than the incubation time of the etching material, and without depositing the deposition film on the etching material. , it is desirable to control the plasma etching parameters so that the etching progresses.

A schematic cross-sectional view of an ECR (Electron Cyclotron Resonance) type microwave plasma etching device (hereinafter also referred to as a “plasma processing device”) according to an embodiment of the present invention is shown in FIG. 1 . In this microwave plasma etching device, a shower plate 102 (for example, made of quartz) for supplying etching gas into the vacuum container 101, and a dielectric window 103 are provided on the top of the open-top vacuum container 101. ) (for example, made of quartz) is placed and the vacuum container 101 is sealed to form a processing chamber 104, which is a plasma processing chamber. A gas supply device 105 for flowing etching gas is connected to the shower plate 102.

Additionally, a vacuum exhaust device 106 is connected to the vacuum vessel 101 via an exhaust on-off valve 117 and an exhaust speed variable valve 118. The pressure inside the processing chamber 104 is reduced by opening the exhaust opening/closing valve 117 and driving the vacuum exhaust device 106, thereby entering a vacuum state in which the pressure has been reduced from atmospheric pressure. The pressure in the processing chamber 104 is adjusted to a desired pressure by the exhaust speed variable valve 118.

The etching gas is supplied into the processing chamber 104 from the gas supply device 105 through the shower plate 102 and is exhausted by the vacuum exhaust device 106 through the exhaust speed variable valve 118.

Additionally, a sample placement electrode 111, which is a sample stage, is provided at the lower part of the vacuum container 101 opposite to the shower plate 102. In order to supply the first high-frequency power for generating plasma to the processing chamber 104, a waveguide 107 for transmitting electromagnetic waves is provided above the dielectric window 103. The electromagnetic waves transmitted to the waveguide 107 are oscillated from the electromagnetic wave generation power source 109, which is a microwave power source, through the matching device 119. A pulse generation unit 121 is attached to the power source 109 for generating electromagnetic waves, whereby microwaves can be pulse-modulated with a repetition frequency that can be arbitrarily set. The frequency of electromagnetic waves is not particularly limited, but in this embodiment, microwaves of 2.45 GHz are used.

Outside the processing chamber 104, a magnetic field generation coil 110 is provided to generate a magnetic field, and the electromagnetic waves oscillated from the electromagnetic wave generation power source 109 interact with the magnetic field generated by the magnetic field generation coil 110. As a result, a high-density plasma is generated in the processing chamber 104, and an etching process is performed on the wafer 112, which is a sample, placed on the sample mounting electrode 111, which is a sample stand.

The shower plate 102, the sample placement electrode 111, the magnetic field generating coil 110, the exhaust opening/closing valve 117, the exhaust speed variable valve 118, and the wafer 112 are the central axis of the processing chamber 104. Since it is arranged coaxially with respect to the phase, radicals and ions generated by the flow of etching gas or plasma, and reaction products generated by etching are supplied coaxially to the wafer 112 and exhausted. This coaxial arrangement has the effect of improving the uniformity of wafer processing by bringing the in-plane uniformity of the etching rate and etching shape closer to axial symmetry.

The electrode surface of the sample placement electrode 111 is covered with a thermal spray film (not shown), and a direct current power supply 116 is connected through a high-frequency filter 115. Additionally, a high-frequency bias power supply 114 is connected to the sample placement electrode 111 through a matching circuit 113. The high-frequency bias power supply 114 is connected to the pulse generation unit 121, and can selectively supply time-modulated second high-frequency power to the sample placement electrode 111. The frequency of the high-frequency bias is not particularly limited, but a high-frequency bias of 400 kHz is used in this embodiment.

The control unit 120, which controls the above-described ECR microwave plasma etching device, controls the pulses of the electromagnetic wave generation power source 109, the high-frequency bias power source 114, and the pulse generation unit 121 through an input means (not shown). Etching parameters such as repetition frequency and duty ratio including on/off timing, gas flow rate for etching, processing pressure, microwave power, high frequency bias power, coil current, pulse on time, and off time are controlled.

Duty ratio is the ratio of the on period to one cycle of the pulse. In this embodiment, the pulse repetition frequency can be changed from 5 Hz to 10 kHz, and the duty ratio can be changed from 1% to 90%. Additionally, time modulation can be set to on time or off time. Next, each example using this embodiment using the above-described microwave plasma etching device will be described below.

[Example 1]

Figure 2 shows the etching process when a resist formed by EUV lithography is used as a mask material. In this embodiment, a sample with a structure of patterning the EUV resist 203 on SiARC 202 deposited on OPL (Organic Planarization Layer) 201 was used, but on SOC (Spin On Carbon) A sample with a structure in which EUV resist is patterned on SOG deposited on may be used.

Etching using EUV resist 203 as the mask material and SiARC 202 as the etching material proceeds in the direction of the arrow shown in FIG. 2, respectively (a) before etching, (b) during etching, and (c) etching. It shows the state afterward. At this time, for example, when the film thickness of the EUV resist 203 and the SiARC 202 are the same, the pattern width dimension is reduced unless the selectivity during etching is at least 1, so the selectivity during etching must be made higher. Alternatively, it is preferable to selectively deposit a deposition film on the EUV resist 203 to increase the film thickness combined with the mask material.

Here, the etching selectivity of the SiARC (202) with respect to the EUV resist (203) is the etching rate of the SiARC (202) divided by the etching rate of the EUV resist (203). Additionally, when the film thickness of the EUV resist 203 is thinner than the film thickness of the SiARC 202, a higher selectivity ratio is used, or a deposition film with a thicker film thickness is selectively deposited on the EUV resist 203. Therefore, it is desirable to make the film thickness combined with the mask material thicker.

Meanwhile, in order to reduce the roughness of the sidewall of the EUV resist 203 before etching from being transferred to the sidewall of the SiARC 202 during the etching of the SiARC 202, a deposition film is selectively deposited on the sidewall of the EUV resist 203. It is desirable to reduce roughness. Therefore, in order to improve the etching selectivity of the SiARC 202 with respect to the EUV resist 203 compared to the prior art and to reduce roughness, it is necessary to selectively deposit a deposition film on the top surface and side walls of the EUV resist 203. There is.

At this time, since etching is inhibited if a deposition film is deposited on the upper surface of SiARC 202, which is a material to be etched, the deposition film must not be deposited on the upper surface of SiARC 202 or etching must proceed.

Etching is performed using a mixed gas consisting of Ar gas, N ₂ gas, and CH ₄ gas as shown in Table 1, gas pressure, microwave power supply power, repetition frequency, and duty ratio, and high-frequency bias power supply power, repetition frequency, and duty ratio. This was done taking advantage of the rain conditions.

[Table 1]

In addition, under the conditions of this example and the comparative example, the samples before etching shown in FIG. 2 were each etched. After that, the sample was cleaved, its cross section was observed and measured using a SEM (Scanning Electron Microscope), and the etching rate, etching selectivity, and EUV resist width were compared and examined. In addition, the LWR roughness values were compared and examined by SEM observation and measurement from directly above the sample.

Figure 3 shows the etching rate and etching selectivity. As shown in FIG. 3, under the conditions of the comparative example, the etching selectivity of SiARC to EUV resist is 2, indicating a value of 1 or more, but the etching rate of EUV resist and SiARC are positive, so the etching selectivity of EUV resist and SiARC is 2. All etching is in progress.

On the other hand, under the conditions of this example, the etching rate of SiARC is lower than the conditions of the comparative example, but the etching rate of the EUV resist is a negative value, indicating that a deposited film is formed on the EUV resist. For this reason, under the conditions of this embodiment, the selectivity ratio of SiARC to EUV resist becomes infinite.

Next, Figure 4 shows the EUV resist width and LWR value. Comparing the conditions before etching and the comparative example, in the conditions of the comparative example, the EUV resist width is slightly narrowed by etching, and the LWR value is also slightly reduced. In other words, it can be seen that the LWR value is slightly reduced as etching proceeds in the horizontal direction of the EUV resist.

On the other hand, under the conditions of this example, the EUV resist width becomes thicker by about 2 nm, and the LWR value is greatly reduced by about 30%. This shows that under the conditions of this example, a deposited film is also formed on the sidewall of the EUV resist, thereby significantly reducing the LWR value. In this way, in this example, from the conditions of the comparative example, the etching selectivity of SiARC to EUV resist could be significantly improved, and the LWR value could also be significantly reduced.

Next, the condition adjustment procedure and mechanism until the conditions of this embodiment are reached will be described. In this embodiment, a mixed gas consisting of Ar gas, N ₂ gas, and CH ₄ gas as shown in Table 1 is used.

In this embodiment, Ar gas is used as the dilution gas, but He, Ne, Kr, Xe, H ₂ , etc., which are generally used as dilution gases, may also be used. In addition, CH ₄ gas and N ₂ gas are used as gases for forming the deposited film. However, according to the mask material and the etching material and the condition adjustment procedure described later, C ₂ H, which is a gas containing carbon C, is used. ₂ , C ₂ H ₄ , CHF ₃ , CH ₃ F, CH ₂ F _2, etc. may be used, or gases containing nitrogen N such as BN, NF ₃ , NCl ₃ , NBr _3, etc. may be used.

The condition adjustment procedure is shown in Figure 5. In the first step of the condition adjustment procedure, the microwave power supply power is adjusted. At this time, as noted in FIG. 5, the microwave power source power is not repeated, and the gas combination and gas pressure are sufficient as long as the deposition film is deposited on both the mask material and the etching material. Therefore, high frequency bias is applied. The power supply power is set to 0W to suppress sputter etching due to ions.

Here, since the film thickness of the deposited film varies depending on the gas flow rate, gas pressure, and microwave power source power, for example, in the first step of the condition adjustment procedure leading to Example 1, the film thickness of the deposited film is set to 0 to 2. Conditions of approximately ㎚ are adopted.

Fig. 6 shows the microwave power supply power dependence of the first stage of the condition adjustment procedure leading to Example 1. Here, the microwave power supply power was set to 800 W so that the deposition rate of the deposited film on the EUV resist and on the SiARC was 0 to 2 nm/min.

Next, in the second step of the condition adjustment procedure, the high-frequency bias power supply power is adjusted. At this time, as noted in FIG. 5, the high-frequency bias power supply is not repeated, and the microwave power supply power is set to be the same as in the first step, and the second step of the condition adjustment procedure leading to Example 1 is the deposition rate of the deposited film. The negative side, that is, the condition in which etching proceeds at about 0 to -2 nm/min, is adopted.

Figure 7 shows the high-frequency bias power supply power dependence of the second stage of the condition adjustment procedure leading to Example 1. Here, the high-frequency bias power supply power was set to 20 W so that the deposition rate of the deposited film on the EUV resist and SiARC was 0 to -2 nm/min.

As an important matter up to the second stage of the condition adjustment procedure leading to Example 1, the microwave power supply power is adjusted centering on the deposition rate of the deposited film at 0 nm/min, so that both sides, that is, the side on which the deposited film is deposited, and the high-frequency bias power supply power The goal is to determine conditions that are symmetrical to the negative side, that is, the etched side, by adjusting . As a result, the deposition rate of the deposited film on the EUV resist and the SiARC is set to ± It can be adjusted within the range of 2 nm/min.

Next, in the third step (adjustment step) of the condition adjustment procedure leading to Example 1, the deposition rate of the deposited film on the EUV resist is on the positive side, that is, on the side where the deposited film is deposited, while the deposition rate of the deposited film on SiARC is on the positive side, that is, on the side where the deposited film is deposited. 0 nm/min, or on the negative side, that is, on the side where no deposited film is deposited and no etching is performed, or on the side where etching is performed, the plasma etching parameters, the microwave power source repetition frequency and microwave power source duty ratio, and the high frequency bias Adjust the power repetition frequency and high frequency bias power duty ratio. That is, the control of etching parameters includes a process of generating plasma using pulse-modulated first high-frequency power and a process of supplying pulse-modulated second high-frequency power to the sample stage. In this case, the period of the pulse for modulating the first high-frequency power is equal to the period of the pulse for modulating the second high-frequency power, and the duty ratio of the pulse for modulating the first high-frequency power modulates the second high-frequency power. It is desirable if it is greater than the duty ratio of the pulse.

Figure 8 shows the deposition rate of the deposited film on the EUV resist and SiARC in the third step of the condition adjustment procedure leading to Example 1. By setting the microwave repetition frequency to 1 kHz, the microwave power supply duty ratio to 50%, the high-frequency bias power repetition frequency to 1 kHz, and the high-frequency bias power duty ratio to 20%, the deposition rate of the deposited film on the EUV resist was set to 1.5 nm/min, and that of the deposited film on SiARC was set to 1.5 nm/min. The deposition rate was able to be set to -0.2 nm/min.

Figure 9 shows the trends in the deposition amounts of the EUV resist and SiARC deposited films, which can be estimated from the results in Figure 8, and the trends in the microwave power supply power and high-frequency bias power supply power output at that time. Since the repetition frequency of the microwave power supply power and the high frequency bias power supply power is 1 kHz, 1 msec is one cycle, and the output ON time is a ratio of each duty ratio.

When the microwave power supply is OFF, no plasma is generated, so deposition or etching of the deposited film does not proceed. Additionally, when the high-frequency bias power output is ON, the deposition rate becomes less than the etching rate, so the deposition film is not deposited and etching does not proceed, or the etching proceeds on the side. Therefore, the deposition amount changes of the deposited film on the EUV resist and on the SiARC follow the dotted lines shown in FIG. 9, respectively.

Here, in Fig. 10, the time 0 to 0.5 msec of the deposition amount change of the deposited film shown in Fig. 9 is extracted, and the incubation time of Example 1 is explained. The incubation time of the deposited film deposited on the EUV resist is the time until deposition starts, that is, the time until the graph takes a positive slope. On the other hand, the incubation time of the deposited film on SiARC is a repeated time in addition to the 0.5 msec period shown on the horizontal axis of the graph. In other words, it can be said that the incubation time of the deposited film on the EUV resist is shorter than the incubation time of the deposited film deposited on SiARC.

Therefore, by adjusting the plasma etching parameters, that is, the microwave power source repetition frequency and the microwave power source duty ratio, and the high-frequency bias power source repetition frequency and the high-frequency bias power source duty ratio, the incubation time of the deposited film on the EUV resist as the mask material can be adjusted to that of the etching material. It becomes possible to shorten the incubation time of the deposited film on SiARC. Additionally, in order to obtain the desired incubation time, it is sufficient to adjust at least one value among the microwave power source repetition frequency and microwave power source duty ratio, and the high-frequency bias power source repetition frequency and high-frequency bias power source duty ratio. This adjustment can be performed by the control unit 120 in the microwave plasma etching device shown in FIG. 1.

In Example 1, the microwave power supply and high frequency bias power supply conditions as shown in Table 1 were optimal. However, depending on the target mask material and etching material, the microwave power supply power and high frequency bias power supply power, microwave power supply repetition frequency and high frequency bias power supply repetition frequency, microwave power supply duty ratio and high frequency bias duty ratio are appropriately selected, It is desirable to obtain optimal conditions by adjusting according to the adjustment procedure in FIG. 5.

[Example 2]

Figure 11 shows the etching process when formed using DSA lithography technology. In this example, a sample having a structure of patterning PMMA (113) and PS (114) on NUL (112) deposited on SiN (111) was used.

First, using PS as a mask material, PMMA, which is an etching material, is etched to form a PS mask pattern. Next, the NUL is etched using the formed PS as a mask pattern. The etching proceeds in the direction of the arrow shown in FIG. 11, and shows the states (a) before etching, (b) after PMMA etching, and (c) after NUL etching, respectively.

In this embodiment, the case of application to NUL etching will be described. Etching is performed using a mixed gas consisting of Ar gas, N ₂ gas, and CH ₄ gas as shown in Table 2, gas pressure, microwave power supply power, repetition frequency, and duty ratio, and high-frequency bias power supply power, repetition frequency, and duty ratio. This was done taking advantage of the rain conditions. Under the conditions of this example and the comparative example, the samples after PMMA etching shown in FIG. 11 were each etched.

[Table 2]

After that, the sample was cleaved, its cross section was observed and measured using a SEM (Scanning Electron Microscope), and the etching rate, etching selectivity, and PS width were compared and examined. In addition, the LWR roughness values were compared and examined by SEM observation and measurement from directly above the sample.

Figure 12 shows the etching rate and etching selectivity. As shown in FIG. 12, under the conditions of the comparative example, the etching selectivity of NUL to PS is 1.5, indicating a value of 1 or more. However, since the etching rate of PS and the etching rate of NUL are positive, etching of PS and NUL proceeds. It is becoming.

On the other hand, under the conditions of this example, the etching rate of NUL is lower than the conditions of the comparative example, but the etching rate of PS is a negative value, indicating that a deposited film is formed on PS. For this reason, under the conditions of this embodiment, the selectivity ratio of NUL to PS becomes infinite.

Next, Figure 13 shows the PS width and LWR values. Comparing the conditions after PMMA etching with the conditions of the comparative example, the PS width was slightly narrowed by etching, and the LWR value was also slightly reduced. In other words, it can be seen that the LWR value is slightly reduced as etching proceeds in the horizontal direction of the EUV resist.

On the other hand, under the conditions of this example, the PS width becomes thicker by about 2 nm, and the LWR value is drastically reduced by about 60%. From this, it is shown that under the conditions of this example, a deposited film is also formed on the PS side wall, thereby significantly reducing the LWR value. In this way, in this example, the etching selectivity of NUL to PS could be significantly improved compared to the conditions of the comparative example, and the LWR value could also be significantly reduced. In addition, the condition adjustment procedure until the conditions of this embodiment were reached was performed according to FIG. 5.

In this embodiment, an application example in an ECR (Electron Cyclotron Resonance) type microwave plasma etching device using microwaves has been described, but it is not limited to this. It may be applied to a plasma etching device using a capacitively coupled or inductively coupled plasma generation means. Additionally, control of etching parameters is preferably performed using a mixed gas of argon gas, nitrogen gas, and methane gas.

In addition, in the present embodiment, after forming the deposited film in the processing chamber of the etching apparatus, the etching process is subsequently performed in the same processing chamber. However, as a method of forming the deposited film generally used in the manufacturing process of semiconductor devices, There are film forming devices using deposition methods, sputtering methods, vapor phase growth methods, and ALD (Atomic Layer Deposition) methods. When forming a deposition film according to the present embodiment using these film formation devices, time is required to transport the wafer from the processing room of the film forming device to the processing room of the etching device, or from the processing room of the etching device to the processing room of the film forming device. As a result, throughput decreases. Additionally, if the processing chamber of the film forming device and the processing chamber of the etching device are not connected through a vacuum transport path, the wafer is exposed to the atmosphere during transport, so the pattern surface after film forming or etching is exposed to atmospheric components (nitrogen, oxygen, etc.). ) and deterioration of the membrane quality occurs, impeding subsequent processing. In addition, when forming a deposited film on the sidewall of the fine mask pattern using the EUV and DSA lithography technology used in this embodiment, an ALD device using the ALD method may be considered suitable. However, according to the principle of the ALD method, a deposited film is formed on the sidewall of the pattern. At the same time, a deposited film is also formed on the bottom of the pattern, thereby inhibiting the subsequent etching process. Therefore, it can be said that the method of forming the deposited film and performing the etching process within the processing chamber of the etching device shown in this embodiment is most suitable.

As described above, in the plasma etching method of the present embodiment, in order to selectively deposit a deposited film on a mask material with respect to an etched material, the incubation time of the deposited film deposited on the mask material is determined by the deposition time on the etched material. The plasma etching parameters are controlled to be shorter than the incubation time of the membrane. For this reason, the etching selectivity of the etching material to the mask material can be significantly improved from the technique of the comparative example, and the roughness of the mask pattern side walls can also be significantly reduced.

101: Vacuum container
102: shower plate
103: Dielectric window
104: processing room
105: gas supply device
106: Vacuum exhaust device
107: waveguide
109: Power supply for electromagnetic wave generation
110: magnetic field generation coil
111: Electrode for sample placement
112: wafer
113: matching circuit
114: high frequency bias power supply
115: high frequency filter
116: DC power
117: Open/close valve for exhaust
118: Exhaust speed variable valve
119: matcher
120: control unit
121: pulse generation unit

Claims (8)

In a plasma treatment method for selectively depositing a deposition film on a mask material with respect to an etching material,
A plasma processing method comprising controlling etching parameters so that the incubation time of the mask material is shorter than that of the etching material, and using a gas to deposit a deposition film on the etching material and the mask material. According to paragraph 1,
Control of the etching parameters includes a process of generating plasma by pulse-modulated first high-frequency power,
A plasma treatment method comprising a step of supplying pulse-modulated second high-frequency power to a sample table on which a sample on which the etching material is deposited is placed. According to paragraph 1,
A plasma processing method characterized in that the mask material is EUV resist, and the etching material is SiARC. According to paragraph 1,
A plasma treatment method characterized in that the mask material is PS, and the etching material is PMMA. According to paragraph 1,
A plasma treatment method, characterized in that the gas is a mixed gas of argon gas, nitrogen gas, and methane gas. According to paragraph 2,
A plasma treatment method, characterized in that the gas is a mixed gas of argon gas, nitrogen gas, and methane gas. According to paragraph 2,
The period of the pulse for modulating the first high-frequency power and the period of the pulse for modulating the second high-frequency power are equal,
A plasma processing method, characterized in that the duty ratio of the pulse for modulating the first high-frequency power is greater than the duty ratio of the pulse for modulating the second high-frequency power. In clause 7,
A plasma processing method characterized in that the mask material is EUV resist, and the etching material is SiARC.

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