KR102578710B1 - X-ray detector - Google Patents

Abstract

The present invention provides an x-ray detector. The X-ray detector includes a plurality of photo-sensing pixels defined by crossing data lines and gate lines, parasitic capacitors connected to each of the data lines, a common voltage line provided by a common voltage crossing the data lines, and the common voltage line. It includes a switching element disposed on a voltage line to apply the common voltage to the parasitic capacitors.

Description

X-ray detector {X-ray detector}

The present invention relates to an X-ray detector for applying a common voltage to photo-sensing pixels.

An imaging device refers to a device that displays an image externally using an electrical input signal, or a device that converts a detection signal detected from the outside into an electrical signal and displays an image through an external circuit. Examples of the former include: There are displays such as liquid crystal display device, organic electro-luminescence display device, plasma display panel, and field emission display device, the latter An example is a digital x-ray detector.

In other words, conventionally, diagnostic Thanks to this, a digital X-ray detector (DXD) using a thin film transistor (TFT) was researched and developed.

The digital X-ray detector uses a thin-film transistor as a switching element, and has the advantage of being able to diagnose the results in real time immediately after taking the X-ray. However, there is a problem of low reliability in the process of reading the electrical signal of the photo diode due to the residual current in the data lines connected to each pixel.

The technical object of the present invention is to provide an X-ray detector including a switching element that applies a common voltage to parasitic capacitors provided to each of the data lines.

The technical problem of the present invention is to connect the data lines and the readout integrated circuit so that the first switching element and the readout integrated circuit that apply a common voltage to the parasitic capacitors provided to each of the data lines are not affected by the common voltage. To provide an X-ray detector including a second switching element that controls.

The present invention provides an x-ray detector. The X-ray detector includes a plurality of photo-sensing pixels defined by crossing data lines and gate lines, parasitic capacitors connected to each of the data lines, a common voltage line provided by a common voltage crossing the data lines, and the common voltage line. It includes a switching element disposed on a voltage line to apply the common voltage to the parasitic capacitors.

In one example, each of the parasitic capacitors is charged to the common voltage by the common voltage line during an initialization period for initializing the photo-sensing pixels.

In one example, it includes a read-out integrated circuit that reads out the detection signal from the photo-sensing pixels, and the read-out integrated circuit includes an integrator that integrates current between the source and drain of the transistor constituting the photo-sensing pixel. and a sampling unit that samples the output of the integrator.

By one example, the integrator includes an amplifier whose first input terminal is connected to the data lines and whose second input terminal receives a reference voltage, a feedback capacitor connected to the first input terminal of the amplifier and the output terminal of the amplifier, and the feedback terminal. It includes a reset element connected in parallel with a capacitor, and the switching element is turned on during an initialization period in which the reset element is closed to initialize the feedback capacitor.

By one example, the sampling unit includes a sample switch switched according to a sampling signal and a holding capacitor connected to one end of the sample switch and the other end connected to a base voltage source, and when the switching element is turned on, the sample The switch is turned off.

In one example, the switching element is turned off while the holding capacitor is charged with the voltage output by the integrator.

In one example, the common voltage line and the switching element are provided to the readout integrated circuit.

In one example, the common voltage line and the switching element are provided in an inactive area of the photo-sensing pixel.

As an example, it further includes a control signal line for applying a signal that controls on/off of the switch element.

As an example, it may further include a second switching element provided to each of the plurality of data lines, wherein the second switching element reads out the detection signal from the photo-sensing pixels and the photo-sensing pixels. Out Controls connections between integrated circuits.

In one example, the second switching element is turned off while the common voltage is applied to the parasitic capacitor.

As an example, it further includes a second control signal line for applying a signal that controls on/off of the second switch element.

In one example, the first switching element and the second switching element receive a switching signal through one control signal line, and the control signal line is divided into two branches to control the first switching element and the second switching element. A switching signal is applied to each element, and an inverter is provided to one branch of the control signal line to invert the signal.

It further includes an X-ray detector according to an embodiment of the present invention. A plurality of photo-sensing pixels defined by intersections of data lines and gate lines, parasitic capacitors connected to each of the data lines, and a common voltage line that intersects the data lines and applies a common voltage to the parasitic capacitors. Includes.

As an example, it further includes a first switching element provided between the adjacent data lines to apply the common voltage to the parasitic capacitors.

As an example, it further includes a second switching element provided to each of the data lines to control a connection between the photo-sensing pixels and an integrator in the readout integrated circuit.

By one example, the second switching element is turned off in a section in which the first switching element is turned on.

As an example, in a section in which the integrator in the readout integrated circuit is initialized, the first switching element is turned on and each of the parasitic capacitors is charged with a common voltage.

According to an embodiment of the present invention, by applying a common voltage to the parasitic capacitors provided to each of the data lines, even after reading the electrical signal output from the photo diode, each of the data lines DL1, DL2, DL3, and DL4 All remaining currents may become the same. Accordingly, currently read data can be prevented from being affected by currents remaining in the data lines DL1, DL2, DL3, and DL4 during the previous data read process.

According to an embodiment of the present invention, the first switching element and the readout integrated circuit that apply a common voltage to the parasitic capacitors provided to each of the data lines are connected to the data lines and the readout integrated circuit so that the first switching element and the readout integrated circuit are not affected by the common voltage. By providing a second switching element that controls the connection, the common voltage may be applied only to the data lines and not to the readout integrated circuit.

1 is a diagram schematically showing an X-ray detector according to an embodiment of the present invention.
Figure 2 is a diagram showing a panel of an X-ray detector according to an embodiment of the present invention.
Figure 3 is a diagram showing the configuration of an integrator and a sampling unit according to an embodiment of the present invention.
FIG. 4 is a diagram showing waveforms of signals for driving the X-ray detector of FIG. 2.
Figure 5 is a diagram showing a panel of an X-ray detector according to another embodiment of the present invention.
FIG. 6 is a diagram showing waveforms of signals for driving the X-ray detector of FIG. 5.
Figure 7 is a diagram showing a panel of an X-ray detector according to another embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are only provided to ensure that the disclosure of the present invention is complete and to provide common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

Additionally, embodiments described in this specification will be described with reference to cross-sectional views and/or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, the form of the illustration may be modified depending on manufacturing technology and/or tolerance. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include changes in form produced according to the manufacturing process. For example, an etch area shown at a right angle may be rounded or have a shape with a predetermined curvature. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of the region of the device and are not intended to limit the scope of the invention.

1 is a diagram schematically showing an X-ray detector according to an embodiment of the present invention.

Referring to FIG. 1 , the X-ray detector 100 includes a panel 200, a bias driver 300, a gate driver 400, and a readout integrated circuit 500. In Figure 1, the gate line (GL), data line (BL), and bias line (BL) are omitted.

The panel 200 can detect X-rays, convert the detected signal into a photoelectric signal, and output it as an electrical signal. The panel 200 includes a plurality of light-sensing pixels arranged in a matrix form by a plurality of gate lines (GL) in the row direction and a plurality of data lines (DL) in the column direction. The plurality of gate lines GL and the plurality of data lines DL may be arranged to cross each other.

The panel 200 may be divided into an active area (AA) and a non-active area (NAA) outside (peripheral) of the active area (AA). The pixels in the active area (AA) are light-sensing pixels (AMPX) for outputting a valid image signal, and the pixels in the non-active area (NAA) are dummy pixels (DPX) for removing noise from the image signal. Each pixel may include a photodiode (PD) and a transistor (TR). The non-active area (NAA) includes one or more rows of dummy pixels (DPX) arranged in parallel with the rows of photo-sensing pixels (AMPX) in the row direction where the gate lines are formed, and/or photo-sensing pixels (AMPX) in the column direction where the data lines are formed. One or more dummy pixel (DPX) columns arranged in parallel with the column may be provided.

The bias driver 300 can apply a driving voltage to a plurality of bias lines (BL). The bias driver 300 can selectively apply a reverse bias and a forward bias to the photo diode (PD). The bias line BL may be formed parallel to the data line DL.

The gate driver 400 sequentially applies gate signals to a plurality of gate lines GL. The gate driver 400 may be in the form of an IC and mounted on one side of the panel 200, or may be formed directly on the panel 200 through a thin film process.

The readout integrated circuit 500 can read the electrical signal of each pixel through a plurality of data lines DL. The readout integrated circuit 500 can read signals from pixels in the active area (AA) and pixels in the non-active area (NAA).

FIG. 2 is a diagram showing the panel of an X-ray detector according to an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of an integrator and a sampling unit according to an embodiment of the present invention.

1 to 3, the X-ray detector 100 may include light-sensing pixels P, a switching element SW1, an integrator 510, and a sampling unit 530. The integrator 510 and the sampling unit 530 may be components provided in the readout integrated circuit 500.

The light-sensing pixels P may be defined by the intersection of a plurality of data lines DL1, DL2, DL3, and DL4 and a plurality of gate lines GL1, GL2, GL3, and GL4. The light-sensing pixels P may be arranged in a matrix form. The light-sensing pixels P may be connected to any one of the data lines DL1, DL2, DL3, and DL4 and any one of the gate lines GL1, GL2, GL3, and GL4. Parasitic capacitors C1, C2, C3, and C4 may be provided to each of the data lines DL1, DL2, DL3, and DL4.

Each of the photo-sensing pixels (P) may be provided with a photo diode (PD) that detects X-rays and outputs a photo-detection voltage, and a transistor (TR) that switches the electrical signal output from the photo diode (PD). One end of the transistor TR may be connected to the photodiode PD, and the other end of the transistor TR may be connected to a data line. A photodiode (PD) detects X-rays and outputs the detected signal as an electrical signal. The photo diode (PD) may be an amorphous silicon (a-Si) PIN photo diode that receives visible light. The first electrode of the photodiode PD is electrically connected to the drain electrode of the transistor TR, and the second electrode is electrically connected to the bias line BL to which a bias voltage is applied. The source electrode of the transistor TR is electrically connected to the data lines DL1, DL2, DL3, and DL4 to transmit the electrical signal output from the photodiode PD to the integrator 510. The gate electrode of the transistor TR may be electrically connected to the gate lines GL1, GL2, GL3, and GL4.

A common voltage line (VL) and a switching element (SW1) disposed on the common voltage line (VL) may be provided between the photo-sensing pixels (P) and the integrator 510. The common voltage line (VL) may intersect the data lines (DL1, DL2, DL3, and DL4). The common voltage line VL may apply a common voltage to the parasitic capacitors C1, C2, C3, and C4 provided to each of the data lines DL1, DL2, DL3, and DL4. The switching elements SW1 may be provided in plural numbers and may be respectively disposed between adjacent data lines DL1, DL2, DL3, and DL4. The switching element (SW1) can be turned on/off by receiving a control signal through the control signal line (CL), and the common voltage is transferred to the parasitic capacitors (C1, C2, C3, C4) by turning on/off the switching element (SW1). ) can be controlled. The plurality of switching elements (SW1) can be simultaneously turned on by a control signal to control the common voltage to be applied to the parasitic capacitors (C1, C2, C3, and C4). However, the timing at which each of the plurality of switching elements (SW1) is turned on may be adjusted according to a change in the control signal.

The common voltage line (VL), switching element (SW1), and control signal line (CL) may be disposed between the data lines (DL1, DL2, DL3, and DL4) and the integrator 510. For example, the common voltage line (VL), the switching element (SW1), and the control signal line (CL) may be provided to the non-active area (NAA) constituting the pixel. As another example, the common voltage line (VL), switching element (SW1), and control signal line (CL) may be provided in the readout integrated circuit 500.

The readout integrated circuit 500 may include an integrator 510, a sampling unit 530, and an analog-to-digital converter (ADC).

The integrator 510 may have a one-to-one correspondence with the plurality of data lines DL1, DL2, DL3, and DL4. The integrator 510 may include an amplifier (AMP), a feedback capacitor (Cfb), and a reset element (S1). The amplifier (AMP) may include a first input terminal connected to one of the data lines (DL1, DL2, DL3, and DL4), a second input terminal that receives the reference voltage (Vref), and an output terminal. The reference voltage (Vref) may be the ground voltage. The first input terminal may be an inverting input of the amplifier (AMP), and the second input terminal may be a non-inverting input of the amplifier (AMP). The signal output from the output terminal of the amplifier (AMP) may be input to the sampling unit 530. One end of the feedback capacitor Cfb may be electrically connected to the first input terminal of the amplifier (AMP), and the other end may be electrically connected to the output terminal of the amplifier (AMP). The reset element S1 may initialize the feedback capacitor Cfb by discharging the voltage charged in the feedback capacitor Cfb. The reset element (S1) is connected in parallel to the feedback capacitor (Cfb), one end of which is electrically connected to one end of the feedback capacitor (Cfb), and the other end of which is electrically connected to the other end of the feedback capacitor (Cfb). The reset element S1 may include a switch that can electrically connect both ends of the feedback capacitor Cfb. When the reset element S1 is closed, both ends of the feedback capacitor Cfb are electrically connected to each other, and the voltage charged at both ends of the feedback capacitor Cfb may be discharged.

The sampling unit 530 may receive a voltage signal from the amplifier (AMP) of the integrator 510. The sampling unit 530 may include a first switch (Q1), a second switch (Q2), a third switch (Q3), and a fourth switch (Q4), and a first holding device connected to the first switch (Q1). A capacitor (Ch1), a second holding capacitor (Ch2) connected to the second switch (Q2), a third holding capacitor (Ch3) connected to the third switch (Q3), and a fourth holding capacitor (Ch3) connected to the fourth switch (Q4) Ch4) may be included. The first holding capacitor (Ch1), the second holding capacitor (Ch2), the third holding capacitor (Ch3), and the fourth holding capacitor (Ch4) may be charged through the voltage output from the integrator 510. The voltage stored in the first holding capacitor (Ch1), the second holding capacitor (Ch2), the third holding capacitor (Ch3), and the fourth holding capacitor (Ch4) may be transferred to an analog-to-digital converter (ADC). The opening and closing timings of the first switch Q1 and the third switch Q3 may be the same, and the opening and closing timings of the second switch Q2 and the fourth switch Q4 may be the same. However, the timing at which the first switch (Q1), the second switch (Q2), the third switch (Q3), and the fourth switch (Q4) are opened and closed may not be particularly limited.

A low-pass filter (LPF) may be provided between the integrator 510 and the sampling unit 530. The low-pass filter (LPF) may include a filter switch (S2) and a variable resistor (R) connected in parallel. The low-pass filter (LPF) can transmit only signals of a certain band to the sampling unit 530 by opening and closing the filter switch (S2). For example, a low-pass filter (LPF) may transmit low-band frequencies to the sampling unit 530 and block high-band frequencies. The low-pass filter (LPF) can remove noise present in the signal for initializing the sampling unit 530 and the signal for sampling the signal output from the photo diode (PD).

According to an embodiment of the present invention, the switching device (SW1) may be turned on in the section where the photo-sensing pixels (P) are initialized, and the parasitic capacitors (C1, C2, C3) may be turned on by turning on the switching device (SW1). , A common voltage may be applied to C4). The section in which the photo-sensing pixels P are initialized may be the same as the section in which the feedback capacitor Cfb of the integrator 510 is initialized. While the photo-sensing pixels P are being initialized, the parasitic capacitors C1, C2, C3, and C4 provided to each of the data lines DL1, DL2, DL3, and DL4 may also be initialized. Accordingly, after reading the electrical signal output from the photo diode PD, the currents remaining in each of the data lines DL1, DL2, DL3, and DL4 may all become the same. That is, as the parasitic capacitors (C1, C2, C3, and C4) are all charged to the common voltage, the currents remaining in the data lines (DL1, DL2, DL3, and DL4) in the previous data read process Data can be prevented from being affected.

FIG. 4 is a diagram showing waveforms of signals for driving the X-ray detector of FIG. 2.

Referring to FIGS. 2 to 4 , the switching device (SW1) may be turned on in the first section (①) in which the reset device (S1) is closed. The second section (②) in which the switching device (SW1) is turned on may overlap with the first section (①) in which the reset device (S1) is closed. As the reset element (S1) is closed in the first section (①), the feedback capacitor (Cfb) may be discharged. However, as the switching element SW1 is turned on, the data lines DL1, DL2, DL3, and DL4 are not discharged but can be charged by the common voltage. The plurality of switching elements SW1 may be turned on simultaneously to charge all of the parasitic capacitors C1, C2, C3, and C4 provided to the data lines DL1, DL2, DL3, and DL4 with a common voltage. Accordingly, the current value flowing through each of the data lines DL1, DL2, DL3, and DL4 may be the same. Therefore, in the process of reading an electrical signal through each of the data lines (DL1, DL2, DL3, and DL4), the current remaining in each of the data lines (DL1, DL2, DL3, and DL4) is different from each other, so that the electrical signal It is possible to prevent problems that reduce the reliability of the reading process from occurring.

In the third section ③ and the fourth section ④, the signal transmitted from the integrator 510 to the sampling unit 530 may be filtered by the filter switch S2. For example, a low-pass filter (LPF) may transmit low-band frequencies to the sampling unit 530 and block high-band frequencies. The third section (③) may be a section in which noise present in the signal for initializing the sampling unit 530 transmitted from the integrator 510 to the sampling unit 530 is filtered. The fourth section (④) may be a section in which noise present in the electrical signal output by the photo diode (PD) transmitted from the integrator 510 to the sampling unit 530 is filtered. For example, the fourth section (④) and the third section (③) may be long. This is because the initialization period of the sampling unit 530 is generally longer than the period during which the sampling unit 530 samples the signal output from the photo diode (PD). However, the timing of the third section (③) and the fourth section (④) may not be particularly limited. The point where the third section (③) starts may be after the point where the second section (②) ends. . That is, the third section (③) and the second section (②) may not overlap. This is to prevent the common voltage applied to the parasitic capacitors C1, C2, C3, and C4 from affecting the capacitors present in the sampling unit 530. During the second section ②, the filter switch S2 may be open, and the low-pass filter LPF may be controlled to prevent the common voltage from being applied to the sampling unit 530 through a variable resistor. However, the timing of the second section (②) and the third section (③) may not be particularly limited.

The fifth section (⑤) and the sixth section (⑥) may be sections for reading and sampling the electrical signal output from the photo diode (PD). Specifically, the fifth section (⑤) may be a section for discharging some of the holding capacitors (Ch1, Ch2, Ch3, Ch4) constituting the sampling unit 530, and the sixth section (⑥) may be a section for discharging the sampling unit ( This may be a section for charging some of the holding capacitors (Ch1, Ch2, Ch3, Ch4) constituting 530). In the fifth section (⑤), the first switch (Q1) and the third switch (Q3) are closed to discharge the first holding capacitor (Ch1) and the third holding capacitor (Ch3). In the fifth section (⑤), the voltage charged in the first holding capacitor (Ch1) and the third holding capacitor (Ch3) can be discharged through the voltage output by the integrator 510 in the previous section. In the sixth section (⑥), the second switch (Q2) and the fourth switch (Q4) are closed to charge the second holding capacitor (Ch2) and the fourth holding capacitor (Ch4). In the sixth section (⑥), the second holding capacitor (Ch2) and the fourth holding capacitor (Ch4) discharged in the previous section can be charged with the voltage output by the integrator 510. The electrical signal output from the photo diode PD can be sampled by controlling the opening and closing of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4. As an example, generally, the length of the fifth section (⑤) may be longer than the length of the sixth section (⑥). This is because the period for initializing the sampling unit 530 is longer than the period for the sampling unit 530 to sample the signal output from the photo diode (PD). However, the timing of the fifth section (⑤) and the sixth section (⑥) may not be particularly limited.

The fifth section (⑤) and the sixth section (⑥) may not overlap with the second section (②). That is, the switching element (SW1) can be turned on when the first switch (Q1), the second switch (Q2), the third switch (Q3), and the fourth switch (Q4) are all open. Through this, when the parasitic capacitors C1, C2, C3, and C4 are charged with the common voltage, the first holding capacitor (Ch1), the second holding capacitor (Ch2), and the third holding capacitor (Ch1) of the sampling unit 530 Ch3) and the fourth holding capacitor (Ch4) can be prevented from being charged to the common voltage. In addition, the parasitic capacitors (C1, C2, C3, C4) are all charged to a common voltage, so that the currently read data is In addition, the reliability of the sampling process of the electrical signal output from the photo diode (PD) can be maintained by preventing the sampling unit 530 from being influenced by the common voltage. Additionally, after the switching element SW1 is turned off, the sampling unit 530 may sample the signal detected by the photo-sensing pixels P and transmit it to the analog-to-digital converter (ADC). In conclusion, the switching light (SW1) can be turned off in the section where the light irradiated to the photo diode (PD) is sensed.

Between the fifth section (⑤) and the sixth section (⑥), the transistor (TR) is turned on by a signal applied to the gate electrode, and the electrical signal output by the photodiode (PD) in the sixth section (⑥) is turned on. It may be transmitted to the sampling unit 530 through the integrator 510.

Figure 5 is a diagram showing a panel of an X-ray detector according to another embodiment of the present invention. For brevity of explanation, description of content that overlaps with FIG. 3 is omitted.

1 and 5, the X-ray detector 100 includes light-sensing pixels P, a first switching element SW1, a second switching element SW2, an integrator 510, and a sampling unit 530. It can be included.

A common voltage line (VL) and a first switching element (SW1) disposed on the common voltage line (VL) may be provided between the photo-sensing pixels (P) and the integrator 510. The common voltage line (VL) may intersect the data lines (DL1, DL2, DL3, and DL4). The common voltage line VL may apply a common voltage to the parasitic capacitors C1, C2, C3, and C4 provided to each of the data lines DL1, DL2, DL3, and DL4. The first switching element SW1 may be provided in plural numbers and may be respectively disposed between adjacent data lines DL1, DL2, DL3, and DL4. The first switching element (SW1) can be turned on/off by receiving a control signal through the first control signal line (CL1), and the common voltage is transferred to the parasitic capacitor (C1) by turning on/off the first switching element (SW1). , C2, C3, C4) can be controlled.

A second switching element (SW2) may be provided on each of the data lines (DL1, DL2, DL3, and DL4). The second switching element (SW2) can be turned on/off by receiving a control signal from the second control signal line (CL2), and the common voltage is transferred to the parasitic capacitors (C1, C2) by turning on/off the second switching element (SW2). , C3, and C4), the integrator 510 and the sampling unit 530 can be prevented from being affected by the common voltage. That is, the second switching element SW2 is turned off while the first switching element SW1 is turned on, thereby controlling the common voltage from being applied to the integrator 510 and the sampling unit 530.

The common voltage line (VL), the first switching element (SW1), the second switching element (SW2), the first control signal line (CL1), and the second control signal line (CL2) are connected to the data lines (DL1, DL2, and DL3). , DL4) and the integrator 510. For example, the common voltage line (VL), the first switching element (SW1), the second switching element (SW2), the first control signal line (CL1), and the second control signal line (CL2) are inactive areas constituting the pixel. (NAA). As another example, the common voltage line (VL), the first switching element (SW1), the second switching element (SW2), the first control signal line (CL1), and the second control signal line (CL2) are connected to the readout integrated circuit 500. ) can be provided within.

FIG. 6 is a diagram showing waveforms of signals for driving the X-ray detector of FIG. 5. For brevity of explanation, description of overlapping content is omitted.

Referring to FIGS. 2, 5, and 6, the switching device (SW1) may be turned on in the first section (①) in which the reset device (S1) is closed. The second section (②) in which the switching device (SW1) is turned on may overlap with the first section (①) in which the reset device (S1) is closed. As the reset element (S1) is closed in the first section (①), the feedback capacitor (Cfb) may be discharged. However, as the switching element SW1 is turned on, the data lines DL1, DL2, DL3, and DL4 are not discharged but can be charged by the common voltage. The plurality of switching elements SW1 may be turned on simultaneously to charge all of the parasitic capacitors C1, C2, C3, and C4 provided to the data lines DL1, DL2, DL3, and DL4 with a common voltage. Additionally, while the first switching device SW1 is turned on, the second switching device SW2 may be turned off. That is, the second section ② in which the first switching device SW1 is turned on and the third section ③ in which the second switching device SW2 is turned off may overlap. Accordingly, the second switching element SW2 is configured so that the common voltage applied to the data lines DL1, DL2, DL3, and DL4 when the first switching element SW1 is turned on is connected to the integrator 510 and the sampling unit 530. ) can be turned off to disconnect the common voltage line (VL) and the integrator 510 so as not to affect the voltage. Therefore, in the process of reading an electrical signal through each of the data lines (DL1, DL2, DL3, and DL4), the current remaining in each of the data lines (DL1, DL2, DL3, and DL4) is different from each other, so that the electrical signal It is possible to prevent problems with reduced reliability in the process of reading, and to sample the electrical signal output from the photo diode (PD) by controlling the timing of the switches so that the common voltage does not affect the sampling unit 530. The reliability of the process can be maintained.

In the fourth section ④ and the fifth section ⑤, the signal transmitted from the integrator 510 to the sampling unit 530 may be filtered by the filter switch S2. The starting point of the fourth section (④) may be after the point where the second section (②) and the third section (③) end. That is, the fourth section (④), the second section (②), and the third section (③) may not overlap. This is to prevent the common voltage applied to the parasitic capacitors C1, C2, C3, and C4 from affecting the capacitors present in the sampling unit 530. During the second section (②) or the third section (③), the filter switch (S2) may be open, and a low-pass filter (LPF) may be used to prevent the common voltage from being applied to the sampling unit 530 through the variable resistor. can be controlled. However, the timing of the third section (③) and the fourth section (④) may not be particularly limited.

The sixth section (⑥) and the seventh section (⑦) may be sections for reading and sampling the electrical signal output from the photo diode (PD). In the sixth section (⑥), the first switch (Q1) and the third switch (Q3) are closed to discharge the first holding capacitor (Ch1) and the third holding capacitor (Ch3). In the seventh section (⑦), the second switch (Q2) and the fourth switch (Q4) are closed to charge the second holding capacitor (Ch2) and the fourth holding capacitor (Ch4). The electrical signal output from the photo diode PD can be sampled by controlling the opening and closing of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4.

Between the fifth section (⑤) and the sixth section (⑥), the transistor (TR) is turned on by a signal applied to the gate electrode, and the electrical signal output by the photodiode (PD) is sampled through the integrator (510). It may be transmitted to unit 530.

The sixth section (⑥) and the seventh section (⑦) may not overlap with the second section (②) and the third section (③). That is, when the first switching device (SW1) is turned on and the second switching device (SW2) is turned off, the first switch (Q1), the second switch (Q2), the third switch (Q3) and the All 4 switches (Q4) can be opened. Through this, when the common voltage charges the parasitic capacitors C1, C2, C3, and C4, the first holding capacitor (Ch1), the second holding capacitor (Ch2), and the third holding capacitor (Ch1) of the sampling unit 530 Ch3) and the fourth holding capacitor (Ch4) can be prevented from being charged to the common voltage.

Figure 7 is a diagram showing a panel of an X-ray detector according to another embodiment of the present invention.

Referring to Figures 1 and 7, the It may include unit 530.

A common voltage line (VL) and a first switching element (SW1) disposed on the common voltage line (VL) may be provided between the photo-sensing pixels (P) and the integrator 510. The common voltage line (VL) may intersect the data lines (DL1, DL2, DL3, and DL4). The common voltage line VL may apply a common voltage to the parasitic capacitors C1, C2, C3, and C4 provided to each of the data lines DL1, DL2, DL3, and DL4. The first switching element SW1 may be provided in plural numbers and may be respectively disposed between adjacent data lines DL1, DL2, DL3, and DL4. The first switching element (SW1) can be turned on/off by receiving a control signal through the control signal line (CL), and the common voltage is transferred to the parasitic capacitors (C1, C2) by turning on/off the first switching element (SW1). , C3, C4) can be controlled.

A second switching element (SW2) may be provided on each of the data lines (DL1, DL2, DL3, and DL4). The second switching element (SW2) can be turned on/off by receiving a control signal from the control signal line (CL), and the common voltage is transferred to the parasitic capacitors (C1, C2, C3) by turning on/off the second switching element (SW2). , It is possible to prevent the integrator 510 and the sampling unit 530 from being affected by the common voltage while it is applied to C4). An inverter 50 may be provided on the control signal line CL that applies a signal to the second switching element SW2. The control signal line (CL) can be divided into two branches, one branch of the line applies the first switching signal to the first switching element (SW1), and one branch of the line applies the second switching signal to the second switching element (SW2). A switching signal can be applied. The inverter 50 may invert the phase of a signal applied through the control signal line CL. For example, the inverter 50 may include an inverter configured with CMOS. The inverter 50 can generate two switching signals whose phases are opposite to each other through one control signal line CL. That is, the second switching signal may be an inverted signal of the first switching signal. Accordingly, the second switching device SW2 is turned off while the first switching device SW1 is turned on, thereby controlling the common voltage from being applied to the integrator 510 and the sampling unit 530. In an embodiment of the present invention, the inverter 50 is provided on the control signal line (CL) for applying a switch signal to the second switching element (SW2), but the control signal for applying the switch signal to the first switching element (SW) An inverter 50 may be provided on the line CL.

The common voltage line (VL), the first switching element (SW1), the second switching element (SW2), the first control signal line (CL1), and the second control signal line (CL2) are connected to the data lines (DL1, DL2, and DL3). , DL4) and the integrator 510. As an example, the common voltage line (VL), the first switching element (SW1), the second switching element (SW2), the control signal line (CL), and the inverter 50 may be provided in the non-active area (NAA) constituting the pixel. You can. As another example, the common voltage line (VL), the first switching element (SW1), the second switching element (SW2), the control signal line (CL), and the inverter 50 may be provided in the readout integrated circuit 500.

According to an embodiment of the present invention, two switching signals can be generated by inverting the phase of one switching signal through the inverter 50 without the need to form two lines to generate two switching signals. Therefore, since two switching signals can be generated with one line, the layout of the X-ray detector 100 can be simplified.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims (18)

A plurality of light-sensing pixels defined by intersections of data lines and gate lines;
Parasitic capacitors connected to each of the data lines;
a common voltage line crossing the data lines and providing a common voltage; and
A first switching element disposed between adjacent data lines and connecting the adjacent data lines in response to a control signal,
When the first switching element is turned on, the common voltage is applied to the parasitic capacitors to charge the parasitic capacitors with the same common voltage.
X-ray detector. According to claim 1,
Each of the parasitic capacitors is charged to the common voltage by the common voltage line during an initialization period for initializing the photo-sensing pixels,
X-ray detector. According to claim 1,
A read-out integrated circuit that reads out detection signals from the photo-sensing pixels,
The readout integrated circuit,
an integrator that integrates current between the source and drain of the transistor constituting the photo-sensing pixel; and
Including a sampling unit that samples the output of the integrator,
X-ray detector. According to clause 3,
The integrator is:
an amplifier whose first input terminal is connected to the data lines and whose second input terminal receives a reference voltage;
a feedback capacitor connected to the first input terminal of the amplifier and the output terminal of the amplifier; and
It includes a reset element connected in parallel with the feedback capacitor,
The first switching element is turned on in an initialization period in which the reset element is closed to initialize the feedback capacitor,
X-ray detector. According to clause 4,
The sampling unit,
a sample switch that switches according to the sampling signal; and
A holding capacitor connected to one end of the sample switch and the other end connected to a base voltage source,
When the first switching element is turned on, the sample switch is turned off,
X-ray detector. According to clause 5,
The first switching element is in a turned-off state while charging the holding capacitor with the voltage output by the integrator.
X-ray detector. According to clause 3,
The common voltage line and the first switching element are provided to the readout integrated circuit,
X-ray detector. According to claim 1,
The common voltage line and the first switching element are provided in an inactive area of the photo-sensing pixel,
X-ray detector. According to claim 1,
Further comprising a control signal line for applying the control signal to control on/off of the first switching element,
X-ray detector. According to claim 1,
Further comprising a second switching element provided to each of the plurality of data lines,
The second switching element controls the connection between the photo-sensing pixels and a readout integrated circuit that reads out detection signals from the photo-sensing pixels.
X-ray detector. According to claim 10,
The second switching element is turned off during the period when the common voltage is applied to the parasitic capacitor.
X-ray detector. According to claim 10,
Further comprising a second control signal line for applying a signal to control on/off of the second switching element,
X-ray detector. According to claim 10,
The first switching element and the second switching element receive a switching signal through one control signal line,
The control signal line is divided into two branches and applies a switching signal to each of the first switching element and the second switching element,
An inverter for inverting the signal is provided on one branch of the control signal line,
X-ray detector. delete delete delete According to clause 5,
In the section where the first switching element is turned on, the second switching element is turned off,
X-ray detector. According to clause 3,
In the section in which the integrator in the readout integrated circuit is initialized, the first switching element is turned on and each of the parasitic capacitors is charged with the common voltage.
X-ray detector.

Images