KR102569872B1 - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device capable of reducing a load of a clock line. A display device according to an exemplary embodiment of the present invention includes a display panel, a gate driver including stages arranged in a non-display area of the display panel and supplying gate signals to gate lines, and supplying gate control signals to the stages. It includes a gate control line for The gate control line includes clock lines for supplying clock signals and a start signal line for supplying a start signal. In the non-display area of the display panel, stages, start lines, and clock lines are arranged in an order in an outer direction based on the display area, and the gate control line is connected to the stages through a connection line.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

As the information society develops, demands for display devices for displaying images are increasing in various forms. Accordingly, recently, various flat panel displays (FPDs) capable of reducing the weight and volume, which are disadvantages of cathode ray tubes, have been developed and marketed. For example, non-light emitting display devices such as liquid crystal displays (LCDs) and plasma display panels (PDPs), organic light emitting diodes (OLEDs), and quantum dot light emitting devices Various flat panel display devices, such as an electroluminescence display such as a quantum dot light emitting display (QLED), are being used.

Such a flat panel display device includes data lines, gate lines, a display panel including a plurality of pixels connected to the data lines and the gate lines, a gate driver supplying gate signals to the gate lines, and data lines to the data lines. A data driver supplying voltages, and a timing control unit controlling operation timings of the gate driver and the data driver. As shown in FIG. 1 , the gate driver GD may be formed in a non-display area of the display panel except for the display area AA, and may include stages having a plurality of transistors. In this case, the gate driver GD receives the clock signals CLK through the clock lines CL and supplies the gate signals to the gate lines. In FIG. 1, only one clock line is shown for convenience of description.

Meanwhile, when the size of the flat panel display device increases, the length of the clock line CL increases, so the load of the clock line CL increases. An increase in the load of the clock line CL may cause a delay of the clock signal CLK.

As shown in FIG. 1 , the clock signal may be supplied from an integrated driver (ID) that integrates functions of a data driver and a timing controller. In this case, the clock signal CLK moves from the gate-off voltage Voff to the gate-on from the first point P1 closest to the integrated driver ID to the third point P3 farthest from the integrated driver ID. A period of changing to the voltage Von may be longer, and a period of changing from the gate-on voltage Von to the gate-off voltage Voff may be longer.

Due to the delay of the clock signal CLK, problems such as abnormal driving of the gate driver GD or deterioration in luminance uniformity due to insufficient data voltage supply period of the pixels may occur.

An embodiment of the present invention provides a display device capable of reducing the load of a clock line.

A display device according to an exemplary embodiment of the present invention includes a display panel, a gate driver including stages arranged in a non-display area of the display panel and supplying gate signals to gate lines, and supplying gate control signals to the stages. It includes a gate control line for The gate control line includes clock lines for supplying clock signals and a start signal line for supplying a start signal. In the non-display area of the display panel, stages, start lines, and clock lines are arranged in an order in an outer direction based on the display area, and the gate control line is connected to the stages through a connection line.

In the display panel according to an exemplary embodiment, a planarization layer disposed on the gate driver and the gate control line, an auxiliary cathode electrode disposed on the planarization layer while overlapping the gate driver and the gate control line, and a planarization layer overlapping the stages and the gate control line. It further includes a plurality of outgas holes penetrating the cathode auxiliary electrode to expose a portion of the surface of the layer.

In an embodiment of the present invention, each of the clock lines and the start line corresponding to the gate control line includes first and second gate control lines disposed on different layers. As a result, the embodiment of the present invention can reduce the load of the clock lines and the start line corresponding to the gate control line.

In addition, according to an embodiment of the present invention, a second gate control line is formed in a remaining space between two planarization layers, that is, the first and second planarization layers in the non-display area, and the second gate is formed through the first contact hole. A control line is connected with the first gate control line. As a result, since the second gate control line can be formed in the same process as the anode auxiliary electrode and the second high-potential voltage line in the embodiment of the present invention, a separate process does not need to be added to form the second gate control line. does not exist.

In addition, in an embodiment of the present invention, the second outgas hole is formed on the clock lines and the start line corresponding to the gate control line. As a result, the embodiment of the present invention prevents the low potential voltage supplied to the cathode auxiliary electrode from being affected by the parasitic capacitance between the cathode auxiliary electrode and the gate control line since the cathode auxiliary electrode does not overlap with the gate control line. can

Furthermore, in an embodiment of the present invention, the size of the first outgas hole formed on the stages is smaller than the size of the second outgas hole formed on the clock lines and the start line corresponding to the gate control line. As a result, the embodiment of the present invention can minimize the decrease in the area of the auxiliary cathode electrode due to the outgas hole.

1 is an exemplary diagram showing a clock line of a display device.
FIG. 2 is a waveform diagram showing clock signals at first to third points of the clock line of FIG. 1 .
3 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
4 is an exemplary diagram showing a lower substrate of a display device, an integrated drive IC, a power circuit board, and a power supply unit.
FIG. 5 is an exemplary view showing in detail the display area, first gate driver, and second gate driver of FIG. 4 .
FIG. 6 is an exemplary view showing a kth stage of the first gate driver of FIG. 5 .
FIG. 7 is an exemplary diagram showing in detail a connection structure of first to fourth stages, first and second clock lines, and a start line of FIG. 5 .
FIG. 8 is an exemplary diagram further showing a cathode auxiliary electrode formed on first to fourth stages, first and second clock lines, and a start line.
9 is a cross-sectional view of the pixel of FIG. 5 .
FIG. 10 is a cross-sectional view taken along line II′ of FIG. 8 .
FIG. 11 is a cross-sectional view taken along line II-II' of FIG. 8 .

Like reference numbers throughout the specification indicate substantially the same elements. In the following description, detailed descriptions of components and functions not related to the core components of the present invention and known in the art may be omitted. The meaning of terms described in this specification should be understood as follows.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is made upright, and may be broader within the range in which the configuration of the present invention can function functionally. It can mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention. 4 is an exemplary diagram showing a lower substrate of a display device, an integrated drive IC, a power circuit board, and a power supply unit.

A display device according to an exemplary embodiment of the present invention may include any display device that supplies data voltages to pixels using a line scanning method in which gate signals are supplied to the gate lines G1 to Gn. For example, a display device according to an embodiment of the present invention includes a liquid crystal display, an organic light emitting display, an electroluminescence display, and a quantum dot light emitting display. dot Lighting Emitting Diode) and electrophoresis display. Hereinafter, a display device according to an embodiment of the present invention is exemplified as an organic light emitting display device, but is not limited thereto.

3 and 4 , a display device according to an exemplary embodiment of the present invention includes a display panel 10, a first gate driver 11, a second gate driver 12, an integrated driver 50, and a power supply unit. (60), and a flexible printed circuit board (70). The integrated driver 50 includes a data driver 20 , a level shifter 30 , and a timing controller 40 .

The display panel 10 includes an upper substrate and a lower substrate. The lower substrate has a display area AA including data lines (D1 to Dm, where m is a positive integer greater than or equal to 2), gate lines (G1 to Gn, where n is a positive integer greater than or equal to 2), and pixels P. is formed The data lines D1 to Dm are formed to cross the gate lines G1 to Gn. The pixel P may be connected to one of the data lines D1 to Dm and one of the gate lines G1 to Gn. As shown in FIG. 9 , the pixel P may be implemented as an organic light emitting diode including an anode electrode, a light emitting layer, and a cathode electrode to emit light.

The first and second gate drivers 11 and 12 are connected to the gate lines G1 to Gn to supply gate signals. Specifically, the first and second gate drivers 11 and 12 receive clock signals CLKs and a gate control signal including a start voltage VST from the level shifter 30 . The gate driver 30 generates gate signals according to the clock signals CLKs and the start voltage VST and outputs them to the gate lines G1 to Gn.

The first and second gate drivers 11 and 12 may be formed in the non-display area in a gate driver in panel (GIP) method. For example, as shown in FIGS. 3 and 4 , the first gate driver 11 is formed outside one side of the display area AA, and the second gate driver 12 is formed outside the other side of the display area AA. can be formed Meanwhile, any one of the first and second gate driving units 11 and 12 may be omitted, and in this case, one gate driving unit may be formed outside one side of the display area DA.

The level shifter 30 converts the voltage levels of the clock signals CLKs and the start voltage VST input from the timing controller 40 to a gate-on voltage Von capable of switching thin film transistors formed on the display panel 10 and the gate-off voltage (Voff). The level shifter 30 supplies the level-shifted clock signals CLKs to the first and second gate drivers 11 and 12 through the clock lines CLs, and supplies the level-shifted start signal VST. It is supplied to the first and second gate drivers 11 and 12 through the start line STL. Since the clock lines CLs and the start line STL are lines for transmitting clock signals and start signals corresponding to gate control signals, in this specification, the clock lines CLs and the start line STL are referred to as gate control lines. shall be collectively referred to as

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives digital image data DATA and a data control signal DCS from the timing controller 40 . The data driver 20 converts the digital image data DATA into analog data voltages according to the data control signal DCS. The data driver 20 supplies analog data voltages to the data lines D1 to Dm.

The timing controller 40 receives digital image data DATA and timing signals TS from an external system board. Timing signals may include a vertical sync signal, a horizontal sync signal, and a data enable signal.

The timing controller 40 controls the gate control signal for controlling the operation timing of the first and second gate drivers 11 and 12 and the operation timing of the data driver 20 based on the timing signals TS. to generate a data control signal (DCS) for

The data driver 20 , the level shifter 30 , and the timing controller 40 may be formed as one driving integrated circuit (IC) like the integrated driver 50 of FIG. 4 . However, the embodiment of the present invention is not limited thereto, and each of the data driver 20, the level shifter 30, and the timing controller 40 may be formed as a separate driving IC. The integrated driving unit 50 may be directly attached to the lower substrate of the display panel 10 using a COG method (Chip on Glass) or a COP (Chip on Plastic) method.

The power supply unit 60 includes a plurality of power supply voltages required to drive the pixels P, such as the VDD voltage and the VSS voltage, and the first and second gate driver units such as the gate-on voltage Von and the gate-off voltage Voff. A gate driving voltage required to drive (11, 12), a source driving voltage required to drive the data driver 20, and a control driving voltage required to drive the timing controller 40 are generated. The power supply unit 60 may be mounted on the flexible printed circuit board 70 as shown in FIG. 4 . The flexible circuit board 70 may be a flexible printed circuit board.

FIG. 5 is an exemplary view showing in detail the display area, first gate driver, and second gate driver of FIG. 4 .

Referring to FIG. 5 , in the display area AA of the display panel 10 , pixels P are formed at intersections of data lines D1 to Dm and gate lines G1 to Gn. Also, the high potential voltage line VDDL to which the high potential voltage is applied may be formed in a mesh structure form to surround each of the pixels P. Since the high potential voltage line VDDL is formed in a mesh structure, a difference between high potential voltages due to a voltage drop of the high potential voltage can be minimized.

Each of the first and second gate drivers 11 and 12 includes first to nth stages ST1 to STn. The kth stage (STk, where k is a positive integer satisfying 1≤k≤n) is the start voltage of the start signal line STL or the output signal of the previous stage and any one of the clock lines CL1 and CL2. It receives a clock signal from and outputs the clock signal input to the kth gate line as a gate signal. For example, the first stage ST1 receives the start voltage of the start signal line STL and the second clock signal of the second clock line CL2, and supplies a first gate signal to the first gate line GL1. print out The second stage ST2 receives the output signal of the first stage ST1 and the first clock signal of the first clock line CL1, and outputs the second gate signal to the second gate line GL2. Meanwhile, in FIG. 5 , for convenience of explanation, clock signal lines are mainly described as being composed of two clock signal lines CL1 and CL2 , but the present invention is not limited thereto. That is, the clock signal lines may be composed of three or more clock signal lines.

As shown in FIG. 6 , the kth stage STk includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU, a pull-down transistor TD, and a node controller NC. can do.

The pull-up transistor TU is turned on when the pull-up node NQ is charged to the gate-on voltage. The pull-down transistor TD is turned on when the pull-down node NQB is charged to the gate-on voltage.

The node controller NC controls charging and discharging of the pull-up node NQ and the pull-down node NQB. The node control unit NC connects the pull-up node TU and the pull-up node TU according to a clock terminal connected to any one of the start terminal to which the start signal or the output signal of the previous stage is input and the clock lines CLs to which clock signals are input. -The charging and discharging of the down node (TD) can be controlled. The node controller NC may further include a reset terminal RT to which an output signal of a later stage is input to control charging and discharging of the pull-up node TU and the pull-down node TD.

Specifically, the node controller NC controls charging and discharging of the pull-up node TU and the pull-down node TD according to a start signal input to a start terminal or an output signal of a previous stage. The node control unit NC discharges the pull-down node NQB to the gate-off voltage when the pull-up node NQ is charged to the gate-on voltage in order to stably control the output of the kth stage STk, When the pull-down node NQB is charged to the gate-on voltage, the pull-up node NQ is discharged to the gate-off voltage.

The pull-up transistor TU is turned on when the pull-up node NQ is charged to the gate-on voltage and outputs the clock signal input to the clock terminal CT to the output terminal OT. The pull-down transistor TD is turned on when the pull-down node NQB is charged at the gate-on voltage, and discharges at the gate-off voltage by connecting the output terminal OT to the gate-off voltage terminal VGLT.

As described above, when the start signal or the output signal of the previous stage is input using the node control unit NC, the kth stage STk converts the clock signal input to the clock terminal CT into a gate signal to the output terminal ( OT) can be output. Accordingly, in an embodiment of the present invention, the first to nth stages ST1 to STn of each of the first and second gate drivers 11 and 12 may sequentially generate outputs.

FIG. 7 is an exemplary diagram showing in detail a connection structure of first to fourth stages, first and second clock lines, and a start line of FIG. 5 . FIG. 8 is an exemplary diagram further showing a cathode auxiliary electrode formed on first to fourth stages, first and second clock lines, and a start line.

Referring to FIG. 7 , the clock lines CL1 and CL2 corresponding to the gate control lines and the start line STL each include first and second gate control lines disposed on different layers. The first and second gate control lines of the clock lines CL1 and CL2 and the start line STL may be connected to each other through the first contact hole CT1.

The start line STL may be connected to the first stage ST1 through a first bridge line BE1. The first connection line BE1 may be connected to the start line STL through the second contact hole CT2.

The first clock line CL1 may be connected to some stages through the second connection line BE2. Although FIG. 7 illustrates that the first clock line CL1 is connected to the even stages ST2, ST4, ..., STn through the second connection line BE2, it is not limited thereto. The second connection line BE2 may be connected to the first clock line CL1 through the second contact hole CT2.

The second clock line CL2 may be connected to the remaining stages ST1 to STn through the third connection line BE3. Although FIG. 7 illustrates that the second clock line CL2 is connected to the odd stages ST1, ST3, ??, and STn-1 through the third connection line BE3, it is not limited thereto. The third connection line BE3 may be connected to the second clock line CL2 through the second contact hole CT2.

In order to increase the load reduction effect of the clock lines CL1 and CL2 corresponding to the gate control lines and the start line STL, the contact area of the first and second gate control lines disposed on different layers is widened. it is desirable Accordingly, the size of the first contact hole CT1 through which the first and second gate control lines contact each other may be greater than that of the second contact hole CT2 .

Referring to FIG. 8 , the cathode auxiliary electrode CATL is connected to the cathode electrode and may be formed in a non-display area to surround the display area AA in order to stably supply a low potential voltage to the cathode electrode. In this case, the auxiliary cathode electrode CATL may be formed on the first and second gate drivers 11 and 12 .

The auxiliary cathode electrode CATL may include an outgas hole OUTH for discharging outgas of the planarization layer. Since the planarization film is formed of a resin such as photo acryl and polyimide, it can absorb moisture when exposed to the air. As a result, moisture may remain in the planarization film, and the light emitting layer or the cathode electrode may be damaged by the outgas of the planarization film. Therefore, the outgas hole OUTH of the auxiliary cathode electrode CATL provides a path through which outgas from the planarization film is discharged to prevent damage to the light emitting layer or the cathode electrode due to moisture.

The outgas hole OUTH is a clock line corresponding to the first outgas hole OUTH1 disposed on the stages ST1 to STn of the first and second gate drivers 11 and 12 and the gate control line. It may include a second outgas hole OUTH2 disposed on CL1 and CL2 and the start line STL.

When the cathode auxiliary electrode CATL overlaps the clock lines CL1 and CL2 and the start line STL, between each of the clock lines CL1 and CL2 and the start line STL and the cathode auxiliary electrode CATL. The low potential voltage supplied to the auxiliary cathode electrode CATL may be affected by the formed parasitic capacitance. The second outgas hole OUTH2 is connected to the clock lines CL1 and CL2 corresponding to the gate control line and the start line in order to minimize the influence of the low potential voltage supplied to the cathode auxiliary electrode CATL by the parasitic capacitance. (STL).

Also, when the area of the auxiliary cathode electrode CATL is reduced due to the outgas hole OUTH, the low potential voltage supplied to the auxiliary cathode electrode CATL may decrease due to a voltage drop. Accordingly, the size of the first outgas hole OUTH1 formed on the stages ST1 to STn is determined by the size of the second outgas hole OUTH1 formed on the clock lines CL1 and CL2 corresponding to the gate control line and the start line STL. It may be smaller than the size of the outgas hole OUTH2.

As described above, in the embodiment of the present invention, the clock lines CL1 and CL2 corresponding to the gate control lines and the start line STL each include first and second gate control lines disposed on different layers. do. As a result, the embodiment of the present invention can reduce the load of the clock lines CL1 and CL2 corresponding to the gate control lines and the start line STL.

9 is a cross-sectional view of the pixel of FIG. 5 . In FIG. 9 , it has been mainly described that the pixel P includes an organic light emitting diode having an anode electrode 250 , an emission layer 260 , and a cathode electrode 270 .

Referring to FIG. 9 , a buffer layer 110 is formed on one surface of the lower substrate 100 . The lower substrate 100 may be a plastic film or a glass substrate, but is not limited thereto. The buffer film 110 is formed on one surface of the lower substrate 100 to protect the thin film transistors 210 and the light emitting elements from moisture penetrating through the lower substrate 100 , which is vulnerable to moisture permeation. The buffer layer 110 may include a plurality of inorganic layers alternately stacked. For example, the buffer layer 110 may be formed of a multilayer in which one or more inorganic layers of a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), and SiON are alternately stacked. The buffer layer 110 may be omitted.

A thin film transistor 210 , a capacitor 220 , and a high potential voltage line 230 are formed on the buffer layer 110 .

The thin film transistor 210 includes an active layer 211 , a gate electrode 212 , a source electrode 213 and a drain electrode. 9 illustrates that the thin film transistor 210 is formed in a top gate (top gate) method in which the gate electrode 212 is positioned above the active layer 211, it should be noted that it is not limited thereto. That is, the thin film transistor 210 has a bottom gate (bottom gate) method in which the gate electrode 212 is located below the active layer 211 or the gate electrode 212 is located above and below the active layer 211. It may be formed in a double gate method located in both. In addition, it should be noted that the drain electrode of the thin film transistor 210 is not shown in FIG. 9 for convenience of description.

The capacitor 220 includes a first capacitor electrode 221 and a second capacitor electrode 222 . The high potential voltage line 230 includes first and second high potential voltage lines 231 and 232 .

Specifically, the active layer 211 is formed on the buffer layer 100 . The active layer 211 may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer and an insulating layer may be formed between the buffer layer 110 and the active layer 211 to block external light incident on the active layer 211 .

A gate insulating layer 120 may be formed on the active layer 211 . The gate insulating layer 120 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

A gate electrode 212 , a first capacitor electrode 221 , and a gate line may be formed on the gate insulating layer 120 . The first capacitor electrode 221 extends from the gate electrode 212 . The gate electrode 212, the first capacitor electrode 221, and the gate line are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium ( It may be formed as a single layer or multiple layers made of any one of Nd) and copper (Cu) or an alloy thereof.

A first interlayer insulating layer 130 may be formed on the gate electrode 212 , the first capacitor electrode 221 , and the gate line. The first interlayer insulating layer 130 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

A second capacitor electrode 222 may be formed on the first interlayer insulating layer 130 . The second capacitor electrode 222 is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A second interlayer insulating layer 140 may be formed on the second capacitor electrode 222 . The second interlayer insulating layer 140 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

A source electrode 213 , a drain electrode, a first high potential voltage line 231 , and a data line may be formed on the second interlayer insulating layer 140 . The source electrode 213 and the drain electrode may be connected to the active layer 211 through the fourth contact hole CT4 penetrating the gate insulating layer 120 and the first and second interlayer insulating layers 130 and 140 . . The first high potential voltage line 231 may be connected to the second capacitor electrode 222 through the fifth contact hole CT5 penetrating the second interlayer insulating layer 140 . The source electrode 213, the drain electrode, the first high potential voltage line 231, and the data line are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel ( It may be formed of a single layer or multiple layers made of any one of Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

A passivation layer 150 may be formed on the source electrode 213 , the drain electrode, the first high potential voltage line 231 , and the data line to insulate the thin film transistor 210 . The protective layer 150 may be formed of an inorganic layer, for example, a silicon oxide layer (SiO _x ), a silicon nitride layer (SiN _x ), or a multilayer thereof.

A first planarization layer 160 may be formed on the passivation layer 150 to flatten a level difference caused by the thin film transistor 210 . The first planarization layer 160 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

An auxiliary anode electrode 240 and a second high potential voltage line 232 may be formed on the first planarization layer 160 . The auxiliary anode electrode 240 may be connected to the source electrode 213 through the sixth contact hole CT6 penetrating the passivation layer 150 and the first planarization layer 160 . The second high potential voltage line 232 may be connected to the first high potential voltage line 231 through the third contact hole CT3 penetrating the passivation layer 150 and the first planarization layer 160 . The anode auxiliary electrode 240 and the second high potential voltage line 232 are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) ) and copper (Cu), or a single layer or multiple layers made of any one of these alloys.

A second planarization layer 170 may be formed on the anode auxiliary electrode 240 and the second high potential voltage line 232 . The second planarization layer 170 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

A light emitting device and a bank 180 are formed on the second planarization layer 170 . The light emitting device includes an anode electrode 250 , a light emitting layer 260 , and a cathode electrode 270 .

The anode electrode 250 may be formed on the second planarization layer 170 . The anode electrode 250 may be connected to the auxiliary anode electrode 240 through the seventh contact hole CT7 penetrating the second planarization layer 170 . The anode electrode 250 includes aluminum (Al), silver (Ag), molybdenum (Mo), a layered structure of molybdenum and titanium (Mo/Ti), a layered structure of copper (Cu), and a layered structure of aluminum and titanium (Ti/Al/Ti ), a laminated structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, or a laminated structure of APC alloy and ITO (ITO/APC/ITO). An APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The bank 180 may be formed to cover an edge of the anode electrode 250 . Due to this, the light emitting area of the pixel P may be defined by the bank 270 . In the light emitting region of the pixel P, the anode electrode 250, the light emitting layer 260, and the cathode electrode 270 are sequentially stacked so that holes from the anode electrode 250 and electrons from the cathode electrode 270 pass through the light emitting layer ( 260) indicates regions that are combined with each other to emit light. In this case, since the region where the bank 180 is formed does not emit light, it may be defined as a non-light emitting portion. The bank 180 may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. .

An emission layer 260 may be formed on the anode electrode 250 and the bank 180 . The light emitting layer 260 is a common layer commonly formed in the pixels P, and may be a white light emitting layer emitting white light. In this case, the light emitting layer 262 may be formed in a tandem structure of two or more stacks. Each of the stacks may include a hole transporting layer, at least one light emitting layer, and an electron transporting layer. In addition, a charge generating layer may be formed between the stacks.

The hole transport layer serves to smoothly transfer holes injected from the anode electrode 250 or the charge generating layer to the light emitting layer. The light emitting layer may be formed of an organic material including a phosphorescent or fluorescent material, thereby emitting a predetermined light. The electron transport layer serves to smoothly transfer electrons injected from the cathode electrode 270 or the charge generating layer to the light emitting layer.

The charge generation layer may include an n-type charge generation layer positioned adjacent to the lower stack and a p-type charge generation layer formed on the n-type charge generation layer and positioned adjacent to the upper stack. The n-type charge generation layer injects electrons into the lower stack, and the p-type charge generation layer injects holes into the upper stack. The n-type charge generation layer may be an organic layer in which an organic host material capable of transporting electrons is doped with an alkali metal such as Li, Na, K, or Cs, or an alkaline earth metal such as Mg, Sr, Ba, or Ra. The p-type charge generating layer may be an organic layer doped with a dopant in an organic host material having hole transport capability.

9 illustrates that the light emitting layer 260 is a common layer commonly formed in the pixels P and emits white light, but the embodiment of the present invention is not limited thereto. That is, the light emitting layer 260 may be formed for each pixel P. In this case, the pixel P is a red pixel including a red light emitting layer emitting red light, a green pixel including a green light emitting layer emitting green light, and a blue pixel emitting blue light.

The cathode electrode 270 is formed on the light emitting layer 260 . The cathode electrode 270 is a common layer commonly formed in the pixels P. The cathode electrode 270 is made of a transparent conductive material (TCO, Transparent Conductive Material) such as ITO or IZO capable of transmitting light, or magnesium (Mg), silver (Ag), or magnesium (Mg) and silver (Ag). It may be formed of a semi-transmissive conductive material such as an alloy. When the cathode electrode 270 is formed of a transflective metal material, light emission efficiency may be increased by a micro cavity. A capping layer may be formed on the cathode electrode 270 .

An encapsulation film 190 is disposed on the cathode electrode 270 . The encapsulation film 190 serves to prevent oxygen or moisture from penetrating the light emitting layer 260 and the cathode electrode 270 . The encapsulation film 190 may include at least one inorganic film. The inorganic layer may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. In addition, the encapsulation film 190 may further include at least one organic film to prevent particles from penetrating the inorganic film and being injected into the light emitting layer 260 and the cathode electrode 270 .

Color filters and a black matrix may be disposed on the encapsulation film 190 . Each of the color filters may be disposed to correspond to the emission area of the pixel P. The black matrix 310 may be disposed between the color filters 310 and 302 and may be disposed corresponding to the bank 270 .

A color filter and a black matrix may be formed on an upper substrate, and the upper substrate and the lower substrate may be adhered to each other using an adhesive layer. In this case, the color filters may be disposed to correspond to the light emitting region of the pixel P, and the black matrix may be disposed to correspond to the bank 180 between the color filters. The adhesive layer may be a transparent adhesive film or a transparent adhesive resin. The upper substrate may be a plastic film, a glass substrate, or an encapsulation film (protective film).

FIG. 10 is a cross-sectional view taken along line II′ of FIG. 8 . FIG. 11 is a cross-sectional view taken along line II-II' of FIG. 8 .

10 and 11, the lower substrate 100, the buffer film 110, the gate insulating film 120, the first interlayer insulating film 130, the second interlayer insulating film 140, the protective film 150, the first planarization film ( 160), the second planarization layer 170, and the bank 180 are substantially the same as those described in conjunction with FIG. 9, so detailed descriptions thereof are omitted.

Referring to FIGS. 10 and 11 , first to third connection lines 281 , 282 , and 283 may be formed on the gate insulating layer 120 . That is, the first to third connection lines 281 , 282 , and 283 may be formed of the same material on the same layer as the gate electrode 212 and the first capacitor electrode 221 of the thin film transistor 210 .

Alternatively, the first to third connection lines 281 , 282 , and 283 may be formed on the first interlayer insulating layer 130 . In this case, the first to third connection lines 281 , 282 , and 283 may be formed of the same material on the same layer as the second capacitor electrode 222 .

The gate control line 290 such as the first and second clock lines CL1 and CL2 and the start line STL includes first and second gate control lines 291 and 292 .

The first gate control line 291 may be formed on the second interlayer insulating layer 140 . In this case, the first gate control line 291 may be formed of the same material on the same layer as the source electrode 213 and the drain electrode of the thin film transistor 210 and the first high potential voltage line 231 . The first gate control line 291 connects the first to third connection lines through the second contact hole CT2 penetrating the second interlayer insulating film 140 or the first and second interlayer insulating films 130 and 140 . (281, 282, 283) and can be connected respectively.

The second gate control line 292 may be formed on the first planarization layer 160 . In this case, the second gate control line 292 may be formed of the same material on the same layer as the auxiliary anode electrode 240 and the second high potential voltage line 232 . The second gate control line 292 may be connected to the first gate control line 291 through the first contact hole CT1 penetrating the passivation layer 150 and the first planarization layer 160 .

The auxiliary cathode electrode 300 may be formed on the second planarization layer 170 . The outgas hole OUTH of the auxiliary cathode electrode 300 is formed on the gate control line 290 . Due to this, in the embodiment of the present invention, since the auxiliary cathode electrode 300 does not overlap with the gate control line 290, the auxiliary cathode electrode ( 300) can be prevented from being affected by the low potential voltage.

As described above, in the exemplary embodiment of the present invention, the second gate control line 292 is provided in the remaining space between the two planarization films, that is, the first and second planarization films 160 and 170 in the non-display area. and connects the second gate control line 292 to the first gate control line 291 through the first contact hole CT1. As a result, since the second gate control line 292 can be formed in the same process as the anode auxiliary electrode 240 and the second high-potential voltage line 232 in the embodiment of the present invention, the gate control without adding a separate process. The load of the clock lines CL1 and CL2 and the start line STL corresponding to the line may be reduced.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the scope of the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10: display panel 11: first gate driver
12: second gate driver 20: data driver
30: level shifter 40: timing control unit
50: integrated drive unit 60: power supply unit
70: flexible circuit board 100: lower board
110: buffer film 120: gate insulating film
130: first interlayer insulating film 140: second interlayer insulating film
150: protective film 160: first planarization film
170: second planarization film 180: bank
190: encapsulation film 210: thin film transistor
211: active layer 212: gate electrode
213: source electrode 220: capacitor
221: first capacitor electrode 222: second capacitor electrode
230: high potential voltage line 231: first high potential voltage line
232: second high potential voltage line 240: anode auxiliary electrode
250: anode electrode 260: light emitting layer
270: cathode electrode 281, BE1: first connection line
282, BE2: second connection line 283, BE3: third connection line
290: gate control line 291: first gate control line
292: second gate control line 300, CATL: cathode auxiliary electrode
CT1: first contact hole CT2: second contact hole
CT3: Third contact hole CT4: Fourth contact hole
CT5: 5th contact hole CT6: 6th contact hole
CT7: 7th contact hole CL1: 1st clock line
CL2: Second Clock Line STL: Start Line
OUTH: outgas hole OUTH1: first outgas hole
OUTH2: 2nd outgas hole

Claims (34)

Including pixels arranged in the display area,
Each of the plurality of pixels,
a thin film transistor including a gate electrode, a source electrode, and a drain electrode;
an auxiliary anode electrode connected to the source electrode or the drain electrode of the thin film transistor; and
a display panel including an anode electrode connected to the auxiliary anode electrode;
a gate driver disposed in a non-display area of the display panel and including stages supplying gate signals to gate lines connected to the pixels; and
a gate control line for supplying a gate control signal to the stages;
The gate control line includes clock lines for supplying clock signals and a start signal line for supplying a start signal;
In the non-display area of the display panel, the stages, the start signal line, and the clock lines are arranged in an order in an outer direction with respect to the display area;
The gate control line is connected to the stages through a connection line;
The connection line is made of the same material on the same layer as the gate electrode,
The gate control line is made of the same material on the same layer as the source electrode and the drain electrode, or is made of the same material on the same layer as the anode auxiliary electrode,
A display device comprising a first interlayer insulating layer and a second interlayer insulating layer disposed between the connection line and the gate control line. delete According to claim 1,
The display panel
A light emitting layer and a cathode electrode disposed on the anode electrode;
Further comprising an encapsulation film disposed on the cathode electrode,
The encapsulation layer includes at least one inorganic layer and at least one organic layer. According to claim 3,
A display device further comprising a color filter and a black matrix disposed on the encapsulation film. Including pixels arranged in the display area,
Each of the plurality of pixels,
a thin film transistor including a gate electrode, a source electrode, and a drain electrode;
an auxiliary anode electrode connected to the source electrode or the drain electrode of the thin film transistor; and
a display panel including an anode electrode connected to the auxiliary anode electrode;
a gate driver disposed in a non-display area of the display panel and including stages supplying gate signals to gate lines connected to the pixels; and
a gate control line for supplying a gate control signal to the stages;
The gate control line includes clock lines for supplying clock signals and a start signal line for supplying a start signal;
In the non-display area of the display panel, the stages, the start signal line, and the clock lines are arranged in an order in an outer direction with respect to the display area;
The gate control line is connected to the stages through a connection line;
The display panel
a planarization layer disposed on the gate driver and the gate control line;
an auxiliary cathode electrode disposed on the planarization layer and overlapping the gate driver and the gate control line;
and a plurality of outgas holes penetrating the cathode auxiliary electrode to expose a surface of a portion of the planarization layer overlapping the stages and the gate control line. According to claim 5,
The gate control line,
a first gate control line; and
a display comprising a second gate control line overlapping the first gate control line with at least one insulating layer interposed therebetween and connected to the first gate control line through a first contact hole penetrating the at least one insulating layer; Device. According to claim 6,
The first gate control line is made of the same material on the same layer as the source and drain electrodes of the thin film transistor, and the second gate control line is made of the same material on the same layer as the anode auxiliary electrode. According to claim 7,
The first gate control line is connected to the connection line through a second contact hole penetrating the interlayer insulating film;
The display device of claim 1 , wherein a size of the first contact hole is greater than a size of the second contact hole. According to claim 6,
The display panel further includes a high potential voltage line supplying a high potential voltage to the pixels,
The high potential voltage line is
a first high potential voltage line; and
A second high potential voltage line overlapping the first high potential voltage line with the at least one insulating layer interposed therebetween and connected to the first high potential voltage line through a third contact hole penetrating the at least one insulating layer. A display device including a. According to claim 9,
The first gate control line is made of the same material on the same layer as the first high-potential voltage line, and the second gate control line is made of the same material on the same layer as the second high-potential voltage line. According to claim 9,
Each of the pixels,
a first capacitor electrode extending from the gate electrode of the thin film transistor; and
and a second capacitor electrode overlapping the first capacitor electrode and connected to the first high-potential voltage line. According to claim 11,
The second capacitor electrode is disposed between the first capacitor electrode and the first high potential voltage line. According to claim 5,
The plurality of outgas holes,
first outgas holes provided on the stages; and
A display device comprising a second outgas hole provided on the gate control line. According to claim 13,
A size of the first outgas hole is smaller than a size of the second outgas hole. According to claim 5,
The cathode auxiliary electrode is a display device made of the same material in the same layer as the anode electrode. Including pixels arranged in the display area,
Each of the above pixels is
a thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode;
an anode electrode connected to the source electrode or the drain electrode of the thin film transistor;
a bank disposed on the periphery of the anode electrode;
a light emitting layer disposed on the anode electrode and the bank; and
And a cathode electrode disposed on the light emitting layer,
a display panel in which light emitting layers of the pixels are formed of a common layer and cathode electrodes of the pixels are formed of a common layer;
a voltage line formed in a mesh structure in the display area;
a gate driver disposed in a non-display area of the display panel and including stages supplying gate signals to gate lines connected to the pixels; and
a gate control line for supplying a gate control signal to the stages;
The gate control line includes clock lines for supplying clock signals and a start signal line for supplying a start signal;
In the non-display area of the display panel, the stages, the start signal line, and the clock lines are arranged in an order in an outer direction with respect to the display area;
The gate control line is connected to the stages through a connection line;
The connection line is made of the same material on the same layer as the gate electrode,
The gate control line is made of the same material on the same layer as the source electrode and the drain electrode, or is made of the same material on the same layer as the anode auxiliary electrode connected to the anode electrode,
A display device comprising a first interlayer insulating layer and a second interlayer insulating layer disposed between the connection line and the gate control line. 17. The method of claim 16,
The voltage line is a high-potential voltage line supplying a high-potential power supply voltage to the pixels. 17. The method of claim 16,
The active layer includes a silicon-based semiconductor material or an oxide-based semiconductor material. 17. The method of claim 16,
The display panel
a buffer film disposed between the substrate and the active layer;
a light blocking layer disposed between the buffer layer and the active layer; and
The display device further comprises an insulating layer disposed between the light blocking layer and the active layer. 17. The method of claim 16,
The light emitting layer is a white light emitting layer emitting white light,
The white light emitting layer has a tandem structure of two or more stacks. 17. The method of claim 16,
Further comprising an encapsulation film disposed on the cathode electrode,
The encapsulation layer includes at least one inorganic layer and at least one organic layer. According to claim 21,
A display device further comprising a color filter and a black matrix disposed on the encapsulation film. delete Including pixels arranged in the display area,
Each of the above pixels is
a thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode;
an anode electrode connected to the source electrode or the drain electrode of the thin film transistor;
a bank disposed on the periphery of the anode electrode;
a light emitting layer disposed on the anode electrode and the bank; and
And a cathode electrode disposed on the light emitting layer,
a display panel in which light emitting layers of the pixels are formed of a common layer and cathode electrodes of the pixels are formed of a common layer;
a voltage line formed in a mesh structure in the display area;
a gate driver disposed in a non-display area of the display panel and including stages supplying gate signals to gate lines connected to the pixels; and
a gate control line for supplying a gate control signal to the stages;
The gate control line includes clock lines for supplying clock signals and a start signal line for supplying a start signal;
In the non-display area of the display panel, the stages, the start signal line, and the clock lines are arranged in an order in an outer direction with respect to the display area;
The gate control line is connected to the stages through a connection line;
The display panel
a planarization layer disposed on the gate driver and the gate control line;
an auxiliary cathode electrode disposed on the planarization layer and overlapping the gate driver and the gate control line;
and a plurality of outgas holes penetrating the cathode auxiliary electrode to expose a surface of a portion of the planarization layer overlapping the stages and the gate control line. 25. The method of claim 24,
The gate control line,
a first gate control line; and
a display comprising a second gate control line overlapping the first gate control line with at least one insulating layer interposed therebetween and connected to the first gate control line through a first contact hole penetrating the at least one insulating layer; Device. 26. The method of claim 25,
The first gate control line is made of the same material on the same layer as the source and drain electrodes of the thin film transistor, and the second gate control line is made of the same material on the same layer as the anode auxiliary electrode connected to the anode electrode. Device. 27. The method of claim 26,
The first gate control line is connected to the connection line through a second contact hole penetrating the interlayer insulating film;
The display device of claim 1 , wherein a size of the first contact hole is greater than a size of the second contact hole. 26. The method of claim 25,
A high potential voltage line supplying a high potential voltage to the pixels is
a first high potential voltage line; and
A second high potential voltage line overlapping the first high potential voltage line with the at least one insulating layer interposed therebetween and connected to the first high potential voltage line through a third contact hole penetrating the at least one insulating layer. Display device comprising a. 29. The method of claim 28,
The first gate control line is made of the same material on the same layer as the first high-potential voltage line, and the second gate control line is made of the same material on the same layer as the second high-potential voltage line. 29. The method of claim 28,
Each of the pixels,
a first capacitor electrode extending from the gate electrode of the thin film transistor; and
and a second capacitor electrode overlapping the first capacitor electrode and connected to the first high-potential voltage line. 31. The method of claim 30,
The second capacitor electrode is disposed between the first capacitor electrode and the first high potential voltage line. 25. The method of claim 24,
The plurality of outgas holes,
first outgas holes provided on the stages; and
A display device comprising a second outgas hole provided on the gate control line. 33. The method of claim 32,
A size of the first outgas hole is smaller than a size of the second outgas hole. 25. The method of claim 24,
The auxiliary cathode electrode is made of the same material on the same layer as the anode electrode.

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