KR102562247B1 - MLCC with improved impact resistance - Google Patents

Abstract

A plurality of unit capacitors including first internal electrodes, second internal electrodes, and first dielectrics spaced apart from each other and having electrode surfaces positioned in parallel are stacked, and first external electrodes and second external electrodes that conduct electricity with the respective internal electrodes are stacked. A multilayer ceramic capacitor comprising: a buffer electrode provided with a first dielectric interposed between the unit capacitors; and a shielding electrode unit in which a plurality of unit shielding electrodes including a first shielding electrode and a second shielding electrode formed side by side on an upper or lower surface made of a first dielectric are stacked in plurality with a second dielectric layer interposed therebetween, wherein the unit shielding electrode unit is In the electrode, one end of each of the first shielding electrode and the second shielding electrode is in contact with the first external electrode and the second external electrode, and the other end of each has a spaced part spaced apart from each other, and the spaced part has different positions on a vertical cross section. Provided is a multilayer ceramic capacitor having improved impact resistance, characterized in that the shielding electrode portion is formed so as to be provided on the.

Description

Multilayer ceramic capacitor with improved impact resistance {MLCC with improved impact resistance}

The present invention relates to a multilayer ceramic capacitor, and relates to a multilayer ceramic capacitor having improved impact resistance against an external impact and an overvoltage component of high voltage surge and electrostatic discharge (ESD) generated in a circuit after mounting or mounting on a substrate. will be.

The multilayer ceramic electronic component consists of a configuration including a plurality of laminated ceramic layers and an electrode arranged between the ceramic layers, and includes a multi-layer ceramic capacitor, a multi-layer chip inductor, and a multi-layer ceramic capacitor. It may include a power inductor (Multi-Layer Power Inductor) or a multi-layer chip bead (Multi-Layer Chip Bead), etc. Multi-layer ceramic electronic components are DC in electronic devices such as digital AV devices, computers, smart pads, and communication terminals. -It is used for various purposes such as blocking, by-passing, and coupling.

In general, multi-layer ceramic capacitors (MLCCs) are mostly manufactured in the shape of a rectangular parallelepiped, and a plurality of dielectric sheets having electrode patterns are laminated and compressed. The compressed chips are cut to make green chips, and the binder is degreased (plasticized) and fired. It is manufactured by polishing the sintered firing chips to derive internal electrodes, forming external electrodes, and then plating them.

Recently, with the ultra-high integration of electronic products, electronic components tend to be miniaturized and highly functional, and multilayer ceramic electronic components are also required for high-capacity and high-voltage products that are small in size and have large capacities. In particular, for capacitors used in power conversion circuits for electric vehicles, there is an increasing demand for multilayer capacitors requiring high energy surge energy tolerance according to the use of high voltage and switching frequency of power semiconductor devices.

EOS (Electric Over Stress) that applies high voltage surge during switching or external mechanical shock can cause dielectric damage (breaking) to the multilayer ceramic capacitor. A problem in which the dielectric is damaged due to an external impact may occur.

Korean Registered Patent No. 10-1069989 (registration date: 2011. 09. 27.) Korean Registered Patent No. 10-0946007 (registration date: 2010. 02. 26.)

A technical problem to be achieved by the present invention is to provide a multilayer ceramic capacitor having improved impact resistance against external shocks and overvoltage components of high voltage surge and electrostatic discharge (ESD) generated in circuits after mounting or mounting on a substrate has a purpose in

The object of the present invention is not limited to the above-mentioned object, and other objects not mentioned will be clearly understood by those skilled in the art from the description below.

In order to solve the above problem, the present invention is stacked in a plurality of unit capacitors composed of first internal electrodes and second internal electrodes and first dielectrics spaced apart from each other and having electrode surfaces parallel to each other, and conducting current with each internal electrode. A multilayer ceramic capacitor comprising a first external electrode and a second external electrode, comprising: a buffer electrode provided between the unit capacitors with a first dielectric interposed therebetween; and a shielding electrode unit in which a plurality of unit shielding electrodes including a first shielding electrode and a second shielding electrode formed side by side on an upper or lower surface made of a first dielectric are stacked in plurality with a second dielectric layer interposed therebetween, wherein the unit shielding electrode unit is In the electrode, one end of each of the first shielding electrode and the second shielding electrode is in contact with the first external electrode and the second external electrode, and the other end of each has a spaced part spaced apart from each other, and the spaced part has different positions on a vertical cross section. It is possible to provide a multilayer ceramic capacitor having improved impact resistance, characterized in that the shielding electrode portion is formed so as to be provided on the.

The spaced portion may be a space that widens at a predetermined rate from the unit shielding electrode of the outermost layer toward the inside.

The spacing of the spacers (interval of the spacers/upper and lower spacing of the internal electrodes) compared to the vertical spacing of the first internal electrode and the second internal electrode is widened toward the inside at a rate of 0.4 to 0.6, 0.65 to 0.75, or 0.8 to 0.9. can

The first internal electrode and the second internal electrode may have patterned electrode surfaces, but end portions of the patterned electrode surfaces of the first internal electrode and the second internal electrode may not coincide with each other.

The unit shielding electrode may be formed so that the other end of each is sharp toward the center, but the end may have a dot-shaped gentle shape.

The second dielectric may have a dielectric constant lower than that of the first dielectric.

In the multilayer ceramic capacitor, a ratio of a thickness of the second dielectric to a thickness of the entire stacked dielectric may be 1/10 to 2/10.

The high-voltage multilayer ceramic capacitor having improved impact resistance according to an embodiment of the present invention has impact resistance against external impact and overvoltage components of high voltage surge and electrostatic discharge (ESD) generated in circuits after mounting or mounting on a substrate. As a result of the improvement, there is an advantage in that it is possible to improve the high voltage surge energy tolerance and increase the voltage by minimizing the internal electrodes of the multilayer ceramic capacitor and the dielectric damage caused by the internal electrodes.

1 is a top view showing a multilayer ceramic capacitor having improved impact resistance according to an embodiment of the present invention;
2 and 3 are cross-sectional views showing a multilayer ceramic capacitor having improved impact resistance according to an embodiment of the present invention;
4 is a graph showing EOS (Electric over stress) surge test waveforms.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention may be embodied in other forms without being limited to the embodiments described below. Also, in the drawings, the lengths and thicknesses of layers and regions may be exaggerated for convenience. Like reference numbers indicate like elements throughout the specification.

1 is a top view showing a multilayer ceramic capacitor having improved impact resistance according to an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views showing a multilayer ceramic capacitor having improved impact resistance according to an embodiment of the present invention, and FIG. is a graph showing EOS (Electric over stress) surge test waveform.

1 to 3, the multilayer ceramic capacitor having improved impact resistance according to an embodiment of the present invention includes first internal electrodes 41 and second internal electrodes 43 spaced apart from each other and having electrode surfaces parallel to each other. and a multilayer ceramic capacitor including first external electrodes 11 and second external electrodes 13 in which a plurality of unit capacitors made of the first dielectric 31 are stacked and electrically connected to the internal electrodes 41 and 43 respectively. , a buffer electrode 50 provided with a first dielectric 31 interposed between the unit capacitors; And unit shielding electrodes (20a, 20b, 20c) composed of a first shielding electrode and a second shielding electrode formed side by side on the upper or lower surface made of the first dielectric 31 interpose the second dielectric layer 32, It includes a shielding electrode part 20 stacked in plurality, and the unit shielding electrodes 20a, 20b, and 20c have one end of each of the first shielding electrode and the second shielding electrode connected to the first external electrode 11 and the second shielding electrode. In contact with the external electrodes 13, each other end has a spaced portion (A) spaced apart from each other, and the spaced portion (A) is provided at different positions on a vertical cross section, so that the shield electrode portion 20 is formed it could be

In detail, in the multilayer ceramic capacitor, a plurality of unit capacitors including a first dielectric 31 and a pair of first internal electrodes 41 and a second internal electrode 43 are stacked, and a first A buffer electrode 50 may be provided with the dielectric 31 interposed therebetween. In addition, the first external electrode 11 electrically connected to the first internal electrode 41 and the first buffer electrode 51 and electrically connected to the second internal electrode 43 and the second buffer electrode 53 An external electrode 10 including a second external electrode 13 may be provided.

The buffer electrode 50 may be formed to minimize displacement of the multilayer ceramic capacitor when a high voltage is applied or to minimize non-uniform compression during a manufacturing process, and between the first buffer electrode 51 and the second buffer electrode 53 It may be said that the first dielectric 31 is interposed therebetween. For example, the buffer electrode 50 may be formed by pressing and firing a plurality of green sheets in which a green sheet printed with a buffer electrode and a green sheet without a buffer electrode are stacked using a paste made of a conductive composition.

The multilayer ceramic capacitor according to the present invention is obtained by stacking a plurality of unit capacitors including first internal electrodes 41 and second internal electrodes 43 and first dielectrics 31 spaced apart from each other and having electrode surfaces parallel to each other. , The first internal electrode 41 and the second internal electrode 43 are provided with patterned electrode surfaces, but the ends of the patterned electrode surfaces of the first internal electrode and the second internal electrode do not coincide with each other. can That is, the first internal electrode 41 and the second internal electrode 43 can be said to have a floating structure, and the horizontal distance B2 between the patterned electrode surfaces is the first internal electrode 41 and the second internal electrode 41. Internal electrodes 40 may be formed such that the electrodes 43 do not overlap each other.

Furthermore, the ratio (B2/B1) of the horizontal spacing B2 between the patterned electrode surfaces to the vertical spacing B1 between the first internal electrode 41 and the second internal electrode 43 may be 2 to 5. there is. When the (B2/B1) ratio is less than 2, electrode spread or short occurs in forming the pattern of the first internal electrode 41 and the second internal electrode 43 having a floating structure, thereby reducing the dielectric breakdown voltage of the capacitor. Sudden deterioration may occur. When the ratio (B2/B1) exceeds 5, the breakdown voltage increases and durability against high voltage can be improved, but the opposing area between the first internal electrode 41 and the second internal electrode 43 decreases, so that the capacitor Since the capacitance of may decrease, it is preferable to have the above range.

The plurality of unit capacitors including the first internal electrodes 41 and the second internal electrodes 43 are stacked, and the green sheet printed with internal electrodes using a paste made of a conductive composition and the internal electrodes are not printed. It may be formed by pressing and firing a plurality of green sheets in which green sheets are stacked.

The green sheet may include first dielectric powder constituting the first dielectric 31 of the ceramic body, a binder binding the first dielectric powder, a solvent, and other additives. The binder may include a resin composition such as PVB or epoxy resin, and preferably, the binder or other organic components containing carbon are removed during firing of the green sheet. It can be removed by being discharged to the outside in the form of carbon dioxide (CO ₂ ).

The first dielectric 31 may include BaTiO ₃ or (BaCa)TiO ₃ as dielectrics, and may include MnO ₂ , MgO, Cr ₂ O ₃ , Y ₂ O ₃ , Dy ₂ O ₃ , Yb ₂ O ₃ At least one selected from the group consisting of, V ₂ O ₅ , SiO ₂ and the like may be added. The first internal electrode 41 and the second internal electrode 43 may be formed of a material selected from among Ni, Ag, and Ag-Pd alloys, have different polarities, and are spaced apart from each other and alternately located inside the ceramic body, It may be electrically insulated by the first dielectric 31 .

The external electrode 10 is connected to the ends of the plurality of first internal electrodes 41 and the first buffer electrode 51 exposed from the first dielectric 31, and the first external electrode 11 and the first dielectric It may include a plurality of second internal electrodes 43 exposed from (31) and a second external electrode 13 connected to the end of the second buffer electrode 53 to conduct electricity. That is, the external electrode 10 may be electrically connected to the internal electrode 40 and the buffer electrode 50 to supply electricity of different polarities. For example, the external electrode 10 may be Cu, Ag, Ag- It may be formed of a metal such as a Pd alloy, or may be formed by applying a paste containing a conductive composition to exposed end regions of the internal electrode 40 and the buffer electrode 50 and firing it, but is not limited thereto.

The multilayer ceramic capacitor having improved impact resistance according to the present invention may include a uniformly formed silane coating layer (not shown) such that a part of the outer surface of the external electrode 10 is exposed, and the external electrode 10 is exposed. A plating layer (not shown) may be positioned on the area. The plating layer may be provided through plating of Ni and Sn, and in the subsequent soldering process for the circuit board of the multilayer ceramic capacitor, the soldering bondability is improved through the plating layer and corrosion of the external electrode 10 is prevented due to the silane coating layer. can Moisture resistance is improved due to the silane coating layer, thereby minimizing the effect of humidity, thereby improving the lifespan and reliability of the multilayer ceramic capacitor. For example, the silane coating layer may have a thickness of 10 to 300 nm. If the thickness is less than 10 nm, it is difficult to have the effect of moisture resistance, and if it exceeds 300 nm, capacitance may decrease and discoloration may occur. Therefore, the silane coating layer preferably has a thickness of 10 to 300 nm.

Furthermore, the multilayer ceramic capacitor having improved impact resistance according to the present invention may further include a polyxylene polymer film formed on the silane coating layer. For example, the polyxylene polymer film may be a parylene film. The polyxylene polymer film may be formed through the deposition chamber after the pyrolysis step through the evaporator, and halogen-free parylene (Parylene-N) and halogen-containing parylene (Parylene-F) may be applied, but is not limited thereto. . The surface of the external electrode is further strengthened through the coating containing the polyxylene polymer film, so that the mechanical strength of the multilayer ceramic capacitor and the breakdown characteristics due to thermal shock can be improved. Furthermore, it is applied to high pressure by minimizing surface discharge and electric field concentration. You can have the advantages of being able to do it. The polyxylene polymer film may have a thickness of 10 to 100 Å. If the thickness is less than 10 Å, it is difficult to realize the effect of improving moisture resistance and strengthening the surface, and if it exceeds 100 Å, it may take a long time to remove the polyxylene polymer film for exposing the external electrode 10 or cause a defect in appearance. It is desirable to have a range.

In addition, in the multilayer ceramic capacitor having improved impact resistance according to the present invention, a metal epoxy electrode layer may be interposed between the exposed region of the external electrode 10 and the plating layer. For example, the metal epoxy electrode layer may be formed of Ag epoxy, but is not limited thereto. Accordingly, the multilayer ceramic capacitor has an advantage in that bending strength characteristics can be improved by improving durability against bending cracks by providing a metal epoxy electrode layer between the external electrode 10 and the plating layer.

The shielding electrode unit 20 includes unit shielding electrodes 20a, 20b, and 20c composed of a first shielding electrode and a second shielding electrode formed side by side on the upper or lower side of the first dielectric 31, and the second dielectric layer. (32) may be interposed and stacked in plurality. In addition, in the unit shielding electrodes 20a, 20b, and 20c, one end of each of the first shielding electrode and the second shielding electrode is in contact with the first external electrode 11 and the second external electrode 13, respectively, and each other The ends may have spaced portions A spaced apart from each other.

Through the separation portion (A), the shielding electrode unit 20 can prevent an electrical short (short) from occurring between the first external electrode 11 and the second external electrode 13, and separate discharge. Since gap discharge is performed through the other end region of each of the shielding electrode units 20 even without an electronic device for the shielding electrode unit 20, the possibility of occurrence of fatal defects such as short circuits in the existing applied circuit environment can be reduced. In addition, when a high surge voltage is applied, the first dielectric 31 may be damaged due to dielectric breakdown occurring in the thickness or distance of the first dielectric 31 between the internal electrodes. At this time, the shield electrode portion formed on the upper surface ( 20) may occur in a short time, and thus damage to the internal electrodes 40 and the first dielectric 31 caused by the internal electrodes of the multilayer ceramic capacitor can be minimized.

This can protect devices and circuits from device destruction and EOS caused by instantaneous high voltage generation by power semiconductor switching in electric vehicles or industrial high-voltage circuits, and can prevent malfunctions.

In addition, depending on the size or shape of the other end of the shielding electrode unit 20 and the permittivity or thickness of the second dielectric 32 of the separation unit A, it is possible to implement a high energy clamping voltage that cannot be expressed in a varistor or diode. It is possible to implement more excellent surge tolerance characteristics compared to existing varistors or diodes.

Furthermore, as shown in FIG. 1 , the other end of each unit shielding electrode 20a, 20b, 20c may be formed to be sharp toward the center, but the end 22 may have a dot-shaped gentle shape. Therefore, even if the other ends of each of the first shielding electrode and the second shielding electrode have a sharp shape, the dielectric strength of the first dielectric 31 and the second dielectric 32 is improved by EOS impact, resulting in cracks due to dielectric breakdown. And electrical short phenomenon can be minimized. Although the shape of a dot is exemplified in the drawings, it is obvious that a shape of a gentle curve having a curvature is also possible.

In addition, the second dielectric 32 in the region where the shielding electrode part 20 is located may have a lower permittivity than the first dielectric 31 . For example, the first dielectric 31 may have a dielectric constant of 2000 to 6000 to obtain a high capacity, and the second dielectric 32 may have a dielectric constant of 20 to 200 in consideration of dielectric breakdown voltage and polarization characteristics per unit thickness. It may be provided with one or more selected from MgO-CaO-TiO ₂ , CaTiO ₃ based, SrTiO ₃ based, and (CaSr)(ZrTi)O ₃ based.

Therefore, irrespective of the permittivity of the first dielectric 31, the surge voltage and energy of the high voltage power conversion circuit are reflected by the permittivity of the second dielectric 32 in the region where the shielding electrode unit 20 is located to improve impact resistance. A multilayer ceramic capacitor may be provided by separately adjusting the permittivity or spacing according to the size of the capacitor. Due to the dielectric characteristics of the second dielectric 32, it may be possible to implement very good overvoltage component blocking characteristics such as static electricity and surge, which cannot be exhibited by varistors or diodes.

Another capacitor may be formed due to the other ends of the first shielding electrode and the second shielding electrode and the second dielectric 32 located therebetween in the spaced portion (A) of the shielding electrode unit. When the capacitance increases, signal delay and distortion may occur. Therefore, it is preferable that the other end of the shielding electrode be as sharp as possible. Therefore, by reducing the permittivity of the second dielectric 32 located in the spaced portion A, the capacitance is reduced, thereby solving the problem of signal delay or distortion. In this case, the ratio (T2/T1) of the thickness T2 of the second dielectric 32 to the total dielectric thickness T1 stacked may be 1/10 to 2/10 considering appropriate capacitance.

As shown in FIGS. 2 and 3 , the shielding electrode portion 20 may be formed such that the spaced portion A is provided at different positions on a vertical cross section. Therefore, even if an impact is applied to the unit shielding electrode 20a located in the outermost layer, the cracking of the second dielectric 32 can be minimized by positioning the other end of each unit shielding electrode at a different location. Even if 32 is damaged, it has the advantage of being able to protect the first dielectric 31, the internal electrode 40, and the buffer electrode 50 by acting as a buffer.

Furthermore, the spaced portion A may have a space that widens at a predetermined rate from the unit shielding electrode 20a of the outermost layer toward the inside. That is, the spacing of the separation portions A may gradually widen toward the inside, such as A1, A2, and A3.

When a high surge voltage is applied, a flashover phenomenon may occur in a short time at the spaced portion A1 of the outermost layer unit shielding electrode 20a, and as a result, the outermost layer shielding electrode 20a and the surrounding second dielectric 32 may be damaged. However, by forming the inner unit shielding electrodes 20b and 20c such that the distance between the spacers A2 and A3 gradually widens toward the inner side, the limit value for the surge voltage can be gradually increased. Accordingly, damage to the internal electrodes 40 and the first dielectric 31 caused by the internal electrodes of the multilayer ceramic capacitor can be minimized or prevented.

Furthermore, in the multilayer ceramic capacitor, the distance between the spacers (A) compared to the distance (B1) between the first internal electrodes 41 and the second internal electrodes 43 (the space between the spacers/the distance between the top and bottom of the internal electrodes) may be widened toward the inside at a rate of 0.4 to 0.6, 0.65 to 0.75, or 0.8 to 0.9.

The spacer (A) is the vertical distance (B1) between the first internal electrode 41 and the second internal electrode 43, that is, the first internal electrode 41 and the second internal electrode 43. Based on the thickness of the dielectric 31, A1/B1 may be formed asymmetrically at ratio intervals of 0.4 to 0.6, A2/B1 of 0.65 to 0.75, and A3/B1 of 0.8 to 0.9. The reason for the asymmetric formation is that when a flash over occurs in the spaced part due to a surge, the insulation breakdown phenomenon in the upper spaced part (A1) directly affects the lower spaced part (A2, A3). because it can alleviate it. The spacer (A) is a vertical distance between the first internal electrode 41 and the second internal electrode 43 having a floating structure, that is, the first internal electrode 41 and the second internal electrode 43. Based on the thickness B1 of the dielectric 31, dielectric breakdown occurs at a voltage lower than the dielectric breakdown voltage in consideration of the characteristics of the dielectric breakdown voltage of 50 to 100 V/um of the first dielectric 31 The thickness can be adjusted so that Forming the shielding electrode unit into a plurality of unit shielding electrodes is to improve the reliability characteristics of the multilayer ceramic capacitor by EOS by minimizing electric field concentration due to surface flash over while increasing surge energy tolerance.

The following Table 1 shows experimental examples and results according to the present invention, the number of unit shielding electrodes and the vertical distance (B1) between the first internal electrode 41 and the second internal electrode 43 compared to the spaced portion (A) It shows the result of testing the characteristics for the interval of .

That is, as an experimental example according to the present invention, a multilayer chip ceramic capacitor having a size of 4532 (4.5 mm x 3.2 mm), a capacitance of 0.1 uF, and a rated voltage of 630 V was fabricated. Ni electrodes were used as internal electrodes, BaTiO3-based materials were used for the first dielectric 31 as a high-permittivity material, and (CaSr)(CaZr)TiO3-based raw materials having 20 to 200 were used for the second dielectric T2. After the first dielectric 30 was made of a slurry, a green sheet was molded by a doctor braid method, and internal electrodes 40 were printed using Ni. In addition, after the second dielectric 33 was made of slurry, a green sheet was formed, and the shielding electrode 20 was printed using Ni. The printed dielectric sheets were laminated, but the dielectric sheets having the shielding electrodes 20 formed thereon were positioned on the upper and lower surfaces, pressed, and then cut. The cut product was degreased at 240 ° C for 48 hours and then sintered at 1200 ~ 1280 ° C for 2 hours in a reducing atmosphere. After polishing the sintered body, an external electrode and a coating layer were formed. The chip on which the external electrode and the coating layer were formed was plated with Ni and Sn to fabricate a final multilayer chip ceramic capacitor. In this case, the ratio (T2/T1) of the thickness T2 of the second dielectric 32 to the total dielectric thickness T1 stacked is in the range of 1/10 to 2/10 considering appropriate capacitance.

At this time, the number of unit shielding electrodes was formed differently from 0 to 3 according to the case of the sample, and the spacing (A1, A2, A3) of each shielding electrode is the first internal electrode 41 and the second internal electrode 41. It is expressed as a ratio compared to the upper and lower spacing B1 of the electrode 43. In addition, samples were manufactured by varying the ratio of the horizontal spacing B2 between the patterned electrode surfaces to the first dielectric thickness B1 between the first internal electrode 41 and the second internal electrode 43.

In the measurement method, the EOS stress is measured by applying the surge voltage (waveform 1.2 μs x 50 μs) of the waveform as shown in FIG. 4 50 times to the rated voltage of the multilayer ceramic capacitor, and then leaving it at room temperature for 24 hours. Dielectric breakdown voltage and insulation resistance were measured. The rate of change of capacitance, breakdown voltage, and insulation resistance was calculated as the change rate of the initial value and the characteristic change value after EOS stress.

turn Unit number of shielding electrodes A1/B1 A2/B1 A3/B1 B2/B1 low permittivity layer
permittivity capacitance
[uF] After EOS stress
capacitance
Decrease rate (%) EOS
Dielectric breakdown voltage reduction rate after stress (%) EOS
after stress
Insulation Resistance
Decrease rate (%) One 0 x x x 2.5 4000 0.1 1.8 6 4.2 2 0 x x x 1.5 150 0.13 2.1 12 11.3 3 One 0.3 x x 1,5 25 0.13 1.6 10 15.1 4 One 0.4 x x 2 80 0.105 1.2 3.4 3.2 5 One 0.5 x x 3 50 0.101 0.8 2.5 3.0 6 One 0.5 x x 5 120 0.92 0.8 2.3 2.8 7 One 0.6 x x 7 150 0.75 0.7 2.3 2.5 8 2 0.3 0.5 x 1,5 30 0.135 1.6 10 13.2 9 2 0.4 0.65 x 2 25 0.106 1.1 3.0 3.0 10 2 0.5 0.65 x 3 50 0.102 0.77 2.2 2.5 11 2 0.5 0.7 x 3 120 0.11 0.76 2.1 2.3 12 2 0.5 0.75 x 3 150 0.12 0.75 2.1 2.4 13 2 0.5 0.75 x 5 30 0.93 0.70 2.05 2.4 14 2 0.7 0.85 x 5 50 0.92 1.6 4.3 1.4 15 2 0.4 0.5 x 7 120 0.78 0.7 2.3 2.5 16 3 0.4 0.65 0.6 1,5 120 0.135 1.7 9.8 8.1 17 3 0.5 0.7 0.8 2 30 0.12 0.78 2.3 1.8 18 3 0.5 0.7 0.85 3 50 0.11 0.75 2.1 1.5 19 3 0.6 0.75 0.9 5 30 0.93 0.72 1.8 1.35 20 3 0.6 0.85 0.95 7 25 0.79 1.4 1.5 1.10

In the measurement results, it can be confirmed that the capacitance reduction rate, insulation breakdown voltage reduction rate, and insulation resistance reduction rate after EOS stress are further improved when there is a shielded electrode, A1/B1 is 0.4 ~ 0.6, A2/B1 is 0.65 ~ 0.75 , A3 / B1 can be confirmed that the capacitance is maintained when the shielding electrode part is formed within the ratio of 0.8 to 0.9, and the characteristics of capacitance reduction rate, dielectric breakdown voltage reduction rate, and insulation resistance reduction rate are improved.

The multilayer ceramic capacitor with improved impact resistance according to an embodiment of the present invention has improved impact resistance against external impact and overvoltage components of high voltage surge and electrostatic discharge (ESD) generated in circuits after mounting or mounting on a substrate This has the advantage of minimizing internal electrodes of the multilayer ceramic capacitor and dielectric damage caused by the internal electrodes.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

10; external electrode
11; 1st external electrode
13; Second external electrode
20; shielded electrode part
20a, 20b, 20c; unit shielding electrode
22; dotted end
31; first dielectric
32; second dielectric
40; internal electrode
41; 1st internal electrode
43; Second internal electrode
50; buffer electrode
51; 1st buffer electrode
53; 2nd buffer electrode
A1, A2, A3; spacing
B1; The vertical distance between the first internal electrode and the second internal electrode
B2; Horizontal spacing between patterned electrode surfaces

Claims (7)

A plurality of unit capacitors including first internal electrodes, second internal electrodes, and first dielectrics spaced apart from each other and having electrode surfaces positioned in parallel are stacked, and first external electrodes and second external electrodes that conduct electricity with the respective internal electrodes are stacked. In the multilayer ceramic capacitor comprising,
a buffer electrode provided with a first dielectric interposed between the unit capacitors; and
A unit shielding electrode composed of a first shielding electrode and a second shielding electrode formed side by side on an upper or lower surface made of a first dielectric includes a shielding electrode portion stacked in plurality with a second dielectric interposed therebetween,
The unit shielding electrode has one end of each of the first shielding electrode and the second shielding electrode in contact with the first external electrode and the second external electrode, respectively, and the other end of each has a spaced part spaced apart from each other,
The multilayer ceramic capacitor with improved impact resistance, characterized in that the shielding electrode portion is formed so that the spacer portion is provided at different positions on the vertical cross section.
According to claim 1,
The multilayer ceramic capacitor with improved impact resistance, characterized in that the spaced part widens at a predetermined rate from the unit shielding electrode of the outermost layer toward the inside.
According to claim 2,
The distance between the spacers (interval between spacers/upper and lower distance between internal electrodes) compared to the vertical distance between the first and second internal electrodes is widened toward the inside at a rate of 0.4 to 0.6, 0.65 to 0.75, and 0.8 to 0.9. A multilayer ceramic capacitor characterized by improved impact resistance.
According to claim 1,
The first internal electrode and the second internal electrode are provided with patterned electrode surfaces, but the end portions of the patterned electrode surfaces of the first internal electrode and the second internal electrode do not coincide with each other to improve impact resistance. multilayer ceramic capacitors.
According to claim 1,
The unit shielding electrode is multilayer ceramic capacitor with improved impact resistance, characterized in that the other end of each is formed to be sharp toward the center, but the end has a dot-shaped gentle shape.
According to claim 1,
The multilayer ceramic capacitor having improved impact resistance, characterized in that the second dielectric has a lower dielectric constant than the first dielectric.
According to claim 1,
The multilayer ceramic capacitor has improved impact resistance, characterized in that the ratio of the thickness of the second dielectric to the total thickness of the laminated dielectric is 1/10 to 2/10.