KR102559510B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and the display device according to an embodiment includes a substrate including a bending area and a non-bending area extending from both sides of the bending area, a plurality of inorganic layers disposed in the non-bending area, and an organic layer filling a space between the plurality of inorganic layers in the bending area. Therefore, the step difference between the bending area and the non-bending area of the substrate can be reduced.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of improving a problem in which wires are disconnected or adjacent wires are shorted in a bending area.

Display devices used in computer monitors, TVs, mobile phones, etc. include Organic Light Emitting Displays (OLEDs) that emit light by themselves and Liquid Crystal Displays (LCDs) that require a separate light source.

The range of applications of display devices is diversifying from computer monitors and TVs to personal portable devices, and research into display devices having a reduced volume and weight while having a large display area is being conducted.

Also, recently, a display device manufactured to display an image even when bent like paper by forming a display unit and wires on a flexible substrate such as plastic, which is a flexible material, is attracting attention as a next-generation display device.

A plurality of inorganic layers are disposed on the substrate of the display device to minimize penetration of moisture or impurities. However, a plurality of inorganic layers made of inorganic materials such as silicon oxide (SiOx) and silicon nitride (SiNx) have poor ductility compared to metal, and are prone to cracking when a bending region is bent. The inventors of the present invention recognized that, when a substrate is bent, cracks may occur in a plurality of inorganic layers disposed in a bending region, and cracks in the plurality of inorganic layers propagate to wires disposed in contact with the plurality of inorganic layers, thereby damaging the wires.

Therefore, the inventors of the present invention can prevent cracking of the inorganic layer in the bending area by removing the plurality of inorganic layers in the bending area and reduce damage to wires disposed in the bending area. However, the inventors of the present invention recognized that a step difference occurs between a region where a plurality of inorganic layers is removed and a region where a plurality of inorganic layers are disposed, and wiring may be disconnected due to the step difference.

In addition, the inventors of the present invention recognized that the surface of the substrate may become uneven in the process of removing the plurality of inorganic layers. That is, when the plurality of inorganic layers are removed by etching the plurality of inorganic layers in a state where the plurality of inorganic layers are disposed on the substrate, the surface of the substrate from which the plurality of inorganic layers are removed may have a concavo-convex structure. Therefore, when wiring is formed directly on the surface of a substrate having a concavo-convex structure, a conductive layer may be non-uniformly deposited along the surface of the substrate, and even when wiring is formed by etching the conductive layer, the remaining film of the conductive layer remains on the surface of the substrate, and short circuits between wires may occur.

Accordingly, the inventors of the present invention invented a display device having a novel structure capable of reducing a level difference generated when a plurality of inorganic layers are removed from a bending area and flattening a surface of a substrate from which a plurality of inorganic layers are removed.

An object of the present invention is to provide a display device capable of reducing a step difference between a bending area and a non-bending area of a substrate.

Another object to be solved by the present invention is to provide a display device capable of flattening a bending region of a substrate from which a plurality of inorganic layers are removed.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an embodiment of the present invention includes a substrate including a bending area and a non-bending area extending from both sides of the bending area, a plurality of inorganic layers disposed in the non-bending area, and an organic layer filling a space between the plurality of inorganic layers in the bending area. Therefore, the step difference between the bending area and the non-bending area of the substrate can be reduced.

In order to solve the above problems, a display device according to another embodiment of the present invention includes a substrate including a non-bending area and a bending area between the non-bending area, a plurality of inorganic layers disposed in the non-bending area, and a first planarization layer disposed in the bending area to planarize an upper portion of the substrate in the bending area. Accordingly, the upper portion of the substrate may be planarized in the bending area by disposing the first planarization layer in the bending area of the substrate where the plurality of inorganic layers are not disposed.

Other embodiment specifics are included in the detailed description and drawings.

According to the present invention, a step difference between a bending area and a non-bending area of a substrate can be minimized.

According to the present invention, by flattening the surface of the substrate in the bending area, remaining film of the wiring during the process of forming the wiring can be minimized and short circuit defects can be improved.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view along line II-II′ of FIG. 1 .
3 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention.
4 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention.
5 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention.
6 is a plan view of the display device of FIG. 5 .

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of the present invention complete, and those skilled in the art are provided to fully inform the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the illustrated details. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', 'on ~ below', 'next to', etc., one or more other parts may be located between the two parts unless 'directly' or 'directly' is used.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

In addition, although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a plan view of a display device according to an exemplary embodiment of the present invention. In FIG. 1 , only the substrate 110 , the sub-pixel SP, the data line DL, the first link line 141 , and the pad PD among various components of the display device 100 are illustrated for convenience of description.

The substrate 110 is a substrate 110 for supporting various components of the display device 100 . The substrate 110 may be made of a material having flexibility, and may be made of, for example, a plastic material such as polyimide (PI).

Referring to FIG. 1 , the substrate 110 includes a display area AA and a non-display area NA.

The display area AA is an area where a plurality of sub-pixels SP are disposed to display an image. A sub-pixel SP including a light emitting area for displaying an image and a circuit for driving the sub-pixel SP may be disposed in the display area AA.

The plurality of sub-pixels SP is a minimum unit constituting the display area AA, and each of the plurality of sub-pixels SP includes a light emitting area. In this case, a display element for emitting light in a light emitting area may be disposed in each of the plurality of sub pixels SP. The display element may vary according to the type of display device 100 . For example, the display device may be a liquid crystal display device or an organic light emitting device 130, but is not limited thereto. Hereinafter, it is assumed that the display device 100 according to an exemplary embodiment of the present invention is an organic light emitting display device.

The non-display area NA is an area in which an image is not displayed, and is an area in which various driving circuits and wirings for driving the sub-pixels SP and driving circuits disposed in the display area AA are disposed. Various driving ICs such as gate driver ICs and data driver ICs may be disposed in the non-display area NA.

Referring to FIG. 1 , the non-display area NA includes a first non-display area NA1 , a bending area BA, a second non-display area NA2 , and a pad area PA.

The pad area PA is an outermost area of the substrate 110 and includes a plurality of pads PD. The plurality of pads PD may be electrically connected to a driving IC such as a data driver IC to transfer data voltages and the like to the plurality of first link wires 141 .

The second non-display area NA2 is an area extending from the pad area PA. A first link wire 141 electrically connected to the plurality of pads PD of the pad area PA may be disposed in the second non-display area NA2 .

The bending area BA is an area extending from the second non-display area NA2. The bending area BA is a bending area on the final product. Meanwhile, the non-display area NA is an area on which an image is not displayed, and does not need to be visually recognized from the upper surface of the display device 100, and a part of the non-display area NA of the substrate 110, for example, the second non-display area NA2 and the pad area PA may be disposed on the lower surface of the display device 100. The bending area BA may be bent.

Specifically, the pad area PA and the second non-display area NA2 may be disposed to correspond to the display area AA when the substrate 110 is bent. That is, when the substrate 110 is bent, the pad area PA and the second non-display area NA2 may be disposed below the display area AA and overlap the display area AA.

The first non-display area NA1 extends from the bending area BA and is connected to the display area AA. A first link wire 141 electrically connected to the plurality of pads PD of the pad area PA may be disposed in the first non-display area NA1 .

A plurality of first link wires 141 and a plurality of data wires DL are disposed on the substrate 110 .

The data line DL is a line for transferring data voltages to the plurality of sub-pixels SP disposed in the display area AA. The plurality of data lines DL receive data voltages from the plurality of first link lines 141 and transfer the data voltages to the plurality of sub-pixels SP.

The plurality of first link wires 141 are wires for transferring data voltages from the data driver IC disposed in the non-display area NA to the data wires DL in the display area AA. The plurality of first link wires 141 connect each of the plurality of pads PD electrically connected to the data driver IC and the plurality of data wires DL. Accordingly, the plurality of first link wires 141 may transmit data voltages from the data driver IC to the plurality of data wires DL.

In FIG. 1 , it has been described that the plurality of first link wires 141 are connected only to the plurality of data wires DL and transmit data voltages from the data driver IC to the plurality of data wires DL. However, the plurality of first link wires 141 may transmit other signals. In addition, the plurality of first link wires 141 may be connected to various signal wires in addition to the data wires DL. Here, the signal wiring may be, for example, a gate wiring, a high potential voltage wiring, a low potential voltage wiring, or a reference voltage wiring, but is not limited thereto.

The plurality of data lines DL and the plurality of first link lines 141 are formed of a conductive material, and in particular, the first link lines 141 passing through the bending area BA may be formed of a conductive material with excellent ductility to minimize the occurrence of cracks when the substrate 110 is bent.

Specifically, the plurality of data lines DL and the plurality of first link wires 141 may be made of the same material as the source electrode 123 and the drain electrode 124 of the thin film transistor 120, and may be composed of a single layer or a multi-layer. However, it is not limited thereto, and may be made of the same material as the gate electrode 122 of the thin film transistor 120 . For example, the plurality of data lines DL and the plurality of first link wires 141 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

Meanwhile, as the bending area BA is bent, a crack may occur due to stress concentrated in a portion of the first link wire 141 disposed in the bending area BA. Accordingly, the first link wire 141 may include a pattern having a specific shape to minimize cracks. For example, a conductive pattern having at least one of a diamond shape, a rhombus shape, a zigzag shape, and a circular shape may be repeatedly disposed on a portion of the first link wire 141 disposed in the bending area BA. A portion of the first link wire 141 may have a shape other than the above-described shape to minimize stress and cracks concentrated on the first link wire 141, but is not limited thereto.

A plurality of pads PD are respectively connected to ends of the plurality of first link wires 141 . The plurality of pads PD may be electrically connected to a driving IC such as a data driver IC to transfer data voltages and the like to the plurality of first link wires 141 .

Meanwhile, the substrate 110 may be defined as a display area AA and a non-display area NA, or may also be defined as a bending area BA and a non-bending area NBA. The display area AA and the non-display area NA may be defined according to whether an image is displayed, and the bending area BA and non-bending area NBA may be defined according to whether the substrate 110 is bent.

The bending area BA is the same area as the bending area BA of the non-display area NA, and the substrate 110 may be bent in the bending area BA.

The non-bending area NBA is an area where the substrate 110 is not bent and the substrate 110 is kept flat, and may extend from both sides of the bending area BA. The non-bending area NBA includes a display area AA, a first non-display area NA1 , a second non-display area NA2 , and a pad area PA.

Hereinafter, the bending area BA and the non-bending area NBA will be described in more detail with reference to FIG. 2 .

FIG. 2 is a cross-sectional view along line II-II′ of FIG. 1 . Referring to FIG. 2 , a display device 100 according to an exemplary embodiment of the present invention includes a substrate 110, a multi-buffer layer 111, an active buffer layer 112, a gate insulating layer 113, an interlayer insulating layer 114, a passivation layer 115, a first planarization layer 116, a second planarization layer 117, a bank 118, a thin film transistor 120, and an organic light emitting element 13. 0) included.

In the non-bending region, a multi-buffer layer 111 is disposed on the substrate 110 . The multi-buffer layer 111 may delay diffusion of moisture and/or oxygen penetrating from the lower portion of the substrate 110 . The multi-buffer layer 111 may be formed by alternately stacking silicon oxide (SiOx) and silicon nitride (SiNx).

An active buffer layer 112 is disposed on the multi-buffer layer 111 in the non-bending area NBA of the substrate 110 . The active buffer layer 112 protects the active layer 121 of the thin film transistor 120 and blocks defects from the bottom of the substrate 110 . In addition, when an additional metal layer such as a light blocking layer is disposed between the thin film transistor 120 and the buffer layer according to the type of the thin film transistor 120, the active buffer layer 112 may insulate the additional metal layer from the active layer of the thin film transistor 120. The active buffer layer 112 may be formed by alternately stacking silicon oxide (SiOx) and silicon nitride (SiNx), but is not limited thereto. For example, silicon nitride (SiNx) may be deposited after forming a multilayer of silicon oxide (SiOx).

A thin film transistor 120 is disposed on the active buffer layer 112 . In this case, the thin film transistor 120 may be a driving thin film transistor that is electrically connected to the organic light emitting element 130 and drives the organic light emitting element 130 . The thin film transistor 120 includes an active layer 121 , a gate electrode 122 , a source electrode 123 and a drain electrode 124 . In the display device 100 according to an embodiment of the present invention, the thin film transistor 120 has a structure in which an active layer 121, a gate electrode 122, a source electrode 123, and a drain electrode 124 are disposed on the active layer 121, and the gate electrode 122 is disposed on the top gate structure.

An active layer 121 is disposed on the active buffer layer 112 . The active layer 121 may be formed of, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, or an organic semiconductor, but is not limited thereto.

A gate insulating layer 113 is disposed on the active layer 121 in the non-bending region NBA of the substrate 110 . The gate insulating layer 113 is a layer for insulating the gate electrode 122 and the active layer 121 and may be made of an insulating material. For example, the gate insulating layer 113 may include a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A gate electrode 122 is disposed on the gate insulating layer 113 . The gate electrode 122 may be made of a conductive material, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or may be composed of a single layer or multiple layers of alloys thereof, but is not limited thereto.

An interlayer insulating layer 114 is disposed on the gate electrode 122 in the non-bending region NBA of the substrate 110 . The interlayer insulating layer 114 may be made of the same material as the gate insulating layer 113, but is not limited thereto. For example, the interlayer insulating layer 114 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode 123 and a drain electrode 124 are disposed on the interlayer insulating layer 114 . Each of the source electrode 123 and the drain electrode 124 may be electrically connected to the active layer 121 through contact holes formed in the interlayer insulating layer 114 and the gate insulating layer 113 . The source electrode 123 and the drain electrode 124 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but are not limited thereto.

The source electrode 123 is electrically connected to one of the plurality of data lines DL. Also, the source electrode 123 may transfer the data voltage applied from the data line DL to the active layer 121 and the drain electrode 124 .

The drain electrode 124 is electrically connected to the anode 131 of the organic light emitting element 130 . The drain electrode 124 may transmit the data voltage transmitted from the source electrode 123 and the active layer 121 to the organic light emitting diode 130 .

In FIG. 2 , it is illustrated that the source electrode 123 of the thin film transistor 120 is connected to the data line DL and the drain electrode 124 is connected to the anode 131 of the organic light emitting element 130, but is not limited thereto.

A passivation layer 115 is disposed on the thin film transistor 120 in the non-bending region NBA of the substrate 110 . The passivation layer 115 is an insulating layer for protecting components under the passivation layer 115 . The passivation layer 115 may be made of the same material as the gate insulating layer 113, but is not limited thereto. For example, the passivation layer 115 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

Meanwhile, in the bending area BA, a first planarization layer 116 is disposed on the substrate 110 . The first planarization layer 116 may planarize an upper portion of the substrate 110 in the bending area BA. The first planarization layer 116 may be composed of a single layer or a multi-layer, and may be made of an organic material. For example, the first planarization layer 116 may be made of an acryl-based organic material, but is not limited thereto.

Meanwhile, on the passivation layer 115 , a second planarization layer 117 is disposed in some areas of the bending area BA and the non-bending area NBA of the substrate 110 . The second planarization layer 117 may planarize an upper portion of the substrate 110 on which the thin film transistor 120 is formed. The second planarization layer 117 may be made of the same material as the first planarization layer 116, and the second planarization layer 117 may be composed of a single layer or multiple layers, and may be made of an organic material. For example, the second planarization layer 117 may be made of an acryl-based organic material, but is not limited thereto.

Meanwhile, the organic light emitting element 130 is disposed on the second planarization layer 117 . The organic light emitting device 130 may be electrically connected to the drain electrode 124 of the thin film transistor 120 and receive a driving current to emit light. The organic light emitting device 130 includes an anode 131 , an organic light emitting layer 132 and a cathode 133 .

An anode 131 is disposed on the second planarization layer 117 . The anode 131 may supply holes to the organic light emitting layer 132 of the organic light emitting element 130 and may be made of a conductive material having a high work function. For example, the anode 131 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

However, when the display device 100 according to an embodiment of the present invention is a top emission type, a metal material having excellent reflection efficiency may be further disposed below the anode 131 so that light emitted from the organic light emitting layer 132 is reflected by the anode 131 and directed upward, that is, toward the cathode 133 side. For example, a reflective layer made of a material such as aluminum (Al) or silver (Ag) may be added under the anode 131 .

Conversely, when the display device 100 according to an exemplary embodiment is a bottom emission type, the anode 131 may be formed of only a transparent conductive material.

A bank 118 is disposed on the anode 131. The bank 118 is disposed to cover the edge of the anode 131 and may distinguish each of a plurality of sub-pixels SP. Bank 118 may be made of an insulating material. For example, the bank 118 may be made of polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

Meanwhile, as described above, the multi-buffer layer 111, the active buffer layer 112, the gate insulating layer 113, the interlayer insulating layer 114, and the passivation layer 115 are made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), so they may also be referred to as inorganic layers. Accordingly, a plurality of inorganic layers made of inorganic materials, for example, a multi-buffer layer 111, an active buffer layer 112, a gate insulating layer 113, an interlayer insulating layer 114, and a passivation layer 115 are disposed in the non-bending region NBA of the substrate 110, that is, in a partial region of the substrate 110 maintaining a flat state. However, a plurality of inorganic layers are not disposed in the bending area BA of the substrate 110 .

In addition, since the first planarization layer 116 and the second planarization layer 117 are made of an organic material such as an acryl-based organic material, they may be referred to as organic layers. Accordingly, an organic layer made of an organic material, that is, the first planarization layer 116 is disposed in the bending area BA of the substrate 110 . Also, the second planarization layer 117, which is another organic layer made of an organic material, may be further disposed not only in the bending area BA but also in the non-bending area NBA.

Meanwhile, the edge of the first planarization layer 116, which is an organic layer, is disposed on a plurality of inorganic layers. Specifically, in the bending area BA, the first planarization layer 116 filling the space between the plurality of inorganic layers may extend to both sides of the bending area BA. For example, the first flattening layer 116 may be disposed to cover the edge of the plurality of inorganic layers of the first non-display area NA1 extending to one side of the bending area BA and the edge of the plurality of inorganic layers of the second non-display area NA2 extending to the other side of the bending area BA, respectively.

Meanwhile, the source electrode 123 of the thin film transistor 120 is electrically connected to the data line DL, and the data line DL is disposed on the same layer as the source electrode 123 . Specifically, the data line DL is disposed on the interlayer insulating layer 114 in the non-bending area NBA and display area AA.

Meanwhile, the first link wire 141 is electrically connected to the data wire DL. Also, the first link wires 141 are disposed in both the non-bending area NBA and the bending area BA. Specifically, the first link wire 141 is disposed on the interlayer insulating layer 114 in the first non-display area NA1 extending from the display area AA. The first link wiring 141 is disposed on the first planarization layer 116 in the bending area BA extending from the first non-display area NA1. Also, the first link wiring 141 is disposed on the interlayer insulating layer 114 in the second non-display area NA2 extending from the bending area BA.

In a conventional display device, a plurality of inorganic layers are removed from a bending area of a substrate, and first link wires are disposed directly on the upper surface of the substrate. Specifically, when a plurality of inorganic layers made of inorganic materials, such as a multi-buffer layer, an active buffer layer, a gate insulating layer, an interlayer insulating layer, a passivation layer, etc., are disposed in a bending region where the substrate is bent, the inorganic layer has high hardness and poor ductility and is easily cracked. Accordingly, the plurality of inorganic layers may be removed from the bending area and the first link wires may be disposed along the upper surface of the substrate and the upper surface of the plurality of inorganic layers. However, a step may occur between the non-bending region where the plurality of inorganic layers are disposed and the bending region where the plurality of inorganic layers are not disposed, and the first link wiring may be disconnected due to the step.

In the display device 100 according to an embodiment of the present invention, a step difference between the bending area BA and the non-bending area NBA may be minimized by disposing the organic layer in the bending area BA of the substrate 110 from which the plurality of inorganic layers are removed. Specifically, an organic layer, that is, the first planarization layer 116 may be further disposed to fill the space between the plurality of inorganic layers. In this case, the first planarization layer 116 made of an organic material has a lower hardness than the plurality of inorganic layers made of an inorganic material, and even when disposed in the bending area BA, it absorbs stress when the substrate 110 is bent, thereby minimizing crack generation.

In addition, the first planarization layer 116 is disposed in the bending area BA to have a thickness similar to that of the plurality of inorganic layers, so that a step difference between the bending area BA and the non-bending area NBA is reduced. Accordingly, it is difficult to cause problems such as disconnection of the first link wiring 141 disposed along the first planarization layer 116 and the plurality of inorganic layers due to a sharp step difference. Therefore, in the display device 100 according to an embodiment of the present invention, the first planarization layer 116 is disposed in the bending area BA, and the plurality of inorganic layers are disposed in the non-bending area NBA, thereby minimizing the step difference between the bending area BA and the non-bending area NBA, thereby minimizing disconnection of the first link wire 141. Also, in the bending area BA, a first planarization layer 116 having a low hardness may be disposed instead of a plurality of inorganic layers having a high hardness, thereby reducing cracks in the first planarization layer 116 caused by bending of the substrate 110 .

3 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention. Compared to the display device 100 of FIG. 1 , the display device 300 of FIG. 3 is different from the display device 100 of FIG. 1 except for the substrate 310 and is substantially the same in other configurations, so redundant description will be omitted.

Referring to FIG. 3 , the upper surface of the substrate 310 in the bending area BA of the display device 300 according to another embodiment of the present invention may be uneven. Specifically, the top surface of the substrate 310 in the bending area BA is not smooth, and an irregular concavo-convex structure is disposed. On the other hand, the upper surface of the substrate 310 in the non-bending area NBA may be flat.

The concavo-convex structure on the upper surface of the substrate 310 may be formed in the process of removing a plurality of inorganic layers. Specifically, a plurality of inorganic layers including a multi-buffer layer 111 , an active buffer layer 112 , a gate insulating layer 113 , and an interlayer insulating layer 114 are disposed on the entire top surface of the substrate 310 . Next, in order to prevent cracks in the plurality of inorganic layers due to bending of the substrate 310 in advance, only the plurality of inorganic layers overlapping the bending area BA among the plurality of inorganic layers disposed on the entire upper surface of the substrate 310 are removed. If the plurality of inorganic layers are not removed, cracks may occur in the plurality of inorganic layers in the bending area BA, and the cracks in the plurality of inorganic layers may propagate to wires disposed in contact with the plurality of inorganic layers, thereby damaging the wires. Accordingly, the plurality of inorganic layers overlapping the bending area BA may be removed. Also, in the process of removing the plurality of inorganic layers, the upper surface of the substrate 310 is damaged, so that the upper surface of the substrate 310 is not smooth and a concavo-convex structure may be disposed.

When a conductive layer is deposited on the upper surface of the substrate 310, the conductive layer may be non-uniformly deposited. In addition, when wiring is formed by etching the non-uniformly deposited conductive layer, a residual film of the conductive layer may remain on the surface of the substrate 310 and cause a short circuit between the wires.

Meanwhile, a first planarization layer 116 is disposed on the substrate 310 in the bending area BA. The first planarization layer 116 may planarize the upper surface of the substrate 310 in the bending area BA. Accordingly, the first planarization layer 116 may be disposed on the top surface of the substrate 310 in the bending area BA to planarize the top surface of the substrate 310 . In addition, the conductive layer can be uniformly deposited on the first planarization layer 116 of the substrate 310, and the remaining film of the conductive layer can be minimized even when the conductive layer is etched.

In the display device 300 according to another embodiment of the present invention, the substrate 310 may be flattened by disposing the first planarization layer 116 on the non-flat substrate 310 . Specifically, the plurality of inorganic layers may be cracked due to bending of the substrate 310, and such cracks may propagate to other structures on the plurality of inorganic layers. Therefore, in order to minimize cracks in the plurality of inorganic layers, the plurality of inorganic layers may be removed from the bending area BA of the substrate 310 . At this time, the upper surface of the substrate 310 in the bending area BA may not be smooth due to the process of removing the plurality of inorganic layers, and may be uneven due to a concave-convex structure. When wiring is formed directly on the upper surface of the substrate 310, the conductive layer is deposited non-uniformly, and when the conductive layer is etched, a remaining film of the conductive layer remains and problems such as a short circuit between wires may occur. At this time, in the display device 300 according to another embodiment of the present invention, the upper surface of the substrate 310 in the bending area BA may be flattened by disposing the first planarization layer 116 on the upper surface of the substrate 310 in the bending area BA. Therefore, when wiring is formed on the plurality of inorganic layers and the first planarization layer 116, the conductive layer is uniformly deposited, and the remaining film of the conductive layer is minimized when the conductive layer is etched, thereby reducing problems such as short circuit between wires.

4 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention. Since the display device 400 of FIG. 4 is different from the display device 100 of FIG. 1 except for the first planarization layer 416 and substantially the same in other configurations, redundant description will be omitted.

Referring to FIG. 4 , in another display device 400 of the present invention, the first flattening layer 416 of the bending area BA extends to the first non-display area NA1 and the second non-display area NA2, and extends to overlap the edges of the plurality of inorganic layers and partial regions of the plurality of inorganic layers.

Specifically, the first planarization layer 416 disposed in the bending area BA may be further disposed even to the first non-display area NA1 extending to one side of the bending area BA. For example, the first planarization layer 416 may further extend to cover the upper surface of the interlayer insulating layer 114 in the first non-display area NA1 . The first planarization layer 416 may be further disposed to cover the edge of the first non-display area NA1 and at least an area near the edge. Accordingly, the first planarization layer 416 may be disposed on the upper surface of the substrate 110 in the bending area BA, and may be disposed to cover at least a portion of the upper surface of the plurality of inorganic layers in the first non-display area NA1.

In addition, the first planarization layer 416 disposed in the bending area BA may be further disposed even to the second non-display area NA2 extending to the other side of the bending area BA. For example, the first planarization layer 416 may further extend to cover the upper surface of the interlayer insulating layer 114 in the second non-display area NA2 . The first planarization layer 416 may be further disposed to cover an edge of the second non-display area NA2 and at least an area near the edge. Accordingly, the first planarization layer 416 may be disposed on the upper surface of the substrate 110 in the bending area BA and may be disposed to cover at least a portion of the upper surface of the plurality of inorganic layers in the second non-display area NA2 .

In the display device 400 according to another embodiment of the present invention, the first flattening layer 416 disposed in the bending area BA may extend to both sides of the bending area BA so as to cover the first non-display area NA1 and the second non-display area NA2 on both sides of the bending area BA. The first planarization layer 416 is made of an organic material. The higher the flowability of the organic material, the flatter the top of the substrate 110 can be, but it is difficult to control the application area of the organic material. Therefore, when the first planarization layer 416 is applied to cover the edges of the plurality of inorganic layers, the first planarization layer 416 does not cover the edges of the plurality of inorganic layers and easily flows in other directions. Accordingly, when the application area of the first planarization layer 416 is further expanded, the first planarization layer 416 may be stably disposed to cover the edges of the plurality of inorganic layers. In addition, when the first planarization layer 416 is disposed only near the edges of the plurality of inorganic layers, a margin area for control is required when the first planarization layer 416 is applied, but when the disposition area of the first planarization layer 416 is expanded, there is no need to design such a margin area. In addition, when the application area of the first planarization layer 416 is expanded, the thickness of a partial area of the first planarization layer 416 covering the upper surfaces of the plurality of inorganic layers can be stably controlled. Therefore, in the display device 400 according to another embodiment of the present invention, the first planarization layer 416 having excellent flowability may be stably disposed to cover the edges of the plurality of inorganic layers by extending the disposition area of the first planarization layer 416 .

5 is a cross-sectional view of a display device according to another exemplary embodiment of the present invention. 6 is a plan view of the display device of FIG. 5 . Since the display device 500 of FIGS. 5 and 6 is substantially the same as the display device 400 of FIG. 4 except for the addition of the second link wire 542 , redundant description will be omitted.

Referring to FIGS. 5 and 6 , a second link wire 542 is further disposed in the first non-display area NA1 . Specifically, the second link wiring 542 is disposed between the gate insulating layer 113 and the interlayer insulating layer 114 . The second link wires 542 may be electrically connected to the first link wires 141 and the data wires DL to transfer data voltages.

The second link wiring 542 may be made of a conductive material, and may be made of the same material on the same layer as the gate electrode 122 of the thin film transistor 120 . For example, the second link wiring 542 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.

First, the second link wire 542 is electrically connected to the first link wire 141 . Specifically, contact holes may be formed in the interlayer insulating layer 114 and the first planarization layer 516 in the first non-display area NA1 to expose one end of the second link wire 542 . Also, one end of the first link wire 141 is disposed to be in contact with one end of the second link wire 542, so that the first link wire 141 and the second link wire 542 may be electrically connected.

The second link line 542 is electrically connected to the data line DL. Specifically, a contact hole may be formed in the interlayer insulating layer 114 to expose the other end of the second link wire 542 . Also, one end of the data line DL is disposed to contact the other end of the second link line 542, so that the second link line 542 and the data line DL may be electrically connected.

Meanwhile, one end of the first link wire 141 may be disposed closer to the bending area BA than the edge of the first planarization layer 516 . Specifically, the first planarization layer 516 is disposed to cover at least a portion of the first non-display area NA1 and the second non-display area NA2 in the bending area BA. At this time, when the first link wiring 141 is formed to the outside of the first planarization layer 516, due to a step difference between the upper surface of the first planarization layer 516 and the interlayer insulating layer 114, the lower portion of the edge of the first planarization layer 516 may not be exposed well, and a remaining film may be generated when the first link wiring 141 is formed.

Therefore, in the display device 500 according to another embodiment of the present invention, one end of the first link line 141 may be disposed in the first planarization layer 516, and the first link line 141 may be connected to the second link line 542 under the first planarization layer 516 to transfer the data voltage to the data line DL of the display area AA. In addition, since the second link wiring 542 is formed on the flat gate insulating layer 113 , when forming the second link wiring 542 , remaining film of the conductive layer is minimized, so that the data voltage can be transferred stably. Therefore, in order to prevent a problem caused by a residual film of the first link wiring 141, for example, a short circuit between wirings, which may occur during a process after the formation of the first planarization layer 516, the first link wiring 141 may not be extended and disposed. Instead, the first link wire 141 is formed to be disposed only on the first planarization layer 516, which is a region in which the first link wire 141 can be stably formed, and the first link wire 141 is connected to the second link wire 542 disposed on a different layer in an area where the first planarization layer 516 is not disposed to transmit data voltage.

Meanwhile, in the display area AA of the substrate 110, numerous lines such as gate lines, data lines DL, high-potential voltage lines, low-potential voltage lines, and reference voltage lines are disposed, and in the non-display area NA, link lines connected to these lines and transmitting gate voltage, data voltage, high-potential voltage, low-potential voltage, and reference voltage from the driving IC are disposed. However, when arranging these wires on one layer, space for arranging the wires is insufficient, and in particular, the size of the non-display area NA where an image is not displayed may also increase. In the case of the display device 500, research is being conducted to implement the display device 500 having a large display area AA and reduced volume and weight by reducing the non-display area NA.

Therefore, in the display device 500 according to another embodiment of the present invention, the size of the non-display area NA can be reduced by arranging the first link wire 141 and the second link wire 542, which transfer the data voltage to the data wire DL, on different layers. Specifically, the non-display area NA can be reduced when the first link wires 141 are divided and disposed on several layers, compared to when the first link wires 141 are disposed at regular intervals only on the same layer without the second link wires 542. When the data voltage transmitted to the first link wire 141 is transferred to the second link wire 542 disposed on another layer, a link wire transmitting another signal may be further disposed on the first planarization layer 516 on the second link wire 542, for example, in the first non-display area NA1 where the first link wire 141 is not disposed. Therefore, regardless of whether the first planarization layer 516 is disposed, the size of the non-display area NA can be reduced by freely changing the design of the first link wire 141 and the second link wire 542, and since the wires are disposed on different layers and insulated with an insulating material, short circuits between wires can be minimized.

A display device according to various embodiments of the present disclosure can be described as follows.

A display device according to an exemplary embodiment includes a substrate including a bending area and a non-bending area extending from both sides of the bending area, a plurality of inorganic layers disposed in the non-bending area, and an organic layer filling a space between the plurality of inorganic layers in the bending area.

According to another feature of the present invention, a first link wiring disposed on the organic layer may be further included, and an edge of the organic layer may be disposed on a plurality of inorganic layers.

According to another feature of the present invention, a second link wiring disposed between the plurality of inorganic layers may be further included, and the first link wiring and the second link wiring may be in contact with each other through contact holes of at least some inorganic layers among the plurality of inorganic layers and contact holes of the organic layer.

According to another feature of the present invention, an end of the first link wiring may be closer to the bending area than an edge of the organic layer.

According to another feature of the present invention, a signal wire disposed in the non-bending area and connected to the second link wire may be further included.

According to another feature of the present invention, the non-bending area includes a first non-display area extending from one side of the bending area and a second non-display area extending from the other side of the bending area, and both edges of the organic layer may be disposed in the first non-display area and the second non-display area, respectively.

According to another feature of the present invention, the substrate further includes a plurality of thin film transistors disposed in a non-bending region and a planarization layer disposed to cover the plurality of thin film transistors, and the organic layer and the planarization layer may be made of the same material.

According to another feature of the present invention, the plurality of inorganic layers may be at least one of a multi-buffer layer, an active buffer layer, a gate insulating layer, an interlayer insulating layer, and a passivation layer.

According to another feature of the invention, the surface of the substrate may be non-planar.

A display device according to another embodiment of the present invention includes a substrate including a non-bending area and a bending area between the non-bending area, a plurality of inorganic layers disposed in the non-bending area, and a first planarization layer disposed in the bending area to planarize an upper portion of the substrate in the bending area.

According to another feature of the present invention, a first link wiring disposed on the first planarization layer may be further included, and the first planarization layer may cover edges of the plurality of inorganic layers.

According to another feature of the present invention, a second link wiring disposed on the plurality of inorganic layers, a plurality of thin film transistors disposed on the substrate, and a second planarization layer covering the plurality of thin film transistors may be further included.

According to another feature of the present invention, the first link wiring and the second link wiring contact between the edge of the first planarization layer and the edge of the plurality of inorganic layers, and the first planarization layer may be opened in a region where the first link wiring and the second link wiring contact each other.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100, 300, 400, 500: display device
110, 310: substrate
111: multi-buffer layer
112: active buffer layer
113: gate insulating layer
114: interlayer insulating layer
115: passivation layer
116, 416, 516: first planarization layer
117: second planarization layer
118: bank
120: thin film transistor
121: active layer
122: gate electrode
123: source electrode
124: drain electrode
130: organic light emitting element
131: anode
132: organic light emitting layer
133: cathode
141: first link wiring
542: second link wiring
SP: sub pixel
DL: data wiring
PD: pad
AA: display area
NA: non-display area
NA1: first non-display area
NA2: Second non-display area
PA: pad area
BA: bending area
NBA: non-bending area

Claims (17)

a substrate including a bending area and a non-bending area extending from both sides of the bending area;
a plurality of inorganic layers disposed in the non-bending area;
an organic layer filling a space between the plurality of inorganic layers in the bending area;
a bank disposed on the plurality of inorganic layers in the non-bending area; and
a first link wiring disposed on the organic layer in the bending region;
The bank is disposed spaced apart from the bending region,
A top surface of the uppermost inorganic layer among the plurality of inorganic layers is disposed higher than a top surface of the organic layer. According to claim 1,
An edge of the organic layer is disposed between the plurality of inorganic layers. According to claim 2,
Further comprising a second link wiring disposed between the plurality of inorganic layers,
The first link wiring and the second link wiring are in contact with each other through contact holes of at least some of the inorganic layers and contact holes of the organic layer, among the plurality of inorganic layers. According to claim 3,
The display device of claim 1 , wherein an end of the first link wiring is closer to the bending region than an edge of the organic layer. According to claim 3,
and a signal wire disposed in the non-bending area and connected to the second link wire. According to claim 2,
The non-bending region,
a first non-display area extending from one side of the bending area; and
A second non-display area extending from the other side of the bending area;
Both edges of the organic layer are disposed in the first non-display area and the second non-display area, respectively. According to claim 1,
a plurality of thin film transistors disposed in the non-bending region on the substrate; and
Further comprising a planarization layer disposed to cover the plurality of thin film transistors,
The organic layer and the planarization layer are made of the same material. According to claim 1,
The plurality of inorganic layers is at least one of a multi-buffer layer, an active buffer layer, a gate insulating layer, an interlayer insulating layer, and a passivation layer. According to claim 1,
The surface of the substrate is non-flat, the display device. a substrate including a non-bending area and a bending area between the non-bending area;
a plurality of inorganic layers disposed in the non-bending area;
a first planarization layer disposed in the bending area to planarize an upper portion of the substrate in the bending area;
a bank disposed on the plurality of inorganic layers in the non-bending area; and
A first link wiring disposed on the first planarization layer in the bending region;
The bank is spaced apart from the bending region,
A top surface of the uppermost inorganic layer among the plurality of inorganic layers is disposed higher than a top surface of the first planarization layer. According to claim 10,
The first planarization layer covers edges of some of the inorganic layers among the plurality of inorganic layers. According to claim 11,
a second link wire disposed on the plurality of inorganic layers;
a plurality of thin film transistors disposed on the substrate; and
The display device further comprises a second planarization layer covering the plurality of thin film transistors. According to claim 12,
The first link wiring and the second link wiring contact between an edge of the first planarization layer and an edge of the plurality of inorganic layers,
The first planarization layer is open in a region where the first link wiring and the second link wiring contact each other. According to claim 7,
wherein the planarization layer is disposed under the bank to cover the plurality of inorganic layers, the organic layer, and the plurality of thin film transistors. According to claim 14,
The plurality of inorganic layers,
a multi-buffer layer disposed on the substrate;
an active buffer layer disposed on the multi-buffer layer;
a gate insulating layer disposed on the active buffer layer;
an interlayer insulating layer disposed on the gate insulating layer; and
A passivation layer disposed on the interlayer insulating layer;
At least a portion of the upper surface of the organic layer is disposed between the upper surface of the passivation layer and the lower surface of the multi-buffer layer. According to claim 12,
wherein the second planarization layer is disposed on the first planarization layer in the bending region and disposed between the plurality of inorganic layers and the bank in the non-bending region to planarize upper portions of the first planarization layer and the plurality of inorganic layers. According to claim 10,
The plurality of inorganic layers,
a multi-buffer layer disposed on the substrate;
an active buffer layer disposed on the multi-buffer layer;
a gate insulating layer disposed on the active buffer layer;
an interlayer insulating layer disposed on the gate insulating layer; and
A passivation layer disposed on the interlayer insulating layer;
At least a portion of the upper surface of the first planarization layer is disposed between the upper surface of the passivation layer and the lower surface of the multi-buffer layer.

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