KR102559479B1 - Method for manufacturing a compound semiconductor solar cell - Google Patents

Abstract

The present invention relates to a method for manufacturing a compound semiconductor solar cell.
A method of manufacturing a compound semiconductor solar cell according to one aspect of the present invention includes forming a sacrificial layer on a mother substrate; forming a compound semiconductor layer on the sacrificial layer; performing primary mesa etching to form a first region of the compound semiconductor layer as a first portion having a first thickness and forming a second region of the compound semiconductor layer as a second portion having a second thickness smaller than the first thickness; forming a protective layer on the first surface of the compound semiconductor layer; separating the compound semiconductor layer from the mother substrate; forming a rear electrode on a second surface of the compound semiconductor layer opposite to the first surface; removing the protective layer; removing the second portion of the compound semiconductor layer in the second region by performing secondary mesa etching; and scribing the back electrode of the second region.

Description

Manufacturing method of compound semiconductor solar cell {METHOD FOR MANUFACTURING A COMPOUND SEMICONDUCTOR SOLAR CELL}

The present invention relates to a method for manufacturing a compound semiconductor solar cell, and more particularly, to a method for manufacturing a compound semiconductor solar cell capable of improving yield by securing stability in a mesa etching process and reducing manufacturing cost by forming a back electrode using inexpensive electrode materials.

A compound semiconductor operates as a semiconductor by combining two or more elements rather than a single element such as silicon or germanium. Various types of compound semiconductors have been developed and used in various fields, and are typically used in light emitting devices such as light emitting diodes and laser diodes using photoelectric conversion effects, solar cells, and thermoelectric conversion devices using Peltier Effect.

Among them, the compound semiconductor solar cell is a group III-V compound semiconductor such as gallium arsenide (hereinafter referred to as GaAs), gallium indium phosphorus (hereinafter referred to as GaInP), gallium aluminum arsenide (hereinafter referred to as GaAlAs), gallium indium arsenide (hereinafter referred to as GaInAs), aluminum indium arsenide (hereinafter referred to as AlInP), cadmium sulfur (CdS), cadmium tellurium (CdTe), zinc sulfur Various layers are formed using group II-VI compound semiconductors such as (ZnS) and group I-III-VI compound semiconductors represented by copper indium selenium (CuInSe2).

Various layers formed of compound semiconductors (hereinafter, referred to as compound semiconductor layers) are formed on a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or any other suitable method for forming an epitaxial layer, and then a grid pattern front electrode is formed on the front surface of the compound semiconductor layer and a sheet-shaped rear electrode is formed on the rear surface of the compound semiconductor layer.

Therefore, conventionally, after forming a front electrode and a rear electrode on a compound semiconductor layer, an anti-etching film is formed on the entire surface of the compound semiconductor layer, mesa etching is performed using an etching solution (acid/base) for etching the compound semiconductor forming the compound semiconductor layer, and then the rear electrode exposed by the mesa etching is scribed to manufacture a plurality of compound semiconductor solar cells.

Here, mesa etching refers to an etching process for manufacturing a plurality of compound semiconductor solar cells from one compound semiconductor layer by separating one compound semiconductor layer into several layers.

In the manufacturing method of the compound semiconductor solar cell having this configuration, the metal forming the rear electrode of the compound semiconductor solar cell must satisfy conditions such as low contact resistance with the lowermost layer of the compound semiconductor layer, for example, a rear contact layer formed of GaAs, not being etched through a mesa etching process and an Epotaxial Lift Off (ELO) process, and having high rear surface reflectivity.

Therefore, gold (Au) is generally used as a metal forming the back electrode.

However, since gold (Au) forming the back electrode is very expensive, it is very difficult to lower the manufacturing cost of the compound semiconductor solar cell.

Therefore, a novel method capable of securing stability in a mesa etching process while reducing manufacturing cost by forming a rear electrode with a metal cheaper than gold (Au) is required.

An object of the present invention is to provide a method for manufacturing a compound semiconductor solar cell capable of improving yield by securing stability in a mesa etching process and reducing manufacturing cost by manufacturing a back electrode using an inexpensive metal material.

A method of manufacturing a compound semiconductor solar cell according to one aspect of the present invention includes forming a sacrificial layer on a mother substrate; forming a compound semiconductor layer on the sacrificial layer; performing primary mesa etching to form a first region of the compound semiconductor layer as a first portion having a first thickness and forming a second region of the compound semiconductor layer as a second portion having a second thickness smaller than the first thickness; forming a protective layer on the first surface of the compound semiconductor layer; separating the compound semiconductor layer from the mother substrate; forming a rear electrode on a second surface of the compound semiconductor layer opposite to the first surface; removing the protective layer; removing the second portion of the compound semiconductor layer in the second region by performing secondary mesa etching; and scribing the rear electrode of the second region.

According to one aspect of the present invention, the forming of the rear electrode may include forming a first electrode layer directly contacting the second surface of the compound semiconductor layer with silver (Ag); and forming a second electrode layer of copper (Cu) on the rear surface of the first electrode layer.

In this case, the second electrode layer may have a thickness of 70% or more of the total thickness of the rear electrode.

The compound semiconductor layer may have a single junction structure or a multi-junction structure.

In the case of a single junction structure, the compound semiconductor layer includes a first light absorbing layer based on indium phosphate (InP); at least one first peripheral layer located on the first surface of the first light absorption layer and based on indium phosphide (InP) and/or gallium arsenide (GaAs); and at least one second peripheral layer positioned on the second surface of the first light absorption layer and based on indium phosphide (InP) and/or gallium arsenide (GaAs).

In the case of a single junction structure, the first mesa etching step includes a first mesa etching step of removing the first peripheral layer of the second region using a first solution containing hydrochloric acid (HCl) and/or a second solution of a mixture of ammonium hydroxide (NH ₄ OH)/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI); A second mesa etching step to remove the; and a third mesa etching step of removing the second peripheral layer of the second region using a third solution obtained by mixing the second solution and/or phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI).

In the case of a multi-junction structure, the compound semiconductor layer may include a second light absorbing layer based on gallium arsenide (GaAs); at least one third peripheral layer located on the first surface of the second light absorption layer and based on indium phosphide (InP) and/or gallium arsenide (GaAs); and at least one fourth peripheral layer positioned on a second surface of the second light absorbing layer and based on indium phosphide (InP) and/or gallium arsenide (GaAs), wherein the second light absorbing layer may be positioned between the first light absorbing layer and the back electrode.

In the case of a multi-junction structure, the first mesa etching step may include a first mesa etching step of removing the first peripheral layer of the second region using a second solution in which a first solution containing hydrochloric acid (HCl) and/or a mixture of ammonium hydroxide (NH ₄ OH)/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) is used; a second mesa etching step of removing the first light absorbing layer of the second region using the first solution; and a third mesa etching step of removing the second peripheral layer of the second region using the first solution and/or the second solution, wherein the secondary mesa etching step comprises: a fourth mesa etching step of removing the third peripheral layer of the second region using the first solution and/or the second solution; a fifth mesa etching step of removing the second light absorbing layer of the second region using the second solution; A sixth mesa etching step of removing the fourth peripheral layer of the second region using a second solution and/or a third solution in which a mixture of phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) is used.

According to one aspect of the present invention, among the second peripheral layer in the case of a single junction structure and the fourth peripheral layer in the case of a multi-junction structure, the lowermost layer directly contacting the rear electrode may be formed based on gallium arsenide (GaAs), and the lowermost layer may be removed using the third solution.

The third solution may be formed by mixing phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) at a ratio of 1:0.3 to 3:5 to 20.

And the forming of the protective layer may include forming a first protective layer based on indium phosphorus (InP) on the first peripheral layer, forming a second protective layer made of copper (Cu) on the first protective layer, forming a third protective layer formed of at least one selected from silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), and molybdenum (Mo) or an alloy thereof on the second protective layer, and attaching a protective film on the third protective layer.

The performing of the first mesa etching and the performing of the second mesa etching may be performed using the same etch stop layer.

In this case, the anti-etching layer for performing the first mesa etching is not removed after completing the first mesa etching, and may be removed after performing the second mesa etching.

Alternatively, the performing of the first mesa etching and the performing of the second mesa etching may be performed using different etch stop layers.

In this case, after the first mesa etching is performed using the anti-etching layer formed on the second region, the anti-etching layer is removed, and another anti-etching layer for performing the secondary mesa etching may be formed on the second region.

According to the method for manufacturing a compound semiconductor solar cell according to the present invention, it is not necessary to use expensive gold (Au) when forming a rear electrode, and since the rear electrode can be formed using copper (Cu)/silver (Ag), which is very inexpensive compared to gold, the manufacturing cost of the compound semiconductor solar cell can be reduced.

In addition, since the first mesa etching is performed before forming the back electrode and the second mesa etching is performed after forming the back electrode, it is possible to prevent the indium phosphorus (InP) based light absorbing layer or the surrounding layer from not being well removed by the first solution even when copper (Cu) or silver (Ag) having a higher oxidation tendency than the indium phosphorus (InP) based light absorbing layer or the surrounding layer is used as the rear electrode material.

In addition, since the lowermost layer of the second peripheral layer is removed using a third solution in which silver (Ag) forming the first electrode layer of the rear electrode has etching resistance, the first electrode layer can be prevented from being etched even if the first electrode layer is exposed to the third solution at the moment the lowermost layer is removed.

Accordingly, stability in a mesa etching process may be secured, yield may be improved, and manufacturing cost may be reduced.

1 is a block diagram showing a method of manufacturing a compound semiconductor solar cell according to a first embodiment of the present invention.
FIG. 2 is a process diagram illustrating the step of forming the sacrificial layer and the step of forming the compound semiconductor layer shown in FIG. 1 .
FIG. 3 is a process chart showing a first embodiment of the primary mesa etching step shown in FIG. 1 .
4 is a process chart showing the protective layer forming step shown in FIG. 1 .
FIG. 5 is a process chart showing the separation step shown in FIG. 1 .
FIG. 6 is a process chart showing a step of forming a back electrode shown in FIG. 1 .
FIG. 7 is a process chart showing a first embodiment of the secondary mesa etching step shown in FIG. 1 .
FIG. 8 is a process chart showing the scribing step shown in FIG. 1 .
FIG. 9 is a cross-sectional view of a compound semiconductor solar cell having a single junction structure compound semiconductor layer manufactured by the manufacturing method shown in FIG. 1 .
10 is a graph comparing light reflectivity for each wavelength of back electrode forming materials.
FIG. 11 is a process chart showing a second embodiment of the primary mesa etching step shown in FIG. 1 .
FIG. 12 is a process chart showing a second embodiment of the secondary mesa etching step shown in FIG. 1 .
FIG. 13 is a cross-sectional view of a compound semiconductor solar cell having a double junction structure compound semiconductor layer manufactured by the manufacturing method shown in FIG. 1 .

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. This is not intended to limit the present invention to specific embodiments, and it can be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

In describing the present invention, terms such as first and second may be used to describe various components, but the components may not be limited by the terms. The terms may only be used for the purpose of distinguishing one component from another.

For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention.

The term “and/or” can include a combination of a plurality of related recited items or any one of a plurality of related recited items.

When an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, but it may be understood that another element may exist in the middle.

On the other hand, when a component is referred to as “directly connected” or “directly coupled” to another component, it may be understood that no other component exists in the middle.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions may include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "include" or "have" are intended to specify that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, and one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

In the drawings, the thickness is shown enlarged to clearly express the various layers and regions. When a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between.

Unless defined otherwise, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs.

Terms such as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with the meaning in the context of the related art, and may not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application.

In addition, the following embodiments are provided to more completely explain to those with average knowledge in the art, and the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing a method of manufacturing a compound semiconductor solar cell according to a first embodiment of the present invention, FIG. 2 is a process diagram showing the sacrificial layer formation step and the compound semiconductor layer formation step shown in FIG.

4 is a process chart showing the protective layer formation step shown in FIG. 1, FIG. 5 is a process chart showing the separation step shown in FIG. 1, and FIG. 6 is a process chart showing the rear electrode formation step shown in FIG.

7 is a process chart showing a first embodiment of the secondary mesa etching step shown in FIG. 1, and FIG. 8 is a process chart showing the scribing step shown in FIG.

9 is a cross-sectional view of a compound semiconductor solar cell having a compound semiconductor layer having a single junction structure manufactured by the manufacturing method shown in FIG. 1, and FIG. 10 is a graph comparing light reflectivity for each wavelength of a back electrode forming material.

First, a compound semiconductor solar cell having a single junction structure compound semiconductor layer manufactured by the manufacturing method of the present invention will be described with reference to FIG. 9 .

A compound semiconductor solar cell having a compound semiconductor layer having a single junction structure includes only one cell, that is, a first cell C1, and each layer forming the first cell C1 is all formed of a compound semiconductor.

The first cell C1 includes a first light absorbing layer PV1, a first window layer WD1 positioned on a first surface of the first light absorbing layer PV1, for example, a front surface, a first back surface electric field layer BSF1 positioned on a second surface of the first light absorbing layer PV1, for example, a rear surface, a front contact layer FC positioned on the front surface of the first window layer WD1, and a first back surface electric field layer BSF1. It includes a back contact layer (BC) located on the back side.

Here, the front window layer WD1 and the front contact layer FC form a first peripheral layer BL1, and the back surface electric layer BSF1 and the back contact layer BC form a second peripheral layer BL2.

In addition to the first cell C1, the compound semiconductor solar cell having a single junction structure compound semiconductor layer further includes a grid-shaped front electrode 100 positioned on the front contact layer FC and a sheet-shaped rear electrode 200 positioned on the rear surface of the rear contact layer BC.

The first light absorbing layer PV1 includes a first base layer PV1-1 containing n-type impurities and in contact with the first window layer WD1, and a first emitter layer PV1-2 containing p-type impurities and forming a pn junction with the first base layer PV1-1 and positioned on the rear surface of the first base layer PV1-1. The first base layer PV1-1 and the first emitter layer PV1-2 ) is formed of a compound semiconductor based on indium phosphorus (hereinafter referred to as InP).

For example, the first base layer PV1-1 is formed of n-type GaInP, and the first emitter layer PV1-2 is formed of p-type GaInP.

The p-type impurity doped into the first emitter layer PV1-2 may be selected from carbon (C), magnesium (Mg), zinc (Zn), or a combination thereof, and the n-type impurity doped into the first base layer PV1-1 may be selected from silicon (Si), selenium (Se), tellurium (Te), or a combination thereof.

The first base layer PV1-1 may be located in an area adjacent to the front electrode 100, and the first emitter layer PV1-2 may be positioned immediately below the first base layer PV1-1 and in an area adjacent to the rear electrode 200.

That is, the distance between the first base layer PV1-1 and the front electrode 100 is smaller than the distance between the first emitter layer PV1-2 and the front electrode 100, and the distance between the first base layer PV1-1 and the rear electrode 200 is greater than the distance between the first emitter layer PV1-2 and the rear electrode 200.

Accordingly, since a pn junction in which the first emitter layer PV1-2 and the first base layer PV1-1 are bonded is formed inside the first light absorbing layer PV1, electron-hole pairs generated by light incident on the first light absorbing layer PV1 are separated into electrons and holes due to an internal potential difference formed by the pn junction of the first light absorbing layer PV1, so electrons move toward the n-type side and holes move toward the p-type side.

Accordingly, holes generated in the first light absorbing layer PV1 move to the rear electrode 200 through the back contact layer BC, and electrons generated in the first light absorbing layer PV1 move to the front electrode 100 through the first window layer WD1 and the front contact layer FC.

In contrast, when the positions of the first emitter layer PV1-2 and the first base layer PV1-1 are reversed, holes generated in the first light absorbing layer PV1 move to the front electrode 100 through the front contact layer FC, and electrons generated in the first light absorbing layer PV1 move to the rear electrode 200 through the rear contact layer BC.

When the first cell C1 includes the first back surface electric field layer BSF1, the first back surface electric field layer BSF1 has the same conductivity type as an upper layer that is in direct contact with, that is, the first emitter layer PV1-2, and may be formed of the same material as the first window layer WD1.

The first back surface electric field layer BSF1 is formed entirely on the rear surface of the first emitter layer PV1-2, i.e., an upper layer in direct contact, in order to effectively block the movement of charges (holes or electrons) that should move toward the front electrode 100 toward the rear electrode 200.

That is, in the solar cell shown in FIG. 9, when the first back surface electric field layer (BSF1) is formed on the rear surface of the first emitter layer (PV1-2), the first back surface electric field layer (BSF1) acts to block electrons from moving toward the rear electrode 200. located

The first emitter layer PV1-2 and the first base layer PV1-1 may be made of the same material having the same band gap (homojunction), or may be made of different materials having different band gaps (heterojunction).

In the case of a homogeneous junction, the first base layer PV1 - 1 may be formed of n-type GaInP, and the first emitter layer PV1 - 2 may be formed of p-type GaInP.

The first window layer WD1 may be formed between the first light absorbing layer PV1 and the front electrode 100, and may be formed by doping a 4-component group III-VI semiconductor compound with a second conductivity type, that is, an n-type impurity.

However, when the first emitter layer PV1-2 is positioned on the first base layer PV1-1 and the first window layer WD1 is positioned on the first emitter layer PV1-2, the first window layer WD1 may include impurities of the first conductivity type, that is, p-type.

The first window layer WD1 serves to passivate the front surface of the first light absorbing layer PV1. Therefore, when carriers (electrons or holes) move to the surface of the first light absorbing layer PV1, the first window layer WD1 can prevent the carriers from recombination on the surface of the first light absorbing layer PV1.

In addition, since the first window layer WD1 is disposed on the front surface of the first light absorbing layer PV1, that is, on the light incident surface, it needs to have an energy bandgap higher than that of the first light absorbing layer PV1 in order to absorb almost no light incident on the first light absorbing layer PV1.

In addition, it is necessary to form the first window layer WD1 with a material that is difficult to dissolve in the ELO process using hydrofluoric acid.

Therefore, in the present invention, the first window layer WD1 may be formed of AlInP or AlGaInP.

AlGaInP can exhibit bandgap characteristics similar to those of AlInP by appropriately adjusting the aluminum (Al) content, and unlike AlInP, it can suppress the dissolution by hydrofluoric acid used in the ELO process.

In the band gap of AlGaInP, a direct/indirect transition occurs when the aluminum content is 53%, and in the section where the aluminum content is 53% or less, the band gap rapidly decreases as the aluminum content decreases, and in the section where the aluminum content is 53% or more, it can be seen that it has a band gap almost similar to that of AlInP.

For example, when the content of aluminum is 50%, that is, when the content of aluminum and gallium is 1:1, it can be seen that AlGaInP has a band gap of 2.22Ev, similar to that of 2.3eV, which is the band gap of AlInP.

In addition, as a result of testing the dissolution tendency of AlGaInP according to the aluminum content, it was found that defects having a size of 100 μm or more occur after the ELO process when the aluminum content exceeds 70%.

Therefore, it is desirable to control the aluminum content within a range capable of suppressing the occurrence of defects due to hydrofluoric acid while having a band gap similar to that of AlInP, for example, 2.2 eV or more.

Here, the reason for limiting the minimum aluminum content to 45 is to form a band gap of 2.2ev or more of AlGaInP, and the reason for limiting the maximum aluminum content to 70 is to suppress dissolution by hydrofluoric acid.

Therefore, the first window layer WD1 is preferably formed of n-type Al _x Ga _{1 - x} InP having X of 0.45 to 0.7.

The first window layer WD1 formed of AlGaInP may be formed to a thickness of 20 to 35 nm, and the first back surface electric layer BSF1 may be formed of the same material as the first window layer WD1.

Also, the first back surface electric field layer BSF1 may be formed thicker than the thickness of the first window layer WD1. For example, the first back surface field layer BSF1 may be formed to a thickness of 50 to 100 nm.

The anti-reflection film (not shown) may be positioned on the entire surface of the first window layer WD1 except for the area where the front electrode 100 and/or the front contact layer FC are positioned.

Alternatively, the anti-reflection layer may be disposed not only on the first window layer WD1 but also on the front contact layer FC and the front electrode 100 .

The antireflection film of this configuration may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, a derivative thereof, or a combination thereof.

Although not shown in FIG. 9 , the compound semiconductor solar cell may further include a bus bar electrode that physically connects the plurality of front electrodes 100 , and the bus bar electrode may be exposed to the outside without being covered by an anti-reflection film.

The front electrode 100 may be formed to elongate in a first direction, and may be spaced apart at regular intervals along a second direction (YY′) orthogonal to the first direction.

The front electrode 100 having this configuration may be formed of an electrically conductive material, and for example, may include at least one of metals such as gold (Au), germanium (Ge), and nickel (Ni).

The front contact layer FC positioned between the first window layer WD1 and the front electrode 100 may be formed by doping a group III-VI semiconductor compound with impurities of the second conductivity type at a higher doping concentration than that of the first base layer PV1-1. For example, the front contact layer FC may be formed of n+ type GaAs.

The front contact layer FC forms an ohmic contact between the first window layer WD1 and the front electrode 100 . That is, when the front electrode 100 directly contacts the first window layer WD1, the ohmic contact between the front electrode 100 and the first light absorbing layer PV1 is not well formed due to the low impurity doping concentration of the first window layer WD1.

Therefore, the carriers that have migrated to the first window layer WD1 cannot easily move to the front electrode 100 and can disappear.

However, when the front contact layer FC is formed between the front electrode 100 and the first window layer WD1, carriers are smoothly moved by the front contact layer FC forming an ohmic contact with the front electrode 100, thereby increasing the short-circuit current density (Jsc) of the compound semiconductor solar cell. Accordingly, the efficiency of the solar cell can be further improved.

The front contact layer FC may be formed in the same planar shape as the front electrode 100 .

The back surface contact layer BC positioned on the rear surface of the first back surface electric field layer BSF1 is entirely positioned on the rear surface of the first back surface electric field layer BSF1, and may be formed by doping a III-VI semiconductor compound with impurities of the first conductivity type. For example, the back contact layer BC may be formed of p-type GaAs.

The back contact layer BC can form an ohmic contact with the back electrode 200, so that the short-circuit current density (Jsc) of the compound semiconductor solar cell can be further improved. Accordingly, the efficiency of the solar cell can be further improved.

The thickness of the front contact layer FC and the back contact layer BC may each be formed to a thickness of 100 nm to 300 nm. For example, the front contact layer FC may be formed to a thickness of 100 nm and the back contact layer BC may be formed to a thickness of 300 nm.

Unlike the front electrode 100, the rear electrode 200 positioned on the rear surface of the rear contact layer BC may be formed of a sheet-shaped conductor entirely located on the rear surface of the rear contact layer BC. That is, the rear electrode 200 may be referred to as a sheet electrode located on the entire rear surface of the rear contact layer BC.

In this case, the back electrode 200 may be formed on the same plane as the first light absorbing layer PV1 and may include a first electrode layer 200A and a second electrode layer 200B.

The first electrode layer 200A is located on the lowermost layer of the second peripheral layer BL2 of the first cell C1, for example, on the rear surface of the back contact layer BC, and directly contacts the rear surface of the rear contact layer BC to transmit carriers. The second electrode layer 200B is located on the rear surface of the first electrode layer 200A to support the first electrode layer 200A.

At this time, the first electrode layer 200A that transmits the charge (carrier) is formed of a material having a similar level of contact resistance as the conventional back electrode forming material, that is, gold (Au), and high reflectivity. It is preferable to form.

Accordingly, as the zinc (Zn) confirmed the contact resistance with the P+GAAS layer doped at a high concentration of 1E19/cm 3, gold (AU) has a contact resistance of approximately 3.5 × ^10-3 Ω cm ^{2, and the silver (AG) has a contact resistance of approximately 3.6 × 10-3 ω} , and copper (Cu) is approximately 5.2 ^× 10-2. It can be seen that it has a contact resistance ^of Ω cm ² .

In addition, according to the confirmation of the light reflectivity for each wavelength with reference to FIG. 10, silver (Ag) has an average reflectance of 95% or more in the wavelength range of interest from 600 nm to 950 nm, but copper (Cu) It can be seen that the reflectance is lower than that of silver (Ag).

Therefore, as the first electrode layer 200A directly in contact with the back contact layer, silver (Ag) having excellent electrical bonding characteristics with the back contact layer BC and having an average reflectance of 95% or more in a wavelength range of 600 nm to 950 nm can be formed by depositing silver (Ag) to a thickness of 50 to 500 nm by physical vapor deposition.

And, as the second electrode layer 200B, copper (Cu), which has a higher contact resistance than silver (Ag) forming the first electrode layer 200B and has a low reflectivity in a wavelength range of 600 nm to 950 nm, but a low material cost, can be formed by plating to a thickness of 1 to 10 μm by electroplating.

As described above, when silver (Ag) having a low contact resistance with the back contact layer (BC) and a high average reflectance in a wavelength range of 600 nm to 950 nm is used as a material forming the first electrode layer (200A), the contact resistance with the back contact layer (BC) is maintained well, and photon recycling can be increased due to light loss reduction, thereby improving the efficiency of the solar cell.

A compound semiconductor solar cell having such a configuration can be manufactured using an ELO process.

Hereinafter, a method of manufacturing the compound semiconductor solar cell shown in FIG. 9 will be described with reference to FIGS. 1 to 8 .

The manufacturing method of the present invention largely includes: forming the sacrificial layer 400 on the mother substrate 300 (S10), forming the first compound semiconductor layer CS1 on the sacrificial layer 400 (S20), and performing primary mesa etching to form the second region A2 of the first compound semiconductor layer CS1 to a smaller second thickness T2 than the first thickness T1 of the first region A1 (S30). , Forming a protective layer PL on the first surface of the first compound semiconductor layer CS1 (S40), separating the first compound semiconductor layer CS1 from the mother substrate 300 (S50), forming a back electrode 200 on the second surface of the first compound semiconductor layer CS1 opposite to the first surface (S60), removing the protective layer PL (S70), performing secondary mesa etching to obtain a second region ( It may include removing the second portion P2 of the first compound semiconductor layer CS1 located in A2) (S80), and scribing the back electrode 200 located in the second region A2 (S90).

To explain this in detail, first, the sacrificial layer 400 is formed on one side of the mother substrate 300, for example, the GaAs substrate, which serves as a base layer to provide an appropriate lattice structure on which the first compound semiconductor layer CS1 is formed (S10), and the first compound semiconductor layer CS1 is formed on the sacrificial layer 400 (S20).

The sacrificial layer 400 and the first compound semiconductor layer CS1 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or any other suitable method for forming an epitaxial layer.

At this time, the mother substrate 300 has a size capable of manufacturing a plurality of compound semiconductor solar cells, and the first compound semiconductor layer CS1 formed on the sacrificial layer 400 of the mother substrate 300 also has the same size as the mother substrate 300. For example, the planar area of the mother substrate 300 and the planar area of the first compound semiconductor layer CS1 are equal to each other.

For simplification of the drawings, FIGS. 2 to 9 illustrate an example in which one first compound semiconductor layer CS1 separated from the mother substrate 300 forms two compound semiconductor solar cells, but the number of compound semiconductor solar cells may be appropriately selected as needed.

In the first compound semiconductor layer CS1, a back contact layer BC formed of p-type GaAs and a first back surface electric field layer BSF1 formed of p-type AlGaInP are sequentially formed to form a second peripheral layer BL2, and a first emitter layer PV1-2 formed of p-type GaInP and a first base layer PV1-1 formed of n-type GaInP are sequentially formed to form a first light absorption layer PV1, n-type AlGa The first peripheral layer BL1 may be manufactured by sequentially forming a first window layer WD1 formed of InP and a front surface contact layer FC formed of n+ type GaAs to form the first peripheral layer BL1.

In this case, at least one layer among the plurality of layers constituting the first peripheral layer BL1 may be omitted, and at least one layer among the plurality of layers constituting the second peripheral layer BL2 may also be omitted.

Subsequently, an anti-etching film 500A exposing the second area A2 of the first compound semiconductor layer CS1 is formed on the first peripheral layer BL1 of the first area A1, and a first mesa etching is performed using the anti-etching film 500A as a mask (S30).

In the present invention, the reason why the first mesa etching is performed before forming the rear electrode 200 is that when an etching process using a first solution containing hydrochloric acid (HCl) is performed to remove a layer formed based on InP such as GaInP, AlInP, or AlGaInP among the first peripheral layers BL1 forming the first cell C1, silver (Ag) / copper (Cu), which is a material forming the rear electrode 200, is oxidized This is to prevent poor etching of InP-based compound semiconductor layers due to a higher tendency than that of InP-based compound semiconductor layers.

In this way, if the first mesa etching is performed before forming the back electrode, the portion to be removed of the layer formed of GaInP, AlInP, or AlGaInP in the first compound semiconductor layer CS1 can be effectively removed using the first solution.

When the first compound semiconductor layer CS1 having a single junction structure is provided, the first mesa etching step S30 includes a first mesa etching step of removing the first peripheral layer BD1 of the second region A2 by using a first solution containing hydrochloric acid (HCl) and/or a second solution in which ammonium hydroxide (NH ₄ OH)/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) is mixed.

Specifically, the portion located in the second region A2 of the front contact layer FC formed of n+ type GaAs of the first peripheral layer BL1 is removed using a second solution formed by mixing ammonium hydroxide, hydrogen peroxide and deionized water in a ratio of 1:2:10, and then, the portion located in the second region A2 of the first window layer WD1 formed of n-type AlInP or n-type AlGaInP is removed using the first solution. do

When the first peripheral layer BL1 is formed of only one layer, the corresponding layer may be removed using only one of the first solution and the second solution in the first mesa etching step.

When the first mesa etching step is performed, the first region A1 of the first compound semiconductor layer CS1 is formed of a first portion P1 of a first thickness T1, and the second region A2 of the first compound semiconductor layer CS1 is formed of a second portion P2 of a second thickness T2 smaller than the first thickness T1.

The anti-etching layer 500A for performing the first mesa etching step (S30) is removed after performing the first mesa etching step. However, it is also possible to use it as a mask in the second mesa etching step without removing the anti-etching layer 500A after performing the first mesa etching step.

Subsequently, a protective layer PL is formed on the first surface of the first compound semiconductor layer CS1 (S40).

The forming of the protective layer PL may include forming a first protective layer PL1 based on indium phosphide (InP) on the first peripheral layer BL1, and forming a second protective layer PL2 made of copper (Cu) on the first protective layer PL1, and a metal capable of preventing the surface of the second protective layer PL2 from being oxidized, such as silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel After forming a third protective layer (PL3) formed of at least one selected from (Ni) and molybdenum (Mo) or an alloy thereof on the second protective layer (PL2), a fourth protective layer (PL4) formed of a lamination film may be attached on the third protective layer (PL3).

As such, if the first protective layer PL1 and the front contact layer FC are formed of different compound semiconductors, it is possible to effectively prevent a phenomenon in which the first compound semiconductor layer CS1 and the protective layer PL, in particular, the first compound semiconductor layer CS1 and the second protective layer PL2 are separated during a plurality of etching processes, particularly the ELO process, and a phenomenon in which a portion of the first compound semiconductor layer CS1 is etched during the process of removing the protective layer PL can be effectively prevented. can

The third protective layer PL3 may be formed between the first protective layer PL1 and the second protective layer PL2, and when there are at least two second protective layers PL2, the third protective layer PL3 may be formed between the two second protective layers PL2.

The lamination film forming the fourth protective layer PL4 may be formed of a PET film acting as a support substrate and an EVA film positioned on one side of the PET film and acting as an adhesive.

At this time, if the thickness of the PET film and the EVA film are respectively formed to be 25 μm to 75 μm, and the fourth protective layer (PL4) is attached at a temperature of 70 ° C to 150 ° C, the PET film is condensed and greatly deformed due to the temperature decrease of the fourth protective layer (PL4) during the ELO process.

For example, each of the PET film and the EVA film may have a thickness of 50 μm, and the fourth protective layer PL4 may be attached at a temperature of 100° C.

After forming the protective layer PL, the first compound semiconductor layer CS1 is separated from the mother substrate 300 by removing the sacrificial layer 400 by performing an epitaxial lift off (ELO) process (S50).

In the ELO process, hydrofluoric acid (HF) can be used as an etching solution. In the ELO process, since the sacrificial layer 400 is removed by the hydrofluoric acid (HF), the first compound semiconductor layer CS1 and the protective layer PL can be separated from the mother substrate 300, and the fourth protective layer PL4 is deformed due to condensation of the PET film, so that the separation process can be completed within a short time.

Then, the back electrode 200 is formed on the second surface of the first compound semiconductor layer CS1 opposite to the first surface (S60).

In the rear electrode forming step (S60), a sheet-shaped rear electrode 200 including a first electrode layer 200A directly contacting the rear surface contact layer BC of the second peripheral layer BL2 and a second electrode layer 200B located on the rear surface of the first electrode layer 200A is formed on the rear surface of the first compound semiconductor layer CS1.

In this case, the first electrode layer 200A may be formed by depositing silver (Ag) to a thickness of 50 to 500 nm using physical vapor deposition, and the second electrode layer 200B may be formed by plating copper (Cu) to a thickness of 1 to 10 μm using an electroplating method.

Also, the thickness of the second electrode layer 200B is preferably formed to be 70% or more of the total thickness of the back electrode 200 .

In FIG. 6 , non-explained reference numeral 600 denotes a support substrate attached to the rear surface of the rear electrode 200 .

Subsequently, the protective layer PL is removed (S70).

When the third passivation layer PL3 is removed, an etching solution in which a metal material forming the second passivation layer PL2 has corrosion resistance is used. According to this process, the second passivation layer PL2 is not removed while the third passivation layer PL3 is removed.

Also, the first protective layer PL1 may be removed with a first solution in which the front contact layer FC formed of GaAs has etch resistance.

After removing the protective layer PL, an anti-etching film 500B exposing the second area A2 of the first compound semiconductor layer CS1 is formed on the first area A1 of the first compound semiconductor layer CS1, and secondary mesa etching is performed using the anti-etching film 500B as a mask (S80).

As described above, the step of performing the first mesa etching and the step of performing the second mesa etching may be performed using different etch stop films.

In this case, after performing the first mesa etching as described above, the anti-etching layer 500A may be removed, and another anti-etching layer 500B for performing the second mesa etching may be formed in the second region.

Alternatively, the step of performing the first mesa etching and the step of performing the second mesa etching may be performed using the same etch stop layer.

In this case, the anti-etching layer 500A for performing the first mesa etching is not removed after completing the first mesa etching and may be removed after performing the second mesa etching.

The second mesa etching step (S80) includes a second mesa etching step of removing the first light absorbing layer PV1 located in the second region A2 and formed of GaInP using a first solution, and removing the second peripheral layer BL2 of the second region A2 using a third solution obtained by mixing the first solution and/or phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI). A third mesa etching step may be included.

In the third mesa etching step, the first back surface electric layer layer BSF1 located in the second region A2 and formed of AlGaInP is removed using the first solution, and the back contact layer BC formed of GaAs located in the second region A2 is removed using the third solution.

Typically, the lowermost layer of the second peripheral portion BL2 directly contacting the rear electrode 200 is a rear contact layer BC formed of GaAs or AlGaAs.

However, when the lowermost layer, for example, the back contact layer (BC) is removed using the second solution, the first electrode layer 200A is exposed to the second solution the moment the back contact layer (BC) is removed. Silver (Ag) forming the first electrode layer 200A is dissolved by the second solution.

Therefore, in the present invention, the lowermost layer (eg, the back contact layer) of the second peripheral layer BL2 is etched using a third mesa etching step using a third solution capable of removing the back contact layer BC formed of GaAs or AlGaAs and preventing the first electrode layer 200A formed of silver (Ag) from being dissolved.

As the third solution, a mixed solution of phosphoric acid (H ₃ PO ₄ ) / hydrogen peroxide (H ₂ O ₂ ) / deionized water (DI), in which silver (Ag) forming the first electrode layer 200A has corrosion resistance, may be used. The third solution may be formed by mixing phosphoric acid: hydrogen peroxide: deionized water in a ratio of 1:0.3 to 3:5 to 20.

As described above, the third mesa etching step using the third solution may be performed as the last step in the mesa etching process.

In this way, when the lowermost layer BC of the second peripheral layer BL2 is etched using the third mesa etching step using the third solution, the first electrode layer 200A is exposed to the third solution as soon as the lowermost layer BC is removed. However, since silver (Ag) forming the first electrode layer 200A has etching resistance to the third solution, the first electrode layer 60 is not dissolved by the third solution.

When the second peripheral layer BL2 does not include the first back surface electric layer BSF1, the second peripheral layer BL2 may be removed by a single etching process using the third solution.

When the secondary mesa etching step ( S80 ) is completed, cell-to-cell separation of the first compound semiconductor layer CS1 is completed, and a plurality of compound semiconductor solar cells can be manufactured from one mother substrate 300 .

After the secondary mesa etching step (S80) is completed, the back electrode portion located in the second region A2 is scribed (S90). Scribing may be performed using a cutting device such as a laser.

The front electrode 100 may be formed before or after the scribing step S90, and the front contact layer FC may be removed by an etching process using the front electrode 100 as a mask. Therefore, as shown in FIG. 9 , the front contact layer FC may be formed in the same pattern as the front electrode 100 .

In the compound semiconductor solar cell manufactured according to the method described above, while forming the back electrode 200 using silver (Ag) and copper (Cu), which are very inexpensive as raw materials compared to gold (Au), problems occurring during the manufacturing process of the compound semiconductor solar cell, such as the phenomenon that the indium phosphide (InP)-based layer in the first compound semiconductor layer CS1 is not etched and the phenomenon that a part of the back electrode 200 is dissolved, can be effectively suppressed.

Table 1 below measures the electrical characteristics of a conventional compound semiconductor solar cell having a back electrode formed of gold (Au) and the compound semiconductor solar cell of Examples 1 and 2 having a back electrode 200 including a first electrode layer 200A formed of silver (Ag) and a second electrode layer 200B formed of copper.

In Table 1 below, the compound semiconductor solar cell of Example 1 and the compound semiconductor solar cell of Example 2 are two solar cells selected from a plurality of solar cells manufactured by the manufacturing method of the present invention.

Open circuit voltage (Voc) Curve factor (FF) Efficiency (Eff) Conventional example 2.528 82.1 21.6 Example 1 2.521 81.9 21.7 Example 2 2.535 81.9 21.6

Referring to Table 1, it can be seen that the compound semiconductor solar cells of Examples 1 and 2 exhibit the same or similar electrical characteristics as those of the conventional compound semiconductor solar cell.

In the above description, the compound semiconductor solar cell having the first compound semiconductor layer CS1 having a single junction structure has been described as an example, but the compound semiconductor solar cell may also have a second compound semiconductor layer having a multi-junction structure.

That is, the manufacturing method of the present invention can be used even when manufacturing a compound semiconductor solar cell having a second compound semiconductor layer having a multi-junction structure.

Hereinafter, a compound semiconductor solar cell having a second compound semiconductor layer CS2 having a double junction structure will be described as an example, but it is obvious that the manufacturing method of the present invention can also be used when manufacturing a compound semiconductor solar cell having a compound semiconductor layer having a triple junction or higher structure.

1 and 11 to 13, the compound semiconductor solar cell having the double junction structure second compound semiconductor layer CS2 may include a first cell C1-1, a second cell C2 positioned on the rear surface of the first cell C1-1, and a first tunnel layer TRJ1 positioned between the first cell C1-1 and the second cell C2.

At this time, the first cell C1-1 has the same configuration as the first cell C1 shown in FIG. 9 except that the second peripheral layer BL2-1 does not include the back contact layer BC. Therefore, a detailed description of the first cell C1-1 will be omitted.

That is, in the compound semiconductor solar cell having the second compound semiconductor layer CS2 of the double junction structure, the front contact layer FC is positioned only on the top cell, and the rear contact layer BC is positioned only on the bottom cell.

In FIG. 13 , the top cell is the first cell C1-1, and the bottom cell is the second cell C2.

The second cell C2 of the compound semiconductor solar cell having the second compound semiconductor layer CS2 of the double junction structure has a second light absorbing layer PV2 based on GaAs, a third peripheral layer BL3 positioned on the first surface of the second light absorbing layer PV2 and based on indium phosphorus (InP) and/or gallium arsenide (GaAs), and a second light absorbing layer positioned on the second surface of the second light absorbing layer PV2, and indium phosphorus ( InP) and/or gallium arsenide (GaAs) based on at least one fourth peripheral layer (BL4) is further included.

In this configuration, the first tunnel layer TRJ1 positioned between the first cell C1-1 and the second cell C2 may be defined as a component of the second peripheral layer BL2 of the first cell C1-1, may be defined as a component of the third peripheral layer BL3 of the second cell C2, or may be defined as a layer separate from the second peripheral layer BL2 and the third peripheral layer BL3.

In the following description, the first tunnel layer TRJ is defined and described as a component of the third peripheral layer BL3.

The second cell C2 is formed of a GaAs-based compound semiconductor, for example, a second base layer PV2-1 formed of n-type GaAs and a second emitter layer PV2-2 formed of p-type GaAs and forming a pn junction with the second base layer PV2-1, located between the second light absorbing layer PV2, the first tunnel layer TRJ1 and the second base layer PV2-1, and formed of n-type GaInP A third peripheral layer BL3 including the second window layer WD2 and the first tunnel layer TRJ1, and a second back surface electric layer BSF2 positioned on the rear surface of the second emitter layer PV2-2 and formed of p-type GaAs, and a fourth peripheral layer BL4 including a back contact layer BC positioned between the second back surface electric field layer BSF2 and the rear electrode 200.

The second cell C2 is positioned on the rear side of the first cell C1-1 to absorb long-wavelength light that is not absorbed by the first cell C1-1 and passes through the first cell C1-1.

Accordingly, the second base layer PV2-1 and the second emitter layer PV2-2 are formed of a material having a band gap lower than that of GaInP (approximately 1.9Ev) forming the first base layer PV1-1 and the first emitter layer PV1-2 of the first cell C1-1, for example, GaAs having a band gap of approximately 1.42 eV.

Also, the second window layer WD2 and the second back surface electric layer BSF2 of the second cell C2 may be formed of a material having a higher bandgap than the second base layer PV2-1 and the second emitter layer PV2-2, for example, GaInP or AlGaInP.

At this time, the second window layer WD2 and the second back surface electric layer BSF2 of the second cell C2 may be formed of GaInP that does not contain aluminum, unlike the first window layer WD1 and the first back surface electric layer BSF1, because the band gap between the second base layer PV2-1 and the second emitter layer PV2-2 of the second cell C2 is 1-1) and the first emitter layer PV1-2.

The first tunnel layer TRJ1 includes a first layer TRJ1-1 formed of p+ type AlGaAs doped with p-type impurities at a higher concentration than the first back surface electric field layer BSF1 and in direct physical contact with the first back surface electric field layer BSF1, and a second layer TRJ1-2 formed of n+ type GaInP doped with n-type impurities at a higher concentration than the second window layer WD2 and in direct physical contact with the second window layer WD2. can include

Hereinafter, a method of manufacturing the compound semiconductor solar cell shown in FIG. 13 will be described.

In the manufacturing method of this embodiment, except for the compound semiconductor layer forming step (S20), the first mesa etching step (S30), and the second mesa etching step (S80), the rest of the components are the same as the manufacturing method of the compound semiconductor solar cell having the first compound semiconductor layer CS1 having a single junction structure, and thus a detailed description thereof will be omitted.

That is, in the manufacturing method of this embodiment, the sacrificial layer forming step (S10) is the same as the configuration shown in FIG. 2, the protective layer forming step (S40) is the same as the configuration shown in FIG. 4, and the separation step is the same as the configuration shown in FIG. 5.

The back electrode formation step is the same as the configuration shown in FIG. 6, and the scribing step is the same as the configuration shown in FIG.

And the protective layer removal step (S70) is also the same as the configuration of the above-described embodiment.

The manufacturing method according to the present embodiment is characterized in that, before forming the back electrode 200, a first mesa etching step is performed to mesa-etch the plurality of layers forming the first cell C1-1 among the plurality of layers forming the second compound semiconductor layer CS2, and after forming the back electrode 200, a second mesa etching step is performed to mesa-etch the plurality of layers forming the second cell C2 in the second compound semiconductor layer CS2.

That is, when manufacturing the compound semiconductor solar cell having the second compound semiconductor layer CS2 of the double junction structure, the first mesa etching step of mesa etching the compound semiconductor layer forming the first cell C1-1 includes the first mesa etching step of removing the first peripheral layer BL1 of the second region A2 using the first solution and/or the second solution, and the second mesa etching step of removing the first light absorbing layer PV1 of the second region A2 using the first solution. A mesa etching step and a third mesa etching step of removing the second peripheral layer BL2 of the second region A2 using the first solution and/or the second solution.

The secondary mesa etching step of mesa-etching the compound semiconductor layer forming the second cell C2 includes a fourth mesa etching step of removing the third peripheral layer BL3 of the second region A2 using the first solution and/or the second solution, a fifth mesa etching step of removing the second light absorbing layer PV2 of the second region A2 using the second solution, and a fourth mesa etching step of the second region A2 using the second solution and/or the third solution. A sixth mesa etching step of removing the peripheral layer BL4 may be included.

11 and 12 describe forming two compound semiconductor solar cells using one second compound semiconductor layer CS2 separated from the mother substrate 300 as an example, but the number of compound semiconductor solar cells can be appropriately selected as needed.

Specifically, after the sacrificial layer 400 is formed on the mother substrate 300 , the second compound semiconductor layer CS2 having a double junction structure is formed on the sacrificial layer 400 .

In the second compound semiconductor layer CS2 having a double junction structure, a fourth peripheral layer BL4 including a back surface contact layer BC and a second back surface electric field layer BSF2 is formed on the sacrificial layer 400, a second light absorbing layer PV2 including a second emitter layer PV2-2 and a second base layer PV2-1, and a third peripheral layer BL including a second window layer WD2 and a first tunnel layer TRJ1. 3), a second peripheral layer BL2 including a first back surface electric layer layer BSF1, a first light absorbing layer PV1 including a first emitter layer PV1-2 and a first base layer PV1-1, and a first peripheral layer BL1 including a first window layer WD1 and a front contact layer FC on the fourth peripheral layer BL4 in order.

In this case, in the case of a peripheral layer composed of a plurality of layers among the first peripheral layer BL1 to the fourth peripheral layer BL4 , at least one layer may be omitted.

After the double junction structure of the second compound semiconductor layer CS2 is formed, primary mesa etching is performed using the etch stop layer 500A exposing the second region A2 of the second compound semiconductor layer CS2.

In this embodiment, the reason why the first mesa etching is performed before forming the back electrode 200 is that when the etching process using the first solution is performed to remove the InP-based layer from the compound semiconductor layer (CS) forming the second cell (C2), silver (Ag) / copper (Cu), which is a material forming the back electrode 200, has higher oxidation tendency than InP-based layers (GaInP, AlInP, AlGaInP, etc.) This is to prevent poor etching of the layers due to this.

In this way, if the compound semiconductor layer forming the first cell C1-1 is subjected to primary mesa etching before forming the back electrode 200, a portion of the layer formed of GaInP, AlInP, or AlGaInP to be removed can be effectively removed from the compound semiconductor layer CS forming the second cell C2.

The first mesa etching step of mesa-etching the first cell C1-1 includes a first mesa etching step of removing a portion of the first peripheral layer BL1 positioned in the second region A2 using the first solution and/or a second solution, a second mesa etching step of removing a portion of the first light absorbing layer PV1 positioned in the second region A2 using the first solution, and a portion of the second peripheral layer BL2 positioned in the second region A2. and a third mesa etching step to remove using the first solution and/or the second solution.

Specifically, the front contact layer FC located in the second region A2 and formed of n+ type GaAs is removed using the second solution, and the first window layer WD1 formed of n-type AlGaInP is removed using the first solution (first mesa etching step for removing the first peripheral layer).

Subsequently, the first light absorbing layer PV1 formed of GaInP and the first back surface electric field layer BSF1 formed of p-type AlGaInP are sequentially removed using the first solution (a second mesa etching step to remove the first light absorbing layer and a third mesa etching step to remove the second peripheral layer).

When the first mesa etching step (S30) is performed, the compound semiconductor layer located in the second region A2 of the second compound semiconductor layer CS2 and forming the first cell C1-1 is removed, so that the first region A1 is formed of the first portion P1 of the first thickness T1, and the second region A2 of the second compound semiconductor layer CS2 is a third portion of the third thickness T3 smaller than the first thickness T1. (P3).

The anti-etching film 500A for performing the first mesa etching step (S30) may be removed after performing the first mesa etching step (S30), but may be used as a mask in the second mesa etching step (S80) without removing the anti-etching film 500A after performing the first mesa etching step (S30).

Subsequently, the passivation layer PL is formed on the first surface of the second compound semiconductor layer CS2 (S40), and the sacrificial layer 400 is removed by performing an epitaxial lift off (ELO) process to separate the second compound semiconductor layer CS2 from the mother substrate 300 (S50).

Subsequently, the back electrode 200 is formed on the second surface of the second compound semiconductor layer CS2 opposite to the first surface (S60), the protective layer PL is removed (S70), and secondary mesa etching is performed (S80).

The secondary mesa etching step S80 of mesa etching the compound semiconductor layer forming the second cell C2 includes a fourth mesa etching step of removing a portion of the third peripheral layer BL3 located in the second region A2 using the first solution and/or a second solution, a fifth mesa etching step of removing a portion of the second light absorbing layer PV2 located in the second region A2 using the second solution, and a fourth mesa etching step located in the second region A2. A sixth mesa etching step of removing a portion of the peripheral layer BL4 using the second solution and/or the third solution may be included.

Specifically, the portion of the first layer TRJ1-1 of the first tunnel layer TRJ1 positioned in the second area A2 is removed using the second solution, and the portion of the second layer TRJ1-2 and the portion of the second window layer WD2 of the first tunnel layer TRJ1 positioned in the second area A2 are removed using the first solution to remove the third peripheral layer BL3 (the fourth mesa for removing the third peripheral layer). etching step).

Subsequently, a portion of the second light absorbing layer PV2 located in the second region A2 is removed using a second solution (a fifth mesa etching step for removing the second light absorbing layer).

Subsequently, the second back surface electric layer layer (BSF2) is removed using the second solution, and the back surface contact layer (BC) is removed using the third solution (a sixth mesa etching step to remove the fourth peripheral layer).

When the secondary mesa etching step ( S80 ) is completed, cell separation of the second compound semiconductor layer CS2 is completed.

Then, the back electrode 200 located in the second region A2 is scribed (S90), the front electrode 100 is formed before or after the scribing step S90 is performed, and the front contact layer FC is patterned by an etching process using the front electrode 100 as a mask.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also within the scope of the present invention.

C1: first cell C2: second cell
FC: front contact layer BC: back contact layer

Claims (10)

forming a sacrificial layer on the mother substrate;
forming a compound semiconductor layer on the sacrificial layer;
performing primary mesa etching to form a first region of the compound semiconductor layer as a first portion having a first thickness and forming a second region of the compound semiconductor layer as a second portion having a second thickness smaller than the first thickness;
forming a protective layer on the first surface of the compound semiconductor layer;
separating the compound semiconductor layer from the mother substrate by removing the sacrificial layer;
forming a rear electrode on a second surface of the compound semiconductor layer opposite to the first surface;
removing the protective layer;
removing the second portion of the compound semiconductor layer in the second region by performing secondary mesa etching; and
scribing the back electrode of the second region;
including,
The compound semiconductor layer,
a first light absorbing layer based on indium phosphorus (InP);
at least one first peripheral layer located on the first surface of the first light absorption layer and based on indium phosphide (InP) and/or gallium arsenide (GaAs); and
Located on the second surface of the first light absorption layer, at least one second peripheral layer based on indium phosphide (InP) and/or gallium arsenide (GaAs)
including,
The step of performing the first mesa etching,
A first mesa etching step of removing the first peripheral layer of the second region using a first solution containing hydrochloric acid (HCl) and/or a second solution containing a mixture of ammonium hydroxide (NH ₄ OH)/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI);
In the step of performing the secondary mesa etching,
a second mesa etching step of removing the first light absorbing layer in the second region using the second solution; and
and a third mesa etching step of removing the second peripheral layer of the second region using a third solution obtained by mixing the first solution and/or phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI). In paragraph 1,
Forming the rear electrode,
forming a first electrode layer directly contacting the second surface of the compound semiconductor layer with silver (Ag); and
Forming a second electrode layer of copper (Cu) on the rear surface of the first electrode layer
Method for manufacturing a compound semiconductor solar cell comprising a. delete delete In paragraph 1,
The compound semiconductor layer,
a second light absorbing layer based on gallium arsenide (GaAs);
at least one third peripheral layer located on the first surface of the second light absorption layer and based on indium phosphide (InP) and/or gallium arsenide (GaAs); and
Located on the second surface of the second light absorbing layer, at least one fourth peripheral layer based on indium phosphide (InP) and/or gallium arsenide (GaAs)
Including more,
The second light absorbing layer is a method of manufacturing a compound semiconductor solar cell positioned between the first light absorbing layer and the rear electrode. In paragraph 5,
The step of performing the first mesa etching,
A first mesa etching step of removing the first peripheral layer of the second region using a first solution containing hydrochloric acid (HCl) and/or a second solution in which ammonium hydroxide (NH ₄ OH)/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) is mixed;
a second mesa etching step of removing the first light absorbing layer of the second region using the first solution; and
A third mesa etching step of removing the second peripheral layer of the second region using the first solution and/or the second solution.
including,
In the step of performing the secondary mesa etching,
a fourth mesa etching step of removing the third peripheral layer of the second region using the first solution and/or the second solution;
a fifth mesa etching step of removing the second light absorbing layer of the second region using the second solution; and
A sixth mesa etching step of removing the fourth peripheral layer of the second region by using the second solution and/or a third solution in which phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) is mixed.
Method for manufacturing a compound semiconductor solar cell comprising a. In paragraph 6,
Among the second peripheral layer or the fourth peripheral layer, the lowermost layer directly contacting the back electrode is formed based on gallium arsenide (GaAs), and the lowermost layer is removed using the third solution. Manufacturing method of a compound semiconductor solar cell. In paragraph 7,
The third solution is formed by mixing phosphoric acid (H ₃ PO ₄ )/hydrogen peroxide (H ₂ O ₂ )/deionized water (DI) at a ratio of 1:0.3 to 3:5 to 20. Method for manufacturing a compound semiconductor solar cell. In paragraph 8,
Forming the protective layer,
forming a first passivation layer based on indium phosphorus (InP) on the first peripheral layer;
forming a second passivation layer made of copper (Cu) on the first passivation layer;
Forming a third protective layer formed of at least one selected from among silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), and molybdenum (Mo) or an alloy thereof on the second protective layer; and
Attaching a protective film on the third protective layer
Method for manufacturing a compound semiconductor solar cell comprising a. In paragraph 8,
The method of manufacturing a compound semiconductor solar cell in which the performing of the first mesa etching and the performing of the second mesa etching are performed using different anti-etching films.