KR102552752B1 - Successive-Approximation-Register Analog-to-Digital-Converter Using Redundant Capacitor And Operating Method thereof - Google Patents

Abstract

A successive approximation register analog-to-digital converter using redundant capacitors and an operating method thereof are disclosed.
According to one aspect of the present disclosure, a successive approximation register analog-to-digital converter for converting an analog signal into a digital code, comprising: a comparator including a first input end, a second input end, and an output end; a first CDAC connected to the first input of the comparator and including binary-weighted capacitors; A second CDAC connected to the second input terminal of the comparator, having the same total capacitance as that of the first CDAC, and including a plurality of capacitors corresponding to the least significant bits of the digital code. ; and a SAR controller configured to determine the digital code by switching reference voltages applied to capacitors included in the first CDAC and the second CDAC.

Description

Successive Approximation Register Analog-to-Digital Converter Using Redundant Capacitor and Operation Method thereof

The present disclosure relates to a successive approximation register analog-to-digital converter using redundant capacitors and an operating method thereof.

The information described in this section simply provides background information on the present invention and does not constitute prior art.

An analog to digital converter (ADC) refers to a circuit that converts an analog input signal into a digital output signal.

Successive-Approximation-Register ADC (SAR ADC) is an ADC in the form of sequentially changing the reference voltage to be compared with the analog input while finding a digital output value that is as close as possible to the analog input. Also called type ADC.

The SAR ADC is equipped with a digital-to-analog converter (Capacitor Digital-to-Analog-Converter) to sequentially change the reference voltage to be compared with the analog input. Based on the charge redistribution principle, the comparison corresponding to the analog input and reference voltage A capacitor DAC that forms a voltage is mainly used.

In order to increase the resolution of the SAR ADC by 1 bit, generally, the capacitance of the capacitor DAC needs to be doubled. As the capacitance increases, the settling time required to stabilize the comparison voltage also increases. If this settling time is not sufficiently guaranteed, since the digital output value is determined in a state where the comparison voltage is not stabilized, measurement errors often occur, making it difficult to implement a high-speed and high-resolution SAR ADC.

The main purpose of the present disclosure is to provide a SAR ADC capable of realizing high speed and high resolution and its operation method by increasing voltage coverage and correcting measurement errors by repeatedly switching capacitors having the same size in different capacitor DACs. There is a purpose.

According to one aspect of the present disclosure, a successive approximation register analog-to-digital converter for converting an analog signal into a digital code, comprising: a comparator including a first input end, a second input end, and an output end; a first CDAC connected to the first input of the comparator and including binary-weighted capacitors; A second CDAC connected to the second input terminal of the comparator, having the same total capacitance as that of the first CDAC, and including a plurality of capacitors corresponding to the least significant bits of the digital code. ; and a SAR controller configured to determine the digital code by switching reference voltages applied to capacitors included in the first CDAC and the second CDAC.

According to another aspect of the present disclosure, a first CDAC including capacitors weighted in binary and having the same total capacitance as the first CDAC, but corresponding to at least one lower bit for each lower bit of a digital code A method of operating a successive approximation register analog-to-digital converter including a second CDAC having a plurality of capacitors, comprising: determining at least one upper bit of the digital code using the first CDAC; determining at least one lower bit of the digital code using the second CDAC; and determining the digital code, the measurement error of which is corrected, from the at least one upper bit and the at least one lower bit.

As described above, according to the embodiment of the present disclosure, it is possible to realize high speed and high resolution by repeatedly switching capacitors having the same size in different capacitor arrays, increasing the voltage application range and correcting measurement errors.

1 is a configuration diagram showing a SAR ADC according to an embodiment of the present disclosure.
2 is a flowchart for explaining the operation of a SAR ADC according to an embodiment of the present disclosure.
3A and 3B are signal flow diagrams illustrating the operation of a 6-bit SAR ADC according to an embodiment of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail through exemplary drawings. In adding reference numerals to components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description will be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present disclosure. These terms are only used to distinguish the component from other components, and the nature, order, or order of the corresponding component is not limited by the term. Throughout the specification, when a part 'includes' or 'includes' a certain component, it means that it may further include other components without excluding other components unless otherwise stated. . In addition, the '... Terms such as 'unit' and 'module' refer to a unit that processes at least one function or operation, and may be implemented as hardware, software, or a combination of hardware and software.

1 is a configuration diagram showing a SAR ADC according to an embodiment of the present disclosure.

Referring to FIG. 1, a SAR ADC (Successive-Approximation-Register Analog-to-Digital-Converter, 10) according to an embodiment of the present disclosure includes a S/H switch unit (Sample-and-hold switch unit, 100, 102 and 104), a first CDAC (Capacitor Digital-to-Analog-Converter, 110), a second CDAC (120), a comparator (130), and a SAR control unit (SAR control unit, 140) in whole or in part. All components shown in FIG. 1 are not essential components, and some components included in the SAR ADC 10 may be added, changed, or deleted in other embodiments.

The S/H switch units 100, 102, and 104 respectively convert the input signal V _IN and the common mode voltage V _CM to the first CDAC 110 and the second CDAC in response to the control of the SAR controller 140. is sampled and held. Here, the common mode voltage (V _CM ) has an intermediate value between the first reference voltage (V _REF ) and the second reference voltage (GND) to which the switching elements of the first CDAC 110 and the second CDAC 120 are connected. can

As shown in FIG. 1, when the S/H switch units 100, 102, and 104 are turned on, the top plates of the capacitors constituting the first CDAC 110 and the second CDAC 120 A common mode voltage (V _CM ) is applied to, an input signal (V _IN ) is applied to a bottom plate of capacitors constituting the first CDAC (110), and a capacitor constituting the second CDAC (120) A bottom plate sampling technique in which a first reference voltage V _REF or a second reference voltage GND is applied to a lower plate of each may be applied. However, the present disclosure is not limited to these examples, and a top plate sampling technique may be applied in other embodiments of the present disclosure.

The first CDAC 110 includes a plurality of capacitors having a binary weighted array structure. The total number of capacitors included in the first CDAC 110 may be determined according to a resolution and a switching technique.

A plurality of capacitors included in the first CDAC 110 have one end connected in common and connected to one end (eg, a non-inverting terminal) of the comparator 130 .

A plurality of capacitors included in the first CDAC 110 may constitute a coarse capacitor array 112 and a first residual capacitor array 114 .

Capacitors included in the coarse capacitor array 112 correspond to upper K (K is a natural number less than or equal to N)-bits of the N-bit digital output of the SAR ADC 10, respectively. The coarse capacitor array 112 may include K capacitors having a binary weighted array structure. Meanwhile, the first residual capacitor array 114 may mean a set of remaining capacitors not included in the coarse capacitor array 112 among a plurality of capacitors included in the first CDAC 110 .

For example, when the resolution of the SAR ADC 10 is 6-bit and the coarse capacitor array 112 corresponds to the upper 3-bits, the coarse capacitor array 112 and the first residual capacitor array 114 are as shown in Table 1. can be configured together.

division coarse capacitor array First Residual Capacitor Array weight 2 ⁵ =32 2 ⁴ =16 2 ³ =8 2 ² =4 2 ¹ =2 2 ⁰ =1 2 ⁰ =1 beat B5 B4 B3 - - - -

The second CDAC 120 includes a plurality of capacitors. A total capacitance of capacitors included in the second CDAC 120 is equal to a total capacitance of capacitors included in the first CDAC 110 .

A plurality of capacitors included in the second CDAC 120 have one end connected in common and connected to the other end (eg, an inverting terminal) of the comparator 130 .

A plurality of capacitors included in the second CDAC 120 may constitute a second residual capacitor array 122 , a positive fine capacitor array 124 , and a negative fine capacitor array 126 .

Of the capacitors included in the positive fine capacitor array 124 and the negative fine capacitor array 126, except for the dummy capacitor, the remaining capacitors are the lower (N-K+) of the N-bit digital output of the SAR ADC 10. 1) - may correspond to each bit. Accordingly, the second CDAC 120 may include a plurality of capacitors corresponding to at least one lower bit of the N-bit digital output. For example, as shown in FIG. 1 , the second CDAC 120 may include two capacitors corresponding to each bit for the lower (N-K+1)-bits of the N-bit digital output.

The positive fine capacitor array 124 and the negative fine capacitor array 126 may each include (N−K+1) capacitors and one unit capacitor having a binary weighted array structure. Meanwhile, the second residual capacitor array 122 refers to a set of remaining capacitors not included in the positive fine capacitor array 124 and the negative fine capacitor array 126 among the plurality of capacitors included in the second CDAC 120. can do.

For example, when the resolution of the SAR ADC 10 is 6-bit and the positive fine capacitor array 124 and the negative fine capacitor array 126 each correspond to the lower 4-bits, the second residual capacitor array 122; The positive fine capacitor array 124 and the negative fine capacitor array 126 may be configured as shown in Table 2.

division leftover positive fine capacitor array negative fine capacitor array weight 2 ⁵ =32 2 ³ =8 2 ² =4 2 ¹ =2 2 ⁰ =1 2 ⁰ =1 2 ³ =8 2 ² =4 2 ¹ =2 2 ⁰ =1 2 ⁰ =1 beat - B _p3 B _p2 B _p1 B _p0 - B _n3 B _n2 B _n1 B _n0 -

As shown in FIG. 1 , at least one upper bit corresponding to the coarse capacitor array 112 includes at least one lower bit corresponding to the positive fine capacitor array 124 and the negative fine capacitor array 126 and one or more upper bits. Bits may overlap. In other words, the coarse capacitor array 112, the positive fine capacitor array 124, and the negative fine capacitor array 126 may include capacitors having the same weight.

In the present disclosure, a capacitor included redundantly in the coarse capacitor array 112 , the positive fine capacitor array 124 , and the negative fine capacitor array 126 is referred to as a redundant capacitor.

The redundant capacitor of the coarse capacitor array 112 may correspond to the least significant bit of the higher K-bits. That is, the redundant capacitor of the coarse capacitor array 112 may be a capacitor having the smallest weight among the capacitors included in the coarse capacitor array 112 .

Redundant capacitors of the positive fine capacitor array 124 and the negative fine capacitor array 126 may correspond to the most significant bit among the lower (N−K+1)-bits. That is, the redundant capacitor of the positive fine capacitor array 124 and the negative fine capacitor array 126 may be a capacitor having the largest weight among the capacitors included in the positive fine capacitor array 124 and the negative fine capacitor array 126. there is.

On the other hand, in FIG. 1, only capacitors corresponding to the K-th bit based on the MSB (Most Significant Bit), that is, capacitors having a weight of (2 ^NK ) are the coarse capacitor array 112, the positive fine capacitor array 124, and the negative fine Although shown as being redundantly included in the capacitor array 126, the coarse capacitor array 112, the positive fine capacitor array 124, and the negative fine capacitor array 126 may include a plurality of binary-weighted capacitors redundantly. may be

The first CDAC 110 applies a first reference voltage V _REF or a second reference voltage GND to lower plates of the capacitors included in the coarse capacitor array 112, respectively, in response to the control of the SAR controller 140. It includes a plurality of switching elements (S _N-1 to S _NK ) for applying.

The second CDAC 120 applies a first reference voltage V _REF or a second reference voltage GND to the lower plates of the capacitors included in the positive fine capacitor array 124, respectively, in response to the control of the SAR controller 140. It includes a plurality of switching elements (S _{P (NK)} to S _P0 ) for applying.

In response to the control of the SAR controller 140, the second CDAC 120 applies a first reference voltage V _REF or a second reference voltage GND to lower plates of capacitors included in the negative fine capacitor array 126, respectively. It includes a plurality of switching elements (S _{N (NK)} to S _N0 ) for applying.

Meanwhile, lower plates of the capacitors included in the first residual capacitor array 114 may be connected in common to the S/H switch unit 104 . Accordingly, during the SAR operation, the second reference voltage GND may be applied to the lower plates of the capacitors included in the first residual capacitor array 114 .

Lower plates of the capacitors included in the second residual capacitor array 122 may be connected in common to the second reference voltage GND.

The comparator 130 has a first input terminal (+), a second input terminal (-), and an output terminal, and the first input terminal and the second input terminal are connected to upper ends of the first CDAC 110 and the second CDAC 120, respectively. . The comparator 130 compares the voltage of the first input terminal and the voltage of the second input terminal, that is, the upper voltage (V ₊ ) of the first CDAC 110 and the upper voltage (V _- ) of the second CDAC 120. is output to the SAR controller 140.

The SAR control unit 140 switches the reference voltage applied to the capacitors included in the first CDAC 110 and/or the second CDAC 120, and uses the output of the comparator 130 accordingly to obtain an N-bit digital signal. Determine the code <D _N :D ₁ >.

The SAR control unit 140 switches the reference voltage applied to capacitors included in the coarse capacitor array 112 to sequentially determine outputs of upper K-bits <B _N-1 : B _NK >.

For example, the SAR control unit 140 selects the k-th (k is an integer equal to or greater than N-1 or less NK) bit (B The first reference voltage (V _REF ) is applied to the lower plate of the capacitor corresponding to the k-th bit (B _k ) by controlling the switching element (S _k ) connected to the capacitor corresponding to _k ). Accordingly, the top voltage (V ₊ ) of the first CDAC 110 is changed, and the SAR controller 140 determines the k-th bit (B _k ) using the output of the comparator 130 . Based on the value of the determined k-th bit (B _k ), the SAR controller 140 maintains the capacitor corresponding to the corresponding bit connected to the first reference voltage (V _REF ), or the second reference voltage (GND). Control the switching element (S _k ) to be connected to.

The SAR control unit 140 determines the (NK) th bit (B _NK ), and applies the first reference voltage (V _REF ) or the second reference voltage (GND) to the capacitor corresponding to the corresponding bit. Comparator 130 Based on the output of ), a capacitor array to control the switching elements connected to the lower plate among the positive fine capacitor array 124 and the negative fine capacitor array 126 is determined.

The SAR control unit 140 switches the reference voltage applied to the capacitors included in the positive fine capacitor array 124 or the negative fine capacitor array 126 to lower (N-K+1)-bit <B _{p(NK )} :B _p0 > or <B _n(NK) :B _n0 > are sequentially determined.

For example, when using the positive fine capacitor array 124, the SAR control unit 140 determines the jth (j is an integer less than or equal to NK) bit (j is an integer less than or equal to NK) based on the LSB among the capacitors included in the positive fine capacitor array 124. The first reference voltage (V _REF ) is applied to the lower plate of the capacitor corresponding to the j-th bit (B _pj ) by controlling the switching element (S _pj ) connected to the capacitor corresponding to B _pj ). Accordingly, the upper voltage (V _- ) of the second CDAC 120 is changed, and the SAR controller 140 determines the j-th bit (B _pj ) using the output of the comparator 130 . Based on the value of the determined j-th bit (B _pj ), the SAR control unit 140 maintains the capacitor corresponding to the bit in a state connected to the first reference voltage (V _REF ), or the second reference voltage (GND). Control the switching element (S _pj ) to be connected to.

Similarly, when using the negative fine capacitor array 126, the SAR control unit 140 is a switching connected to a capacitor corresponding to the j th bit (B _nj ) based on the LSB among the capacitors included in the negative fine capacitor array 126 The second reference voltage is applied to the lower plate of the capacitor corresponding to the j-th bit (B _nj ) by controlling the device (S _nj ). Accordingly, the upper voltage (V _- ) of the second CDAC 120 is changed, and the SAR controller 140 determines the j-th bit (B _pj ) using the output of the comparator 130 . Based on the value of the determined j-th bit (B _pj ), the SAR controller 140 maintains the capacitor corresponding to the bit in a state connected to the second reference voltage (GND), or the first reference voltage (V _REF ). Controls the switching element (S _nj ) to be connected to.

The SAR control unit 140 outputs the upper K-bit <B _{N- 1} :B _{N -K} > and the lower (N-K+1)-bit output <B _p(NK) :B _p0 > or <B _n Based on _(NK) :B _n0 >, an error-corrected N-bit digital code <D _{N - 1} :D ₀ > is output. The SAR control unit 140 outputs the lower (N-K+1)-bits from the upper K-bit output <B _{N- 1} :B _{N -K} ><B _p(NK) :B _p0 > or <B _{( NK)} :B _n0 > can be added or subtracted to obtain the digital code <D _{N - 1} :D ₀ >.

When the SAR controller 140 according to an embodiment of the present disclosure determines the lower (N-K+1)-bit output <B _p(NK) :B _p0 > using the positive fine capacitor array 124, Output of the upper K-bits <B _{N- 1} :B _{N -K} > to the output of the lower (N-K+1)-bits <B _p(NK) :B _p0 > or <B _(N-K+1) :B _n1 > can be subtracted. On the other hand, when the lower (N-K+1)-bit output <B _(NK) :B _n0 > is determined using the negative fine capacitor array 126, the upper K-bit output <B _{N- 1} :B From _{N -K} >, the lower (N-K+1)-bit output <B _(NK) :B _n0 > can be added.

For example, when the resolution of the SAR ADC 10 is 6-bit and the coarse capacitor array corresponds to the upper 3-bits, the digital code <D _{N - 1} :D ₀ > is equivalent to Equation 1 or 2 can be saved together.

Hereinafter, the operation of the SAR ADC according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 2 to 3B.

2 is a flowchart for explaining the operation of a SAR ADC according to an embodiment of the present disclosure.

3A and 3B are signal flow diagrams illustrating the operation of a 6-bit SAR ADC according to an embodiment of the present disclosure.

3A shows a process of _correcting a positive error generated by determining the most significant bit (B ₅ ) before the upper voltage (V ₊ ) of the upper first CDAC is sufficiently charged. FIG. ) shows the process of correcting the negative error caused by determining the next-order bit (B ₄ ) before it is sufficiently discharged.

First, the S/H switch units 100, 102, and 104 are turned on/off in response to the control of the SAR controller 140 to transmit the input signal V _IN to the first CDAC 110. Sampling (S200).

For example, when the sample and hold signal SH becomes 'high', the S/H switch unit 100 is turned on, and the coarse capacitor array 112, the first residual capacitor array 114, and the second residual capacitor are turned on. A common mode voltage V _CM may be applied to upper plates of the array 122 , the positive fine capacitor array 124 , and the negative fine capacitor array 126 . Also, when the S/H switch units 102 and 104 are turned on, respectively, the input signal V _IN may be applied to the lower plates of the coarse capacitor array 112 and the first residual capacitor array 114 . At this time, the second reference voltage (GND) is applied to the lower plate of the second residual capacitor array 122 and the positive fine capacitor array 124, and the first reference voltage (V) is applied to the lower plate of the negative fine capacitor array 126. _REF ) can be applied. As such, while sampling is performed, different reference voltages are applied to the lower plates of the positive fine capacitor array 124 and the negative fine capacitor array 126 so that the positive fine capacitor array 124 Alternatively, the error may be corrected using the negative fine capacitor array 126 .

When the sample and hold signal (SH) becomes 'low', the S/H switch units 100, 102, and 104 are turned off, and the coarse capacitor array 112 and the lower plate of the first residual capacitor array 114 are A second reference voltage (GND) is applied. Accordingly, the top voltage (V ₊ ) of the first CDAC 110 is reduced by the magnitude of the input signal (V _IN ) sampled from the common mode voltage (V _CM ) (① in FIGS. 3A and 3B).

The SAR control unit 140 switches the reference voltage applied to the coarse capacitor array 112 according to a successive approximation technique to generate the upper K-bits <B _N-1 : B _NK > of the N-bit digital code. Determine (S210).

For example, the SAR controller 140 controls the switching element S N-1 connected to a capacitor corresponding to MSB(B _N-1 ) among the capacitors included in the coarse capacitor array 112 to control the MSB (B _N-1 ). A first reference voltage (V _REF ) is applied to the lower plate of the capacitor corresponding to _N-1 ). Accordingly, the top voltage (V ₊ ) of the first CDAC 110 is increased by 1/2*V _REF (② in FIGS. 3A and 3B).

The SAR controller 140 compares the upper voltage (V ₊ ) of the first CDAC 110 and the upper voltage (V _- ) of the second CDAC 120 to determine the MSB (B _N-1 ).

The SAR control unit 140 generates MSB(B _N-1 ) when the upper voltage (V ₊ ) of the first CDAC 110 is greater than the upper voltage (V _- ) of the second CDAC 120, that is, the common mode voltage (V _CM ). ) is determined to be '0', and if it is small, MSB (B _N-1 ) is determined to be '1'.

Based on the determined MSB (B _N-1 ), the SAR controller 140 applies a first reference voltage (V _REF ) to a capacitor corresponding to MSB (B _N-1 ) among capacitors included in the coarse capacitor array 112 . Alternatively, by controlling the switching element (S _N-1 ) so that the second reference voltage (GND) is applied, and by controlling the switching element (S N- ₂ ) connected to the capacitor corresponding to the next bit (B _N-2 ), the corresponding A first reference voltage V _REF is applied to the lower plate of the capacitor corresponding to the bit B _N-2 . For example, when MSB(B _N−1 ) is determined to be 1, the SAR controller 140 applies the first reference voltage V _REF to the capacitor corresponding to MSB(B _N−1 ) to the switching element S _N-1 ) is maintained, and the switching element S N- ₂ is controlled so that the first reference voltage V _REF is applied to the capacitor corresponding to the next bit (B _N-2 ). Accordingly, the top voltage (V ₊ ) of the first CDAC 110 is increased by 1/4*V _REF (③ in FIG. 3A). Conversely, when MSB(B _N ) is determined to be 0, the SAR controller 140 operates the switching element S _N-1 so that the second reference voltage GND is applied to the capacitor corresponding to MSB(B _N-1 ). and controls the switching element S _N-2 so that the first reference voltage V _REF is applied to the capacitor corresponding to the next bit B N- ₂ . Accordingly, the top voltage (V ₊ ) of the first CDAC 110 is reduced by 1/4*V _REF (③ in FIG. 3B).

In the same way, the SAR controller 140 sequentially determines the upper K-bits <B _{N- 1} :B _{N -K} >. When the (N−K+1) th bit (B _NK ) is determined, the first reference voltage (V _REF ) is applied to the capacitor corresponding to the (NK) th bit (B _NK ) among the capacitors included in the coarse capacitor array 112. ) or the second reference voltage (GND) is applied to control the switching element (S _N-1 ). For example, when the (N−K+1) th bit (B _NK ) is determined to be 0, the SAR controller 140 applies the second reference voltage (GND) to the capacitor corresponding to the (NK) th bit (B _NK ). The switching element (S _NK ) is controlled so that is applied. Accordingly, the top voltage (V ₊ ) of the first CDAC 110 decreases by a certain amount and then remains constant (④ in FIG. 3A). Conversely, when the (NK)-th bit (B _NK ) is determined to be 1, the SAR controller 140 selects a capacitor corresponding to the (NK)-th bit (B _NK ) among capacitors included in the coarse capacitor array 112. 1 The switching state of the switching element (S _N-K1 ) is maintained so that the reference voltage (V _REF ) is applied. Accordingly, the top voltage (V ₊ ) of the first CDAC 110 is maintained constant (④ in FIG. 3B).

Thereafter, the SAR controller 140 determines the lower (N-K+1)-bit <B _p(NK) of the positive fine capacitor array 124 and the negative fine capacitor array 126 based on the output of the comparator 130. A capacitor array to be used to determine :B _p0 > or <B _n(NK) :B _n0 > is selected (S220).

After determining the upper K-bit <B _{N- 1} :B _{N -K} >, the upper level voltage (V ₊ ) of the first CDAC 110, which is constantly fixed, is the upper level voltage (V _- ) of the second CDAC 120 , That is, when higher than the common mode voltage (V _CM ), the SAR control unit 140 converts the reference voltage applied to the positive fine capacitor array 124 to a lower (N-K+1)-bit <B _{p(NK )} :B _p0 > is determined (S230 to S235).

For example, the SAR control unit 140 includes a switching element (S _Pj ) connected to a capacitor corresponding to a jth (j is an integer less than or equal to NK) bit (B _pj ) among the capacitors included in the positive fine capacitor array 124 By controlling, a first reference voltage (V _REF ) is applied to the lower plate of the capacitor corresponding to the j-th bit (B _pj ) (S230).

The SAR control unit 140 determines the j-th bit (B _pj ) using the output of the comparator 130 (S231). For example, the SAR control unit 140 sets the j-th bit (B _pj ) to '1' when the upper voltage (V ₊ ) of the first CDAC 110 is greater than the upper voltage (V _- ) of the second CDAC 120. It is determined as (S232), and if it is small, the j-th bit (B _pj ) is determined to be '0' (S233).

Based on the value of the determined j-th bit (B _pj ), the SAR control unit 140 maintains the capacitor corresponding to the bit in a state connected to the first reference voltage (V _REF ), or the second reference voltage (GND). The switching element (S _pj ) is controlled to be connected to (S232 and S233). For example, if the j-th bit (B _pj ) is '1', the switching state of the switching element (S _pj ) is maintained so that the first reference voltage (V _REF ) is applied to the capacitor corresponding to the corresponding bit (S232), If the j-th bit (B _pj ) is '0', the switching element (S _pj ) is controlled so that the second reference voltage (GND) is applied to the capacitor corresponding to the corresponding bit (S233).

Conversely, when the top voltage (V ₊ ) of the first CDAC 110 is lower than the top voltage (V _- ) of the second CDAC 120, that is, the common mode voltage (V _CM ), the SAR control unit 140 generates a negative fine The lower (N-K+1)-bit <B _n(NK) :B _n0 > is determined using the capacitor array 126 (S240 to S245).

The SAR controller 140 controls the switching element (S _nj ) connected to the capacitor corresponding to the j-th bit (B _nj ) based on the LSB among the capacitors included in the negative fine capacitor array 126 to obtain the j-th bit ( A second reference voltage (GND) is applied to the lower plate of the capacitor corresponding to B _nj ( S240 ).

Accordingly, the top voltage (V _- ) of the second CDAC 120 is changed, and the SAR control unit 140 determines the j-th bit (B _nj ) using the output of the comparator 130 (S241). For example, the SAR controller 140 sets the j-th bit (B _nj ) to '0' when the upper voltage (V ₊ ) of the first CDAC 110 is greater than the upper voltage (V _- ) of the second CDAC 120. (S242), and if it is small, the j-th bit (B _nj ) is determined to be '1' (S243).

Based on the value of the determined j-th bit (B _nj ), the SAR controller 140 maintains the capacitor corresponding to the bit in a state connected to the second reference voltage (GND), or the first reference voltage (V _REF ). The switching element (S _nj ) is controlled to be connected to (S242 and S243). For example, if the j-th bit (B _nj ) is '0', the switching element (S nj ) is controlled so that the first reference voltage (V _REF ) is applied to the capacitor corresponding to the corresponding bit ( _S242 ), and the j-th bit If (B _nj ) is '1', the switching state of the switching element S _nj is maintained so that the second reference voltage GND is applied to the capacitor corresponding to the corresponding bit (S243).

When both the lower (N-K+1)-bits <B _p(NK) :B _p0 > or <B _n(NK) :B _n0 > are determined (S234 and S234), the SAR controller 140 moves the upper K- Corrected measurement errors from bits <B _{N- 1} :B _{N -K} > and lower (N-K+1)-bits <B _p(NK) :B _p0 > or <B _n(NK) :B _n0 > The digital code <D _{N - 1} :D ₀ > is calculated (S250). The SAR control unit 140 selects the upper K-bits <B _{N- 1} :B _{N -K} > to the lower (N-K+1)-bits <B _p(NK) :B _p0 > or <B _n(NK) : Add or subtract B _n0 > to get the final digital code <D _N-1 :D ₀ >.

As described above, according to an embodiment of the present disclosure, when determining the upper K-bit, the coarse capacitor array 112 is switched to approximate the upper voltage (V ₊ ) of the first CDAC 110 to the common mode voltage, and the lower ( When N-K+1) bit is determined, the first CDAC 110 fixes the upper voltage (V _- ) of the second CDAC 120 to a constant voltage by switching the positive capacitor array 122 or the negative capacitor array 126 It can be approximated to the top voltage (V ₊ ) of In this way, capacitors having the same weight (eg, 2 ^NK ) may be switched redundantly by changing the capacitor array used to determine the upper bits and the lower bits.

Although each process is described as sequentially executed in FIG. 2 , this is merely an example of the technical idea of an embodiment of the present disclosure. In other words, those skilled in the art to which an embodiment of the present disclosure pertains may change and execute the order described in FIG. 2 or perform one or more of each process within the range that does not deviate from the essential characteristics of an embodiment of the present disclosure. Since it will be possible to apply various modifications and variations by executing in parallel, FIG. 2 is not limited to a time-series order.

Various implementations of the systems and techniques described herein may include digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), computer hardware, firmware, software, and/or their can be realized in combination. These various implementations may include being implemented as one or more computer programs executable on a programmable system. A programmable system includes at least one programmable processor (which may be a special purpose processor) coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. or may be a general-purpose processor). Computer programs (also known as programs, software, software applications or code) contain instructions for a programmable processor and are stored on a “computer readable medium”.

A computer-readable recording medium includes all kinds of recording devices that store data that can be read by a computer system. These computer-readable 　recording media include non-volatile or non-transitory media such as ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, and storage device. It may be a medium, and may further include a transitory medium such as a data transmission medium. In addition, the computer-readable recording medium may be distributed to computer systems connected through a network, and computer-readable codes may be stored and executed in a distributed manner.

Various implementations of the systems and techniques described herein may be implemented by a programmable computer. Here, the computer includes a programmable processor, a data storage system (including volatile memory, non-volatile memory, or other types of storage systems, or combinations thereof) and at least one communication interface. For example, a programmable computer may be one of a server, network device, set top box, embedded device, computer expansion module, personal computer, laptop, personal data assistant (PDA), cloud computing system, or mobile device.

The above description is merely an example of the technical idea of the present embodiment, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of the present embodiment, but to explain, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of this embodiment should be construed according to the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of rights of this embodiment.

10: SAR ADC 100, 102 and 104: S / H switch unit
110: first CDAC 112: coarse capacitor array
114: first residual capacitor array 120: second CDAC
122: second residual capacitor array 124: positive fine capacitor array
126: negative fine capacitor array 130: comparator
140: SAR control unit

Claims (10)

As a successive approximation register analog-to-digital converter that converts analog signals into digital codes,
a comparator including a first input terminal, a second input terminal, and an output terminal;
a first CDAC connected to the first input of the comparator and including binary-weighted capacitors;
A second CDAC connected to the second input terminal of the comparator, having the same total capacitance as that of the first CDAC, and including a plurality of capacitors corresponding to the least significant bits of the digital code. ; and
A SAR controller configured to determine the digital code by switching a reference voltage applied to capacitors included in the first CDAC and the second CDAC,
The second CDAC includes a positive fine capacitor array and a negative fine capacitor array including capacitors respectively corresponding to the at least one lower bit,
The first CDAC includes a coarse capacitor array including capacitors respectively corresponding to at least one upper bit of the digital code,
The SAR control unit selects a capacitor array for determining the at least one lower bit from among the positive fine capacitor array and the negative fine capacitor array based on the output of the comparator after determining the at least one upper bit. A successive approximation register analog-to-digital converter, characterized in that. delete According to claim 1,
The SAR controller,
A successive approximation register analog-to-digital converter, characterized in that determining the at least one lower bit by switching a reference voltage applied to capacitors included in one of the positive fine capacitor array and the negative fine capacitor array. delete According to claim 1,
The SAR controller,
The successive approximation register analog-to-digital converter, characterized in that determining the at least one upper bit by switching a reference voltage applied to capacitors included in the coarse capacitor array. According to claim 1,
The continuous approximation register analog-to-digital converter, wherein the coarse capacitor array, the positive fine capacitor array, and the negative fine capacitor array include one or more capacitors having the same weight. According to claim 1,
The SAR controller,
and determining the digital code, the measurement error of which is corrected, from the at least one upper bit and the at least one lower bit. delete According to claim 1,
The SAR controller,
If the voltage of the top plates of the capacitors constituting the first CDAC after determining the at least one upper bit is higher than the voltage of the top plates of the capacitors constituting the second CDAC, the positive fine capacitor array determining the at least one lower bit using
If the upper voltage of the first CDAC after determining the at least one upper bit is lower than the upper voltage of the second CDAC, the at least one lower bit is determined using the negative fine capacitor array. Successive approximation register analog-to-digital converter. A first CDAC including capacitors weighted in binary and a plurality of capacitors having the same total capacitance as the first CDAC and corresponding to at least one lower bit of the digital code A second As a method of operating a successive approximation register analog-to-digital converter including a CDAC,
determining at least one upper bit of the digital code using the first CDAC;
determining at least one lower bit of the digital code using the second CDAC; and
Determining the digital code, the measurement error of which is corrected, from the at least one upper bit and the at least one lower bit,
The second CDAC includes a positive fine capacitor array and a negative fine capacitor array including capacitors respectively corresponding to the at least one lower bit,
The first CDAC includes a coarse capacitor array including capacitors respectively corresponding to at least one upper bit of the digital code,
The process of determining the at least one lower bit may include determining the at least one lower bit among the positive fine capacitor array and the negative fine capacitor array based on the output of the comparator after determining the at least one upper bit. A method of operating a successive approximation register analog-to-digital converter, characterized in that for selecting a capacitor array for.

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