KR102548508B1 - Successive-Approximation-Register Analog-to-Digital-Converter Using Capacitor Split And Operating Method thereof - Google Patents

Abstract

A successive approximation register analog-to-digital converter using capacitor isolation and an operating method thereof are disclosed.
According to one aspect of the present disclosure, a successive approximation register analog-to-digital converter for converting an analog signal into a digital code includes at least one upper array and a terminal capacitor, wherein the at least one upper array comprises at least one a capacitor array including capacitors, each configured to correspond to at least one upper bit of the digital code; and determining a correction code by changing a voltage applied to a lower end of an upper array corresponding to a bit (hereinafter referred to as target bit) having a different value from the terminating capacitor or the least significant bit (LSB) of the digital code, It provides a successive approximation register analog-to-digital converter comprising a SAR controller for outputting an output code obtained by correcting the digital code using the correction code.

Description

Successive Approximation Register Analog-to-Digital Converter Using Capacitor Separation and Operation Method thereof

The present disclosure relates to a successive approximation register analog-to-digital converter using capacitor isolation and an operating method thereof.

The information described in this section simply provides background information on the present invention and does not constitute prior art.

An analog to digital converter (ADC) refers to a circuit that converts an analog input signal into a digital output signal.

Successive-Approximation-Register ADC (SAR ADC) is an ADC in the form of sequentially changing the reference voltage to be compared with the analog input while finding a digital output value that is as close as possible to the analog input. Also called type ADC.

The SAR ADC is equipped with a digital-to-analog converter (Capacitor Digital-to-Analog-Converter) to sequentially change the reference voltage to be compared with the analog input. Based on the charge redistribution principle, the comparison corresponding to the analog input and reference voltage A capacitor array that forms a voltage is mainly used, and is also called a capacitor DAC.

In order to increase the resolution of the SAR ADC by 1 bit, generally, the capacitance of the capacitor array must be doubled. As the capacitance increases, the settling time required to stabilize the comparison voltage also increases. If this settling time is not sufficiently guaranteed, since the digital output value is determined in a state where the comparison voltage is not stabilized, measurement errors often occur, making it difficult to implement a high-speed and high-resolution SAR ADC.

The main object of the present disclosure is to provide a SAR ADC capable of realizing high speed and high resolution and an operating method thereof by correcting measurement errors using a correction capacitor separated from a capacitor corresponding to an upper bit.

According to one aspect of the present disclosure, a successive approximation register analog-to-digital converter for converting an analog signal into a digital code includes at least one upper array and a terminal capacitor, wherein the at least one upper array comprises at least one a capacitor array including capacitors, each configured to correspond to at least one upper bit of the digital code; and determining a correction code by changing a voltage applied to a lower end of an upper array corresponding to a bit (hereinafter referred to as target bit) having a different value from the terminating capacitor or the least significant bit (LSB) of the digital code, It provides a successive approximation register analog-to-digital converter comprising a SAR controller for outputting an output code obtained by correcting the digital code using the correction code.

According to another aspect of the present disclosure, as a method of operating a successive approximation register analog-to-digital converter including at least one capacitor and including at least one upper array and a terminating capacitor respectively corresponding to at least one upper bit of a digital code, determining a digital code corresponding to the signal; determining a correction code by changing a lower voltage of an upper array corresponding to a bit having a different value from the terminating capacitor or a least significant bit (LSB) of the digital code; and outputting an output code obtained by correcting the digital code using the correction code.

As described above, according to the embodiment of the present disclosure, there is an effect that a high-speed and high-resolution SAR ADC can be implemented by correcting the measurement error using a correction capacitor separated from the capacitor corresponding to the upper bit.

1 is a configuration diagram showing a SAR ADC according to an embodiment of the present disclosure.
2 is an exemplary view showing the structure of a capacitor array according to an embodiment of the present disclosure.
3 is a flowchart for explaining the operation of a SAR ADC according to an embodiment of the present disclosure.
4a to 4d are signal flow diagrams illustrating the operation of a 5-bit SAR ADC according to an embodiment of the present disclosure.
5 is an exemplary view showing the structure of a capacitor array according to another embodiment of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail through exemplary drawings. In adding reference numerals to components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description will be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present disclosure. These terms are only used to distinguish the component from other components, and the nature, order, or order of the corresponding component is not limited by the term. Throughout the specification, when a part 'includes' or 'includes' a certain component, it means that it may further include other components without excluding other components unless otherwise stated. . In addition, the '... Terms such as 'unit' and 'module' refer to a unit that processes at least one function or operation, and may be implemented as hardware, software, or a combination of hardware and software.

1 is a configuration diagram showing a SAR ADC according to an embodiment of the present disclosure.

Referring to FIG. 1, a SAR ADC (Successive-Approximation-Register Analog-to-Digital-Converter, 10) according to an embodiment of the present disclosure includes a S/H switch unit (Sample-and-hold switch unit, 100), First and second capacitor arrays 110_p and 110_n, first and second switch arrays 120_p and 120_n and first and second charge pumps 130_p and 130_n, comparators ( comparator 140) and a SAR control unit 150 in whole or in part. All components shown in FIG. 1 are not essential components, and some components included in the SAR ADC 10 may be added, changed, or deleted in other embodiments. For example, according to another embodiment of the present disclosure, the first and second charge pumps 130_p and 130_n may not be included.

In response to the control of the SAR control unit 150, the S/H switch unit 100 transmits the first input signal V _INp and the second input signal V _INn to the first capacitor array 110_p and the second capacitor array, respectively. The array 110_n is sampled and held. Sampling means charging the first and second input signals V _INp and V _INn , which are analog input signals, in the first capacitor array 110_p and the second capacitor array 110_n, respectively. For example, when the S/H switch unit 100 is turned on, the first input signal V _INp and the second input signal are connected to one end of the first capacitor array 110_p and the second capacitor array 110_n. (V _INn ) is applied. Accordingly, charges corresponding to the first input signal V _INp and the second input signal V _INn are charged in the first capacitor array 110_p and the second capacitor array 110_n, respectively. Thereafter, when the S/H switch unit 100 is turned off, the charges charged in the first capacitor array 110_p and the second capacitor array 110_n are maintained.

Meanwhile, in FIG. 1, an example in which a top plate sampling technique in which the first input signal V _INp and the second input signal V _INn are applied to the top plate of the capacitor is applied is shown, but The present disclosure is not limited thereto. That is, in another embodiment of the present disclosure, a bottom plate sampling technique may be applied.

2 is an exemplary view showing the structure of a capacitor array according to an embodiment of the present disclosure.

The structure of FIG. 2 may be equally applied to the first and second capacitor arrays 110_p and 110_n, the first and second switch arrays 120_p and 120_n, and the first and second charge pumps 130_p and 130_n. In the present disclosure, identification code '_p' means a component/signal related to the first capacitor array 110_p, and identification code '_n' means a component/signal related to the second capacitor array 110_n. Hereinafter, in describing FIG. 2 , the identification code '_p' or '_n' is omitted for contents commonly applied to configurations/signals related to the first and second capacitor arrays 110_p and 110_n.

As shown in FIG. 2 , the capacitor array 110 according to an embodiment of the present disclosure includes an upper array 200 and a lower array 250, and the upper array 200 and the lower array 250 each include a plurality of Including capacitors. One end of the capacitors included in the upper array 200 and the lower array 250 (hereinafter referred to as 'an upper end of the capacitor array 110') is connected in common to one end of the comparator 140, for example, an inverting terminal or a non-inverting terminal. connected to The total number of capacitors constituting the capacitor array 110 may be determined according to a resolution and a switching technique.

The upper array 200 corresponds to the most significant bit (MSB) of the N-bit digital output, and each of the capacitors (C _{N-1 to} C ₁ ) included in the lower array 250 is from the next highest bit to the least significant bit ( LSB: corresponds to one of the bits up to Least Significant Bit). In the present disclosure, the capacitor C k corresponding to the k (k is a natural number smaller than N) th bit B _{k is} a capacitor whose reference voltage applied to the lower end can be changed by a predetermined k th bit value. , and the capacitor corresponding to MSB (B _N ) means all of the capacitors included in the upper array 200 .

The capacitance of the upper array 200 and the capacitance of capacitors included in the lower array 250 are defined by corresponding bits. When the unit capacitance is C, the capacitance of the upper array 200 corresponding to MSB (B _N ) is 2 ^N-2 C, and the capacitor (C corresponding to the next bit (B _{N - 1} ) The capacitance of _{N - 2} ) is 2 ^{N - 3} C. In this order, the capacitance of the capacitor C ₃ corresponding to the third bit B ₃ becomes 2C, and the capacitance of the capacitor C ₂ corresponding to the second bit B ₂ becomes C. Meanwhile, the capacitance of the capacitor (C ₁ ) corresponding to the LSB (B ₁ ) is equal to the capacitance C of the capacitor (C ₂ ) corresponding to the second bit (B ₂ ). Hereinafter, the capacitor C ₁ corresponding to the LSB is referred to as a terminal capacitor.

The upper array 200 has a form in which at least one correction capacitor (C _calM to C _cal1 ) is separated from a capacitor having a capacitance (eg, 2 ^N−2 C) corresponding to MSB (B _N ). In other words, the upper array 200 includes at least one correction capacitor (C _calM ~C _cal1 ) and a residual capacitor (C _{N_res} ). The capacitance of each correction capacitor C _calM to C _cal1 is preferably the same as the unit capacitance C, but is not limited thereto and may vary depending on the applied switching technique. The capacitance of the residual capacitor (C _{N _res} ) is defined as a value limiting the capacitance of at least one correction capacitor (C _calM to C _cal1 ) in the total capacitance of the upper array 200 . In other words, when the resolution of the SAR ADC 10 is N bits and the number of correction capacitors C _calM to C _cal1 in the upper array 200 is M, the capacitance of the remaining capacitor C _{N_res} is (2 ^{N- 2} -M)C becomes.

Table 1 is a table illustrating the weight of each capacitance when the resolution of the SAR ADC 10 is 10 bits and the number of correction capacitors C _calM to C _cal1 in the upper array 200 is two.

Bit _{B10 B9 B8 B7 B6} B _{5 B4 B3 B2 B1} Cap C _cal2 C _cal1 C _{10_res} C ₉ C ₈ C _{7 C6} C ₅ C ₄ C ₃ C ₂ C ₁ Weight 2 ⁰ =1 2 ⁰ =1 2 ⁸ -2=254 2 ⁷ =128 2 ⁶ =64 2 ⁵ =32 2 ⁴ =16 2 ³ =8 2 ² =4 2 ¹ =2 2 ⁰ =1 2 ⁰ =1

Meanwhile, the total capacitance of the capacitor array 110 and/or the weight of each capacitance may vary depending on implementation. For example, although the capacitor array 110 is illustrated as having a binary weight in FIG. 2 , the capacitor array 110 may have a non-binary weight according to embodiments.

The switch array 120 includes a plurality of switches. One end of each of the plurality of switches is connected to the lower ends of the remaining capacitors except for the terminating capacitor C ₁ . The other ends of the plurality of switches correspond to the control of the SAR controller 150, and may be connected to the first reference voltage V _REF or the second reference voltage GND. In the present disclosure, a switch connected to the lower end of the capacitor corresponding to the k-th bit (B _k ) is referred to as a switch corresponding to the k-th bit (B _k ). A switch corresponding to MSB(B _N ) may mean all of the switches S _calM to S _cal1 and S _{N_res} connected to lower ends of the capacitors included in the upper array 200 . In the present disclosure, the correction switch may refer to a switch (S _calM ˜S _cal1 ) connected to a lower end of a correction capacitor (C _calM ˜C _cal1 ) among switches corresponding to MSB (B _N ).

The charge pump 130 is connected to the lower end of the terminating capacitor C ₁ . The charge pump 130 responds to the control of the SAR controller 150 and increases the lower voltage (V _CP ) of the terminating capacitor C ₁ . Preferably, the charge pump 130 may increase the lower voltage V _CP of the terminating capacitor C ₁ by a level corresponding to the number of correction capacitors C _calM to C _cal1 . For example, when M is 2, the charge pump 130 converts the lower end voltage (V _CP ) of the terminating capacitor (C ₁ ) to the first reference voltage (V _REF ) or twice the first reference voltage (2*V _REF ). can be raised to Meanwhile, since the configuration and operation of the charge pump 130 are common in the field, a detailed description thereof will be omitted.

Referring back to FIG. 1 , the comparator 140 has a first input terminal (+), a second input terminal (-), and an output terminal, and the first input terminal and the second input terminal are a first capacitor array 110_p and a second capacitor array. (110_n) is connected to the top of each. The comparator 140 calculates the voltage of the first input terminal and the voltage of the second input terminal, that is, the upper voltage V _{Ctop _p} of the first capacitor array 110_p and the upper voltage V _{Ctop_n} of the second capacitor array 110_n. The comparison result is output to the SAR controller 150.

Based on the output of the comparator 140, the SAR controller 150 determines an N-bit digital code <B _N :B ₁ >. The SAR controller 150 controls the switch corresponding to the corresponding bit based on the value of the k-th bit (B _k ). Accordingly, the upper voltage V _{Ctop_p} of the first capacitor array 110_p and/or the upper voltage V _{Ctop_n} of the second capacitor array 110_n are changed, and the SAR controller 150 controls the comparator 140 to The output is used to determine the next bit (B _{k - 1} ).

The SAR controller 150 determines a correction code <B calT :B _cal1 > for correcting a measurement error _between the analog input signals V _INp and V _INn and the digital code <B _N :B ₁ >. The number of bits T of the correction code may be defined by the number of correction capacitors C _calM to C _cal1 in the upper array 200 and/or the number of voltage levels that the charge pump 130 can raise. For example, when the number of correction capacitors C _calM to C _cal1 in the upper array 200 is M, the number of bits T of the correction code can be obtained as in Equation 1.

Table 2 shows the upper array 200 including two correction capacitors (C _cal2 and C _cal1 ) and the voltage to be raised to the first reference voltage (V _REF ) or twice the first reference voltage (2*V _REF ). This table illustrates a method of correcting an error of ±2 LSB using the charge pump 130 that can be used. In Table 2, the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p is indicated by a solid line, and the top voltage (V _{Ctop_n} ) of the second capacitor array 110_n is indicated by a dotted line.

MSB LSB control Operating Waveform (V _{Ctop_p} , V _{Ctop_n} ) 0 0 2nd charge pump

0 One _{S cal1_n}
and/or
_{S cal2_n}

One 0 S _{cal1 _p}
and/or
_{S cal2_p}

One One 1st charge pump

judgment No error Less than 2 LSB 2 LSBs or higher correction code <00> <01> <10>

After determining the LSB(B ₁ ), the SAR controller 150 according to an embodiment of the present disclosure may additionally determine the correction code <B _cal2 :B _cal1 > by using 2 clocks. The SAR control unit 150 adjusts the compensation switch S of the first charge pump 130_p, the second charge pump 130_n, and the first switch array 120_p according to the combination of the MSB (B _N ) and the LSB (B ₁ ). Controls at least one of _{calM _p} to S _{cal1 _p} , hereinafter, 'first correction switch') and correction switch (S _{calM _n} to S _{cal1 _n} , hereinafter, 'second correction switch') of the second switch array 120_n Thus, the correction code <B _cal2 :B _cal1 > can be determined.

1) When MSB (B _N ) and LSB (B ₁ ) are the same

The SAR controller 150 controls the first charge pump 130_p or the second charge pump 130_n to control the terminating capacitor C ₁ of the first capacitor array 110_p (hereinafter referred to as the first terminating capacitor) or the second capacitor array ( The lower end voltage (V _{CP _p} or V _{CP _n} ) of the terminating capacitor (C ₂ , hereinafter referred to as the second terminating capacitor) of the 110_n is raised to the first reference voltage (V _REF ). Accordingly, the top voltage (V _{Ctop _p} or V _{Ctop _n} ) of the first capacitor array 110_p or the second capacitor array 110_n is a voltage (V _LSB , for example, 1/2 ^{N -1} * corresponding to 1 LSB). V _REF ). When the upper voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the upper voltage (V _{Ctop _n} ) of the second capacitor array 110_n cross each other by this voltage increase, the SAR controller 150 ) determines that there is no error in the digital code <B _N :B ₁ >, and determines the correction code <B _cal2 :B _cal1 > as <00>. The SAR controller 150 determines the output of the comparator 140 used to determine the LSB (B ₁ ) and the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p or the top voltage (V _Ctop ) of the second capacitor array 110_n When the outputs of the comparator 140 after changing _{_n} ) are different, the upper voltage V _{Ctop _p} of the first capacitor array 110_p and the upper voltage V _{Ctop _n} of the second capacitor array 110_n cross each other can be judged to have been

When the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n do not cross each other, the SAR controller 150 generates the first charge pump 130_p Alternatively, by controlling the second charge pump 130_n, the lower voltage (V _{CP _p} or V _{CP _n} ) of the first terminating capacitor (C _{1_p} ) or the second terminating capacitor (C _{1_n} ) is twice the first reference voltage (2 *V _REF ). Accordingly, the top voltage (V _{Ctop _p} or V _{Ctop _n} ) of the first capacitor array 110_p or the second capacitor array 110_n is further increased by VLSB. When the upper voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the upper voltage (V _{Ctop _n} ) of the second capacitor array 110_n cross each other due to this voltage increase, the SAR controller 150 converts the digital It is determined that an error of less than 2 LSB exists in the code <B _N :B ₁ >, and the correction code <B _cal2 :B _cal1 > is determined to be <01>.

On the other hand, even though the top voltage (V _{Ctop_p} or V _{Ctop_n} ) of the first capacitor array _{110_p} or the second capacitor array 110_n is increased by a total of 2*VLSB, the top voltage (V _Ctop ) of the first capacitor array 110_p _{_p} ) and the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n do not cross each other, the SAR controller 150 determines that an error of 2 LSB or more exists in the digital code <B _N : B ₁ > and the correction code <B _cal2 :B _cal1 > is determined as <10>.

2) When MSB (B _N ) and LSB (B ₁ ) are different

The SAR controller 150 controls the 1-1 correction switch (S _{cal1 _p} ) or the 2-1 correction switch (S _{cal1 _n} ), so that the 1-1 correction capacitor (C _{cal1 _p} ) or the 2-1 correction switch The lower voltage of the capacitor C _{cal1 _n} is changed from the first reference voltage V _REF to the second reference voltage GND. Accordingly, the top voltage (V _{Ctop _p} or V _{Ctop_n} ) of the first capacitor array 110_p or the second capacitor array 110_n is reduced by V _LSB . Due to this voltage reduction, when the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n cross each other, the SAR controller 150 ) determines that there is no error in the digital code <B _N :B ₁ >, and determines the correction code <B _cal2 :B _cal1 > as <00>.

If the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the top voltage (V _{Ctop_n} ) of the second capacitor array 110_n do not cross each other, the SAR control unit 150 controls the 1-2 correction switch (S _{cal2 _p} ) or the 2-2 correction switch (S _{cal2 _n} ) is controlled to set the lower voltage of the 1-2 correction capacitor (C _{cal2_p} ) or the 2-2 correction capacitor (C _{cal2 _n} ) to the first reference voltage ( V _REF ) to the second reference voltage (GND). Accordingly, the top voltage (V _{Ctop _p} or V _{Ctop _n} ) of the first capacitor array 110_p or the second capacitor array 110_n is further reduced by VLSB. Due to this voltage decrease, when the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n cross each other, the SAR controller 150 converts the digital It is determined that an error of less than 2 LSB exists in the code <B _N :B ₁ >, and the correction code <B _cal2 :B _cal1 > is determined to be <01>.

On the other hand, even though the top voltage (V _{Ctop_p} or V _{Ctop_n} ) of the first capacitor array _{110_p} or the second capacitor array 110_n is reduced by a total of 2*VLSB, the top voltage (V _Ctop ) of the first capacitor array 110_p _{_p} ) and the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n do not cross each other, the SAR controller 150 determines that an error of 2 LSB or more exists in the digital code <B _N : B ₁ > and the correction code <B _cal2 :B _cal1 > is determined as <10>.

The SAR control unit 150 outputs a final output code <D _N :D ₁ > with an error corrected based on the digital code _< B N :B 1 > and the correction code < _{B calT} :B _cal1 >. The SAR control unit 150 may add or subtract the correction code <B _calT :B _cal1 > from the digital code <B _N :B ₁ > to obtain the final output code <D _N :D ₁ >. For example, if the resolution of the SAR ADC 10 is 10 bits and the number of correction capacitors (C _calM ~C _cal1 ) in the upper array 200 is 2, the final output code <D _N :D ₁ > is It can be obtained as in Equation 2.

The SAR controller 150 according to an embodiment of the present disclosure may determine an operation method for obtaining the final output code <D _N :D ₁ > based on LSB(B ₁ ). For example, if the LSB(B ₁ ) is '0', the SAR controller 150 subtracts the correction code <B _calT :B _cal1 > from the digital code <B _N :B ₁ >, and the LSB(B ₁ ) is '0'. 1', the final output code can be obtained by adding the correction code <B _calT :B _cal1 > to the digital code <B _N :B ₁ >.

Hereinafter, the operation of the SAR ADC according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 3 to 4D.

3 is a flowchart for explaining the operation of a SAR ADC according to an embodiment of the present disclosure.

4a to 4d are signal flow diagrams illustrating the operation of a 5-bit SAR ADC according to an embodiment of the present disclosure.

4A shows a case where the MSB (B ₅ ) and the LSB (B ₁ ) are 0 and 0, respectively, after determining the next-order bit (B ₄ ) and before the voltage (V _{Ctop _n} ) of the second capacitor array 110_n is stabilized. It shows the process of correcting the measurement error caused by determining the next bit (B ₃ ).

4B is _a case _where the MSB ( _{B 5} ) and the LSB (B ₁ ) are 0 and 1, respectively. It shows the process of correcting the measurement error caused by determining the bit (B ₄ ).

4C is a case where the MSB (B ₅ ) and LSB (B ₁ ) are 1 and 0, respectively, after determining the MSB (B ₅ ) and before the upper voltage (V _{Ctop _n} ) of the second capacitor array 110_n is stabilized, the following It shows the process of correcting the measurement error caused by determining the bit (B ₄ ).

FIG. 4D shows a case in which the MSB (B ₅ ) and the LSB (B ₁ ) are 1 and 1, respectively, after determining the next-order bit (B ₄ ) and before the voltage (V _{Ctop _p} ) of the first capacitor array 110_p is stabilized. It shows the process of correcting the measurement error caused by determining the next bit (B ₃ ).

First, the S/H switch unit 100 is turned on/off in response to the control of the SAR controller 150 to generate the first input signal V _INp and the second input signal V _INn . Sampling and holding are performed on the first capacitor array 110_p and the second capacitor array 110_n, respectively (S300). According to an embodiment of the present disclosure, while sampling is performed, lower ends of the first and second capacitor arrays 110_p and 110_n may be connected to the first reference voltage VREF or the second reference voltage GND. For example, the lower end of all capacitors except for the terminating capacitor C ₁ may be connected to the first reference voltage VREPF and the lower end of the terminating capacitor may be connected to the second reference voltage GND, but is not limited to this example. . For example, according to another embodiment of the present disclosure, while sampling is performed, the first reference voltage V _REF may be connected to lower ends of all capacitors.

The SAR controller 150 determines an N-bit digital code <B _N :B ₁ > using a successive approximation technique (S310).

For example, referring to FIGS. 4A to 4D , after sampling is finished, the comparator 140 determines the top voltage (V Ctop _{_p} ) of the first capacitor array 110_p and the top voltage (V _Ctop _p ) of the second capacitor array 110_n. V _{Ctop _n} ). The SAR controller 150 receives the comparison result, and when the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n is greater than the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p, MSB (B _N ) is determined as '1', and if it is small, it is determined as '0'.

The SAR controller 150 controls a switch connected to a capacitor array determined to have a high upper voltage among switches S _calM to S _cal1 and S _N corresponding to MSB (B _N ). For example, when it is determined that the upper voltage (V _{Ctop _p} ) of the first capacitor array 110_p is high, that is, when MSB (B _N ) is determined to be 0, a switch connected to the lower end of the first capacitor array 110_p ( S _{calM _p} to S _{cal1 _p} and S _{N_p} ) are controlled to be connected to the second reference voltage (GND). Accordingly, the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p is reduced by 1/2*VREF (① in FIGS. 4A and 4B). Conversely, when it is determined that the upper voltage (V _{Ctop _n} ) of the second capacitor array 110_n is high, that is, when the MSB (B _N ) is determined to be 1, the switch S connected to the lower end of the second capacitor array 110_n _{calM_n} to S _cal1 and S _{N_n} ) are controlled to be connected to the second reference voltage (GND). Accordingly, the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n is reduced by 1/2*VREF (① in FIGS. 4C and 4D).

In the same way, the SAR control unit 150 receives the comparison result of the comparator 140, determines the value of the k-th bit (B _{k ,} where k is a natural number smaller than N and larger than 1), and switches corresponding to the bit ( The value of the next bit ( _{B k -} 1 ) is controlled by controlling the switch connected to the capacitor array 110 of which the upper end voltage is determined to be high among S _{k _p} and S _{k _n} (②, ③ and ④ in FIGS. 4A to _4D ) Decide.

Next, the SAR controller 150 determines that one of the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p and the top voltage (V Ctop _{_n} ) of the second capacitor array _{110_n} is a voltage size corresponding to 1 LSB. (V _LSB , eg, 1/2 ^{N -1} *VREF) (S320). For example, when it is determined that the top voltage (V _{Ctop_p} ) of the first capacitor array 110_p is higher than the top voltage (V _{Ctop_n} ) of the second capacitor array 110_n when the LSB (B ₁ ) is determined, that is, the LSB ( When B ₁ ) is determined to be 0, the upper voltage (V _{Ctop_n} ) of the second capacitor array 110_n is increased by VLSB (⑤ in FIG. 4A ), or the upper voltage (V _{Ctop _p} ) of the first capacitor array 110_p can be lowered by VLSB (⑤ in FIG. 4C). Conversely, when it is determined that the top voltage (V _{Ctop_n} ) of the second capacitor array 110_n is higher than the top voltage (V Ctop_p ) of the first capacitor array _{110_p} at the time of determining the LSB (B ₁ ), LSB (B ₁ ) When is determined to be 1, the top voltage (V _{Ctop_p} ) of the first capacitor array 110_p is increased by VLSB (⑤ in FIG. 4D), or the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n is set to V _LSB It can be lowered as much as (⑤ in FIG. 4B).

The SAR controller 150 determines whether the top voltages V _{Ctop_p} and V Ctop_n of the first and second capacitor arrays 110_p and _{110_n} cross each other (S330). For example, by comparing the output of the comparator 140 before and after step S320 of the SAR controller 150, and the output of the comparator 140 is different, the upper end voltage of the first and second capacitor arrays 110_p and 110_n ( It can be determined that V _{Ctop _p} and V _{Ctop _n} ) intersect.

When it is determined that the top voltages (V _{Ctop _p} and V _{Ctop _n} ) of the first and second capacitor arrays 110_p and 110_n do not cross, the SAR controller 150 re-performs step S320 (see FIGS. 4A to 4D). ⑥). When the upper array 200 and/or the charge pump 130 are designed to change the upper voltage (V _Ctop ) of the capacitor array 110 by a total of M * VLSB, the SAR control unit 150 sets step S320 up to M It can be performed once (S312, S332 and S334).

When it is determined that the top voltages V _{Ctop _p} and V _{Ctop _n} of the first and second capacitor arrays 110_p and 110_n cross, the SAR controller 150 calculates the correction code <B based on the number of times that step S320 has been performed. _calT :B _cal1 > is determined (S340). When step S320 is performed j times, the correction code <B _calT :B _cal1 > may be a value obtained by expressing (j-1) as a binary number. For example, when M is 2, if j is performed once in step S320, the correction code <B _calT :B _cal1 > is determined to be <00>, and if j is performed twice in step S320, the correction code <B _calT :B _cal1 > can be determined as <10>.

Even though the top voltage (V _{Ctop _p} ) of the first capacitor array 110_p or the top voltage (V _{Ctop _n} ) of the second capacitor array 110_n is changed by a total of M * VLSB, the output of the comparator 140 is not changed If it is determined, the SAR controller 150 determines that there is a measurement error greater than M LSB and determines correction bits <B _calT :B _cal1 > corresponding to the measurement error (S342). In this case, the correction bit may be a value obtained by expressing M as a binary number. For example, when M is 2, the correction bit <B _calT :B _cal1 > may be determined as <10>.

The SAR controller 150 calculates the final output code <D _N :D ₁ > using <B _N :B ₁ > and <B _calT :B _cal1 > (S350). The SAR controller 150 may add or subtract <B _calT :B _cal1 > from <B _N :B ₁ > to obtain the final output code <D _N :D ₁ >.

Although each process is described as sequentially executed in FIG. 3 , this is merely an example of the technical idea of an embodiment of the present disclosure. In other words, those skilled in the art to which an embodiment of the present disclosure pertains may change and execute the order described in FIG. 3 or perform one or more of each process within the range that does not deviate from the essential characteristics of an embodiment of the present disclosure. Since it will be possible to apply various modifications and variations by executing in parallel, FIG. 3 is not limited to a time-series order.

5 is an exemplary view showing the structure of a capacitor array according to another embodiment of the present disclosure.

5 shows the structure of a capacitor array when the resolution of the SAR ADC 10 is 5 bits and the number of correction capacitors in the upper array 500 is two.

Referring to FIG. 5 , a capacitor array 110 according to another embodiment of the present disclosure includes a plurality of upper arrays 500 to 504 and a lower array 550, and the upper array 500 to 504 and the lower array ( 550) each includes a plurality of capacitors. One end of the capacitors included in the upper arrays 500 to 504 and the lower array 550 (hereinafter referred to as 'an upper end of the capacitor array 110') is connected in common to one end of the comparator 140 (eg, an inverting terminal or a non-reversing terminal). inverted terminal). The total number of capacitors constituting the capacitor array 110 may be determined according to a resolution and a switching technique.

The plurality of upper arrays 500 to 504 correspond to upper bits of N-bit digital output, and capacitors included in the lower array 550 correspond to lower bits. The number of upper bits and lower bits may be determined according to resolution and the number of correction capacitors. For example, referring to FIG. 5 , the first to third upper arrays 500 to 504 each correspond to one of the upper 3 bits (B ₅ to B ₃ ), and the capacitor included in the lower array 550 Each of (C ₂ and C ₁ ) may correspond to one of the lower 2 bits (B ₂ and B ₁ ).

The capacitance of the upper arrays 500 to 504 and the capacitances of capacitors included in the lower array 550 are defined by corresponding bits.

In the upper arrays 500 to 504, at least one correction capacitor (C _{k_calM} to C _{k_cal1} ) is separated from a capacitor having a capacitance value (eg, 2 ^N-2 C) defined by a corresponding bit (eg, B _k ). has a form Accordingly, the upper arrays 500 to 504 may include all or part of at least one correction capacitor (C _{k_calM} to C _{k_cal1} ) and a residual capacitor (C _{k_res} ). The capacitance of each correction capacitor (C _{k_calM} to C _{k_cal1} ) is preferably the same as the unit capacitance C, but is not limited thereto and may vary depending on an applied switching technique or the like. The capacitance of the residual capacitor (C _{k _res} ) is defined as a value limiting the capacitance of at least one correction capacitor (C _{k_calM} to C _{k_cal1} ) in the total capacitance (2 ^N-2 C) of the upper arrays 500 to 504 . Accordingly, as in _the third upper array 504 of FIG. 5 , when the total capacitance corresponding to the bits is equal to _or smaller than the sum of the capacitances of the plurality of correction capacitors C _{3_cal2} to C _{3_cal1} , the upper arrays 500 to 500 504) may not include a residual capacitor.

Table 3 is a table illustrating a method of correcting a measurement error using the capacitor array structure of FIG. 5 . In Table 3, information unnecessary for description is omitted by expressing it with -.

case B ₈ B ₄ B ₃ B ₂ B _One control One ~B ₁ - - - 0 S _{5_ cal1 _p} and/or S ₅ : V _REF → GND One S _{5_ cal1 _n} and/or S _{5_ cal2 _n} : V _REF → GND _- ~B ₁ - - 0 S _{4_ cal1 _p} and/or S _{4_ cal2 _p} : V _REF → GND One S _{4_ cal1 _n} and/or S _{4_ cal2 _n} : V _REF → GND _{- -} ~B ₁ - 0 S _{3_ cal1 _p} and/or S _{3_ cal2 _p} : V _REF → GND One S _{3_ cal1 _n} and/or S _{3_ cal2 _n} : V _REF → GND 2 - _{- -} ~B ₁ 0 S _{2_p} and/or S _{1_p} : V _REF → GND One S _{2_n} and/or S _{1_n} : V _REF → GND 3 _{B1 B1 B1 B1} 0 S _{1_p} : V _REF → GND One S _{1_n} : V _REF → GND

The SAR controller 150 according to another embodiment of the present disclosure may include a correction switch (S _{k _ calM} ~S _{l _ cal1} ) and/or a sub-array corresponding to a bit (B _k ) having a value different from the LSB (B ₁ ) The correction code <B _cal2 :B _cal1 > may be determined by controlling at least one switch S ₂ and S ₁ connected to the lower end of 550 . On the other hand, when there are a plurality of bits having values different from LSB (B ₁ ), the switch on which the control target is placed may vary depending on the implementation.

1) When there is a bit having a different value from LSB(B ₁ ) among upper bits <B ₅ :B ₃ >

The SAR controller 150 controls the correction switches S _{k_cal1} and/or S _{k _ cal1} corresponding to the bit B _k having a different value from the LSB (B ₁ ) to generate the correction capacitors C _{k _ cal1 and/or Alternatively,} the lower voltage of C _{k _ cal2} ) is changed from the first reference voltage V _REF to the second reference voltage GND. For example, the SAR controller 150 may select one of the first correction switch (S _{k _ cal1 _p} and/or _{Sk _ cal1 _p} ) and the second correction switch (S _{k _ cal1 _n} and/or _{Sk _ cal1 _n} ). When determining LSB(B ₁ ), a correction switch connected to a capacitor array determined to have a high upper voltage may be controlled. Accordingly, the top voltage (V _{Ctop_p} or V _{Ctop_n} ) of the first capacitor array 110_p or the second capacitor array 110_n is reduced by V _LSB and/or 2*V _LSB . The method for determining the correction code <B _cal2 :B _cal1 > is the same as that described in Table 2, so it is omitted.

2) When the second bit (B ₂ ) has a different value from the LSB (B ₁ )

The SAR controller 150 controls the switches S ₂ and/or S ₁ corresponding to the second bit (B ₂ ) and/or the LSB (B ₁ ). That is, in this case, capacitors (C ₂ and C ₁ ) and switches (S ₂ and S ₁ ) corresponding to the second bit (B ₂ ) and LSB (B ₁ ) are used as a correction capacitor and a correction switch.

3) When all bits have the same value as LSB (B ₁ )

The SAR controller 150 controls the switch (S ₁ ) corresponding to the LSB (B ₁ ) to change the lower voltage of the terminating capacitor (C ₁ ) from the first reference voltage (V _REF ) to the second reference voltage (GND) let it In this case, since the top voltage (V _{Ctop_p} or V _{Ctop_n} ) of the first capacitor array 110_p or the second capacitor array 110_n can be reduced only by V _LSB , the correction code <B _cal2 :B _cal1 > is <00> or <01>.

As described above, according to another embodiment of the present disclosure, energy consumed by the charge pump 130 can be saved by using various capacitors as correction capacitors according to the value of the digital code.

Various implementations of the systems and techniques described herein may include digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), computer hardware, firmware, software, and/or their can be realized in combination. These various implementations may include being implemented as one or more computer programs executable on a programmable system. A programmable system includes at least one programmable processor (which may be a special purpose processor) coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. or may be a general-purpose processor). Computer programs (also known as programs, software, software applications or code) contain instructions for a programmable processor and are stored on a “computer readable medium”.

A computer-readable recording medium includes all kinds of recording devices that store data that can be read by a computer system. These computer-readable 　recording media include non-volatile or non-transitory media such as ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, and storage device. It may be a medium, and may further include a transitory medium such as a data transmission medium. In addition, the computer-readable recording medium may be distributed to computer systems connected through a network, and computer-readable codes may be stored and executed in a distributed manner.

Various implementations of the systems and techniques described herein may be implemented by a programmable computer. Here, the computer includes a programmable processor, a data storage system (including volatile memory, non-volatile memory, or other types of storage systems, or combinations thereof) and at least one communication interface. For example, a programmable computer may be one of a server, network device, set top box, embedded device, computer expansion module, personal computer, laptop, personal data assistant (PDA), cloud computing system, or mobile device.

The above description is merely an example of the technical idea of the present embodiment, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of the present embodiment, but to explain, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of this embodiment should be interpreted according to the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of rights of this embodiment.

10: SAR ADC 100: S/H switch unit
110: capacitor array 120: switch array
130: charge pump 140: comparator
150: SAR control unit
200: upper array 50: lower array
500, 502 and 504: upper array 550: lower array

Claims (11)

As a successive approximation register analog-to-digital converter that converts analog signals into digital codes,
At least one upper array and a terminal capacitor, wherein the at least one upper array includes at least one capacitor and is configured to correspond to at least one upper bit of the digital code, respectively. );
a SAR controller for determining a correction code by changing a voltage applied to the termination capacitor or a bottom plate of an upper array corresponding to the target bit, and correcting the digital code using the correction code; and
A charge pump connected to a lower end of the termination capacitor,
The target bit is any one bit having a value different from the least significant bit (LSB) of the digital code among at least one upper bit of the digital code,
The SAR control unit controls the charge pump when there is no upper array corresponding to the target bit. According to claim 1,
The upper array,
A successive approximation register analog-to-digital converter comprising at least one correction capacitor. According to claim 2,
The SAR controller,
and controlling a switch connected to a lower end of the at least one correction capacitor corresponding to the target bit. According to claim 2,
The upper array corresponding to the target bit,
The successive approximation register analog-to-digital converter, characterized in that the at least one correction capacitor is configured in a separate form from the capacitor corresponding to the target bit. delete According to claim 1,
The capacitor array,
A first capacitor array connected to a first input terminal of a comparator and a second capacitor array connected to a second input terminal of the comparator,
Each of the first capacitor array and the second capacitor array includes the at least one upper array and the terminating capacitor,
The SAR controller,
Selecting at least one capacitor array from among the first capacitor array and the second capacitor array based on the output of the comparator;
and changing a voltage applied to the terminating capacitor included in the selected at least one capacitor array or a lower end of an upper array corresponding to the target bit included in the selected at least one capacitor array. converter. According to claim 6,
The SAR controller,
Wherein the correction code is determined based on whether the voltage of the first input terminal and the voltage of the second input terminal cross each other in response to a change in the voltage applied to the lower end. According to claim 6,
The SAR controller,
and changing the voltage applied to the lower end within a predetermined number of times until the voltage of the first input terminal and the voltage of the second input terminal cross each other. According to claim 6,
The SAR controller,
and determining the correction code using at least one upper array included in a capacitor array connected to an input terminal determined to have a higher voltage among the first input terminal and the second input terminal. . According to claim 6,
The SAR controller,
Wherein the correction code is determined using a terminating capacitor included in a capacitor array connected to an input terminal determined to have a lower voltage among the first input terminal and the second input terminal. A method of operating a successive approximation register analog-to-digital converter including at least one capacitor and including at least one upper array and a terminating capacitor respectively corresponding to at least one upper bit of a digital code,
determining a digital code corresponding to an analog signal;
determining a correction code by changing a voltage applied to the terminating capacitor or a bottom plate of an upper array corresponding to a target bit; and
Comprising the process of correcting the digital code using the correction code,
The target bit is any one bit having a value different from the least significant bit (LSB) of the digital code among at least one upper bit of the digital code,
The process of determining the correction code,
and controlling a charge pump connected to a lower end of the terminating capacitor when there is no upper array corresponding to the target bit.

Images