KR102550886B1 - System on chip and operating method thereof - Google Patents

Abstract

A system on a chip according to an embodiment of the present invention stores debugging information in response to an information extraction command received in a deadlock state, and includes a plurality of processors, at least some of which have architectures different from each other, and the plurality of processors. A system on chip (SoC) that generates the information extraction command differently for at least some of the plurality of processors according to a system bus connected to the ) includes the manager.

Description

System on chip and its operating method {SYSTEM ON CHIP AND OPERATING METHOD THEREOF}

The present invention relates to a system on a chip and a method of operating the same.

In recent years, the application fields of system-on-a-chip are gradually widening. A system-on-chip implements a complex system with various functions in a single chip, and one or more processors may be included in one system-on-chip. A plurality of processors included in the system-on-chip may operate by exchanging necessary data with each other, and in this process, an unintended deadlock may occur. When a deadlock occurs, a function of obtaining debugging information necessary for debugging from processors included in the system-on-chip may be implemented in the system-on-chip so that a developer or a user can determine the cause of the deadlock.

One of the problems to be achieved by the technical idea of the present invention is to generate debugging information in consideration of the architecture of each of the plurality of processors when a deadlock occurs in a system-on-a-chip equipped with a plurality of processors designed according to different architectures. It is to provide a system-on-a-chip capable of extracting and/or storing and a method of operating the same.

A system-on-a-chip according to an embodiment of the present invention stores debugging information in response to an information extraction command when entering a deadlock state, and includes a plurality of processors, at least some of which have different architectures, and the plurality of processors. a system bus connected to the .s, and when the deadlock occurs, SoC (System on SoC) differently generating the information extraction command for at least some of the plurality of processors according to the architecture of each of the plurality of processors. Chip) manager.

A system-on-a-chip according to an embodiment of the present invention includes a plurality of processors each including a first interface, a second interface, and a central processing unit, a system bus connected to the first interface, and connected to the second interface. a debugging master, and an SoC controller connected to the plurality of processors through the system bus and detecting a deadlock occurring in the plurality of processors, wherein the debugging master, when the deadlock occurs, An information extraction command generated based on the architecture of each of the plurality of processors is transmitted to the plurality of processors in response to a command of the SoC controller.

A system-on-chip according to an embodiment of the present invention includes a first processor designed according to a first architecture, a second processor designed according to a second architecture different from the first architecture, and at least one of the first and second processors. It is connected to an SoC controller that detects a deadlock that occurs in and a slave interface of each of the first and second processors, and when the deadlock occurs, through the slave interface before the first and second processors are reset. and a debugging master that secures debugging information by transmitting an information extraction command to the first and second processors, wherein each of the first and second processors performs the debugging in a different way in response to the information extraction command. save the information

According to an embodiment of the present invention, when a system-on-a-chip equipped with a plurality of processors designed according to various architectures enters a deadlock state, before the system-on-chip is rebooted, at least one of the processors based on the architecture of each of the processors Some may be controlled to store and/or output debugging information. Therefore, by performing debugging using the debugging information of the processors that caused the deadlock in the system-on-chip, the cause of the deadlock can be accurately identified and the efficiency of debugging work can be improved.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a schematic block diagram of a system on a chip according to an embodiment of the present invention.
2 and 3 are block diagrams simply illustrating a processor included in a system-on-chip according to an embodiment of the present invention.
4 and 5 are diagrams provided to explain the operation of the system on chip according to an embodiment of the present invention.
6 is a simplified block diagram of a system on a chip according to an embodiment of the present invention.
7 and 8 are diagrams provided to explain the operation of the system on chip according to an embodiment of the present invention.
9 and 10 are diagrams provided to explain the operation of the system on chip according to an embodiment of the present invention.
11 to 14 are flowcharts provided to explain the operation of the system on chip according to an embodiment of the present invention.
15 is a block diagram simply illustrating an electronic device including a system on a chip according to an embodiment of the present invention.
16 is a simplified block diagram of an autonomous vehicle including a system on a chip according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of a system on a chip according to an embodiment of the present invention.

Referring to FIG. 1 , a system on a chip 10 according to an embodiment of the present invention includes a plurality of processors 11 to 13, a graphic processing unit (GPU, 14), a digital signal processing unit (DSP, 15), A System on Chip (SoC) manager 16 and a memory controller 17 may be included as components 11 to 17 . The components 11 to 17 may operate while exchanging data through the system bus 18. The system bus 18 includes a plurality of interfaces connected to the components 11 to 17, and may include, for example, a master interface and a slave interface.

For example, the SoC manager 16 may control overall operations of the system on chip 10 and may include power management logic, clock management logic, and the like. The memory controller 18 may include logic for exchanging data and control commands with a volatile memory or non-volatile memory provided outside the system-on-chip 10 . The graphic processing unit 14 may process image data to be displayed on a display device connected to the system on chip 10 .

The system on chip 10 may be mounted on various products such as electronic devices and self-driving vehicles, and may perform calculations required to control the operation of electronic devices and autonomous vehicles. For example, a plurality of processors 11-13 included in the system-on-chip 10 may perform the above operation, and if necessary, the plurality of processors 11-13 may configure other components through the system bus 19. Data can be exchanged with elements 11-18.

When the system on chip 10 enters deadlock, the system on chip 10 provides information for analyzing the cause of the deadlock and the source code that caused the deadlock as debugging information to the developer or user. can do. In one embodiment, the plurality of components 11-17 may be designed and implemented according to different architectures, so that a process that must be executed to save debugging information in case of a deadlock occurs in the plurality of components 11-17. -17) may differ from each other.

For example, the first processor 11 may itself store state information in an internal debugging resource at predetermined intervals. Accordingly, when a deadlock occurs, debugging information for the first processor 11 can be secured only by reading and storing some of the state information stored in the debugging resource inside the first processor 11 as debugging information. On the other hand, in the case of the second processor 12 and the third processor 13, unlike the first processor 11, they may not provide a function of storing state information in debugging resources by themselves. Therefore, when the system on chip 10 enters a deadlock state, the second processor ( 12) and an operation of extracting and storing debugging information from the third processor 13 may be executed.

In one embodiment of the present invention, the SoC manager 16 may generate an information extraction command for storing debugging information and transmit the information extraction command to the second processor 12 and the third processor 13 . The SoC manager 16 may generate the information extraction command in consideration of respective architectures of the second processor 12 and the third processor 13 . In response to the information extraction command, the second processor 12 and the third processor 13 may output and/or store state information before and after the deadlock occurs as debugging information.

For example, when the second processor 12 includes a central processing unit in charge of calculation and a subcomponent capable of obtaining state information from the central processing unit, the SoC manager 16 activates the subcomponent Debugging information of the second processor 12 may be extracted and/or stored. Also, as an example, the SoC manager 16 may switch the third processor 13 to a debugging mode and may transmit an information extraction command including a predetermined instruction to the third processor 13 . In response to the command included in the information extraction command, state information of the central processing unit included in the third processor 13 may be extracted and/or stored as debugging information. For example, debugging information may be stored in a separate storage space different from that of the first to third processors 11-13. The storage space may be a storage space that is not reset despite selective rebooting of the entire system-on-chip 10 or at least some of the first to third processors 11 to 13, and may be a non-volatile memory. can be implemented

Meanwhile, a deadlock that occurs in the system on chip 10 may be accompanied by an error in the system bus 18 . Accordingly, the SoC manager 16 may transmit an information extraction command for storing debugging information to at least some of the components 11 to 17 through a separate path different from the system bus 18 . For example, the system bus 18 is logically partitioned to define a first bus and a second bus, and the second bus is inactive in a normal operation mode and can be activated and used only when a deadlock occurs. Alternatively, a debugging bus physically separated from the system bus 18 may be provided and used in a deadlock state.

2 and 3 are block diagrams simply illustrating a processor included in a system-on-chip according to an embodiment of the present invention.

Referring first to FIG. 2 , the system on chip 20 according to the embodiment shown in FIG. 2 may include a processor 21 , a system bus 25 , and an SoC manager 26 . The SoC manager 26 may include an SoC controller 27 that detects whether a deadlock occurs and a debugging master 28 that transmits an information extraction command to the processor 21 to secure debugging information when a deadlock occurs. there is.

The processor 21 may have at least one central processing unit 22 in charge of arithmetic processing. The central processing unit 22 may have a first interface 23 and a second interface 24 for exchanging data with other components of the system on chip 20 . For example, the central processing unit 22 may exchange data with the SoC controller 27 through the first interface 23 and the system bus 25, and may transmit and receive data through the second interface 24 and the system bus 25. Data can be exchanged with the debugging master 28 through this. The first interface 23 may be a master interface, and the second interface 24 may be a slave interface. That is, when the processor 21 and the debugging master 28 exchange data through the second interface 24, the processor 21 may operate as a slave device for the debugging master 28. In one embodiment, the central processing unit 22 may include two or more cores for processing a plurality of instructions and data constituting software.

In normal operation, the central processing unit 22 may exchange data with the SoC controller 27 and other components of the system-on-chip 20 through the system bus 25 . That is, the central processing unit 22 exchanges data with other components such as the SoC controller 27, GPU, DSP, internal memory, and memory controller through the first interface 23 and the system bus 25. can

When the system-on-chip 20 enters a deadlock state, most components included in the system-on-chip 20 as well as the processor 21 may stop operating and may not respond. Therefore, when the system on chip 20 enters a deadlock state, it may be difficult to determine which command is being executed and which data is being accessed. In addition, when the system on chip 20 is rebooted to resolve the deadlock, it may be difficult to determine the command, data, and/or code that caused the deadlock because all components are reset. Due to the above situation, the efficiency of debugging work to remove the cause of the deadlock may decrease.

In the present invention, the debugging master 28 may extract debugging information of the processor 21 according to a command of the SoC controller 27 that detects a deadlock. The debugging master 28 may transmit an information extraction command for securing debugging information to the central processing unit 22 through the second interface 24, which is not used in a normal operation mode. For example, the debugging master 28 may transmit an appropriate information extraction command suitable for the architecture of the processor 21 to the central processing unit 22 . The system bus 25 may have a first bus and a second bus that are logically partitioned, and the information extraction command may be delivered by a second bus that is not used in a normal operation mode.

For example, the debugging master 28 may include a command for forcibly outputting information indicating a state of the processor 21 as debugging information when a deadlock occurs, in an information extraction command, and transmit the information to the processor 21 . Debugging information output by the processor 21 according to the command may be stored in a predetermined storage space that is not reset while the system on chip 20 is rebooted by the debugging master 28 or the SoC controller 27. .

In other embodiments, a sub-component included in the processor 21 and different from the central processing unit 22 may be activated by an information extraction command transmitted by the debugging master 28 . The sub-component may extract debugging information from the central processing unit 22 or control the central processing unit 22 to store the debugging information in a specific storage space by itself. As can be seen in the above embodiments, the debugging master 28 selects an appropriate command for securing debugging information in consideration of the architecture of the processor 21, includes it in an information extraction command, and transmits it to the processor 21. can The debugging master 28 may directly generate an information extraction command, or may receive and transmit an information extraction command from the SoC controller 27 . Meanwhile, the debugging master 28 may operate in conjunction with an external debugging tool, for example, a JTAG debugging tool.

Referring next to FIG. 3 , the system on chip 30 according to an embodiment of the present invention may include a processor 31 , a system bus 36 , an SoC controller 37 , and the like. In one embodiment shown in FIG. 3 , a debugging master 36 may be implemented between the central processing unit 32 and the system bus 38 . In the embodiment shown in FIG. 3, the debugging master 36 is shown as being included inside the processor 31, but otherwise, it may be provided as a separate component between the system bus 36 and the processor 31. . When the system on chip 30 has a separate debugging bus separated from the system bus 36, the debugging master 35 may be connected between the debugging bus and the processor 31. The debugging master 35 may exchange data with the central processing unit 32 through the second interface 34 as a slave interface.

When the system-on-chip 30 according to the embodiment shown in FIG. 3 enters a deadlock state, the SoC controller 37 transmits a command to secure debugging information to the debugging master 35 through the system bus 36. can In the deadlock state, the operation of the system bus 36 may also be suspended. In the embodiment shown in FIG. 3, the system bus 36 may be partitioned into a first bus and a second bus, and the first bus may be a general In operation only, the second bus can only be used in the event of a deadlock. The SoC controller 37 may transmit a command for obtaining debugging information to the debugging master 35 through the second bus. Alternatively, as described above, the SoC controller 37 may transmit a command for securing debugging information to the debugging master 35 through a separate debugging bus logically separated from the system bus 36 .

The debugging master 35 may access the central processing unit 32 through the second interface 34 . The debugging master 35 may forcibly extract and store debugging information from the central processing unit 32 or control the central processing unit 32 to store the debugging information by itself. Debugging information may be stored in a storage space that is not reset while the system on chip 30 or the processor 31 is rebooted. For example, the debugging information may be included in a storage space inside the processor 31 or in a storage space of a component other than the processor 31 that is included in the system on chip 30 .

4 and 5 are diagrams provided to explain the operation of the system on chip according to an embodiment of the present invention.

4 and 5, a system on chip 100 according to an embodiment of the present invention includes a plurality of processors 110-130, a graphics processing unit 140, a digital signal processing unit 150, and an SoC. The manager 160, the memory controller 170, the system bus 180, and the like may be included as components. The SoC manager 160 may include a SoC controller 161 and a debugging master 162 .

Components included in the system on a chip 100 may be added or changed in various ways according to functions to be implemented or provided by the system on a chip 100 . For example, in addition to the components shown in FIGS. 4 and 5, logic in charge of video/audio codec processing and logic for processing information collected by various sensors connected to the system-on-chip 100 are further included. can

As shown in FIGS. 4 and 5 , the plurality of processors 110 - 130 may have different architectures. For example, the first processor 110 may include a first central processing unit 111 and a debugging resource 112, and state information of the first central processing unit 111 is changed to the debugging resource 112 at predetermined intervals. ) can be stored in When the system-on-chip 100 enters a deadlock state, the debugging master 162 accesses the debugging resource 112 of the first processor 110 and among the state information stored in the debugging resource 112, the deadlock occurs. Debugging information of the first processor 110 may be secured by marking or reading state information stored near the time of occurrence as debugging information.

Unlike the first processor 110, the second processor 120 and the third processor 130 may not provide a function of automatically saving state information that can be utilized as debugging information. Accordingly, when the system-on-chip 100 enters a deadlock state, the debugging master 162 responds to a command from the SoC controller 161 and receives debugging information from the second processor 120 and the third processor 130, respectively. can be obtained.

First, referring to FIG. 4 , when the system on chip 100 enters a deadlock state, the plurality of processors 110-130, the graphic processing unit 140, the digital signal processing unit 150, and the memory controller 170 etc. may be interrupted. In a deadlock state, the system bus 180 may also not operate normally.

A deadlock may be detected by the SoC controller 161 . For example, at least one of the plurality of processors 110 to 130, the graphic processing unit 140, the digital signal processing unit 150, and the memory controller 170 may include a counter circuit therein, and the SoC controller ( 161) may receive a signal from the counter circuit at regular intervals. Accordingly, if a signal is not received from the counter circuit even though the period has elapsed, the SoC controller 161 may determine that the system on chip 100 has entered a deadlock state. Alternatively, it may be determined that the system on chip 100 enters a deadlock state when a predefined specific situation occurs regardless of whether a signal from the counter circuit is received or when an interrupt indicating the occurrence of a malfunction is detected.

When it is determined that the system on chip 100 has entered a deadlock state, the debugging master 162 sends an information extraction command for securing debugging information to the system on chip 100 in response to a command from the SoC controller 161. It can be passed to at least one of the components. In the embodiment shown in FIG. 5, it is assumed that the debugging master 162 transmits an information extraction command to the plurality of processors 110-130, but the graphic processing unit 140, the digital signal processing unit 150, An information extraction command for securing debugging information may also be transmitted to the memory controller 170 and the like.

The information extraction command may include various commands determined according to the architecture of the plurality of processors 110 to 130 . For example, by an information extraction command input to the first processor 110, at least some of the state information stored in the debugging resource 112 may be selected as debugging information of the first processor 110 and stored separately. . In addition, the sub-component 122 is activated by an information extraction command input to the second processor 120 to extract and store debugging information from the second central processing unit 121 . In another embodiment, the second processor 120 may be controlled to forcibly output debugging information by an information extraction command input by the debugging master 160 . Debugging information forcibly output by the second processor 120 may be stored by the debugging master 160 in a predetermined storage space inside the system on chip 100 . As described above, the debugging master 160 may store debugging information in a storage space that is not reset by rebooting the system on chip 100 .

Meanwhile, the third central processing unit 131 of the third processor 130 extracts debugging information by executing a predetermined instruction included in the information extraction command received from the debugging master 160 and stores the debugging information in an internal register. can be saved Debugging information may be stored in a storage space that is not reset by rebooting the system on chip 100 . For example, the storage space for storing debugging information may be a storage space existing outside the third central processing unit 131 .

In summary, each of the plurality of processors 110 to 130 may have a different architecture, and a method for extracting and storing debugging information when the system on chip 100 enters a deadlock state also includes a plurality of processors ( 110-130) may be applied differently. In one embodiment of the present invention, the SoC controller 161 and/or the debugging master 162 recognizes the architecture of each of the plurality of processors 110-130 and appropriately appropriate for each of the plurality of processors 110-130. You can choose how to extract and save debugging information. The SoC controller 161 and/or the debugging master 162 may transmit, to the plurality of processors 110 to 130, an information extraction command generated by referring to a method of extracting and storing debugging information selected based on an architecture. Therefore, each of the plurality of processors 110 to 130 may store the debugging information using an optimized method, and after the system on chip 100 is rebooted, a developer or user may use the debugging information to cause a deadlock. Causes can be efficiently analyzed.

6 is a schematic block diagram of a system on a chip according to an embodiment of the present invention.

Referring to FIG. 6 , a system on chip 200 according to an embodiment of the present invention includes a plurality of processors 210-230, a graphic processing unit 240, a digital signal processing unit 250, and an SoC manager 260. ), and a memory controller 270 as components 210 to 270 . Components 210 to 270 may operate while communicating with each other through the system bus 280 . The SoC manager 260 may include a SoC controller 261 and a debugging master 262 .

In the embodiment shown in FIG. 6 , a debugging bus 290 may be further included in the system-on-chip 200 in addition to the system bus 280 . The debugging bus 290 may be a bus physically separated from the system bus 290 and may remain inactive in a normal operation mode. In one embodiment, the debugging bus 290 may be activated by the SoC manager 260 when the system on chip 200 enters a deadlock state. Hereinafter, the operation of the system on chip 200 will be described in more detail with reference to FIGS. 7 and 8 .

7 and 8 are diagrams provided to explain the operation of the system on chip according to an embodiment of the present invention.

Referring to FIGS. 7 and 8 , the plurality of processors 210 to 230 may have different architectures. For example, the first processor 210 may include a first CPU 211 and a debugging resource 212, and the first CPU 211 provides state information at regular intervals and/or when a deadlock occurs. Debugging information may be stored in the debugging resource 212 . Therefore, when the system on chip 200 enters a deadlock state, the debugging information of the first processor 210 is extracted from the debugging resource 212 and stored in a predetermined storage space before the system on chip 200 is rebooted. It can be. When rebooting of the system on chip 200 is completed, debugging information stored in the storage space may be provided to a user or developer. That is, the first processor 210 can secure debugging information only by selecting and separately storing some of the state information stored in the debugging resource 212 .

Unlike the first processor 210, the second processor 220 and the third processor 230 may not provide a function of automatically storing debugging information necessary for debugging. Therefore, when the system on chip 200 enters a deadlock state, the debugging master 262 responds to a command from the SoC controller 261 or the debugging master 262 determines by itself, and the second processor 220 and Debugging information may be secured from each of the third processors 230 .

Referring first to FIG. 7 , when the system on chip 100 enters a deadlock state, the plurality of processors 210-230 as well as the graphic processing unit 240, the digital signal processing unit 250, and the memory controller ( 270) may be interrupted. In a deadlock condition, system bus 280 may also cease operation.

The SoC controller 261 may generate and transmit an information extraction command for securing debugging information to the debugging master 262 . Alternatively, in another embodiment, the SoC controller 261 may transmit only a command for securing debugging information to the debugging master 262, and the debugging master 262 may generate an information extraction command. That is, in an embodiment of the present invention, an information extraction command may be generated by at least one of the SoC controller 261 and the debugging master 262 .

The debugging master 262 may input an information extraction command to the plurality of processors 210 to 230 through the debugging bus 290 . Debugging bus 290 may become active after system on chip 200 enters a deadlock state. Meanwhile, unlike the embodiment shown in FIGS. 7 and 8 , the information extraction command may be input to other elements such as the graphic processing unit 240, the digital signal processing unit 250, and the memory controller 270. can The type and number of elements to which the information extraction command is to be input may be determined by the SoC controller 261 .

The plurality of processors 210 to 230 have different architectures, and therefore, information extraction commands input to each of the plurality of processors 210 to 230 may include different instructions. For example, the information extraction command input to the first processor 210 may include a command for selecting debugging information from state information stored in the debugging resource 212 and recording the selected debugging information in a separate storage space. there is.

Unlike the first processor 210 , the second processor 220 may not include a debugging resource 212 . The information extraction command input to the second processor 220 includes a command forcing the second central processing unit 221 to output debugging information, or activates the sub-component 222 to activate the second central processing unit 222. It may include a command for controlling extraction of debugging information from 221. The information extraction command input to the third processor 230 is processed by the third central processing unit 231 to include instructions for controlling the third central processing unit 231 to record debugging information in a predetermined storage space. can That is, as exemplified above, in the present invention, different information extraction commands having instructions determined by the architecture of each of the plurality of processors 210-230 may be input to the plurality of processors 210-230. there is.

9 and 10 are diagrams provided to explain the operation of the system on chip according to an embodiment of the present invention.

Referring first to FIG. 9 , in the system on chip 300 according to the embodiment shown in FIG. 9 , each of the plurality of processors 310 to 330 may include a debugging master 313 , 323 , and 333 . When the system on chip 300 enters a deadlock state, the SoC controller 360 may input an information extraction command to each of the plurality of processors 310 to 330 . The information extraction command may include instructions for storing and/or extracting debugging information corresponding to state information when the processors 310 to 330 enter a deadlock state. Since the system bus 380 may not normally operate in a deadlock state, the system on chip 300 may divide the system bus 380 into partitions and allocate a part of the system bus 380 as a dedicated debug bus that operates only in a deadlock state.

When the debugging master 313 of the first processor 310 receives an information extraction command, the debugging master 313 periodically and/or when the first processor 310 enters a deadlock state, the debugging resource 312 State information stored in can be marked as debugging information. The debugging master 313 may store the marked debugging information in a storage space that is not reset along with rebooting of the system on chip 300 . The debugging master 323 of the second processor 320 may activate the subcomponent 322 in response to the information extraction command. The activated subcomponent 322 may receive and store debugging information from the second central processing unit 321 . Alternatively, the debugging master 323 may force the second central processing unit 321 to output debugging information by directly accessing the second central processing unit 321 in response to the information extraction command. When receiving an information extraction command, the debugging master 333 of the third processor 330 may transmit a command for controlling the third central processing unit 331 to extract debugging information to the third central processing unit 331. . Debugging information extracted through the above processes is stored in a storage space that is not reset by rebooting the system-on-chip 300, and can be used for debugging after the system-on-chip 300 is rebooted.

An operation of the system on a chip 400 according to an embodiment shown in FIG. 10 may be similar to an operation of the system on a chip 300 according to an embodiment shown in FIG. 9 . However, in the embodiment shown in FIG. 10 , the debugging bus 490 may be provided as a separate bus physically separated from the system bus 480 . The debugging bus 490 may not be activated in normal operation, and may be activated only when an activation command is transmitted by the SoC controller 460, such as when the system on chip 400 enters a deadlock state. When the system-on-chip 400 enters a deadlock state, the SoC controller 460 sends information to the debugging masters 413, 423, and 433 included in each of the plurality of processors 410-430 through the debugging bus 490. You can enter an extraction command. The debugging masters 413 , 423 , and 433 may obtain debugging information from each of the first to third central processing units 311 , 321 , and 331 by using a command included in the information extraction command.

11 to 14 are flowcharts provided to explain the operation of the system on chip according to an embodiment of the present invention.

Referring first to FIG. 11 , an operation of the system on a chip according to an embodiment of the present invention may start by detecting a deadlock (S10). A deadlock can be detected by a SoC controller or the like included in a system-on-a-chip. For example, a plurality of components included in the system-on-chip may include a counter circuit therein, and the counter circuit may transmit a signal to the SoC controller at predetermined intervals. When the SoC controller does not receive a signal from the counter circuit even though the period has elapsed, it may be determined that a deadlock has occurred. In addition, even when each of the components included in the system-on-chip detects an abnormal operation and generates an interrupt, it may be recognized that a deadlock has occurred.

When deadlock is detected, the SoC controller may transmit a command suitable for each architecture of a plurality of processors (S20). In one embodiment, the command may be an information extraction command including instructions for extracting debugging information indicating a state of each of a plurality of processors when a system-on-chip enters a deadlock state. According to embodiments, the information extraction command may be transmitted to processors through the SoC controller and the debugging master, and the information extraction command may also be transmitted to components other than the processors.

Processors receiving the information extraction command may store and/or output debugging information in response thereto (S30). As described above, a method of storing and/or outputting debugging information by each of the processors may be determined according to the architecture of each of the processors. For example, in the case of a processor including subcomponents, the subcomponents may be activated in response to an information extraction command. The activated subcomponent may extract debugging information from the CPU included in the processor and store it in a predetermined storage space. In the case of a processor not including a subcomponent, the CPU may execute a command included in the information extraction command to store debugging information in a storage space by itself. The storage space may be an area that is not reset even when the system on chip is rebooted.

When the debugging information is stored in the area by the debugging master, the system on chip may be rebooted (S40). However, according to embodiments, only some components that have entered deadlock may be rebooted. When a system on a chip includes a plurality of processors and groups and manages the plurality of processors, rebooting may be performed in units of groups.

When the rebooting is completed, the system-on-chip provides the debugging information stored in step S30 to the developer or user, and the developer or user can proceed with debugging using the debugging information (S50). Accordingly, since it is possible to quickly identify an instruction causing system-on-chip deadlock, it is possible to improve debugging work efficiency of a developer or user.

FIG. 12 may be a flowchart for explaining in detail an embodiment in which step S30 of FIG. 11 is executed in a processor having a first architecture. The processor receiving the information extraction command may access debugging resources (S31). The debugging resource may be a space in which a central processing unit or a core included in a processor records state information at a predetermined period or when a deadlock occurs. Upon receiving the information extraction command, the processor may search state information stored in the debugging resource when a deadlock occurs (S32). For example, state information around the deadlock occurrence point may be retrieved in step S32.

The processor may store the retrieved state information as debugging information (S33). As described above, debugging information may be recorded in a storage space that is not reset regardless of system-on-chip rebooting.

FIG. 13 may be a flowchart for explaining in detail an embodiment in which step S30 of FIG. 11 is executed in a processor having a second architecture. The second architecture may be different from the first architecture described above with reference to FIG. 12 .

In the embodiment shown in FIG. 12, a subcomponent included in the processor may be activated by an information extraction command (S34). The subcomponent activated in step S34 may be a logic that extracts specific information by accessing a central processing unit (CPU) or core of a processor that has entered a deadlock state. That is, the activated subcomponent may extract and store debugging information from the central processing unit (CPU) (S35). Debugging information can be written to a storage space that is not reset regardless of system-on-chip rebooting.

FIG. 14 may be a flowchart for explaining in detail an embodiment in which step S30 of FIG. 11 is executed in a processor having a third architecture. The third architecture may be different from the first architecture and the second architecture previously described with reference to FIGS. 11 and 12 .

In the embodiment shown in FIG. 14, a predetermined command included in the information extraction command may be executed (S36). For example, the command may be executed from an information extraction command by a debugging master or processor. When the command is executed, debugging information may be extracted from the central processing unit or core of the processor and stored in an internal register of the processor (S37). At the same time, the debugging information may be recorded in a storage space outside the processor (S38). As described with reference to FIGS. 12 and 13 , debugging information may be recorded in a storage space that is not reset by system-on-chip rebooting.

The embodiments described with reference to FIGS. 1 to 14 can be applied not only when the system on chip enters a deadlock state, but also when a developer or user needs debugging information for development and/or maintenance. . That is, even if the system-on-chip does not enter a deadlock state, if a developer or a user who needs debugging information controls the SoC controller to output an information extraction command, components including a plurality of processors may issue an information extraction command. You can receive input and save debugging information. A developer or a user may use the stored debugging information to perform a debugging operation regardless of whether or not a deadlock is entered.

15 is a block diagram simply illustrating an electronic device including a system on a chip according to an embodiment of the present invention.

A computer device 1000 according to the embodiment shown in FIG. 15 may include an image sensor 1010, a display 1020, a memory 1030, a system on chip 1040, and a port 1050. In addition, the computer device 1000 may further include a wired/wireless communication device, a power supply, and the like. Among the components shown in FIG. 15 , the port 1050 may be a device provided for the computer device 1000 to communicate with a video card, a sound card, a memory card, a USB device, and the like. The computer device 1000 may be a concept encompassing all of a smart phone, a tablet PC, a smart wearable device, and the like, in addition to a general desktop computer or laptop computer.

The system-on-a-chip 1040 may perform specific operations, commands, and tasks. System-on-a-chip 1040 may communicate with image sensor 1010 , display 1020 , memory device 1030 , as well as other devices connected to port 1050 via bus 1060 . The system-on-chip 1040 may include a plurality of processors designed according to different architectures, and may secure debugging information according to various embodiments described with reference to FIGS. 1 to 14 when entering a deadlock state. there is.

The memory 1030 may be a storage medium that stores data necessary for the operation of the computer device 1000 or multimedia data. The memory 1030 may include volatile memory such as random access memory (RAM) or non-volatile memory such as flash memory. Also, the memory 1030 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. The input/output device 1020 may include an input device provided to a user, such as a keyboard, a mouse, and a touch screen, and an output device such as a display and an audio output unit.

The image sensor 1010 may be mounted on a package substrate and connected to the processor 1040 through a bus 1060 or other communication means. The image sensor 1010 may be employed in the computer device 1000 in a form according to various embodiments described with reference to FIGS. 1 to 14 .

16 is a simplified block diagram of an autonomous vehicle including a system on a chip according to an embodiment of the present invention.

Referring to FIG. 16 , an autonomous vehicle 1100 includes a system on chip 1110, a vision sensor 1120, a body control module 1130, a memory 1140, and a communication module 1150. can include The system-on-chip 1110 may include a plurality of processors designed according to different architectures, and may secure debugging information according to various embodiments described with reference to FIGS. 1 to 14 when entering a deadlock state. there is.

The system on chip 1110 may provide an autonomous driving function of the autonomous vehicle 1100 by controlling the vision sensor 1120, the body control module 1130, the memory 1140, and the communication module 1150. For example, the system on chip 1110 determines the driving environment by using visual information around the vehicle collected by the vision sensor 1120 and traffic information received through the communication module 1150, and based on the driving environment The vehicle body control module 1130 may be controlled together with the driving system of the vehicle.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

10, 20, 30, 100, 200, 300, 400: System on a Chip
11, 12, 13, 21, 31, 110, 120, 130, 210, 220, 230, 310, 320, 330, 410, 420, 430: Processor
16, 26, 160, 260: SoC manager
27, 37, 161, 261, 360, 460: SoC controller
28, 35, 162, 262, 313, 323, 333, 413, 423, 433: Debugging Master

Claims (10)

A plurality of processors that store debugging information in response to an information extraction command received in a deadlock state, and at least some of the processors have different architectures;
a system bus connected to the plurality of processors; and
a System on Chip (SoC) manager configured to differently generate the information extraction command for at least some of the plurality of processors according to the architecture of each of the plurality of processors when the deadlock occurs; Including,
When the deadlock occurs, the SoC manager operates as a master device for each of the plurality of processors, and executes the information extraction command through an interface connected to the SoC manager and operating as a slave interface in each of the plurality of processors. A system on a chip that transmits to the plurality of processors.
According to claim 1,
wherein the SoC manager resets the plurality of processors and the system bus when each of the plurality of processors stores the debugging information in response to the information extraction command.
According to claim 1,
a debugging bus physically separated from the system bus or logically separated from each other by partitioning; A system on a chip further comprising a.
According to claim 3,
wherein the SoC manager transmits the information extraction command to each of the plurality of processors through the debugging bus when the deadlock is detected.
According to claim 1,
The SoC manager includes a SoC controller that detects the deadlock state, and a debugging master that transmits the information extraction command to the plurality of processors.
According to claim 1,
Each of the plurality of processors includes a debugging master configured to store the debugging information in response to the information extraction command.
a plurality of processors each including a first interface, a second interface, and a central processing unit;
a system bus connected to the first interface;
a debugging master connected to the second interface; and
an SoC controller connected to the plurality of processors through the system bus and detecting a deadlock state occurring in the plurality of processors; including,
The debugging master transmits an information extraction command generated based on the architecture of each of the plurality of processors to the plurality of processors in response to a command of the SoC controller when the deadlock occurs,
The second interface operates as a slave interface for the debugging master.
delete a first processor designed according to the first architecture;
a second processor designed according to a second architecture different from the first architecture;
an SoC controller detecting a deadlock state occurring in at least one of the first and second processors; and
It is connected to a slave interface of each of the first and second processors, and when the deadlock occurs, an information extraction command to the first and second processors through the slave interface before the first and second processors are reset. Debugging master to obtain debugging information by sending; Including,
Each of the first and second processors stores the debugging information in different ways in response to the information extraction command.
A method of operating a system on a chip including a plurality of processors having different architectures,
deadlock detection;
generating an information extraction command based on an architecture of each of the plurality of processors;
transmitting the information extraction command to each of the plurality of processors through an interface operating as a slave interface in each of the plurality of processors;
storing debugging information output by each of the plurality of processors in a storage space that is not reset by rebooting in response to the information extraction command; and
rebooting the system on chip; A method of operating a system-on-a-chip comprising a.

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