KR102550422B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device may include a first clock generator including a first control circuit and a first clock gating circuit, a first channel manager communicating with the first clock generator according to a full handshake method, and a second clock generator. a second clock generation unit including a control circuit and a second clock gating circuit; and a second channel management unit communicating with the second clock generation unit according to a full handshake method, wherein the first clock gating circuit comprises a first clock, and the second clock gating circuit outputs a second clock different from the first clock.

Description

Semiconductor device

The present invention relates to a semiconductor device including a semiconductor circuit.

With the convergence of computers, telecommunications, and broadcasting, the demand for existing ASIC (Application Specific IC) and ASSP (Application Specific Standard Product) is being converted into SoC demand. there is a trend In addition, the trend of light, thin, small-sized and highly functional IT (Information Technology) devices is one of the factors promoting SoC.

Such an SoC is a form in which existing functional blocks having various functions, for example, IP (Intellectural Property), are intensively implemented on a single chip thanks to the development of semiconductor process technology.

As the degree of integration and size of SoCs increase and the operating speed increases, the issue of low power consumption also becomes one of the very important factors. This is because, when the power consumption is severe, the temperature of the chip rises, resulting in inoperability as well as damage to the package.

In a semiconductor circuit in an SoC, there are cases where a circuit providing or blocking a clock is required for purposes such as power reduction. A clock gating circuit is used to not supply a clock to a specific circuit when the operation of the circuit is not required.

An object to be solved by the present invention is to provide a semiconductor device capable of applying various clock consumers by defining a connection relationship between a channel management unit and IP (Intellectual Property) in a semiconductor circuit within an SoC. .

The problem to be solved by the present invention is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above object, a semiconductor device according to some embodiments of the present disclosure includes a first clock generator including a first control circuit and a first clock gating circuit, and a full handshake with the first clock generator. ) method, a second clock generator including a second control circuit and a second clock gating circuit, and a second channel manager that communicates with the second clock generator according to a full handshake method. wherein the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.

In order to solve the above object, a semiconductor device according to some embodiments of the present disclosure includes a first clock generator including a first control circuit and a first clock gating circuit, and a full handshake with the first clock generator. ) method, and a second clock generator including a second control circuit and a second clock gating circuit, wherein the second clock generator communicates with the first channel manager in a full handshake method. , the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.

In order to solve the above object, a semiconductor device according to some embodiments of the present disclosure includes a first clock generator including a first control circuit and a first clock gating circuit, and a full handshake with the first clock generator. ) method, and a second channel management unit communicating with the first clock generator according to a full handshake method, wherein the first channel manager transmits a first clock signal to the first clock generator. A request signal is transmitted, and the second channel manager transmits a second clock request signal to the first clock generator.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
2 is a block diagram illustrating a clock management unit included in a semiconductor device according to some embodiments of the inventive concept.
3 is a block diagram illustrating IP included in a semiconductor device according to some embodiments of the present invention.
4 illustrates a signal transmission path between a plurality of control circuits.
5A is a diagram for explaining a clock request signal and a clock response signal used in the present invention.
5B illustrates clock level transitions of a clock request signal and a clock response signal used in the present invention.
6 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
7 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
8 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
FIG. 9A is a block diagram illustrating a semiconductor device according to some example embodiments, and FIG. 9B is a timing diagram illustrating an operation of the semiconductor device of FIG. 9A.
FIG. 10A is a block diagram illustrating a semiconductor device according to some example embodiments, and FIG. 10B is a timing diagram illustrating an operation of the semiconductor device of FIG. 10A.
11 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
12 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
13 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
14 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.
15 is a block diagram illustrating an example of a semiconductor system including a semiconductor device according to some example embodiments of inventive concepts.
16 is a block diagram illustrating another embodiment of a semiconductor system including a semiconductor device according to some embodiments of the inventive concept.

1 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 1 , a semiconductor device according to some embodiments of the present invention includes an input/output pad 101, a clock management unit (CMU) 100, and a power management unit (PMU) 300. ) and logic blocks. For example, a logic block may be implemented as at least one IP block (intellectual property) 200 , 210 , and 220 .

The clock management unit 100 may generate an operation clock signal to be provided to each of the first to third IP blocks 200, 210, and 220. For example, the clock management unit 100 may generate first to third clock signals CLK1 , CLK2 , and CLK3 .

Each of the first to third IP blocks 200, 210, and 220 are connected to a system bus and may communicate with each other through the system bus. In some embodiments of the present invention, each of the first to third IP blocks 200, 210, and 220 is a processor, a graphic processor, a memory controller, an input and output interface block (input and output interface block), etc.

The clock management unit 100 may provide the first clock signal CLK1 to the first IP block 200 . The clock management unit 100 may provide the second clock signal CLK2 to the second IP block 210 . The clock management unit 100 may provide the third clock signal CLK3 to the third IP block 220 .

Any one of the first to third IP blocks 200, 210, and 220 may transmit a clock request signal to the clock management unit 100 according to a full handshake method.

For example, the first IP block 200 may transmit the first clock request signal REQ1 to the clock management unit 100 according to the full handshake method. The clock management unit 100 may receive the first clock request signal REQ1 and transmit the first clock response signal ACK1 to the first IP block 200 . Also, at the same time, the clock management unit 100 may transmit the first clock signal CLK1 to the first IP block 200 .

In some embodiments of the present invention, an interface between the clock management unit 100 and the first to third IP blocks 200, 210, and 220 may have a full handshake method. In some embodiments of the present invention, the interface may be implemented to comply with ARM's Q-Channel Interface or P-Channel Interface, but the scope of the present invention is limited thereto. it is not going to be

Clock gating is a function that divides the inside of a computer system into small functional blocks and cuts power to unused parts. Since not all parts of the computer system always operate while using a real computer, it is possible to reduce power consumption by stopping unused blocks, and also reduce heat generated from disabled blocks.

The clock management unit 100 according to some embodiments of the present invention sequentially performs clock gating from the rear end on IP blocks that do not require operating clocks among the first to third IP blocks 200, 210, and 220, , it is possible to reduce power consumption by automatically performing clock gating without causing errors in IP block operation.

The power management unit 300 controls power supplied to the semiconductor device 100 . For example, when the semiconductor device 100 enters a standby mode, the power management unit 300 turns off a power control circuit to cut off power supplied to the semiconductor device 100 . At this time, the power management unit 300 continuously consumes power, but since the power consumed by the power management unit 300 corresponds to a very small portion of the power consumed by the entire semiconductor device 100, in the standby mode Power consumption of the semiconductor device 100 is greatly reduced.

In detail, the power management unit 300 may cut off power supplied to the clock management unit 100 when the semiconductor device 100 is in a standby mode. This may correspond to a case where there is no clock request from the first to third IP blocks 200, 210, and 220.

2 is a block diagram illustrating a clock management unit included in a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 2, the clock management unit 100 includes clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g, and channel management circuits (CM) 130 and 132. and a clock management unit controller (CMU Controller) 110. The clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g generate clock signals to be provided to the IP blocks 200 and 210, and the channel management circuits 130 and 132 use the clock components 120f and 120g and the IP blocks 200 and 210 to provide a communication channel (Channel, CH) between the clock management unit 100 and the IP blocks 200 and 210. The clock management unit controller 110 provides clock signals to the IP blocks 200 and 210 using the clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g.

In some embodiments of the present invention, the communication channel (CH) provided by the channel management circuits 130 and 132 is an ARM low power interface (LPI), Q-channel interface, or P-channel interface. (P-Channel Interface), but the scope of the present invention is not limited thereto, and may be implemented as a communication channel (CH) conforming to an arbitrary communication protocol determined according to the purpose of implementation.

The clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g are clock sources (Clock Source, CS) 124a, 124b, 124c, 124d, 124e, 124f, and 124g, respectively, and clock sources 124a and 124b. and clock control circuits (CC) 122a, 122b, 122c, 122d, 122e, 122f, and 122g respectively controlling the , 124c, 124d, 124e, 124f, and 124g. The clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g may include, for example, a MUX circuit, a clock dividing circuit, a short stop circuit, and a clock gating circuit ( clock gating circuit) and the like.

Clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g form a parent-child relationship with each other. In this embodiment, clock component 120a is a parent of clock component 120b, and clock component 120b is a child of clock component 120a and a parent of clock component 120c. Also, clock component 120e is a parent of two clock components 120f and 120g, and clock components 120f and 120g are children of clock component 120e. Meanwhile, in this embodiment, the clock component 120a arranged closest to the PLL (Phase Locked Loop) is a root clock component, and the clock components 120f, arranged closest to the IP blocks 200 and 210, 120g) is a leaf clock component. This parent-child relationship is inevitably dependent on the parent-child relationship between the clock components 120a, 120b, 120c, 120d, 120e, 120f, and 120g. ), and between the clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g.

The clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g transmit and receive clock requests (REQs) and acknowledgments (ACKs) therefor between parents and children, and are connected to the IP blocks 200 and 210. Provides a clock signal.

For example, when the IP block 200 does not require a clock signal, for example, when the IP block 200 needs to be in a sleep state, the clock management unit 100 controls the IP block 200 ) to stop providing the clock signal.

Specifically, the channel management circuit 130 transmits a first signal to stop providing the clock signal to the IP block 200 under the control of the clock management unit 100 or the clock management unit controller 110 . Upon receiving the first signal, the IP block 200 transmits to the channel management circuit 130 a second signal indicating that the clock signal may be stopped after completing the task being processed. After receiving the second signal from the IP block 200, the channel management circuit 130 requests the clock component 120f corresponding to its parent to stop providing the clock signal.

For example, if the communication channel (CH) provided by the channel management circuit 130 follows the Q-channel interface, the channel management circuit 130 sends a first logic value (eg, logic low) to the IP block 200. A QREQn signal having (logic low, hereinafter denoted as L) is transmitted as a first signal. Then, the channel management circuit 130 receives a QACCEPTn signal having, for example, a first logic value from the IP block 200 as a second signal, and then sends a clock request (eg, a clock request having a first logic value) to the clock component 120f. REQ) is transmitted. In this case, the clock request REQ having the first logical value refers to a "request to stop providing a clock".

The clock control circuit 122f that receives the clock request REQ having the first logic value from the channel management circuit 130, that is, the clock provision stop request, disables the clock source 124f (eg, the clock gating circuit) ( disable) to stop providing the clock signal, and accordingly, the IP block 200 can enter the sleep mode. During this process, the clock control circuit 122f may provide an ACK having a first logic value to the channel management circuit 130 . It should be noted that the clock supply from the clock source 124f is stopped because the channel management circuit 130 receives an ACK having the first logic value after transmitting a request to stop providing the clock having the first logic value. It is not guaranteed. However, the ACK indicates that the clock control circuit 122f recognizes that the clock component 120f, which is the parent of the channel management circuit 130, no longer needs to provide clocks to the channel management circuit 130. It only has meaning.

Meanwhile, the clock control circuit 122f of the clock component 120f transmits a clock request REQ having a first logic value to the clock control circuit 122e of the clock component 120e corresponding to its parent. If the IP block 210 also does not require a clock signal, for example, if the clock control circuit 122e receives a request to stop providing a clock from the clock control circuit 122g, the clock control circuit 122e is the clock source. 124e (e.g. clock divider circuit) is disabled to stop providing the clock signal. Accordingly, the IP blocks 200 and 210 can enter the sleep mode.

Such an operation may be similarly performed for other clock control circuits 122a, 122b, 122c, and 122d.

Unlike this, although the clock control circuit 122f of the clock component 120f transmits the clock request REQ having the first logic value to the clock control circuit 122e of the clock component 120e corresponding to its parent, When the IP block 210 is in a running state, the clock control circuit 122e cannot disable the clock source 124e. After that, only when the IP block 210 no longer needs the clock signal, the clock control circuit 122e disables the clock source 124e and provides the clock control circuit 120d corresponding to its parent. A clock request (REQ) having a logic value of 1 may be transmitted. That is, the clock control circuit 122e may disable the clock source 124e only when a request to stop providing clocks is received from all of the clock control circuits 122f and 122g corresponding to their children.

Meanwhile, when the IP blocks 200 and 210 are in the sleep state and the clock sources 124a, 124b, 124c, 124d, 124e, and 124f are all disabled and then the IP block 200 enters the run state, clock management Unit 100 resumes providing clock signals to IP blocks 200 and 210.

The channel management circuit 130 requests a clock (eg, logic high) having a second logic value (eg, logic high, hereinafter denoted as H) to the clock control circuit 122f of the clock component 120f corresponding to its parent. REQ) and waits for an ACK from the clock control circuit 122f. Here, the clock request (REQ) having the second logical value refers to a "clock provision request", and an ACK to the clock provision request means that the clock provision from the clock source 124f is resumed. The clock control circuit 122f does not immediately enable the clock source 124f (eg, clock gating circuit) and waits for a clock signal to be provided from the parent.

Next, the clock control circuit 122f transmits a clock request (REQ) having a second logic value, that is, a clock provision request, to the clock control circuit 122e corresponding to its parent, and Wait for ACK. Such an operation may be performed similarly to the clock control circuits 122a, 122b, 122c, and 122d.

Upon receiving the clock request REQ having the second logic value from the clock control circuit 122b, the clock control circuit 122a, which is a root clock component, enables the clock source 124a (eg, multiplexing circuit) and acknowledges (ACK). ) to the clock control circuit 122b. In this way, when the clock sources 124b, 124c, 124d, 124d, and 124e are sequentially enabled, the clock control circuit 122e notifies the clock control circuit 122f that the supply of clocks from the clock source 124e has resumed. Send an ACK. Upon receiving the ACK, the clock control circuit 122f finally enables the clock source 124f to provide a clock signal to the IP block 200, and provides an ACK to the channel management circuit 130. .

In this way, the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g operate in a full handshake method in which a clock request (REQ) and an ACK are transmitted and received between the parent and child. do. Accordingly, the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g control the clock sources 124a, 124b, 124c, 124d, 124e, 124f, and 124g in hardware to control the IP block 200, 210) can be controlled.

These clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, 122g operate by themselves and transmit clock requests (REQ) to their parents or clock sources 124a, 124b, 124c, 124d, 124e, 124f, 124g ), and may operate under the control of the clock management unit controller 110. Meanwhile, in some embodiments of the present invention, the clock control circuits 122a, 122b, 122c, 122d, 122e, 122f, and 122g are clock sources 124a, 124b, and 122g according to clock requests REQ exchanged between parents and children. 124c, 124d, 124e, 124f, 124g) may include a finite state machine (FSM) that controls each.

3 is a block diagram illustrating IP included in a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 3 , a first IP block 200 may include a channel adapter 200 and an IP core 204 . 3 shows the first IP block 200 as an example, and includes substantially the same components for the second and third IP blocks 210 and 220 .

The channel adapter 202 may communicate with the first channel management circuit 130 according to a full handshake method. Through the channel adapter 202, the first IP block 200 can transmit the first clock request signal REQ1 and receive the first clock signal CLK1. Alternatively, the first IP block 200 may transmit a first clock request signal REQ1 through the channel adapter 202 and receive an ACK signal indicating that a clock exists, and the first clock signal CLK1 may be transmitted to the channel adapter ( 202) can be supplied directly from the clock component controlled by

The IP core 204 may include, for example, a processor, a graphic processor, a memory controller, an input and output interface block, and the like.

4 illustrates a signal transmission path between a plurality of control circuits.

Referring to FIG. 4 , the plurality of clock control circuits may operate using a handshake signal including a clock request signal REQ and a response signal ACK (or clock response signal) ACK. The clock request signal REQ and the clock response signal ACK may have, for example, a first logic value (eg, logic low) and a second logic value (eg, logic high), but the clock request signal REQ and clock A method of implementing the response signal ACK is not limited thereto.

In some embodiments of the present invention, a clock consumer transmits information that a clock is needed to a clock provider, for example, by transmitting a clock request signal (REQ) having a second logic value to a clock provider. can Alternatively, the clock consumer may transfer information that the clock is no longer needed to the clock provider by transmitting, for example, a clock request signal REQ having a first logic value to the clock provider.

Meanwhile, the clock provider may transmit, for example, a clock response signal (ACK) having a second logic value to the clock consumer, indicating that the clock signal is stably supplied from the clock provider to the clock consumer. Alternatively, the clock provider may transmit the clock response signal ACK having the first logic value to the clock consumer, indicating that the clock provider cannot inform the clock consumer of whether or not the clock signal is provided.

For example, the clock control circuit 122b transmits, for example, the clock request signal PARENT_CLK_REQ having the second logical value to the clock control circuit 122a from the viewpoint of the clock consumer, thereby corresponding to the clock control circuit corresponding to the clock provider. Information that a clock is required can be transmitted to (122a). Accordingly, the clock component (ie, the clock supplier) including the clock control circuit 122a provides a clock signal to the clock component (ie, the clock consumer) including the clock control circuit 122b, and then the clock control circuit (ie, the clock supplier) 122b) may receive, for example, a clock response signal PARENT_CLK_ACK having a second logic value from the clock control circuit 122a.

On the other hand, the clock control circuit 122b receives the clock request signal CHILD_CLK_REQ having a second logic value from the clock control circuit 122f from the viewpoint of the clock provider, so that the clock control circuit 122f corresponding to the clock consumer ) requires a clock. Accordingly, the clock component (ie, clock supplier) including the clock control circuit 122b provides a clock signal to the clock component (ie, clock consumer) including the clock control circuit 122f, and then the clock control circuit (ie, the clock supplier) 122b) may transmit a clock response signal CHILD_CLK_ACK having a second logic value to the clock control circuit 122f from the perspective of a clock provider.

For another example, the clock control circuit 122b controls the clock corresponding to the clock provider by transmitting, for example, the clock request signal PARENT_CLK_REQ having the first logic value to the clock control circuit 122a from the viewpoint of the clock consumer. Information may be conveyed to circuit 122a that the clock is no longer needed. Accordingly, the clock control circuit 122b may receive, for example, a clock response signal PARENT_CLK_ACK having a first logic value from the clock control circuit 122a, which indicates that provision of a clock from a clock provider is not guaranteed.

On the other hand, the clock control circuit 122b receives the clock request signal CHILD_CLK_REQ having a first logic value from the clock control circuit 122f, from the perspective of the clock provider, so that the clock control circuit 122f corresponding to the clock consumer ) indicates that the clock is no longer needed. Accordingly, the clock control circuit 122b may transmit, for example, a clock response signal CHILD_CLK_ACK having a second logic value to the clock control circuit 122f, indicating that provision of a clock from a clock provider is not guaranteed.

Note that, in the combinational path between the clock control circuits, the clock control circuit 122b transmits the clock request signal PARENT_CLK_REQ to the clock control circuit 122a, which is its parent, and then the clock control circuit 122b. 122b receives a clock response signal (PARENT_CLK_ACK) from its parent clock control circuit 122a, and the clock control circuit 122b receives a clock request signal (CHILD_CLK_REQ) from its child clock control circuit 122f. After reception, the clock control circuit 122b may include a pass in which the clock control circuit 122b transmits the clock response signal CHILD_CLK ACK to the clock control circuit 122f as its child, but the clock control circuit 122b is the clock control circuit 122b as its parent. After receiving the clock response signal PARENT_CLK_ACK from the circuit 122a, the clock control circuit 122b transmits the clock request signal PARENT_CLK_REQ to the parent clock control circuit 122a is not included ( shown as 'X' in Figure 4).

Such a clock request signal (REQ) and clock response signal (ACK) are implemented in a general full handshake method, and the clock provider and clock consumer may belong to the same single clock domain, They may belong to different clock domains.

In some embodiments of the present invention, a clock multiplex circuit, a clock divider circuit, a clock gating circuit, etc. connected to and communicating with each clock control circuit may use different clock domains from those of the clock control circuit. That is, the clock frequency of the signal line transmitting the clock request signal and the clock frequency of the actually provided operation clock may be different from each other.

5A is a diagram for explaining a clock request signal and a clock response signal used in the present invention, and FIG. 5B illustrates a clock level transition for a clock request signal and a clock response signal used in the present invention.

Referring to FIG. 5A , the transition of the clock request signal REQ to the second logic value at time T1 may indicate that the clock consumer transfers information that the clock signal CLK is needed to the clock provider. After the time point T1, the clock provider may provide the clock signal CLK to the clock consumer.

At time T2, the clock provider transmits the clock response signal ACK having the second logic value to the clock consumer, indicating that the clock signal CLK is being stably supplied from the clock provider to the clock consumer (I section reference).

Transition of the clock request signal REQ to the first logic value at time T3 may indicate that the clock consumer transfers information to the clock provider that the clock signal CLK is no longer needed. After the time point T3, the clock provider may stop providing the clock signal CLK to the clock consumer, or may still continue to provide the clock signal CLK.

At time T4, the clock provider transmits a clock response signal ACK having a first logic value to the clock consumer, indicating that the clock provider cannot inform the clock consumer whether or not the clock signal is provided.

That is, in FIG. 5A , only interval I guarantees that the clock signal CLK is stably supplied from the clock provider to the clock consumer, and in the remaining interval II, whether or not the clock provider provides the clock signal to the clock consumer is determined. unknown.

Referring next to FIG. 5B, FIG. 5B shows combinations of possible signals of the clock request signal REQ and the clock response signal ACK when the second logic value is expressed as 1 and the first logic value is expressed as 0. It represents a possible transition between them.

Referring to FIG. 5A together, state S0 represents states before and after time T1 and after time T4, and state S1 represents states from time T1 to time T2. And state S2 represents the state of the time point T2 to the time point T3, and state S3 represents the state of the time point T3 to the time point T4. The combination of values of the clock request signal REQ and the clock response signal ACK sequentially changes to state S0, state S1, state S2, state S3, and state S0 (solid arrow). reference).

However, if a circuit is implemented such that the clock request signal REQ transitions to the second logic value and the clock response signal ACK transitions to the second logic value at the same time at time T1, the clock request signal REQ and clock A combination of the values of the response signal ACK may directly switch from state S0 to state S2. Similarly, if a circuit is implemented such that the clock request signal REQ transitions to the first logic value and the clock response signal ACK transitions to the first logic value at the time T3, the clock request signal REQ The combination of the value of the clock response signal ACK and the value of the clock response signal ACK can be directly converted from the state S2 to the state S0 (refer to the dotted line arrow).

Referring again to FIGS. 1, 2, and 4, a full handshake method will be described.

In the full handshake method, when the first IP block 200 needs a clock, the first IP block 200 activates the first clock request signal REQ1. For example, the first IP block 200 makes the first clock request signal REQ1 a high state.

The clock management unit 100 activates the first clock response signal ACK1 to the first clock request signal REQ1 in response to activation of the first clock request signal REQ1. That is, the clock management unit 100 makes the first clock response signal ACK1 a high state.

The clock management unit 100 may transmit the first clock signal CLK1 to the first IP block 200 before the first clock response signal ACK1 is activated. Alternatively, the clock management unit 100 may transmit the first clock signal CLK1 to the first IP block 200 at the same time as the first clock response signal ACK1 is activated.

If the first IP block 200 does not require a clock, the first clock request signal REQ1 is deactivated. That is, the first IP block 200 makes the first clock request signal REQ1 into a low state.

When the first clock request signal REQ1 is in a low state, the clock management unit 100 sets the first clock response signal ACK1 to a low state. Also, the clock management unit 100 may deactivate the first clock signal CLK1 at the same time.

The first IP block 200 can operate normally while the first clock response signal ACK1 is in an active state.

Referring to FIGS. 1 and 2 , a full handshake method of the clock management unit 100 according to some embodiments of the present invention will be described. In this regard, the clock components 120a, 120b, 120c, 120d, 120e, and 120f of FIG. 2 include a PLL controller, a clock mux unit, a first clock dividing unit, a short-term pause circuit, a second clock dividing unit, and a first clock gating, respectively. Although it is assumed and described as a unit, this is only an example in which the present invention can be implemented, and the scope of the present invention is not limited thereto.

Each of the PLL controller, clock mux unit, first clock division unit, short-term pause circuit, second clock division unit, and first clock gating unit may include clock sources 124a, 124b, 124c, 124d, 124e, and 124f. .

Specifically, the PLL controller may include an oscillator (OSC) and a clock mux circuit that receives an input of a phase locked loop (PLL). The clock mux unit may include a clock mux circuit that receives a plurality of clock signals. The first clock dividing unit may include a first clock dividing circuit. The short stop circuit may include a first clock gating circuit. The second clock dividing unit may include a second clock dividing circuit. The first clock gating unit may include a second clock gating circuit.

In addition, the PLL controller may include a clock control circuit 122a. The clock mux unit may include a clock control circuit 122b. The first clock division unit may include a clock control circuit 122c. The short stop circuit 114 may include a clock control circuit 122d. The second clock division unit may include a clock control circuit 122e. The first clock gating unit may include a clock control circuit 122f.

Each of the clock control circuits 122a, 122b, 122c, 122d, 122e, and 122f may communicate according to a full handshake method. For example, each of the clock control circuits 122a and 122b may support a full handshake scheme between the PLL controller and the clock mux unit.

Each of the clock control circuits 122b and 122c may support a full handshake method between the clock mux unit and the first clock division unit.

Each of the clock control circuits 122c and 122d may support a full handshake scheme between the first clock division unit and the short-term pause circuit.

Each of the clock control circuits 122d and 122e may support a full handshake scheme between the short-term pause circuit and the second clock dividing unit.

Each of the clock control circuits 122e and 122f may support a full handshake method between the second clock dividing unit and the first clock gating unit.

Likewise, each of the clock control circuit 122f and the channel management circuit 130 may support a full handshake method between the first clock gating unit and the channel management circuit 130 .

The first IP block 200 may request an operating clock from the clock management unit 100 according to a full handshake method. For example, when an operating clock is required, the first IP block 200 may activate a clock request signal. That is, when an operation clock is required, the first IP block 200 may transmit an activated clock request signal to the clock management unit 100 .

The channel management circuit 130 receives the activated clock request signal. The channel management circuit 130 transmits the activated clock request signal to the first clock gating unit. The first clock gating unit transmits the activated clock request signal to a second clock dividing unit. The second clock division unit transmits the activated clock request signal to the short-term stop circuit. The short-term stop circuit transmits the activated clock request signal to the first clock dividing unit. The first clock division unit transmits the activated clock request signal to a clock mux unit. The clock mux unit transmits the activated clock request signal to the PLL controller.

In some embodiments of the invention, each of the PLL controller, clock mux unit, first clock dividing unit, short pause circuit, second clock dividing unit, first clock gating unit, and first channel management circuit 130 is a combinational circuit. (combinational circuit). Accordingly, the activated clock request signal may be transmitted from the first channel management circuit to the PLL controller at once.

The PLL controller activates a clock response signal in response to the activated clock request signal. That is, the PLL controller transmits a clock response signal to the activated clock request signal to the clock mux unit. At the same time, the PLL controller transmits the clock signal CLK to the clock mux unit.

The clock mux unit transmits the activated clock response signal to a first clock dividing unit. At the same time, the clock mux unit transmits the clock signal CLK to the first clock dividing unit.

The first clock dividing unit transmits the activated clock response signal to the short-term stop circuit. At the same time, the first clock dividing unit transmits the clock signal CLK to the short-term stop circuit.

The short-term stop circuit transmits the activated clock response signal to the second clock dividing unit. At the same time, the short-term stop circuit transmits the clock signal CLK to the second clock dividing unit.

The second clock dividing unit transmits the activated clock response signal to the first clock gating unit. At the same time, the second clock dividing unit transmits the clock signal CLK to the first clock gating unit.

The first clock gating unit transmits the activated clock response signal to the first channel management circuit 130 . Simultaneously, the first clock gating unit provides the clock signal CLK to the first IP block 200 .

In this embodiment, the clock response signal may be transmitted from the PLL controller to the first channel management circuit at one time.

The first IP block 200 may deactivate the clock request signal when the clock is unnecessary. That is, when the clock is unnecessary, the first IP block 200 may transmit a deactivated clock request signal to the clock management unit 100 .

Channel management circuit 130 receives the deactivated clock request signal. The channel management circuit 130 may transmit the deactivated clock request signal to a first clock gating unit. The first clock gating unit transmits the deactivated clock request signal to a second clock dividing unit. The second clock dividing unit transmits the deactivated clock request signal to the short-term stop circuit. The short-term stop circuit may transmit the deactivated clock request signal to the first clock dividing unit. The first clock division unit may transmit the deactivated clock request signal to a clock mux unit. The clock mux unit may transmit the deactivated clock request signal to the PLL controller.

Each of the PLL controller, clock mux unit, first clock division unit, short-term pause circuit, second clock division unit, first clock gating unit, and first channel management circuit 130 may be implemented as a combinational circuit. Accordingly, the deactivated clock request signal may be transmitted from the channel management circuit 130 to the PLL controller at once.

The PLL controller deactivates the clock response signal for the deactivated clock request signal. That is, the PLL controller may transmit the deactivated clock response signal to the clock mux unit. At the same time, the PLL controller may deactivate the clock signal CLK and still transmit the clock signal CLK to the clock mux unit.

The clock mux unit transmits the deactivated clock response signal to a first clock dividing unit. At the same time, the clock mux unit may inactivate the clock signal CLK and still transmit the clock signal CLK to the first clock dividing unit.

The first clock dividing unit transmits the deactivated clock response signal to the short-term stop circuit. At the same time, the first clock dividing unit may deactivate the clock signal CLK, and may still transmit the clock signal CLK to the short stop circuit.

The short-term stop circuit transmits the deactivated clock response signal to the second clock dividing unit. At the same time, the short-term stop circuit may deactivate the clock signal CLK, and may still transmit the clock signal CLK to the second clock dividing unit.

The second clock dividing unit transmits the deactivated clock response signal to the first clock gating unit. At the same time, the second clock dividing unit may inactivate the clock signal CLK and still transmit the clock signal CK to the first clock gating unit.

The first clock gating unit transmits the deactivated clock response signal to the channel management circuit 130 . At the same time, the first clock gating unit inactivates the clock signal CLK.

Similarly, the clock response signal may be transmitted from the PLL controller to the first channel management circuit 130 at once.

6 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 6 , the clock management unit 110a in the semiconductor device 1 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, and a first clock division unit ( 113), first clock gating unit 114, first channel management unit 115, second PLL controller 121, second clock mux unit 122, second clock division unit 123, second clock gating unit 124 and the like.

6 shows a case where the operation of the second IP 172 is dependent on the operation of the first IP 171, in other words, when the first IP 171 operates, the second IP ( 172) also means the case of always operating. Also, a case in which there is a possibility that the second IP 172 operates when the first IP 171 operates is included.

The first channel management unit 115 communicates with at least one of the first clock gating unit 114 and the second clock gating unit 124 according to a full handshake method. For example, when the first IP 171 transmits the clock request signal REQ to the first channel management unit 115, the first channel management unit 115 transmits it to the first clock gating unit 114. do.

The first PLL controller 111, the first clock mux unit 112, the first clock dividing unit 113, the first clock gating unit 114, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the first clock gating unit 114 and is controlled by the control circuit included in the first clock gating unit 114. is inactivated, and the first clock CLK1 is provided to the first IP 171 .

When the first IP 171 does not need the first clock CLK1, the clock request signal REQ is deactivated. Accordingly, the clock request signal REQ transmitted to the first clock gating unit 114 is deactivated. Clock gating is performed under the control of the control circuit included in the first clock gating unit 114 .

Since the operation of the second IP 172 depends on the operation of the first IP 171, the second IP 172 cannot generate a clock request signal, and the first IP 171 generates a clock request signal (REQ). ) is activated, the second clock CLK2 is also provided to the second IP 172 from the second clock gating unit 124 .

The second PLL controller 121, the second clock mux unit 122, the second clock division unit 123, the second clock gating unit 124, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the second PLL controller 121 at once.

When the clock response signal ACK is transmitted from the second PLL controller 121, it is transmitted to the second clock gating unit 124 and is controlled by the control circuit included in the second clock gating unit 124. is inactivated, and the second clock CLK2 is provided to the second IP 172 .

7 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 7 , the clock management unit 110b in the semiconductor device 2 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, and a first clock division unit ( 113), a first clock gating unit 114, a first channel management unit 115, a third clock gating unit 125, a second channel management unit 126, and the like.

The case shown in FIG. 7 shows a case in which the second channel management unit 126 is used as a dummy unit. In other words, the second channel management unit 126 does not control the clock request signal REQ by communication with the second IP 172, but clocks according to software control stored in a separate SFR (Special Function Register). It means to control the request signal (REQ).

The software stored in the SFR (Special Function Register) determines whether the second IP 172 needs a clock, and controls the clock request signal REQ under the control of separate software.

The first channel management unit 115 communicates with the first clock gating unit 114 according to a full handshake method, and the second channel management unit 126 communicates with the third clock gating unit 125 according to a full handshake method. communicate according to

For example, when the first IP 171 transmits the clock request signal REQ to the first channel management unit 115, the first channel management unit 115 transmits it to the first clock gating unit 114. do. However, as described above, the second IP 172 does not directly communicate with the second channel management unit 126 .

The first PLL controller 111, the first clock mux unit 112, the first clock dividing unit 113, the first clock gating unit 114, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the first clock gating unit 114 and is controlled by the control circuit included in the first clock gating unit 114. is inactivated, and the first clock CLK1 is provided to the first IP 171 .

In addition, the first PLL controller 111, the first clock mux unit 112, the first clock division unit 113, the third clock gating unit 125, and the second channel management unit 126 are mutually pooled. Communication is performed according to the handshake method, and the clock request signal REQ may be transmitted from the second channel management unit 126 to the first PLL controller 111 at one time.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the third clock gating unit 125 and is controlled by the control circuit included in the third clock gating unit 125. is inactivated, and the second clock CLK2 is provided to the second IP 172 .

When the first IP 171 does not need the first clock CLK1, the clock request signal REQ is deactivated. Accordingly, the clock request signal REQ transmitted to the first clock gating unit 114 is deactivated. Clock gating is performed under the control of the control circuit included in the first clock gating unit 114 .

When the second IP 172 does not require the second clock CLK2, the clock request signal REQ is deactivated and included in the third clock gating unit 125 under the control of the software included in the SFR (Special Function Register). Clock gating is performed under the control of the controlled circuit.

8 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 8 , the clock management unit 110c in the semiconductor device 3 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, and a first clock dividing unit ( 113), a first clock gating unit 114, a first channel management unit 115, a third clock gating unit 125, a third channel management unit 127, and the like.

The case shown in FIG. 8 shows a case where the operation of the first IP 171 and the operation of the second IP 172 are independent of each other. In other words, whether the first IP 171 performs the operation or not and whether the second IP 172 performs the operation are irrelevant, and each can independently perform a clock request.

The first channel management unit 115 communicates with the first clock gating unit 114 according to a full handshake method, and the third channel management unit 127 communicates with the third clock gating unit 125 according to a full handshake method. communicate according to

For example, when the first IP 171 transmits the clock request signal REQ to the first channel management unit 115, the first channel management unit 115 transmits it to the first clock gating unit 114. do. In addition, the second IP 172 may independently transmit the clock request signal REQ to the third channel management unit 127, and the third channel management unit 127 sends it to the third clock gating unit 125. send.

The first PLL controller 111, the first clock mux unit 112, the first clock dividing unit 113, the first clock gating unit 114, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the first clock gating unit 114 and is controlled by the control circuit included in the first clock gating unit 114. is inactivated, and the first clock CLK1 is provided to the first IP 171 .

In addition, the first PLL controller 111, the first clock mux unit 112, the first clock division unit 113, the third clock gating unit 125, and the third channel management unit 127 are mutually pooled. Communication is performed according to the handshake method, and the clock request signal REQ may be transmitted from the third channel management unit 127 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the third clock gating unit 125 and is controlled by the control circuit included in the third clock gating unit 125. is inactivated, and the second clock CLK2 is provided to the second IP 172 .

When the first IP 171 does not need the first clock CLK1, the clock request signal REQ is deactivated. Accordingly, the clock request signal REQ transmitted to the first clock gating unit 114 is deactivated. Clock gating is performed under the control of the control circuit included in the first clock gating unit 114 .

When the second IP 172 does not need the second clock CLK2, the clock request signal REQ is deactivated. Accordingly, the clock request signal REQ transmitted to the third clock gating unit 125 is deactivated. Clock gating is performed under the control of the control circuit included in the third clock gating unit 125 .

FIG. 9A is a block diagram illustrating a semiconductor device according to some example embodiments, and FIG. 9B is a timing diagram illustrating an operation of the semiconductor device of FIG. 9A.

9A and 9B , the clock management unit 110d in the semiconductor device 4 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, a first clock It includes a dividing unit 113, a first clock gating unit 114, a first channel management unit 115, a third clock gating unit 125, and the like.

9A and 9B show a case in which a channel management unit and its parent clock gating unit are connected in a 1:n relationship. In other words, a case in which a plurality of clock gating units share and operate one channel management unit.

According to this structure, the operation of the second IP 172 is dependent on the operation of the first IP 171, and the case where the second IP 172 always operates when the first IP 171 operates. it means. Also, a case in which there is a possibility that the second IP 172 operates when the first IP 171 operates is included.

The first channel management unit 115 communicates with at least one of the first clock gating unit 114 and the third clock gating unit 125 according to a full handshake method. For example, when the first IP 171 transmits the clock request signal REQ to the first channel management unit 115, the first channel management unit 115 transmits it to the first clock gating unit 114. do.

The first PLL controller 111, the first clock mux unit 112, the first clock dividing unit 113, the first clock gating unit 114, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the first clock gating unit 114 and is controlled by the control circuit included in the first clock gating unit 114. is inactivated, and the first clock CLK1 is provided to the first IP 171 .

Since the operation of the second IP 172 depends on the operation of the first IP 171, the second IP 172 cannot generate a clock request signal, and the first IP 171 generates a clock request signal (REQ). ) is activated, the second clock CLK2 is also provided to the second IP 172 from the second clock gating unit 124 .

The first PLL controller 111, the first clock mux unit 112, the first clock division unit 113, the third clock gating unit 125, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the third clock gating unit 125 and is controlled by the control circuit included in the third clock gating unit 125. is inactivated, and the second clock CLK2 is provided to the second IP 172 .

When the first IP 171 does not need the first clock CLK1, the clock request signal REQ is deactivated. Accordingly, the clock request signal REQ transmitted to the first clock gating unit 114 is deactivated. Clock gating is performed under the control of the control circuit included in the first clock gating unit 114 . At this time, the clock request signal REQ transmitted to the third clock gating unit 125 is also deactivated, and clock gating is performed under the control of the control circuit included in the third clock gating unit 125 .

FIG. 10A is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept, and FIG. 10B is a timing diagram illustrating an operation of the semiconductor device of FIG. 10A.

10A and 10B , the clock management unit 110e in the semiconductor device 5 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, a first clock A dividing unit 113, a first clock gating unit 114, a first channel management unit 115, a fourth channel management unit 128, and the like.

10A and 10B show a case in which a channel management unit and its parent clock gating unit are connected in an n:1 relationship. In other words, a case in which a plurality of channel management units are connected to one clock gating unit.

According to this structure, there is only one clock used by a plurality of IPs. That is, the plurality of IPs use the same clock, and when a clock request is received from the plurality of IPs, the control circuit included in the clock gating unit performs an OR operation to determine whether a clock is required.

The first channel management unit 115 communicates with the first clock gating unit 114 according to a full handshake method, and the fourth channel management unit 128 communicates with the first clock gating unit 114 according to a full handshake method. communicate according to For example, the first IP 171 transmits a clock request signal (REQ) to the first channel management unit 115, or the second IP 172 transmits a clock request signal (REQ) to the fourth channel management unit 128. REQ), the first clock gating unit 114 performs an OR operation.

The first PLL controller 111, the first clock mux unit 112, the first clock dividing unit 113, the first clock gating unit 114, and the first channel management unit 115 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the first channel management unit 115 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the first clock gating unit 114 and is controlled by the control circuit included in the first clock gating unit 114. is inactivated, and the first clock CLK1 is provided to the first IP 171 .

When the first IP 171 does not need the first clock CLK1, it deactivates the clock request signal REQ, and accordingly, the clock request signal REQ transmitted to the first clock gating unit 114 is deactivated. . At this time, the control circuit included in the first clock gating unit 114 determines whether to perform clock gating by performing an AND operation.

The first PLL controller 111, the first clock mux unit 112, the first clock dividing unit 113, the first clock gating unit 114, and the fourth channel management unit 128 perform full handshake with each other. Communication is performed according to a method, and the clock request signal REQ may be transmitted from the fourth channel management unit 128 to the first PLL controller 111 at once.

When the clock response signal ACK is transmitted from the first PLL controller 111, it is transmitted to the first clock gating unit 114 and is controlled by the control circuit included in the first clock gating unit 114. is inactivated, and the first clock CLK1 is provided to the second IP 172 . That is, the clock provided to the first IP 171 and the clock provided to the second IP 172 are the same.

11 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 11 , a clock management unit 110f in a semiconductor device 6 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, and a first clock dividing unit ( 113), the first clock gating unit 114a, the first channel management unit 115, the third clock gating unit 125, the second PLL controller 121, the second clock mux unit 122, the second clock It includes a dividing unit 123, a second clock gating unit 124, a second channel management unit 126, and the like.

The case shown in FIG. 11 shows a case in which a channel management unit and its parent clock gating unit are connected in an n:m relationship. In other words, it means the case where the 1:n relationship and the n:1 relationship described above are applied in combination.

An operation of the clock management unit 110f in the semiconductor device 6 according to some embodiments of the present invention is substantially the same as that described above.

12 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 12 , a clock management unit 110g in a semiconductor device 7 according to some embodiments of the present invention includes a first PLL controller 111, a first clock mux unit 112, and a first clock dividing unit ( 113), first clock gating unit 114b, first channel management unit 115, second PLL controller 121, second clock mux unit 122, second clock division unit 123, second clock It includes a gating unit 124, a second channel management unit 126, a fifth channel management unit 131, and the like.

The case shown in FIG. 12 shows a case in which a channel management unit and its parent clock gating unit are connected in an n:m relationship. In other words, it means the case where the 1:n relationship and the n:1 relationship described above are applied in combination.

An operation of the clock management unit 110g in the semiconductor device 7 according to some embodiments of the present invention is substantially the same as that described above.

13 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 13 , the semiconductor device 700 includes a central processing unit 710, a clock generator 720, a clock management unit 730, a RAM 740, a ROM 750, a memory control unit 760, and the like. can include Meanwhile, the oscillator OSC may be disposed outside the semiconductor device 700 to provide an oscillation signal to the semiconductor device 700 . However, this is only an example, and the semiconductor device 700 according to an embodiment of the present invention may include various other functional blocks, and the oscillator OSC may be provided inside the semiconductor device 700. . The semiconductor device 700 of FIG. 40 may be included in a semiconductor system as an application processor.

The clock generator 720 generates a reference clock signal CLK_IN having a reference frequency using a signal from the oscillator OSC. The clock management unit 730 may receive the reference clock signal CLK_IN, generate an operation clock signal CLK_OUT having a predetermined frequency, and provide the generated operation clock signal CLK_OUT to each functional block. The clock management unit 730 may include one or more master clock controllers and one or more slave clock controllers, and each clock controller may generate an operation clock signal CLK_OUT using a reference clock signal CLK_IN.

In addition, as the clock controller in the clock management unit 730 is connected through a channel, clock signal management may be performed in hardware. Also, as the clock controller in the clock management unit 730 is connected to the functional block through a channel, clock request and request response may be performed in hardware.

The central processing unit 710 may process or execute codes and/or data stored in the RAM 740 . For example, the CPU 710 may process or execute the codes and/or the data in response to an operation clock output from the clock management unit 730 . The central processing unit 710 may be implemented as a multi-core processor. The multi-core processor is a computing component having two or more independent substantive processors, each of which can read and execute program instructions. Since the multi-core processor can simultaneously drive a plurality of accelerators, a data processing system including the multi-core processor can perform multi-acceleration.

The RAM 740 may temporarily store program codes, data or instructions. For example, program codes and/or data stored in an internal or external memory (not shown) are temporarily stored in the RAM 740 under the control of the CPU 710 or a booting code stored in the ROM 750. can be stored The memory control module 760 is a block for interfacing with an internal or external memory, and the memory control module 760 controls overall memory operations and also controls overall data exchange between the host and the memory.

14 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring to FIG. 14 , an example in which a semiconductor device 800 includes a power management unit 810 that manages supply of power to functional blocks is illustrated. The power management unit 810 may be designed to manage power used inside the semiconductor device 800 .

The semiconductor device 800 includes a power management unit 810 and a plurality of function blocks 821 and 822, and the function blocks 821 and 822 include a master function block 821 and a slave function block 822. can be classified as If, in order for the master function block 821 to operate, power must be supplied to the master function block 821, and at the same time, power must be supplied to one or more slave function blocks 822 related to the operation of the master function block 821. It should be done.

The master power controller 811 may communicate with each of the slave power controllers 812 and 813 through a channel. The power management unit 810 may receive input power (power_in), adjust the power, convert the power to be suitable for each functional block, and generate output power (power_out). Also, the power management unit 810 may provide or cut off power to the master function block 821 and the slave function block 822 according to the power request Req.

The master power controller 811 may receive the power request (Req) in software based on code processing of the central processing unit or receive the power request (Req) in hardware from the master function block 821 . In addition, the master function block 821 may provide a power on/off command (pwr on/off) to the slave power controllers 812 and 813, and a power response (Ack) from the slave power controllers 812 and 813. on/off) can be received.

15 is a block diagram illustrating an example of a semiconductor system including a semiconductor device according to some example embodiments of inventive concepts.

Referring to FIG. 15 , a semiconductor system 900 may include a SoC 901, an antenna 910, a wireless transceiver 920, an input device 930, and a display 940 according to the above-described embodiments. . The wireless transceiver 920 may transmit or receive a radio signal through the antenna 910 . For example, the radio transceiver 920 may change a radio signal received through the antenna 910 into a signal that can be processed by the SoC 901 .

Accordingly, the SoC 901 may process a signal output from the wireless transceiver 920 and transmit the processed signal to the display 940 . In addition, the wireless transceiver 920 may change the signal output from the SoC 901 into a wireless signal and output the changed wireless signal to an external device through the antenna 910 . The input device 930 is a device capable of inputting control signals for controlling the operation of the SoC 901 or data to be processed by the SoC 901, and includes a touch pad and a computer mouse. It can be implemented with the same pointing device, keypad, or keyboard.

16 is a block diagram illustrating another example of a semiconductor system including a semiconductor device according to some example embodiments of inventive concepts.

Referring to FIG. 16 , the memory system 1000 may be implemented as a data processing device such as a solid state drive (SSD). The memory system 1000 includes a plurality of memory devices 1500, a memory controller 1200 capable of controlling data processing operations of each of the plurality of memory devices 1500, a volatile memory device 1300 such as DRAM, and memory. An SoC 1100 controlling storage of data exchanged between the controller 1200 and the host 1400 in the volatile memory device 1300 may be included. The SoC 1100 may be implemented according to the above-described embodiment.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

100: semiconductor device
101: I/O pad
110: clock management unit
150: power management unit
171, 172, 173: first to third IP

Claims (20)

a first clock generator including a first control circuit and a first clock gating circuit;
a first channel manager communicating with the first clock generator according to a full handshake method;
a second clock generator including a second control circuit and a second clock gating circuit; and
A second channel management unit communicating with the second clock generation unit according to a full handshake method;
the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock;
The first channel manager transmits a second clock request signal to the first clock generator in response to the first clock request signal;
The semiconductor device of claim 1 , wherein the first clock generator transmits a first clock response signal to the first channel manager in response to the second clock request signal. delete According to claim 1,
The second channel manager transmits a fourth clock request signal to the second clock generator in response to a third clock request signal;
wherein the second clock generator transmits a second clock response signal to the second channel manager in response to the fourth clock request signal. According to claim 3,
the first control circuit deactivates the first clock gating circuit when the second clock request signal is activated;
The second control circuit deactivates the second clock gating circuit when the fourth clock request signal is activated. According to claim 1,
The semiconductor device further comprising a first logic block communicating with the first channel manager and a second logic block communicating with the second channel manager. According to claim 5,
The semiconductor device of claim 1 , wherein the first channel management unit and the first logic block communicate with each other using a full handshake channel. According to claim 5,
The first logic block includes an intellectual property (IP),
The IP activates a clock request signal when the first clock is required. According to claim 7,
The first clock generator provides the first clock to the IP in response to the clock request signal. According to claim 8,
The IP deactivates the clock request signal when the first clock is unnecessary. According to claim 1,
The semiconductor device of claim 1 , wherein the first clock generator and the first channel manager communicate with each other in a single clock domain. According to claim 10,
The semiconductor device of claim 1 , wherein the first control circuit and the first clock gating circuit use different clock domains. a first clock generator including a first control circuit and a first clock gating circuit;
a first channel manager communicating with the first clock generator according to a full handshake method; and
A second clock generator including a second control circuit and a second clock gating circuit;
The second clock generation unit communicates with the first channel manager according to a full handshake method;
the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock;
The first channel manager transmits a first clock request signal to the first clock generator;
The semiconductor device of claim 1 , wherein the first clock generation unit transmits a first clock response signal to the first channel management unit in response to the first clock request signal. The semiconductor device of claim 12 , wherein the first channel manager transmits a second clock request signal to the second clock generator. delete According to claim 13,
The second clock generation unit transmits a second clock response signal to the first channel management unit in response to the second clock request signal. According to claim 13,
the first control circuit deactivates the first clock gating circuit when the first clock request signal is activated;
The second control circuit deactivates the second clock gating circuit when the second clock request signal is activated. a first clock generator including a first control circuit and a first clock gating circuit;
a first channel manager communicating with the first clock generator according to a full handshake method; and
A second channel management unit communicating with the first clock generation unit according to a full handshake method;
The first channel manager transmits a first clock request signal to the first clock generator, the first clock generator transmits a first clock response signal to the first channel manager according to the first clock request signal,
The second channel manager transmits a second clock request signal to the first clock generator. According to claim 17,
The semiconductor device of claim 1 , wherein the first clock generator outputs a first clock when at least one of the first clock request signal and the second clock request signal is activated. According to claim 18,
a first logic block communicating with the first channel manager using a full handshake channel;
The semiconductor device further includes a second logic block communicating with the second channel manager using a full handshake channel. According to claim 19,
wherein the first clock generator provides the first clock to at least one of the first logic block and the second logic block.

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