KR102547483B1 - Hybrid chip comprising hybrid connector - Google Patents

Abstract

A chip of the present disclosure includes analog circuitry, digital circuitry, at least one first connection, and conversion operatively coupled with the at least one first connection. The switching unit may be configured to operatively couple the analog circuit and the at least one first connection when receiving a first signal, and when receiving a second signal, the digital It can be configured to operatively couple circuitry with the at least one first connection.

Description

Hybrid chip comprising a hybrid connection {HYBRID CHIP COMPRISING HYBRID CONNECTOR}

The descriptions below relate to a hybrid chip that includes a hybrid connector.

In order to generate more precise signals, current chips require a greater number of connectors. However, in order to be installed in an electronic device having various functions, current chips are required to be miniaturized. Therefore, a solution that efficiently utilizes the limited number of connections is desired.

The descriptions below may provide a hybrid connector capable of making connections to digital circuitry as well as connections to analog circuitry.

According to aspects related to the chip, an analog circuitry, a digital circuitry, and at least one first connection unit, and operatively with the at least one first connection unit It may include a switching unit operatively coupled with, the switching unit may be configured to operatively couple the analog circuit and the at least one first connection unit when receiving a first signal, and a second When receiving a signal, it may be configured to operatively couple the digital circuit and the at least one first connector.

For a more complete understanding, the following descriptions are made with reference to the accompanying drawings. Like reference numerals in the drawings indicate like elements.
1 is a diagram illustrating a hybrid chip including an analog circuit and a digital circuit.
2 is a diagram illustrating a hybrid chip including a hybrid connector.
3 is a diagram illustrating a functional configuration of a hybrid chip including a switching unit.
4 is a diagram illustrating a functional configuration of a hybrid chip including a switching unit including a plurality of path determining units.
5 is a diagram illustrating a functional configuration of a path determining unit.
6 is a diagram illustrating a hardware configuration of a path determining unit.
7 is a diagram illustrating a signal flow within a hybrid chip.
8 is a diagram illustrating another signal flow within the hybrid chip.

Terms used in the present disclosure are only used to describe a specific embodiment, and may not be intended to limit the scope of other embodiments. Singular expressions may include plural expressions unless the context clearly dictates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art described in this disclosure. Among the terms used in the present disclosure, terms defined in general dictionaries may be interpreted as having the same or similar meanings as those in the context of the related art, and unless explicitly defined in the present disclosure, ideal or excessively formal meanings. not be interpreted as In some cases, even terms defined in the present disclosure cannot be interpreted to exclude embodiments of the present disclosure.

In various embodiments of the present disclosure described below, a hardware access method is described as an example. However, since various embodiments of the present disclosure include technology using both hardware and software, various embodiments of the present disclosure do not exclude software-based access methods.

A hybrid chip may be a chip including analog circuitry and digital circuitry. Since it must be designed with a limited size in order to be installed in an electronic device having various functions, the hybrid chip inevitably has a limited number of connectors. Meanwhile, in order to control or calibrate an analog signal, a recently designed hybrid chip requires a higher ratio of digital circuits.

In general, for inspection of digital circuits, DFT (design for test) methods having high reliability, such as scan and MBIST (memory built in self test), exist. In order to test the digital circuit using the highly reliable DFT method, a large number (eg, about 10) of digital connectors are required.

In order to process the analog signal, the hybrid chip must secure connections to analog circuits greater than or equal to a standard number. Because of this, the hybrid chip has no choice but to have a small number (eg, 3 to 4) of connections to digital circuits. For the reasons described above, current hybrid chips cannot help but check the performance of the digital circuit included in the hybrid chip through a simplified method. Therefore, for the digital circuit included in the hybrid chip, a design for securing a certain number of digital connection units is required.

Accordingly, the descriptions below are used for analog circuits in a first mode (eg, functional mode) and for digital circuits in a second mode (eg, test mode). It is to provide a hybrid chip including a hybrid connector used. Through the hybrid connection unit, the hybrid chip may provide a more accurate analog signal. In addition, through the hybrid connection unit, the hybrid chip can more accurately check whether a digital circuit has an error. In addition, since the hybrid chip including the hybrid connector uses resources (eg, electrostatic discharge (ESD) and supply voltage) for existing hybrid chips, it has high compatibility with existing electronic devices.

1 is a diagram illustrating a hybrid chip including an analog circuit and a digital circuit.

Referring to FIG. 1 , the hybrid chip 100 may include an analog circuitry 110, a digital circuitry 120, and a plurality of connectors 130 (connection units 130-1 to 130-7). there is.

The analog circuit 110 may be a circuit for processing an analog signal. For example, in order to process the analog signal, the analog circuit may include various types of phase locked loops (PLLs), various types of amplifiers, various types of filters, and the like. .

The digital circuit 120 may be a circuit for controlling or adjusting the analog circuit 110 . For example, the digital circuit 120 may include various types of logic gates (eg, AND gate, OR gate, NOR gate, XOR (exclusive) gate, etc.). The digital circuit 120 may control a PLL, an amplifier, a filter, etc. included in the analog circuit 110 using various types of logic gates included in the digital circuit 120 .

The plurality of connection parts 130 may be elements for connecting the analog circuit 110 or the digital circuit 120 and at least one electronic device. The at least one electronic device may be various types of elements operatively or functionally coupled to the hybrid chip. For example, the at least one electronic device may be another chip outside the hybrid chip.

The plurality of connection parts 130 may also be referred to as a pad, a lead, a ball, or a pin.

Among the plurality of connection units 130 , connection units 130 - 1 to 130 - 4 may be connected to the analog circuit 110 . Each of the connection units 130-1 to 130-4 may provide the analog circuit 110 with a signal received from the at least one electronic device. Each of the connection units 130-1 to 130-4 may provide a signal received from the analog circuit 110 to the at least one electronic device.

Among the plurality of connection units 130 , each of connection units 130 - 5 to 130 - 7 may provide a signal received from the at least one electronic device to the digital circuit 120 . Each of the connection units 130-5 to 130-7 may provide a signal received from the digital circuit 120 to the at least one electronic device.

As described above, the hybrid chip 100 has four connection parts (connecting parts 130-1 to 130-4) for the analog circuit 110 and three connection parts (connecting part 130-5 for the digital circuit 120). to the connection part 130-7). Since a small number of connection parts are included for the digital circuit 120, the digital circuit 120 included in the hybrid chip 100 can be inspected through a simplified test. Therefore, the hybrid chip 100 may not be able to guarantee required performance.

2 is a diagram illustrating a hybrid chip including a hybrid connector.

Referring to FIG. 2, the hybrid chip 200 includes an analog circuitry 210, a digital circuitry 220, a plurality of connectors 230 (connection units 230-1 to 230-7), an analog path ( path) 240-1, analog path 250-1, analog path 260-1, digital path 240-2, digital path 250-2, and digital path 260-2.

The analog circuit 210 may be a circuit for processing an analog signal. For example, to process the analog signal, the analog circuit may include various types of PLLs, various types of filters, and various types of amplifiers. In some embodiments, the analog circuit 210 may process a signal transmitted or received by user equipment including the hybrid chip 200 . For example, the user equipment may be an evolved node B (eNB), a base station, or a mobile station. The analog circuit 210 may phase-lock, amplify, or filter a signal transmitted by the user device. The analog circuit 210 may phase-lock, amplify, or filter the signal received by the user device.

The digital circuit 220 may be a circuit for controlling or adjusting the analog circuit 210 . For example, the digital circuit 220 may include various types of logic gates. The digital circuit 220 may control filters, PLLs, and amplifiers included in the analog circuit 210 using the various types of logic gates. The digital circuit 220 may assist the analog circuit 210 to more accurately process a signal transmitted by the user device or a signal received by the user device.

The plurality of connection parts 230 may be a device for connecting the analog circuit 110 or the digital circuit 120 and at least one electronic device. The plurality of connection parts 230 may also be referred to as a pad, a lead, a ball, or a pin.

The plurality of connectors 230 may include an analog connector 230-1 and an analog connector 230-2, hybrid connectors 230-3 to 230-5, a digital connector 230-6, and a digital connector 230-7.

Each of the analog connection unit 230-1 and the analog connection unit 230-2 may provide the analog circuit 210 with a signal received from the at least one electronic device. Each of the analog connection unit 230-1 and the analog connection unit 230-2 may provide a signal received from the analog circuit 210 to the at least one electronic device.

Each of the digital connection unit 230 - 6 and the digital connection unit 230 - 7 may provide a signal received from the at least one electronic device to the digital circuit 220 . Each of the digital connection unit 230-6 and the digital connection unit 230-7 may provide a signal received from the digital circuit 220 to the at least one electronic device.

Each of the hybrid connection units 230-3 to 230-5 may be used as an analog connection unit according to an operation mode of the hybrid chip 200. For example, when the hybrid chip 200 operates in a first mode (eg, a mode for analog signal processing), the hybrid connection unit 230-3 may be connected to the analog circuit 210 using the analog path 240-1. there is. For another example, when the hybrid chip 200 operates in the first mode, the hybrid connection unit 230-4 may be connected to the analog circuit 210 using the analog path 250-1. For another example, when the hybrid chip 200 operates in the first mode, the hybrid connector 230-5 may be connected to the analog circuit 210 using the analog path 260-1.

Each of the hybrid connection units 230-3 to 230-5 may be used as a digital connection unit according to an operation mode of the hybrid chip 200. For example, when the hybrid 200 operates in the second mode (eg, a mode for checking whether a digital circuit has an error), the hybrid connector 230-3 connects the digital circuit 220 using the digital path 240-2. can be connected with For another example, when the hybrid chip operates in the second mode, the hybrid connector 230-4 may be connected to the digital circuit 220 using the digital path 250-2. For another example, when the hybrid chip 200 operates in the second mode, the hybrid connector 230-5 may be connected to the digital circuit 220 using the digital path 260-2.

As described above, the hybrid chip 200 may use 5 connection units for the analog circuit 210 and 5 connection units for the digital circuit 220 . The hybrid chip 200 can process signals more precisely than the hybrid chip 100 . This is because the hybrid chip 200 can use more analog connection units than the hybrid chip 100 . Also, the hybrid chip 200 can guarantee fewer errors than the hybrid chip 100 . This is because, unlike the hybrid chip 100, which has no choice but to inspect the digital circuit 120 in a simplified manner due to the limited number of digital connection units, the hybrid chip 200 can secure a greater number of digital connection units than the hybrid chip 100. . The hybrid chip 200 can check whether the digital circuit 220 has an error using a highly reliable inspection method (eg, scan, MBIST, etc.) by using a greater number of digital connection units than the hybrid chip 100. there is.

3 is a diagram illustrating a functional configuration of a hybrid chip including a switching unit. The functional configuration of the hybrid chip may be included in the hybrid chip 200 shown in FIG. 2 .

Referring to FIG. 3 , the hybrid chip 200 may include the analog circuit 210, the digital circuit 220, the plurality of connection units 230 (connection unit 230-1 to connection unit 230-7), and a switching unit 310.

The analog circuit 210 may have a minimum of 2 and a maximum of 5 input/output paths. Two of the five input/output paths may be respectively connected to the analog connection unit 230-1 and the analog connection unit 230-2. The remaining three of the five input/output paths may be respectively connected to the conversion unit 310 .

The analog circuit 210 may transmit a signal to the at least one electronic device through the analog connection unit 230-1 and the analog connection unit 230-2. The analog circuit 210 may receive a signal from the at least one electronic device through the analog connector 230-1 and the analog 230-2.

The analog circuit 210 may generate a signal to be transmitted to the at least one electronic device. For example, the analog circuit 210 may generate a processed signal by amplifying, phase-locking, or filtering a signal input to the analog circuit.

The analog circuit 210 may process a signal received from the at least one electronic device. For example, the analog circuit 210 may amplify, phase lock, or filter the received signal.

The digital circuit 220 may have a minimum of 2 and a maximum of 5 input/output paths. Two of the five input/output paths may be connected to the digital connector 230-6 and the digital connector 230-7, respectively. The remaining three of the five input/output paths may be respectively connected to the conversion unit 310 .

The digital circuit 220 may transmit a signal to the at least one electronic device through the digital connection unit 230-6 and the digital connection unit 230-7. The digital circuit 220 may receive a signal from the at least one electronic device through the digital connection unit 230-6 and the digital connection unit 230-7.

The digital circuit 220 may process a signal to be transmitted to the at least one electronic device. For example, the digital circuit 220 may process a signal input to the digital circuit using components included in the digital circuit 220 (eg, a NAND gate, an XOR gate, etc.).

The digital circuit 220 may process a signal received from the at least one electronic device.

In some embodiments, the digital circuit 220 may be operatively coupled with the analog circuit 210. In this case, the digital circuit 220 may be a circuit for controlling the analog circuit 210 . For example, the digital circuit 220 may generate a signal for controlling the analog circuit 210 . For another example, the digital circuit 220 may process an input signal received by the digital circuit 220 to generate a signal for controlling the analog circuit 210 .

Each of the analog connection unit 230-1 and the analog connection unit 230-2 may be a dedicated connector for the analog circuit 210. Each of the digital connection unit 230-6 and the digital connection unit 230-7 may be a dedicated connection unit for the digital circuit 220.

Each of the hybrid connection unit 230-3, the hybrid connection unit 230-4, and the hybrid connection unit 230-5 may be connected to the conversion unit 310.

Each of the hybrid connection unit 230 - 3 , the hybrid connection unit 230 - 4 , and the hybrid connection unit 230 - 5 may provide a signal to the analog circuit 210 through the conversion unit 310 . Each of the hybrid connection unit 230 - 3 , the hybrid connection unit 230 - 4 , and the hybrid connection unit 230 - 5 may provide a signal to the digital circuit 220 through the conversion unit 310 .

Each of the hybrid connection unit 230 - 3 , the hybrid connection unit 230 - 4 , and the hybrid connection unit 230 - 5 may receive a signal from the conversion unit 310 . Each of the hybrid connection unit 230-3, the hybrid connection unit 230-4, and the hybrid connection unit 230-5 may provide the received signal to the at least one electronic device.

The conversion unit 310 may be connected to the analog circuit 310 through an analog path (three analog paths in FIG. 3 ). The conversion unit 310 may be connected to the hybrid connection unit 230-3, the hybrid connection unit 230-4, and the hybrid connection unit 230-5, respectively.

The conversion unit 310 may perform a function of connecting the analog circuit 210 and the hybrid connection units according to a control signal. The control signal may be a signal for connecting the conversion unit 310 and one of the analog circuit 210 and the digital circuit 220 . The control signal may be determined according to an operation mode of the hybrid chip 210 . In some embodiments, the control signal may be a signal received from a controller of a user device including the hybrid chip 210 to set an operation mode of the hybrid chip 210 . In another embodiment, the control signal may be a signal received from an input unit of a user device including the hybrid chip 210 to set an operation mode of the hybrid chip 210 . In another embodiment, the control signal may be a signal input by a user to set an operation mode of the hybrid chip 210 .

For example, when a first signal for setting the operation mode of the hybrid chip 210 to a function mode is received by the switching unit 310, the switching unit 310 connects the analog circuit 210 and the hybrid connection unit 230-3 to the hybrid connection unit 230-3. The connection unit 230-4 and the hybrid 230-5 may be connected. For another example, when a second signal for setting the operation mode of the hybrid chip 210 to the test mode is received by the switching unit 310, the switching unit 310 connects the digital circuit 220 and the hybrid connection unit 230-3 to the hybrid connection unit 230-3. The hybrid connection unit 230-4 and the hybrid connection unit 230-5 may be connected. In the above examples, the conversion unit 310 connects the analog circuit 210 and the hybrid connection unit 230-3, the hybrid connection unit 230-4, and the hybrid connection unit 230-5, and the case where the conversion unit 310 connects the digital connection unit 230-3. A case in which the circuit 220 and the hybrid connection unit 230-3, the hybrid connection unit 230-4, and the hybrid connection unit 230-5 are all connected is described. However, the conversion unit 310 may connect a part of the hybrid connection unit 230-3, the hybrid connection unit 230-4, and the hybrid connection unit 230-6 to the analog circuit 210 and connect the remaining part to the digital circuit 220. .

Unlike one connection unit included in a chip with multiple uses (for example, multiplexing multiple DC signals), the hybrid connection illustrated in FIGS. It may be connected to or connected to a digital circuit. The hybrid chip including the hybrid connection unit may adaptively secure the number of connection units according to an operation mode. Accordingly, the hybrid chip including the hybrid connection unit may have a higher coverage than a chip not including the hybrid connection unit.

4 is a diagram illustrating a functional configuration of a hybrid chip including a switching unit including a plurality of path determining units. The functional configuration of the hybrid chip may be included in the hybrid chip 200 shown in FIG. 2 or FIG. 3 .

Referring to FIG. 4 , the hybrid chip 200 includes an analog circuit 210, a digital circuit 220, a conversion unit 400, and a plurality of hybrid connection units 410 (hybrid connection unit 410-1, hybrid connection unit 410-2 to hybrid connection unit 410-n). , a plurality of path determining units 420-1 to 420-n.

The analog circuit 210 may be connected to the plurality of path determining units 420-1 to 420-n, respectively.

In order to transmit a signal to the at least one electronic device, the analog circuit 210 sends all or some of the plurality of hybrid connectors 410 through all or some of the plurality of path determination units 420-1 to 420-n. signal can be provided.

The analog circuit 210 may receive a signal transmitted from the at least one electronic device through all or some of the plurality of path determining units 420-1 to 420-n. A signal transmitted from the at least one electronic device may be received through all or part of the plurality of hybrid connectors 410 . A signal received through all or part of the plurality of hybrid connectors 410 may be provided to the analog circuit 210 through all or part of the plurality of path determination units 420-1 to 420-n.

The analog circuit 210 can transmit and receive signals using at least 0 hybrid connection units and can transmit and receive signals using up to n hybrid connection units according to the operation mode of the hybrid chip 200 .

The digital circuit 220 may be connected to the plurality of path determining units 420-1 to 420-n, respectively. In order to transmit a signal to the at least one electronic device, the digital circuit 220 sends all or some of the plurality of hybrid connectors 410 through all or some of the plurality of path determining units 420-1 to 420-n. signal can be provided.

The digital circuit 220 may receive a signal transmitted from the at least one electronic device through all or some of the plurality of path determining units 420-1 to 420-n. A signal transmitted from the at least one electronic device may be received through all or part of the plurality of hybrid connectors 410 . A signal received through all or part of the plurality of hybrid connectors 410 may be provided to the digital circuit 220 through all or part of the plurality of path determining parts 420-1 to 420-n.

The digital circuit 220 may transmit and receive signals using at least 0 hybrid connection units and may transmit and receive signals using up to n hybrid connection units according to the operation mode of the hybrid chip 200 .

The conversion unit 400 may include a plurality of path determining units 420-1 to 420-n. The switching unit 400 may receive a control signal indicating an operation mode of the hybrid chip 200 for the plurality of path determining units 420-1 to 420-n.

In some embodiments, according to the control signal, the conversion unit 400 determines which circuit (eg, the analog circuit 210 or the digital circuit 220) is to be connected to the plurality of path determination units 420-1 to 420-n. can decide For example, the control signal connects the hybrid connection unit 410-k and the analog circuit 210 (in other words, connecting the path determination unit 420-k corresponding to the hybrid connection unit 410-k and the analog circuit 210). , the conversion unit 400 may determine to connect the path determination unit 420-k and the analog circuit 210. For another example, when the control signal indicates to connect the hybrid connection unit 410-k and the digital circuit 220, the conversion unit 400 may determine to connect the path determination unit 420-k and the digital circuit 220.

In some other embodiments, each of the plurality of path determining units 420-1 to 420-n, instead of the switching unit 400, may receive a control signal indicating an operation mode of the hybrid chip 200. When each of the plurality of path determination units 420-1 to 420-n receives the control signal, each of the plurality of path determination units 420-1 to 420-n receives the plurality of path determination units 420-1 to 420-n. You can decide which circuit to connect each n to. For example, when the control signal indicates to connect the hybrid connection unit 410-k and the analog circuit 210, the path determination unit 420-k corresponding to the hybrid connection unit 410-k may be connected to the analog circuit 210. . For another example, when the control signal indicates to connect the hybrid connection unit 410-k and the digital circuit 220, the hybrid connection unit 410-k and the corresponding condensation determination unit 420-k may be connected to the digital circuit 220. there is.

Each of the plurality of path determining units 420-1 to 420-n may be connected to a corresponding hybrid connection unit 410-1 to 410-n.

Each of the plurality of path decision units 420-1 to 420-n may be connected to the analog circuit 210 or the digital circuit 220 according to the operation mode of the hybrid chip 200.

As described above, the hybrid chip 200 can adaptively adjust the number of connection units for the analog circuit 210 and the number of connection units for the digital circuit 220 . For example, when only the operation of the analog circuit 210 is required, the hybrid chip 200 may adjust the number of connection units for the analog circuit 210 in response to the workload of the analog circuit 210 . For another example, when only the operation of the digital circuit 220 is required, the hybrid chip 200 may adjust the number of connection units for the digital circuit 220 in response to the workload of the digital circuit 220 . For another example, when it is determined that the workload of the analog circuit 210 is greater than the workload of the digital circuit 220, the hybrid chip 200 connects more connections than the number of connections allocated to the digital circuit 220 to the analog circuit 210. can be assigned to For another example, when it is determined that the workload of the digital circuit 220 is greater than the workload of the analog circuit 210, the hybrid chip 200 connects more connections than the number of connections allocated to the analog circuit 210 to the digital circuit 220. can be assigned to

5 is a diagram illustrating a functional configuration of a path determining unit. The functional configuration of the path determining unit may be included in one of the plurality of path determining units 420-1 to 420-n shown in FIG. 4 .

Referring to FIG. 5, one of the plurality of path determining units 420-1 to 420-n includes a hybrid connector 510, a guard unit 520, a second level shifter 530, and an inverter. ) 540, a linear amplifier 550, and a first level shifter 560.

The hybrid connector 510 may perform the same function as one of the hybrid connectors 230-3 to 230-5 or one of the plurality of hybrid connectors 410 shown in FIG. 2 .

The protection unit 520 may be connected to the hybrid connection unit 510 . The protection unit 520 may be connected to the linear amplifier 550 . The protection unit 520 may be connected to the first level shifter 560 .

The protection unit 520 may perform a function of protecting the hybrid chip 200 or the path determining unit. The protection unit 520 may prevent electrostatic discharge (ESD) from flowing into an output signal of the analog circuit (eg, the analog circuit 210). The protection unit 520 may prevent ESD from flowing into an output signal of a digital circuit (eg, the digital circuit 220).

The protection unit 520 may be composed of a clamp diode in which two diodes are coupled.

The second level shifter 530 may be connected to the inverter 540 .

The second level shifter 530 may receive a control signal. The control signal may indicate an operation mode of the hybrid chip 200 . In some embodiments, the control signal may be a signal received from a controller of a user device including the hybrid chip 200 . In some other embodiments, the control signal may be a signal received by a user's input from an input unit of a user device including the hybrid chip 200 . In some other embodiments, the control signal may be a signal generated by processing a signal received through the control unit or the input unit by the switching unit 400 shown in FIG. 4 .

The second level shifter 530 may level-shift the received control signal. In some embodiments, when the control signal is received at a voltage of 5V (volts), the second level shifter 530 may level-convert the control signal to generate a control signal having a voltage of 1.8V. In some other embodiments, when the control signal having a low voltage is received, the second level shifter 530 may level-shift the control signal to generate a control signal having a high voltage.

The second level shifter 530 may provide the level-converted control signal to a path between the analog circuit and the hybrid connector 510 . The level-converted control signal may indicate whether to activate a path between the analog circuit and the hybrid connection unit 510 . In other words, the level-converted control signal may indicate whether the hybrid connection unit 510 is used as a connection unit for an analog circuit. For example, when the level-converted control signal has a voltage, the level-converted control signal may activate a path between the analog circuit and the hybrid connection unit 510 . For another example, when the level-converted control signal does not have a voltage, the level-converted control signal may deactivate a path between the analog circuit and the hybrid connection unit 510 . In the above examples, when the level-converted control signal has a voltage, a path between the analog circuit and the hybrid connection unit 510 is activated, but this is for explanation. In some embodiments, when the level-converted control signal does not have a voltage, a path between the analog circuit and the hybrid connection unit 510 may be activated.

The second level shifter 530 may provide the level-converted control signal to the inverter 540 to indicate whether to activate a path between the digital circuit and the hybrid connector 510 .

The inverter 540 may be connected to the second level shifter 530 .

The inverter 540 may generate an inverted control signal by inverting the level-converted control signal received from the second level shifter 530 .

The inverter 540 may provide the inverted control signal to a path between the digital circuit and the hybrid connector 510 . The inverted control signal may indicate whether to activate a path between the digital circuit and the hybrid connection unit 510 . In other words, the inverted control signal may indicate whether the hybrid connection unit 510 is used as a connection unit for a digital circuit.

The linear amplifier 550 may be connected to the analog circuit. The linear amplifier 550 may be connected to the protection unit 520 .

The linear amplifier 550 may generate an amplified signal by amplifying a signal received through the hybrid connector 510 . The linear amplifier 550 may generate an amplified signal by amplifying a signal received from the analog circuit. Unlike the illustration of FIG. 5 , in some embodiments, the linear amplifier 550 may be replaced with another type of amplifier.

The linear amplifier 550 may provide the amplified signal to the analog circuit. The linear amplifier 550 may provide the amplified signal to the hybrid connector 510 .

The linear amplifier 550 may operate when the control signal activates an analog path (a path between the analog circuit and the hybrid connector 510).

The first level shifter 560 may be connected to the digital circuit. The first level shifter 560 may be connected to the protection unit 520 .

The first level shifter 560 may level-convert a signal received through the hybrid connector 510 to generate a level-converted signal. The first level shifter 560 may level-convert a signal received from the digital circuit to generate a level-converted signal.

The first level shifter 560 may provide the level-converted signal to the digital circuit. The first level shifter 560 may provide the level-converted signal to the hybrid connector 510 .

The first level shifter 560 may operate when the control signal activates a digital path (a path between the digital circuit and the hybrid connector 510).

The path determination unit including the above-described functional configuration may adaptively adjust the function or number of connection units for the hybrid chip 200 . Through adjusting the function or number of connection parts for the hybrid chip 200, the hybrid chip 200 can increase the amount of received or transmitted signals up to the capabilities of analog circuits or digital circuits according to the type of work.

6 is a diagram illustrating a hardware configuration of a path determining unit.

Referring to FIG. 6 , the path determining unit 600 and the hybrid connection unit 610 are illustrated in FIG. 6 . The path determination unit 600 includes a protection unit 615, an analog path switch 620-1, a digital path switch 620-2, a linear amplifier 630, a high to low level shifter 640, an HtoL level shifter 650, and an inverter. (inverter) 660 may be included.

The hybrid connection unit 610 may be connected to the protection unit 615 .

The hybrid connector 610 may receive a signal from at least one electronic device and provide the received signal to an analog circuit or a digital circuit. The hybrid connection unit 610 may receive a signal from the analog circuit or the digital circuit and provide the received signal to the at least one electronic device.

The hybrid connection unit 610 may be operatively coupled with the analog circuit or operatively coupled with the digital circuit according to a control signal received by the path determining unit 600 .

The protection unit 615 may be connected to the hybrid connection unit 610 . The protection unit 615 may be connected to the analog path switch 620-1. The protection unit 615 may be connected to the digital path switch 620-2.

The protection unit 615 may include a clamp diode in which two diodes are coupled. One of the two diodes may be connected to the ESP supply, and the other may be connected to ground.

The protection unit 615 may perform a function of protecting the path determination unit 600 , the analog circuit, the digital circuit, and the hybrid connection unit 610 .

The HtoL level shifter 650 may be connected to the inverter 650 . The HtoL level shifter 650 may be connected to the analog path switch 620-1.

The HtoL level shifter 650 may receive a control signal.

The HtoL level shifter 650 may level-convert the received control signal and generate a level-converted control signal. For example, the HtoL level shifter 650 may level-convert a control signal having a voltage of 5V to generate a level-converted control signal having a voltage of 1.8V.

The HtoL level shifter 650 may provide the level-converted control signal to the analog path switch 620-1.

For example, when the level-converted control signal is digitally “1”, the level-converted control signal is used to activate an analog path (a path from the hybrid connection unit 610 to an analog output). could be a signal The HtoL level shifter 650 may activate the analog path by providing the level-converted control signal to the analog path switch 620-1.

For another example, when the level-converted control signal is digitally “0”, the level-converted control signal may be a signal for inactivating the analog path. The HtoL level shifter 650 may deactivate the analog path by providing the level-converted control signal to the analog path switch 620-1.

The HtoL level shifter 650 may provide the level-shifted control signal to the inverter 660 .

The inverter 660 may be connected to the HtoL level shifter 650. The HtoL level shifter 650 may be connected to the digital path switch 620-2.

The inverter 660 may receive the level-converted control signal.

The inverter 660 may invert the level-converted signal to generate an inverted control signal.

The inverter 660 may provide the inverted control signal to the digital path switch 620-2.

For example, the inverter 660 may generate a digitally inverted control signal of "0" by inverting a level-converted control signal of "1". The digitally inverted control signal of “0” may be a signal for inactivating a digital path (a path of a digital input branch in the hybrid connection unit 610). The inverter 660 may deactivate the digital path by providing the inverted control signal to the digital path switch 620-2.

For another example, the inverter 660 may generate a digitally inverted control signal of "1" by inverting a level-converted control signal of "0". The digitally “1” inverted control signal may be a signal for activating a digital path. The inverter 660 may activate the digital path by providing the inverted control signal to the digital path switch 620-2.

The analog path switch 620-1 may be connected to the linear amplifier 630. The analog path switch 620-1 may be connected to the protection unit 615. The analog path switch 620-1 may be connected to the digital path switch 620-2.

The analog path switch 620-1 may be a device for activating or inactivating the analog path. For example, when the level-converted control signal DFT_MODE_HV is digitally “1” and the inverted control signal DFT_MODE_B_HV is digitally “0”, the analog path switch 620-1 is the analog path switch 620-1. pathways can be activated. For another example, when the level-converted control signal DFT_MODE_HV is digitally “0” and the inverted control signal DFT_MODE_B_HV is digitally “1”, the analog path switch 620-1 The analog path can be disabled.

The digital path switch 620-2 may be connected to the HtoL level shifter 640. The digital path switch 620-2 may be connected to the protection unit 615. The digital path switch 620-2 may be connected to the analog path switch 620-1.

The digital path switch 620-2 may be a device for activating or inactivating the digital path. For example, when the inverted control signal DFT_MODE_B_HV is digitally “1” and the level-converted control signal DFT_MODE_HV is digitally “0”, the digital path switch 620-2 operates on the digital path switch 620-2. pathways can be activated. For another example, when the inverted control signal DFT_MODE_B_HV is digitally “0” and the level-converted control signal DFT_MODE_HV is digitally “1”, the digital path switch 620-2 The digital pathway can be disabled.

The analog path switch 620-1 and the digital path switch 620-2 may be implemented as one switch. The analog path switch 620-1 and the digital path switch 620-2 may collectively be referred to as an input unit.

The linear amplifier 630 may be connected to the analog path switch 620-1. Although not shown in FIG. 6, the linear amplifier 630 may be operatively coupled with an analog circuit.

The linear amplifier 630 may operate when the analog path is activated. The linear amplifier 630 may generate an amplified analog output by amplifying the analog output. The linear amplifier 630 may provide the amplified analog output to the hybrid connector 610 through the analog path.

The HtoL level shifter 640 may be connected to the digital path switch 620-2. Although not shown in FIG. 6, the HtoL level shifter 640 may be operatively coupled with a digital circuit.

The HtoL level shifter 640 may operate when the digital path is activated. The HtoL level shifter 640 may level-convert the digital input to generate a level-converted digital input. The HtoL level shifter 640 may provide the level-converted digital input to the hybrid connector 610 through the digital path.

Although FIG. 6 illustrates a case in which a signal is output from an analog circuit and a signal is input to a digital circuit, this is for explanation. In the hybrid chip of the present disclosure, when a signal is input to an analog circuit and a signal is input to a digital circuit, a signal is output from the analog circuit, and when a signal is output from the digital circuit, the signal is input to the analog circuit and the digital circuit It can also be applied when a signal is output from .

7 is a diagram illustrating a signal flow within a hybrid chip. The signal flow may occur in the hybrid chip 200 shown in FIG. 2 .

Referring to FIG. 7 , in step S710, the hybrid connector 710 may receive an input signal from at least one electronic device. The input signal may be one of a signal for an analog circuit and a signal for a digital circuit.

In step S720, the hybrid connection unit 710 may provide the input signal to an input unit 720. The input unit 720 may receive the input signal from the hybrid connection unit 710 . The input unit 720 may include the analog path switch 620-1 and the digital path switch 620-2 shown in FIG. 6 .

In step S730, the input unit 720 may receive a control signal. In some embodiments, the control signal may be received from a controller of a user device including the hybrid chip 200 . In some other embodiments, the control signal may be received based on a user's input to the user device including the hybrid chip 200 .

Depending on the embodiment, the process S720 and the process S730 may be performed simultaneously or in reverse order.

In step S740, the input unit 720 may determine whether the received control signal is a first signal. The first signal may be a signal for activating a path (hereinafter referred to as an analog path) between the analog circuitry 750 and the hybrid connector 710 .

When the received control signal is the first signal, the input unit 720 may transmit an input signal to a linear amplifier 730 in step S750. The linear amplifier 730 may receive an input signal from the input unit 720 .

In step S760, the linear amplifier 730 may generate an amplified input signal by amplifying the input signal. The linear amplifier 730 may provide the amplified input signal to the analog circuit 750 . The analog circuit 750 may receive the amplified input signal.

If the received control signal is not the first signal, the input unit 720 may transmit an input signal to the level shifter 740 in step S770. The level shifter 740 may receive an input signal from the input unit 720 .

In step S780, the level shifter 740 may generate a level-shifted input signal by level-converting the input signal. The level shifter 740 may provide a digital signal 760 with the level-converted input signal. The digital circuit 760 may receive the level-converted input signal.

Through the signal flow shown in FIG. 7, the hybrid chip including the hybrid connection unit, the conversion unit, the path determination unit, and the like converts the signal received through one hybrid connection unit according to the control signal to the analog included in the hybrid chip. It can be given to a circuit or given to a digital circuit. Through the signal flow, the hybrid chip can maximize utilization of the analog circuit and/or the digital circuit.

8 is a diagram illustrating another signal flow within the hybrid chip. The signal flow may occur in the hybrid chip 200 shown in FIG. 2 .

Referring to FIG. 8, in step S810, the input unit 820 may receive a first signal. The first signal may activate a path from the hybrid connection unit 810 to the analog circuit 850 (hereinafter referred to as an analog path).

In step S820, the analog circuit 850 may transmit a first output signal (output signal #1) to the linear amplifier 830. Since the analog path is activated through the step S810, the linear amplifier 830 can receive the first output signal from the analog circuit 850.

In step S830, the linear amplifier 830 may generate an amplified first output signal by amplifying the first output signal. The linear amplifier 830 may provide the amplified first output signal to the hybrid connector 810 .

Although not shown in FIG. 8 , the hybrid connector 810 may provide the amplified first output signal to an electronic device or the like.

In step S840, the input unit 820 may receive a second signal. The second signal may activate a path from the hybrid connector 810 to the digital circuit 860 (hereinafter referred to as a digital path).

In step S850, the digital circuit 860 may transmit a second output signal (output signal #2) to the level shifter 840. Since the digital path is activated through the process S840, the level shifter 840 can receive the second output signal from the digital circuit 860.

In step S860, the level shifter 840 may generate a level-shifted second output signal by level-converting the second output signal. The level shifter 840 may provide the level-shifted second output signal to the hybrid connector 810 .

Although not shown in FIG. 8 , the hybrid connector 810 may provide the level-converted second output signal to an electronic device or the like.

Through the signal flow shown in FIG. 8, the hybrid chip including the hybrid connection unit, the conversion unit, and the path determination unit transmits an output signal generated from an analog circuit or a digital circuit according to a control signal through one hybrid connection unit. It can be provided to electronic devices. Through the signal flow, the hybrid chip can maximize utilization of the analog circuit and/or the digital circuit.

As described above, the chip of the present disclosure includes analog circuitry, digital circuitry, at least one first connection, and operatively coupled with the at least one first connection ( operatively coupled with) a switching unit, wherein the switching unit may be configured to operatively couple the analog circuit and the at least one first connection unit when receiving a first signal, and receiving a second signal In the case of doing so, it may be configured to operatively couple the digital circuit and the at least one first connection part. The chip may further include at least one second connection part operatively coupled with the analog circuit and at least one third connection part operatively coupled with the digital circuit. The analog circuit may be configured to receive at least one first analog signal and at least one second analog signal, wherein the at least one first analog signal, when the conversion unit receives the first signal, It may be received from at least one electronic device through the at least one first connection unit, and the at least one second analog signal may be received from the at least one electronic device through the at least one second connection unit. can be received The digital circuit may be configured to receive at least one first digital signal and at least one second digital signal, wherein the at least one first digital signal, when the conversion unit receives the second signal, The at least one second digital signal may be received from the at least one electronic device through the at least one first connection unit, and the at least one second digital signal may be received from the at least one electronic device through the at least one third connection unit. there is. The analog circuit may be further configured to transmit at least one third analog signal and at least one fourth analog signal, wherein the at least one third analog signal is selected when the conversion unit receives the first signal. , The at least one fourth analog signal may be transmitted to the at least one electronic device through the at least one first connection unit, and the at least one fourth analog signal may be transmitted to the at least one electronic device through the at least one second connection unit. can The digital circuit may be further configured to transmit at least one third digital signal and at least one fourth digital signal, wherein the at least one third digital signal is selected when the conversion unit receives the second signal. , The at least one fourth digital signal may be transmitted to the at least one electronic device through the at least one first connection unit, and the at least one fourth digital signal may be transmitted to the at least one electronic device through the at least one third connection unit. can

In addition, the conversion unit may include a plurality of path determining units, each of the plurality of path determining units may be connected to an analog path and may be connected to a digital path, and when receiving the first signal, the analog path may be configured to operatively couple the analog circuit and one of the at least one first connection through a path, and when receiving the second signal, the digital circuit and the at least one first connection through the digital path. 1 can be configured to operatively engage one of the connectors. Each of the plurality of path determining units includes a linearity amplifier connected to the analog circuit and connected to the analog path, and a first level shifter connected to the digital circuit and connected to the digital path. ) may further include. The at least one first connection unit may include a fourth connection unit, the analog circuit may be configured to receive a first analog signal, and the first analog signal may be configured to receive a first analog signal from among the plurality of path determining units. When the first path determination unit receives the first signal, it may be generated by amplifying the first input signal through the linear amplifier, and the first input signal is transmitted from an electronic device through the fourth connection unit. It may be received by the first path determining unit. The at least one first connection unit may include a fifth connection unit, the digital circuit may be configured to receive a first digital signal, and the first digital signal may be configured to receive a first digital signal from among the plurality of path determining units. When the second path determination unit receives the second signal, the second input signal may be generated by converting the second input signal through the first level shifter, and the second input signal may be transmitted from the electronic device through the fifth connection unit. It may be received by the second path determining unit. The at least one first connection unit may include a sixth connection unit, the analog circuit may be further configured to transmit a second analog signal, and the linear amplifier may amplify the second analog signal to generate a second analog signal. 1 may be configured to generate an output signal, wherein the first output signal is transmitted through the sixth connection unit when a third path determination unit among the plurality of path determination units receives the first signal; can be sent to the device. The at least one first connection unit may include a seventh connection unit, the digital circuit may be further configured to transmit a second digital signal, and the first level shifter converts the second digital signal. may be configured to generate a second output signal, wherein the second output signal is configured to generate the at least one signal through the at least one seventh connection unit when a fourth path determination unit among the path determination units receives the second signal. It can be transmitted to one electronic device.

Also, each of the plurality of path determining units may include a second level shifter and an inverter operatively coupled to the second level shifter. The second level shifter may be configured to receive the first signal, and when receiving the first signal, convert the first signal to generate a converted first signal, and the inverter may be configured to convert the polarity of the converted first signal to generate a third signal, the converted first signal may be a signal for activating the analog path, and the third signal may include the It can be a signal to deactivate the digital path. The second level shifter may be further configured to receive the second signal, and when receiving the second signal, may be further configured to convert the second signal to generate a converted second signal, The inverter may be configured to generate a fourth signal by converting a polarity of the converted second signal, the converted second signal may be a signal for activating the digital path, and the fourth signal , may be a signal for inactivating the analog path.

In addition, each of the plurality of path determination units may further include a protection unit operatively coupled to one of the at least one first connection unit. The protection unit may be configured to block static electricity from being input to the analog path or the digital path.

Further, the digital circuitry may be operatively coupled with the analog circuitry and configured to generate signals for controlling the analog circuitry.

Also, the first signal may be a control signal for activating the analog circuit, and the second signal may be a control signal for activating the digital circuit.

Also, the first signal may be received to generate a signal for an apparatus including the chip, and the second signal may be received to check whether the chip has an error.

Methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

When implemented in software, a computer readable storage medium storing one or more programs (software modules) may be provided. One or more programs stored in a computer-readable storage medium are configured for execution by one or more processors in an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specification of the present disclosure.

Such programs (software modules, software) may include random access memory, non-volatile memory including flash memory, read only memory (ROM), and electrically erasable programmable ROM. (EEPROM: Electrically Erasable Programmable Read Only Memory), magnetic disc storage device, Compact Disc-ROM (CD-ROM), Digital Versatile Discs (DVDs), or other forms of It can be stored on optical storage devices, magnetic cassettes. Alternatively, it may be stored in a memory composed of a combination of some or all of these. In addition, each configuration memory may be included in multiple numbers.

In addition, the program may be performed through a communication network such as the Internet, an Intranet, a Local Area Network (LAN), a Wide LAN (WLAN), or a Storage Area Network (SAN), or a communication network composed of a combination thereof. It can be stored on an attachable storage device that can be accessed. Such a storage device may be connected to a device performing an embodiment of the present disclosure through an external port. In addition, a separate storage device on a communication network may be connected to a device performing an embodiment of the present disclosure.

In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed in singular or plural numbers according to the specific embodiments presented. However, the singular or plural expressions are selected appropriately for the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components, and even components expressed in plural are composed of the singular number or singular. Even the expressed components may be composed of a plurality.

Meanwhile, in the detailed description of the present disclosure, specific embodiments have been described, but various modifications are possible without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the described embodiments and should not be defined by the scope of the claims described below as well as those equivalent to the scope of these claims.

Claims (20)

In an integrated circuit (IC),
analog circuitry; and
a digital circuit;
at least one first connector;
at least one second connection operatively coupled with the analog circuitry;
at least one third connection operatively coupled with the digital circuit;
a transition portion operatively coupled with the at least one first connection portion;
The conversion part,
configured to couple the analog circuit and the at least one first connection when receiving a first signal;
configured to couple the digital circuit and the at least one first connection when receiving a second signal;
the analog circuit is configured to receive at least one first analog signal and at least one second analog signal;
When the conversion unit receives the first signal, the at least one first analog signal is received from at least one electronic device through the at least one first connection unit, and the at least one second analog signal is the at least one analog signal. An integrated circuit received from the at least one electronic device through one second connection.
The method according to claim 1, wherein the digital circuit,
configured to receive at least one first digital signal and at least one second digital signal;
When the conversion unit receives the second signal, the at least one first digital signal is received from the at least one electronic device through the at least one first connection unit, and the at least one second digital signal is received from the at least one electronic device. An integrated circuit received from at least one electronic device through the at least one third connection unit.
The method according to claim 2, wherein the analog circuit,
further configured to transmit at least one third analog signal and at least one fourth analog signal;
When the conversion unit receives the first signal, the at least one third analog signal is transmitted to the at least one electronic device through the at least one first connection unit, and the at least one fourth analog signal is transmitted to the at least one electronic device. An integrated circuit transmitted to the at least one electronic device through at least one second connection.
The method according to claim 3, wherein the digital circuit,
further configured to transmit at least one third digital signal and at least one fourth digital signal;
When the conversion unit receives the second signal, the at least one third digital signal is transmitted to the at least one electronic device through the at least one first connection unit, and the at least one fourth digital signal is transmitted to the at least one electronic device. An integrated circuit transmitted to the at least one electronic device through at least one third connection.
The method of claim 1,
The conversion unit includes a plurality of path determining units,
The plurality of path determining units,
connected to the analog path, connected to the digital path,
configured to operatively couple the analog circuit and one of the at least one first connection via the analog path when receiving the first signal;
and upon receiving the second signal, operatively couple the digital circuit and one of the at least one first connection via the digital path.
The method according to claim 5, wherein the plurality of path determining units,
A linear amplifier connected to the analog circuit and connected to the analog path;
The integrated circuit further comprises a first level shifter coupled to the digital circuit and coupled to the digital path.
The method according to claim 6, wherein the at least one first connection unit,
Including a fourth connection,
When a first path determining unit among the plurality of path determining units receives the first signal, the first analog signal is generated by amplifying a first input signal through the linear amplifier;
The first input signal is received from the at least one electronic device to the first path determination unit through the fourth connection unit.
The method according to claim 7, wherein the at least one first connection unit,
Including a fifth connection part,
the digital circuit is configured to receive a first digital signal;
When a second path determining unit among the plurality of path determining units receives the second signal, the first digital signal is generated by converting a second input signal through the first level shifter;
The second input signal is received from the at least one electronic device to the second path determination unit through the fifth connection unit.
The method according to claim 8, wherein the at least one first connection unit,
Including a sixth connection,
the analog circuitry is further configured to transmit a second analog signal;
the linear amplifier is configured to amplify the second analog signal to generate a first output signal;
When a third path determining unit among the plurality of path determining units receives the first signal, the first output signal is transmitted to the at least one electronic device through the sixth connection unit.
The method according to claim 9, wherein the at least one first connection unit,
Including a seventh connection,
the digital circuit is further configured to transmit a second digital signal;
The first level shifter is configured to convert the second digital signal to generate a second output signal;
When a fourth path determining unit among the plurality of path determining units receives the second signal, the second output signal is transmitted to the at least one electronic device through the seventh connection unit.
The method according to claim 6, wherein the plurality of path determining units,
A second level shifter;
and an inverter operatively coupled to the second level shifter.
The method according to claim 11, wherein the second level shifter,
configured to receive the first signal;
When receiving the first signal, the second level shifter is configured to convert the first signal to generate a converted first signal, and the inverter converts the polarity of the converted first signal to generate a third signal. It is configured to generate
The converted first signal is a signal for activating the analog path,
wherein the third signal is a signal for inactivating the digital path.
The method of claim 12,
The second level shifter is configured to receive the second signal,
When receiving the second signal, the second level shifter is configured to convert the second signal to generate a converted second signal, and the inverter converts the polarity of the converted second signal to generate a fourth signal. It is configured to generate
The converted second signal is a signal for activating the digital path,
The fourth signal is a signal for inactivating the analog path.
The method according to claim 6, wherein the plurality of path determining units,
and a protection portion operatively coupled with one of the at least one first connection portion.
The method according to claim 14, wherein the protection unit,
An integrated circuit configured to block static electricity from being input to the analog path or the digital path.
The method of claim 1,
wherein the digital circuitry is operatively coupled with the analog circuitry and is configured to generate signals for controlling the analog circuitry;
the first signal is a control signal for activating the analog circuit;
wherein the second signal is a control signal for activating the digital circuit.
The method of claim 1,
the first signal is received to generate a signal for an apparatus comprising the integrated circuit;
The second signal is configured to be received to check whether the integrated circuit has an error.
In the method of manufacturing an integrated circuit (IC),
forming analog circuitry as part of a wafer or package;
forming a digital circuit as part of the wafer or the package;
forming at least one first connector as part of the wafer or the package;
forming, as part of the wafer or the package, at least one second connection operatively coupled with the analog circuitry;
forming at least one third connection, as part of the wafer or the package, operatively coupled with the digital circuitry; and
forming a transition portion operatively coupled with the at least one first connection portion;
The conversion part,
configured to couple the analog circuit and the at least one first connection when receiving a first signal;
configured to couple the digital circuit and the at least one first connection when receiving a second signal;
the analog circuit is configured to receive at least one first analog signal and at least one second analog signal;
When the conversion unit receives the first signal, the at least one first analog signal is received from at least one electronic device through the at least one first connection unit, and the at least one second analog signal is the at least one analog signal. The method is received from the at least one electronic device through one second connection unit. delete delete

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