KR102540733B1 - Semiconductor Package and Semiconductor device including the same - Google Patents

Abstract

The present invention is a semiconductor chip having a plurality of signal pads; a plurality of electrodes electrically connected to the plurality of signal pads; a first electrode pad contacting an upper surface of each of the plurality of electrodes; a second electrode pad in contact with a lower surface of each of the plurality of electrodes; and an insulating layer provided between the semiconductor chip and the plurality of electrodes, the plurality of electrodes extending in a vertical direction from an upper part to a lower part of the insulating layer, and the first electrode pad is the insulating layer is exposed to the outside from the upper surface of the semiconductor package, and the second electrode pad is exposed to the outside from the lower surface of the insulating layer, and a semiconductor device using the same.

Description

Semiconductor Package and Semiconductor Device including the same}

The present invention relates to a semiconductor package and a semiconductor device using the same.

A semiconductor device may be formed by mounting a semiconductor package on a substrate. At this time, in order to achieve high integration of the semiconductor device, a plurality of semiconductor packages must be mounted on a substrate, and accordingly, a plurality of wires and pads are formed on the substrate.

In the prior art, a plurality of semiconductor packages having the same structure are mounted on a substrate in the same form, and as a result, the arrangement of wires formed on the substrate is also fixed in a specific form depending on the structure of the semiconductor package.

However, when the arrangement of wires formed on a substrate is fixed in a specific shape, it is difficult to actively cope with various problems that may occur in circuit elements, such as signal delay due to a difference in length of wires.

An object of the present invention is to provide a semiconductor package and a semiconductor device using the same for variously changing the arrangement of wires formed on a substrate in order to actively cope with problems such as signal delay.

Solved problems according to embodiments of the present invention are not limited to the above-mentioned problems, and other problems not mentioned above will be clearly understood by those skilled in the art from the description below.

One embodiment of the present invention is a semiconductor chip having a plurality of signal pads; a plurality of electrodes electrically connected to the plurality of signal pads; a first electrode pad contacting an upper surface of each of the plurality of electrodes; a second electrode pad in contact with a lower surface of each of the plurality of electrodes; and an insulating layer provided between the semiconductor chip and the plurality of electrodes, the plurality of electrodes extending in a vertical direction from an upper part to a lower part of the insulating layer, and the first electrode pad is the insulating layer is exposed to the outside from an upper surface of the semiconductor package, and the second electrode pad is exposed to the outside from a lower surface of the insulating layer.

One embodiment of the present invention is a substrate; and a first semiconductor package and a second semiconductor package provided adjacent to the substrate, wherein each of the first semiconductor package and the second semiconductor package is made of the aforementioned semiconductor package, and the first semiconductor package The plurality of signal pads of the second semiconductor package do not face the substrate, and the plurality of signal pads of the second semiconductor package face the substrate.

According to an embodiment of the present invention, the semiconductor package may be electrically connected to each other in a state where the upper surface of the semiconductor package is positioned to face another substrate, and the semiconductor package may be electrically connected to each other in a state where the lower surface of the semiconductor package is positioned to face another substrate. Since the semiconductor package can be electrically connected to the other substrate, the wiring structure of the other substrate can be easily changed when the semiconductor package is mounted on the other substrate, so that the freedom of wiring of the other substrate can be improved.

1 is a schematic top view of a semiconductor package according to an embodiment of the present invention.
2A is a schematic bottom view of a semiconductor package according to an embodiment of the present invention.
2B is a schematic bottom view of a semiconductor package according to another embodiment of the present invention.
3 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention.
4 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.
5 is a schematic top view of a semiconductor package according to another embodiment of the present invention.
6 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.
7 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.
8 is a schematic plan view of a semiconductor device according to an exemplary embodiment.
9 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
10 is a schematic plan view of a semiconductor device according to another embodiment of the present invention.

Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, component names used in the following description may be selected in consideration of ease of writing specifications, and may be different from names of parts of actual products.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings.

1 is a schematic top view of a semiconductor package according to an embodiment of the present invention.

As can be seen in FIG. 1 , the semiconductor package 10 according to an embodiment of the present invention includes a semiconductor chip 100, a plurality of first electrode pads 210a, a plurality of wires 300, and an insulating layer 400. made including

The semiconductor chip 100 may be disposed in a central region of the semiconductor package 10 . The semiconductor chip 100 may include various driving chips for driving a display device, but is not necessarily limited thereto.

The semiconductor chip 100 includes a plurality of signal pads 110 . The plurality of signal pads 110 are arranged to be spaced apart from each other in a peripheral area outside the central area of the semiconductor chip 100 . The plurality of signal pads 110 include a plurality of input pads for inputting various signals supplied from an external device to circuit elements within the semiconductor chip 100 and various signals generated by circuit elements within the semiconductor chip 100. It includes a plurality of output pads for outputting to an external device. The types and locations of the input pad and output pad may be changed in various forms known in the art.

The plurality of first electrode pads 210a are spaced apart from each other in the peripheral area of the semiconductor package 10 . As can be seen through a cross-sectional view described later, the plurality of first electrode pads 210a are formed in a peripheral region of the upper surface of the semiconductor package 10 . In particular, the plurality of first electrode pads 210a may be disposed on the outermost line of the semiconductor package 10, and accordingly, not only the upper surface but also the side surface of the plurality of first electrode pads 210a may be exposed to the outside. can The total length of the outermost lines of the semiconductor package 10 is longer than the total length of innermost lines of the semiconductor package 10 . Therefore, when the plurality of first electrode pads 210a are disposed on the outermost line of the semiconductor package 10, a wide area for forming the plurality of first electrode pads 210a can be secured, and thus a plurality of first electrode pads 210a can be formed. A distance between the pads 210a may be increased, and accordingly, a connection between the plurality of first electrode pads 210a and pads provided on another substrate may be more easily performed.

The plurality of first electrode pads 210a are formed in a number corresponding to the number of the plurality of signal pads 110 of the semiconductor chip 100, and like the plurality of signal pads 110, the plurality of first electrode pads 210a are formed. The electrode pad 210a also includes a plurality of input pads and a plurality of output pads.

The plurality of wires 300 may electrically connect the plurality of signal pads 110 of the semiconductor chip 100 and the plurality of first electrode pads 210a on a one-to-one basis. That is, one signal pad 110 and one first electrode pad 210a may be electrically connected by the wire 300 . More specifically, as can be seen through cross-sectional views described later, the wire 300 connects between the signal pad 110 of the semiconductor chip 100 and the electrode 200 to which the first electrode pad 210a is connected. Accordingly, the signal pad 110 of the semiconductor chip 100 and the first electrode pad 210a may be electrically connected. However, it is not necessarily limited thereto, and one wire 300 connected to one signal pad 110 may be electrically connected to a plurality of first electrode pads 210a, and each of the plurality of signal pads 110 A plurality of connected wires 300 may be electrically connected to one first electrode pad 210a.

The insulating layer 400 is formed between the semiconductor chip 100, the plurality of first electrode pads 210a, and the plurality of wires 300 to insulate them. The insulating layer 400 may be formed to define the shape of the semiconductor package 10 .

2A is a schematic bottom view of a semiconductor package according to an embodiment of the present invention.

As can be seen in FIG. 2A , the lower surface of the semiconductor package 10 includes the insulating layer 400, and the plurality of second electrode pads 210b are spaced apart from each other on the outermost line of the insulating layer 400. are arranged

The plurality of second electrode pads 210b are formed in a peripheral area of the lower surface of the semiconductor package 10 , and in particular, may be disposed on an outermost line of the semiconductor package 10 .

As can be seen through cross-sectional views described later, the plurality of second electrode pads 210b are formed in a number corresponding to the number of the plurality of first electrode pads 210a described above, and the plurality of first electrode pads 210a is connected one-to-one with Accordingly, the plurality of second electrode pads 210b also include a plurality of input pads and a plurality of output pads.

FIG. 2B is a schematic bottom view of a semiconductor package according to another embodiment of the present invention, which is identical to FIG. 2A except that a heat dissipation plate 600 is additionally formed on the bottom surface of the semiconductor package 10 . Therefore, the same reference numerals are assigned to the same components, and only different configurations will be described below.

Referring to FIG. 2B , a heat dissipation plate 600 is provided on the lower surface of the central region of the semiconductor package 10 . The heat sink 600 is insulated from the plurality of second electrode pads 210b by the insulating layer 400 . As can be seen through cross-sectional views described later, the heat sink 600 is provided on the lower surface of the semiconductor chip 100 described above and serves to dissipate heat generated in the semiconductor chip 100 to the outside. Therefore, the heat dissipation plate 600 may include a metal material having excellent heat dissipation characteristics.

FIG. 3 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention, which corresponds to the schematic cross-section of the semiconductor package according to FIGS. 1 and 2A described above.

As can be seen from FIG. 3 , the semiconductor package 10 according to an embodiment of the present invention includes a semiconductor chip 100, a plurality of electrodes 200, a plurality of electrode pads 210a and 210b, and a plurality of wires 300. , an insulating layer 400, and a support 500.

The semiconductor chip 100 is disposed on the support 500, and a plurality of signal pads 110 constituting a plurality of input pads and a plurality of output pads are provided on the upper surface of the semiconductor chip 100.

The plurality of electrodes 200 are disposed to be spaced apart from each other in the peripheral area of the semiconductor package 10 . In particular, the plurality of electrodes 200 may be disposed on the outermost line of the semiconductor package 10, and thus one side surface of the plurality of electrodes 200 may be exposed to the outside. The plurality of electrodes 200 may be formed in the outermost line of the insulating layer 400 and inside grooves provided in some inner portions of the outermost line.

The plurality of electrodes 200 have a first portion 200a arranged in a first direction, for example, a horizontal direction, and a second direction different from that of the first portion 200a at one end of the first portion 200a, For example, it includes a second part 200b extending in the vertical direction.

The first portion 200a extends from the second portion 200b toward the semiconductor chip 100, that is, toward the inside of the semiconductor package 10, and thus the first portion 200a not exposed to the outside

The second part 200b is formed on the outermost line of the semiconductor package 10, and thus, one side surface of the second part 200b is exposed to the outside. In addition, the second portion 200b is configured to extend from the top to the bottom of the insulating layer 400 . That is, the second portion 200b may be configured to extend from the bottom to the top of the semiconductor package 10 . Although the second part 200b may be configured to extend from the upper surface to the lower surface of the insulating layer 400, the upper surface of the insulating layer 400 is formed at a higher position than the upper surface of the second part 200b, The lower surface of the insulating layer 400 may be formed at a position lower than the lower surface of the second part 200b. The second part 200b may be formed to have a uniform width as a whole, and thus, in a plan view, an area of an upper surface of the second part 200b and an area of a lower surface of the second part 200b are mutually exclusive. can be the same

A distance from the first portion 200a to the signal pad 110 of the semiconductor chip 100 is shorter than a distance from the second portion 200b to the signal pad 110 of the semiconductor chip 100. Accordingly, in forming the wire 200 for connecting the plurality of electrodes 200 and the signal pad 110 of the semiconductor chip 100, one end of the wire 200 is connected to the first part 200a. ), the length of the wire 200 can be reduced compared to the case where one end of the wire 200 is connected to the second part 200b.

The plurality of electrode pads 210a and 210b include a plurality of first electrode pads 210a and a plurality of second electrode pads 210b. The plurality of first electrode pads 210a are formed to contact the upper surface of the second part 200b of the electrode 200, and the plurality of second electrode pads 210b are formed to contact the second part 200b of the electrode 200. It is formed so as to come into contact with the lower surface of the portion 200b. Top and one side surfaces of the plurality of first electrode pads 210a are exposed to the outside, and bottom surfaces and one side surface of the plurality of second electrode pads 210b are also exposed to the outside.

As described above, when the area of the upper surface of the second part 200b and the area of the lower surface of the second part 200b are the same on a plan view, the area of the first electrode pad 210a and the area of the second part 200b on a plan view are equal to each other. The areas of the two electrode pads 210b may be the same, and in this case, a connection process between the first or second electrode pads 210a and 210b and a pad of another substrate may be facilitated.

The structure composed of the plurality of electrodes 200, the plurality of first electrode pads 210a, and the plurality of second electrode pads 210b is configured to penetrate from the upper surface to the lower surface of the semiconductor package 10. In particular, the structure including the plurality of electrodes 200, the plurality of first electrode pads 210a, and the plurality of second electrode pads 210b may be configured to form a straight line in the vertical direction.

As such, according to an embodiment of the present invention, the second portion 200b of the electrode 200 is configured to extend from the bottom to the top of the semiconductor package 10, and the upper surface of the second portion 200b Since the first electrode pad 210a and the second electrode pad 210b are formed on the upper and lower surfaces, respectively, the upper surface of the semiconductor package 10 is positioned to face another substrate. A connection may be made between the first electrode pad 210a provided on the upper surface and a pad of another substrate, and the lower surface of the semiconductor package 10 may be placed on the lower surface of the semiconductor package 10 while the lower surface of the semiconductor package 10 is positioned to face another substrate. The provided second electrode pad 210b may be connected to a pad of another substrate.

After all, according to an embodiment of the present invention, in a state where the upper surface of the semiconductor package 10 is positioned to face another substrate, the two may be electrically connected, and the lower surface of the semiconductor package 10 may be electrically connected to another substrate. Since the two can be electrically connected in a state of facing each other, the wiring structure of the other board can be easily changed when the semiconductor package 10 is mounted on the other board, so the wiring freedom of the other board can be improved, which will be easily understood by referring to the embodiments described later.

The plurality of wires 300 may connect the plurality of signal pads 110 of the semiconductor chip 100 and the plurality of electrodes 200 on a one-to-one basis. That is, one signal pad 110 and one electrode 200 may be electrically connected by the wire 300 . However, it is not necessarily limited thereto, and one wire 300 connected to one signal pad 110 may be connected to a plurality of electrodes 200, or a plurality of wires respectively connected to a plurality of signal pads 110 ( 300) may be electrically connected to one electrode 200.

As described above, one end of the wire 200 is connected to the first part 200a of the electrode 200 and the other end of the wire 200 is connected to the signal pad 110 of the semiconductor chip 100. can

The insulating layer 400 is formed between the semiconductor chip 100, the plurality of electrodes 200, the plurality of electrode pads 210a and 210b, and the plurality of wires 300 to insulate them. . The insulating layer 400 is formed below the support 500 and is formed on the top and side surfaces of the support 500, and is also formed in the space between the support 500 and the plurality of electrodes 200 . The insulating layer 400 may have a plurality of stacked structures.

The support 500 is disposed under the semiconductor chip 100 to support the semiconductor chip 100 . Specifically, an adhesive layer 550 may be provided between the support 500 and the semiconductor chip 100, and the semiconductor chip 100 may be fixed on the support 500 by the adhesive layer 550. The support 500 may be disposed to face the first part 200a at the same height as the first part 200a of the electrode 200 . The support 500 may be made of a material having high thermal conductivity and may serve to dissipate heat generated in the semiconductor chip 100 .

FIG. 4 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention, which corresponds to the schematic cross-section of the semiconductor package according to FIGS. 1 and 2B described above.

4 is the same as the above-mentioned FIG. 3 except that the heat dissipation plate 600 is additionally provided, and therefore, the same reference numerals are assigned to the same components, and only different configurations will be described below.

As can be seen in FIG. 4 , according to another embodiment of the present invention, a heat sink 600 is additionally provided under the support 500 .

The heat sink 600 serves to dissipate heat generated in the semiconductor chip 100 to the outside. Accordingly, the heat dissipation plate 600 is provided to protrude from the lower surface of the semiconductor package 10 so that the lower surface of the heat dissipation plate 600 is exposed to the outside. The heat dissipation plate 600 may include a first heat dissipation plate 610 contacting the lower surface of the support 500 and a second heat dissipation plate 620 contacting the lower surface of the first heat dissipation plate 610 . The first heat sink 610 may be made of the same material as the electrode 200, and the second heat sink 620 may be made of the same material as the second electrode pad 210b.

5 is a schematic top view of a semiconductor package according to another embodiment of the present invention.

As can be seen in FIG. 5 , the semiconductor package 10 according to another embodiment of the present invention includes a semiconductor chip 100, a plurality of first electrode pads 210a, a plurality of wires 300, and an insulating layer 400. made including

The semiconductor chip 100 includes a plurality of signal pads 110 . Since the semiconductor chip 100 and the plurality of signal pads 110 are the same as those in FIG. 1 , repeated descriptions will be omitted.

The plurality of first electrode pads 210a are spaced apart from each other in the peripheral area of the semiconductor package 10 . As can be seen through a cross-sectional view described later, the plurality of first electrode pads 210a are formed in a peripheral region of the upper surface of the semiconductor package 10 .

The plurality of first electrode pads 210a are disposed inside the outermost line of the semiconductor package 10 . Accordingly, upper surfaces of the plurality of first electrode pads 210a are exposed to the outside while side surfaces of the plurality of first electrode pads 210a are surrounded by the insulating layer 400 . Thus, side surfaces of the plurality of first electrode pads 210a may be protected by the insulating layer 400 .

As in FIG. 1 described above, the plurality of first electrode pads 210a are formed in a number corresponding to the number of the plurality of signal pads 110 of the semiconductor chip 100, and a plurality of input pads and a plurality of Include an output pad.

As in FIG. 1 described above, the plurality of wires 300 electrically connect between the plurality of signal pads 110 of the semiconductor chip 100 and the plurality of first electrode pads 210a. At this time, according to the arrangement structure of the plurality of first electrode pads 210a, the plurality of wires 300 may have a structure of a bent straight line or a bent curve.

As in FIG. 1 described above, the insulating layer 400 is formed between the semiconductor chip 100, the plurality of first electrode pads 210a, and the plurality of wires 300 to insulate them. . In particular, the insulating layer 400 is formed to surround the plurality of first electrode pads 210a, and accordingly, the outermost outermost part of the insulating layer 400 constitutes the outermost outermost part of the semiconductor package 10. .

FIG. 6 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention, which corresponds to the schematic cross-section of the semiconductor package according to FIG. 5 described above.

As can be seen in FIG. 6 , the semiconductor package 10 according to another embodiment of the present invention includes a semiconductor chip 100, a plurality of electrodes 200, a plurality of electrode pads 210a and 210b, and a plurality of wires 300. , an insulating layer 400, and a support 500.

The semiconductor chip 100 is disposed on the support 500, and a plurality of signal pads 110 constituting a plurality of input pads and a plurality of output pads are provided on the upper surface of the semiconductor chip 100.

The plurality of electrodes 200 are disposed to be spaced apart from each other in the peripheral area of the semiconductor package 10 . In particular, the plurality of electrodes 200 may be disposed inside the outermost line of the semiconductor package 10, and thus, all side surfaces of the plurality of electrodes 200 are surrounded by the insulating layer 400. there is.

The plurality of electrodes 200 are configured to extend from the bottom to the top of the semiconductor package 10 and, in some cases, from the lower surface to the upper surface of the semiconductor package 10, and accordingly, the upper surface of the electrode 200 The contacting first electrode pad 210a and the second electrode pad 210b contacting the lower surface of the electrode 200 may be exposed to the outside.

Although not shown, the first part 200a in which the plurality of electrodes 200 are arranged in the horizontal direction as shown in FIG. 3 and the second part extending in the vertical direction from one end of the first part 200a ( 200b) may be included.

The plurality of electrode pads 210a and 210b include a plurality of first electrode pads 210a provided on the upper surface of the plurality of electrodes 200 and a plurality of second electrodes provided on the lower surface of the plurality of electrodes 200. It is made including a pad (210b). Upper surfaces of the plurality of first electrode pads 210a are exposed to the outside and lower surfaces of the plurality of second electrode pads 210b are exposed to the outside.

As described above, according to another embodiment of the present invention, the electrode 200 is configured to extend from the bottom to the top of the semiconductor package 10, similarly to FIGS. 3 and 4 described above, and the A first electrode pad 210a and a second electrode pad 210b are formed on the upper and lower surfaces, respectively. Therefore, when the top surface of the semiconductor package 10 is positioned to face another substrate, the two may be electrically connected, and when the bottom surface of the semiconductor package 10 is positioned to face another substrate, the two may be electrically connected. Since the semiconductor package 10 can be electrically connected to the other substrate, the wiring structure of the other substrate can be easily changed when the semiconductor package 10 is mounted on the other substrate, so that the freedom of wiring of the other substrate can be improved.

As described above, the plurality of wires 300 connect between the plurality of signal pads 110 of the semiconductor chip 100 and the plurality of electrodes 200 .

The insulating layer 400 is formed between the semiconductor chip 100, the plurality of electrodes 200, the plurality of electrode pads 210a and 210b, and the plurality of wires 300 to insulate them. . The insulating layer 400 is formed below the support 500 and formed on the top and side surfaces of the semiconductor chip 100 on the support 500, and the support 500 and the plurality of electrodes 200 It is also formed in the space between them. The insulating layer 400 may have a plurality of stacked structures.

The support 500 is disposed under the semiconductor chip 100 to support the semiconductor chip 100 . Specifically, an adhesive layer 550 may be provided between the support 500 and the semiconductor chip 100, and the semiconductor chip 100 may be fixed on the support 500 by the adhesive layer 550.

Meanwhile, although not shown, a heat dissipation plate 600 as shown in FIG. 4 may be additionally provided below the support 500 .

7 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

As can be seen in FIG. 7 , a semiconductor device according to an exemplary embodiment includes a substrate 700 and a plurality of semiconductor packages 10a and 10b provided on the substrate 700 .

The substrate 700 may be formed of various substrates known in the art, such as a printed circuit board or a substrate for a display device.

Connection pads 750 electrically connected to the electrodes 200 of the semiconductor packages 10a and 10b are formed on the substrate 700 . Specifically, the connection pad 750 is connected to the second electrode pad 210b formed on the lower surface of the electrode 200 . The connection pads 750 are formed in the same number as the number of electrodes 200, and the plurality of connection pads 750 and the plurality of electrodes 200 correspond one to one.

The semiconductor packages 10a and 10b include a first semiconductor package 10a and a second semiconductor package 10b disposed adjacent to each other. For convenience, only two adjacent semiconductor packages 10a and 10b are shown in the drawing. In addition, although the drawing shows the first semiconductor package 10a and the second semiconductor package 10b having the structure of FIG. 3 described above, the first semiconductor package 10a and the second semiconductor package 10b It may be formed of the semiconductor package 10 according to various embodiments of FIGS. 1 to 6 described above.

The first semiconductor package 10a and the second semiconductor package 10b have the same structure and are mounted on the substrate 700 in the same shape. Specifically, the semiconductor chip 100 of the first semiconductor package 10a and the semiconductor chip 100 of the second semiconductor package 10b are both disposed to face upward. In addition, the electrode 200 for receiving or outputting the first signal ① is disposed on the left side of the first semiconductor package 10a, and the electrode 200 for receiving or outputting the second signal ② is disposed on the left side of the first semiconductor package 10a. An electrode 200 disposed on the right side of the semiconductor package 10a and correspondingly receiving or outputting the same signal as the first signal ① is disposed on the left side of the second semiconductor package 10b and An electrode 200 receiving or outputting the same signal as the second signal ② is disposed on the right side of the second semiconductor package 10b.

According to the arrangement structure, in both the first semiconductor package 10a and the second semiconductor package 10b, the second electrode pad 210b for receiving or outputting the first signal ① and the second electrode pad 210b. The second electrode pads 210b for receiving or outputting the two signals ② are all disposed facing downward and are in contact with the connection pad 750 on the substrate 700 .

FIG. 8 is a schematic plan view of a semiconductor device according to an embodiment of the present invention, which shows an example of a wiring structure formed on a substrate 700 in the semiconductor device according to FIG. 7 .

As can be seen in FIG. 8 , the first semiconductor package 10a and the second semiconductor package 10b are formed adjacent to each other on the substrate 700 .

The first semiconductor package 10a and the second semiconductor package 10b have the same configuration as in FIG. 7 and are mounted on the substrate 700 in the same shape.

The first semiconductor package 10a and the second semiconductor package 10b receive or receive a first signal ①, a second signal ②, a third signal ③, and a fourth signal ④, respectively. A second electrode pad 210b for outputting is provided.

Although the figure shows only the formation of the second electrode pads 210b at four positions for convenience, the formation position and number of the second electrode pads 210b may be variously changed.

The second electrode pad 210b for receiving or outputting the first signal ① may be disposed at the same position, for example, on the upper left side of the first semiconductor package 10a and the second semiconductor package 10b. . The second electrode pad 210b for receiving or outputting the second signal ② may be disposed at the same position, for example, in the upper right corner of the first semiconductor package 10a and the second semiconductor package 10b. . The second electrode pad 210b for receiving or outputting the third signal ③ may be disposed at the same position, for example, in the lower left corner of the first semiconductor package 10a and the second semiconductor package 10b. . The second electrode pad 210b for receiving or outputting the fourth signal ④ may be disposed at the same position, for example, in the lower right corner of the first semiconductor package 10a and the second semiconductor package 10b. .

According to this arrangement structure, the second electrode pad 210b of the first semiconductor package 10a and the second electrode pad 210b of the second semiconductor package 10b facing each other receive or receive signals different from each other. print out For example, the second electrode pad 210b receiving or outputting the second signal ② from the first semiconductor package 10a receives or outputs the first signal ① from the second semiconductor package 10b. facing the second electrode pad 210b. In addition, the second electrode pad 210b receiving or outputting the fourth signal ④ from the first semiconductor package 10a receives or outputs the third signal ③ from the second semiconductor package 10b. It faces the second electrode pad 210b.

On the substrate 700, a plurality of connection pads 750, a plurality of wires 711, 712, 721, 722, 731, 732, 741, and 742, and a plurality of input/output pads 761, 762, 763, and 764 are provided. is formed

The plurality of connection pads 750 correspond to and connect to the plurality of second electrode pads 210b of the first and second semiconductor packages 10a and 10b in a one-to-one correspondence. In this case, the plurality of connection pads 750 may be formed to overlap the plurality of second electrode pads 210b.

The plurality of wires 711 , 712 , 721 , 722 , 731 , 732 , 741 , and 742 connect the plurality of connection pads 750 and the plurality of input/output pads 761 , 762 , 763 , and 764 .

The plurality of wires 711, 712, 721, 722, 731, 732, 741, and 742 include a connection pad 750 overlapping the second electrode pad 210b for receiving or outputting the first signal ①, and 1 first wires 711 and 712 connecting the input/output pads 761, a connection pad 750 overlapping the second electrode pad 210b for receiving or outputting the second signal ②, and the second input/output pad 762, connection pads 750 overlapping with second wires 721 and 722 connecting between them, second electrode pads 210b receiving or outputting a third signal ③, and third input/output pads 763 Between the connection pad 750 and the fourth input/output pad 764 overlapping with the second electrode pad 210b for receiving or outputting the third wires 731 and 732 and the fourth signal ④. and fourth wirings 741 and 742 for connection.

The first wires 711 and 712 are first sub-wires 711 extending from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the first input/output pad 761. ) and from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the connection pad 750 overlapping the second electrode pad 210b of the second semiconductor package 10b. An extended second sub-wire 712 is included. Accordingly, the first semiconductor package 10a receives or outputs the first signal ① through the first sub-wire 711, and the second semiconductor package 10b connects the first sub-wire 711 and the first signal ①. The first signal (①) is received or output through the second sub wire 712 .

The second wires 721 and 722 are first sub-wires 721 extending from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the second input/output pad 762. ) and a second sub-wire 722 extending from the connection pad 750 overlapping the second electrode pad 210b of the second semiconductor package 10b to the second input/output pad 762. Accordingly, the first semiconductor package 10a receives or outputs the second signal ② through the first sub-wire 721, and the second semiconductor package 10b receives or outputs the second signal ② through the second sub-wire 722. The second signal (②) is received or output.

The third wires 731 and 732 are first sub-wires 731 extending from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the third input/output pad 763. ) and from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the connection pad 750 overlapping the second electrode pad 210b of the second semiconductor package 10b. An extended second sub-wire 732 is included. Accordingly, the first semiconductor package 10a receives or outputs the third signal ③ through the first sub-wire 731, and the second semiconductor package 10b connects the first sub-wire 731 and the The third signal ③ is received or output through the second sub wire 732 .

The fourth wires 741 and 742 are first sub-wires 741 extending from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the fourth input/output pad 764. ) and a second sub-wire 742 extending from the connection pad 750 overlapping the second electrode pad 210b of the second semiconductor package 10b to the fourth input/output pad 764. Accordingly, the first semiconductor package 10a receives or outputs the fourth signal ④ through the first sub-wire 741, and the second semiconductor package 10b receives or outputs the fourth signal ④ through the second sub-wire 742. The fourth signal ④ is received or output.

The first signal ①, the second signal ②, the third signal ③, and the fourth signal ④ may be a common voltage such as VDD or a reference voltage or another common signal. Accordingly, each of the input/output pads 761, 762, 763, and 764 receives the first signal ①, the second signal ②, the third signal ③, and the fourth signal ④. It can be simultaneously supplied to the first semiconductor package 10a and the second semiconductor package 10b.

In the semiconductor device according to an embodiment of the present invention, the first semiconductor package 10a receives or outputs the second signal ② through the first sub-wire 721, and the second semiconductor package ( 10b) receives or outputs the second signal ② through the second sub-wire 722, the difference between the length of the first sub-wire 721 and the length of the second sub-wire 722 When is reduced, the transmission distance of the second signal ② from the second input/output pad 762 to the first semiconductor package 10a and the second signal ② from the second input/output pad 762 to the second semiconductor package 10b The difference between signal (②) transmission distances can be minimized.

Similarly, the first semiconductor package 10a receives or outputs the fourth signal ④ through the first sub-wire 741, and the second semiconductor package 10b uses the second sub-wire 742. Since the fourth signal ④ is received or output, when the difference between the length of the first sub-wire 741 and the length of the second sub-wire 742 is reduced, the fourth input/output pad 764 A difference between the transmission distance of the fourth signal ④ from the first semiconductor package 10a and the transmission distance of the fourth signal ④ from the fourth input/output pad 764 to the second semiconductor package 10b may be minimized. there is.

In contrast, the first semiconductor package 10a receives or outputs the first signal ① through the first sub-wire 711, and the second semiconductor package 10b connects to the first sub-wire 711. Since the first signal ① is received or output by the second sub-wire 712, the transmission distance of the first signal ① from the first input/output pad 761 to the first semiconductor package 10a is described above. A large difference from the transmission distance of the first signal ① from the first input/output pad 761 to the second semiconductor package 10b occurs.

In addition, the first semiconductor package 10a receives or outputs the third signal ③ through the first sub-wire 731, and the second semiconductor package 10b connects the first sub-wire 731 and the Since the third signal ③ is received or output through the second sub-wire 732, the transmission distance of the third signal ③ from the third input/output pad 763 to the first semiconductor package 10a is described above. A large difference from the transmission distance of the third signal ③ from the first input/output pad 761 to the second semiconductor package 10b occurs.

As described above, the first signal (①) transmission distance and the third signal (③) transmission distance of the second semiconductor package 10b are respectively the first signal (①) transmission distance and the third signal transmission distance of the first semiconductor package 10a. (③) If it is longer than the transmission distance, delay of the first signal (①) and the third signal (③) may occur in the second semiconductor package 10b.

Hereinafter, a semiconductor device according to another exemplary embodiment capable of reducing signal delay will be described.

9 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 9 is different from the semiconductor device according to FIG. 7 in that the second semiconductor package 10b is provided to be turned upside down on the substrate 700 . Therefore, different configurations will be described below.

As can be seen in FIG. 9 , a first semiconductor package 10a and a second semiconductor package 10b are provided on a substrate 700 .

The first semiconductor package 10a and the second semiconductor package 10b have the same structure, but are mounted on the substrate 700 in different shapes.

Specifically, the semiconductor chip 100 of the first semiconductor package 10a is disposed to face upward, while the semiconductor chip 100 of the second semiconductor package 10b is disposed to face downward. In addition, in the case of the first semiconductor package 10a, the electrode 200 for receiving or outputting the first signal ① is disposed on the left side of the first semiconductor package 10a and receives or outputs the second signal ②. Although the electrode 200 for receiving or outputting the same signal as the first signal (①) is disposed on the right side of the first semiconductor package 10a, in the case of the second semiconductor package 10b, the electrode 200 An electrode 200 disposed on the right side of the second semiconductor package 10b and receiving or outputting the same signal as the second signal ② is disposed on the left side of the second semiconductor package 10b.

According to this arrangement structure, in the case of the first semiconductor package 10a, the second electrode pad 210b receiving or outputting the first signal ① and receiving or outputting the second signal ② The second electrode pad 210b is disposed to face downward and is in contact with the connection pad 750 on the substrate 700 . In contrast, in the case of the second semiconductor package 10b, the first electrode pad 210a receives or outputs the first signal ① and the first electrode pad receives or outputs the second signal ②. 210a is disposed to face downward and is in contact with the connection pad 750 on the substrate 700 .

FIG. 10 is a schematic plan view of a semiconductor device according to another embodiment of the present invention, which shows an example of a wiring structure formed on a substrate 700 in the semiconductor device according to FIG. 9 .

As can be seen from FIG. 10 , the first semiconductor package 10a and the second semiconductor package 10b are formed adjacent to each other on the substrate 700 .

The first semiconductor package 10a and the second semiconductor package 10b have the same configuration as shown in FIG. 9 and are mounted on the substrate 700 in different shapes.

The first semiconductor package 10a includes a second electrode pad 210b for receiving or outputting a first signal ①, a second signal ②, a third signal ③, and a fourth signal ④. and the second semiconductor package 10b receives or outputs the first signal ①, the second signal ②, the third signal ③, and the fourth signal ④. One electrode pad 210a is provided.

The second electrode pad 210b of the first semiconductor package 10a receiving or outputting the first signal ① is the part of the second semiconductor package 10b receiving or outputting the first signal ①. It is disposed at a position different from that of the first electrode pad 201a. For example, the second electrode pad 210b of the first semiconductor package 10a receiving or outputting the first signal ① is disposed on the upper left side of the first semiconductor package 10a, while the second electrode pad 210b of the first semiconductor package 10a The first electrode pad 201a of the second semiconductor package 10b that receives or outputs signal 1 (①) is disposed on the upper right side of the second semiconductor package 10b.

The second electrode pad 210b of the first semiconductor package 10a that receives or outputs the second signal ② is the part of the second semiconductor package 10b that receives or outputs the second signal ②. It is disposed at a position different from that of the first electrode pad 201a. For example, the second electrode pad 210b of the first semiconductor package 10a receiving or outputting the second signal ② is disposed on the upper right side of the first semiconductor package 10a, while the second electrode pad 210b of the first semiconductor package 10a The first electrode pad 201a of the second semiconductor package 10b for receiving or outputting the second signal ② is disposed on the upper left side of the second semiconductor package 10b.

The second electrode pad 210b of the first semiconductor package 10a that receives or outputs the third signal ③ is the part of the second semiconductor package 10b that receives or outputs the third signal ③. It is disposed at a position different from that of the first electrode pad 201a. For example, the second electrode pad 210b of the first semiconductor package 10a receiving or outputting the third signal ③ is disposed on the lower left side of the first semiconductor package 10a, while the second electrode pad 210b of the first semiconductor package 10a is disposed. The first electrode pad 201a of the second semiconductor package 10b for receiving or outputting 3 signals ③ is disposed on the lower right side of the second semiconductor package 10b.

The second electrode pad 210b of the first semiconductor package 10a that receives or outputs the fourth signal ④ is the second electrode pad 210b of the second semiconductor package 10b that receives or outputs the fourth signal ④. It is disposed at a position different from that of the first electrode pad 201a. For example, the second electrode pad 210b of the first semiconductor package 10a receiving or outputting the fourth signal ④ is disposed on the lower right side of the first semiconductor package 10a, while the second electrode pad 210b of the first semiconductor package 10a The first electrode pad 201a of the second semiconductor package 10b for receiving or outputting 4 signals ④ is disposed on the lower left side of the second semiconductor package 10b.

According to this arrangement structure, the second electrode pad 210b of the first semiconductor package 10a and the first electrode pad 210a of the second semiconductor package 10b facing each other receive or receive the same signal. print out For example, the second electrode pad 210b receiving or outputting the second signal ② from the first semiconductor package 10a receives or outputs the second signal ② from the second semiconductor package 10b. facing the first electrode pad 210a. In addition, the second electrode pad 210b receiving or outputting the fourth signal ④ from the first semiconductor package 10a receives or outputs the fourth signal ④ from the second semiconductor package 10b. It faces the first electrode pad 210a.

On the substrate 700, a plurality of connection pads 750, a plurality of wires 711, 712, 721, 722, 731, 732, 741, and 742, and a plurality of input/output pads 761, 762, 763, and 764 are provided. is formed

The plurality of connection pads 750 correspond to the plurality of second electrode pads 210b of the first semiconductor package 10a and the plurality of first electrode pads 210a of the second semiconductor package 10b in one-to-one correspondence. connected while In this case, the plurality of connection pads 750 may be formed to overlap the plurality of second electrode pads 210b and the plurality of first electrode pads 210a.

The plurality of wires 711 , 712 , 721 , 722 , 731 , 732 , 741 , and 742 connect the plurality of connection pads 750 and the plurality of input/output pads 761 , 762 , 763 , and 764 .

The plurality of wires 711, 712, 721, 722, 731, 732, 741, and 742 are connection pads overlapping the first and second electrode pads 210a and 210b for receiving or outputting the first signal ①. 750 and the first wires 711 and 712 connecting between the first input/output pads 761 and overlapping the first and second electrode pads 210a and 210b for receiving or outputting the second signal ②. second wirings 721 and 722 connecting between the connection pad 750 and the second input/output pad 762, the first and second electrode pads 210a and 210b receiving or outputting the third signal ③, and Third wirings 731 and 732 connecting between the overlapping connection pads 750 and the third input/output pads 763, and first and second electrode pads 210a for receiving or outputting a fourth signal ④, 210b) and fourth wires 741 and 742 connecting between the overlapping connection pad 750 and the fourth input/output pad 764 .

The first wires 711 and 712 are first sub-wires 711 extending from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the first input/output pad 761. ) and a second sub-wire 712 extending from the connection pad 750 overlapping the first electrode pad 210a of the second semiconductor package 10b to the first input/output pad 761. Accordingly, the first semiconductor package 10a receives or outputs the first signal ① through the first sub-wire 711, and the second semiconductor package 10b receives or outputs the first signal ① through the second sub-wire 712. The first signal (①) is received or output.

The second wires 721 and 722 are connected to the first electrode pad 210a of the second semiconductor package 10b at the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a. It includes a first sub-wire 721 extending to the overlapping connection pad 750 and a second sub-wire 722 extending from the first sub-wire 721 to the second input/output pad 762 . Accordingly, both the first semiconductor package 10a and the second semiconductor package 10b receive or output the second signal ② through the first sub-wire 721 and the second sub-wire 722 .

The third wires 731 and 732 are first sub-wires 731 extending from the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a to the third input/output pad 763. ) and a second sub-wire 732 extending from the connection pad 750 overlapping the first electrode pad 210a of the first semiconductor package 10a to the third input/output pad 763. Accordingly, the first semiconductor package 10a receives or outputs the third signal ③ through the first sub-wire 731, and the second semiconductor package 10b receives or outputs the third signal ③ through the second sub-wire 732. Receives or outputs the third signal (③).

The fourth wires 741 and 742 are connected to the first electrode pad 210a of the second semiconductor package 10b at the connection pad 750 overlapping the second electrode pad 210b of the first semiconductor package 10a. It includes a first sub-wire 741 extending to the overlapping connection pad 750 and a second sub-wire 742 extending from the first sub-wire 741 to the fourth input/output pad 764 . Accordingly, both the first semiconductor package 10a and the second semiconductor package 10b receive or output the fourth signal ④ through the first sub-wire 741 and the second sub-wire 742 .

As in the foregoing embodiment, the first signal (①), the second signal (②), the third signal (③), and the fourth signal (④) are a common voltage such as VDD or a reference voltage, or It may be another common signal, and accordingly, the first signal (①), the second signal (②), the third signal (③), and the first Each of the four signals ④ may be simultaneously supplied to the first semiconductor package 10a and the second semiconductor package 10b.

In the semiconductor device according to another embodiment of the present invention, the first semiconductor package 10a receives or outputs the first signal ① through the first sub-wire 711, and the second semiconductor package ( 10b) receives or outputs the first signal ① through the second sub-wire 712, the difference between the length of the first sub-wire 711 and the length of the second sub-wire 712 When is reduced, the transmission distance of the first signal ① from the first input/output pad 761 to the first semiconductor package 10a and the first input/output pad 761 to the second semiconductor package 10b The difference between signal (①) transmission distances can be minimized.

Similarly, the first semiconductor package 10a receives or outputs the third signal ③ through the first sub-wire 731, and the second semiconductor package 10b receives or outputs the third signal ③ through the second sub-wire 732. Since the third signal ③ is received or output, when the difference between the length of the first sub-wire 731 and the length of the second sub-wire 732 is reduced, the third input/output pad 763 A difference between the transfer distance of the third signal ③ from the first semiconductor package 10a and the transfer distance of the third signal ③ from the third input/output pad 763 to the second semiconductor package 10b can be minimized. there is.

In addition, since both the first semiconductor package 10a and the second semiconductor package 10b receive or output the second signal ② through the first sub-wire 721 and the second sub-wire 722, , The transmission distance of the second signal ② from the second input/output pad 762 to the first semiconductor package 10a and the second signal from the second input/output pad 762 to the second semiconductor package 10b ( ②) The transmission distance can be made the same.

Similarly, the first semiconductor package 10a and the second semiconductor package 10b both receive or output the fourth signal ④ through the first sub-wire 741 and the second sub-wire 742. , the transmission distance of the fourth signal ④ from the fourth input/output pad 764 to the first semiconductor package 10a and the fourth signal from the fourth input/output pad 764 to the second semiconductor package 10b ( ④) The transmission distance can be made the same.

As such, according to another embodiment of the present invention, the difference between the first signal (①) transmission distance of the first semiconductor package 10a and the first signal (①) transmission distance of the second semiconductor package 10b and It is possible to reduce the difference between the transmission distance of the third signal ③ of the first semiconductor package 10a and the transmission distance of the third signal ③ of the second semiconductor package 10b. The transmission distance of the second signal ② is the same as the transmission distance of the second signal ② of the second semiconductor package 10b, and the transmission distance of the fourth signal ④ of the first semiconductor package 10a is equal to that of the second semiconductor package 10a. Since the transmission distance of the fourth signal ④ of the package 10b may be the same, the problem of signal delay in the first and second semiconductor packages 10a may be minimized.

8 and 10 above show structures of wirings 711, 712, 721, 722, 731, 732, 741, and 742 formed on a substrate 700 according to various embodiments of the present invention. The structures of the wires 711 , 712 , 721 , 722 , 731 , 732 , 741 , and 742 may be variously changed without being limited thereto.

As described above, according to an embodiment of the present invention, the electrode 200 connected to the signal pad 110 of the semiconductor chip 100 is configured to extend from the bottom to the top of the semiconductor package 10, and the electrode ( Since the first electrode pad 210a and the second electrode pad 210b exposed to the outside are formed on the upper and lower surfaces of the semiconductor chip 200, the signal pad 110 provided on the semiconductor chip 100 is formed on the substrate 700. ), the first electrode pad 210a provided on the upper surface of the semiconductor package 10 may be connected to the connection pad 750 on the substrate 700 while facing the In a state where the pad 110 does not face the substrate 700, the second electrode pad 210b provided on the lower surface of the semiconductor package 10 may be connected to the connection pad 750 on the substrate 700.

Accordingly, the degree of freedom of the wirings 711 , 712 , 721 , 722 , 731 , 732 , 741 , and 742 formed on the substrate 700 is increased to minimize the signal delay of the semiconductor package 10 . The structure of (711, 712, 721, 722, 731, 732, 741, 742) can be freely changed.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The protection scope of the present invention should be construed according to the scope of the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

10: semiconductor package 100: semiconductor chip
110: signal pad 200: electrode
210a: first electrode pad 210b: second electrode pad
300: wire 400: insulating layer
500: support 550: adhesive layer
600: heat sink 700: substrate
711, 712, 721, 722, 731, 732, 741, 742: Wiring
750: connection pad
761, 762, 763, 764: first, second, third, fourth input/output pads

Claims (13)

Board; and
It includes a first semiconductor package and a second semiconductor package provided adjacent to the substrate,
Each of the first and second semiconductor packages,
a semiconductor chip having a plurality of signal pads;
a plurality of electrodes electrically connected to the plurality of signal pads;
a first electrode pad contacting an upper surface of each of the plurality of electrodes;
a second electrode pad in contact with a lower surface of each of the plurality of electrodes; and
An insulating layer provided between the semiconductor chip and the plurality of electrodes,
The plurality of electrodes extend in a vertical direction from an upper portion to a lower portion of the insulating layer, the first electrode pad is exposed to the outside from the upper surface of the insulating layer, and the second electrode pad is exposed to the outside from the lower surface of the insulating layer. exposed as
The plurality of signal pads of the first semiconductor package do not face the substrate, and the plurality of signal pads of the second semiconductor package face the substrate. According to claim 1,
The structure of the plurality of electrodes, the first electrode pad and the second electrode pad is provided in a straight line from the upper surface to the lower surface of the semiconductor package. According to claim 1,
The semiconductor device according to claim 1 , wherein in a plan view, areas of lower surfaces and upper surfaces of the plurality of electrodes are equal to each other. According to claim 1,
The semiconductor device of claim 1 , wherein the plurality of electrodes are provided on an outermost line of the semiconductor package, and one side surface of the plurality of electrodes is exposed to the outside. According to claim 1,
The plurality of electrodes are provided inside an outermost line of the semiconductor package, and side surfaces of the plurality of electrodes are surrounded by the insulating layer. According to claim 1,
Further comprising a plurality of wires connecting between the plurality of signal pads and the plurality of electrodes,
The plurality of electrodes include a first portion extending in a horizontal direction and a second portion extending in a vertical direction from one end of the first portion,
One end of the plurality of wires is connected to the first part and the other end of the plurality of wires is connected to the plurality of signal pads. According to claim 1,
a support provided under the semiconductor chip to support the semiconductor chip; and
The semiconductor device further comprising a heat dissipation plate provided under the support. delete According to claim 1,
A plurality of connection pads electrically connected to a plurality of electrodes of each of the first semiconductor package and the second semiconductor package are provided on the substrate;
The plurality of connection pads contact the second electrode pad of the first semiconductor package and the first electrode pad of the second semiconductor package. According to claim 9,
The semiconductor device of claim 1 , wherein the second electrode pad provided on the left side of the first semiconductor package and the first electrode pad provided on the right side of the second semiconductor package receive or output the same first signal. According to claim 10,
On the substrate, a first input/output pad for inputting or outputting the first signal and a first wire connecting the first input/output pad and the plurality of connection pads are included,
The first wiring includes a first sub-wire extending from a connection pad contacting the second electrode pad for receiving or outputting the first signal to the first input/output pad, and the first sub-wire for receiving or outputting the first signal. A semiconductor device comprising a second sub-wire extending from a connection pad contacting an electrode pad to the first input/output pad. According to claim 9,
The second electrode pad provided on the right side of the first semiconductor package and the first electrode pad provided on the left side of the second semiconductor package face each other and receive or output the same second signal. According to claim 12,
On the substrate, a second input/output pad for inputting or outputting the second signal and a second wire connecting the second input/output pad and the plurality of connection pads are included,
The second wiring is a first sub-wire extending from a connection pad in contact with the second electrode pad receiving or outputting the second signal to a connection pad in contact with the first electrode pad receiving or outputting the second signal; and a second sub-wire extending from the first sub-wire to the second input/output pad.

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