KR102526214B1 - Transition metal oxide based 3dimensional structure neuromorphic device and method of manufacturing the same - Google Patents

Abstract

A transition metal oxide-based three-dimensional neuromorphic device having threshold switching characteristics and resistance change memory characteristics depending on the thickness of an electrode and a manufacturing method thereof are disclosed. The transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention comprises: a switching array comprising a switching layer configured to have threshold switching characteristics; a memory array stacked on the switching array and comprising a memory layer configured to have resistance change memory characteristics; a first electrode formed in a through hole penetrating the switching array and the memory array; and a transition metal oxide layer formed in a region between the first electrode and the inner surface of the through hole. The switching layer comprises a switching electrode layer having a first thickness. The memory layer comprises a memory electrode layer having a second thickness greater than the first thickness.

Description

Transition metal oxide based 3dimensional structure neuromorphic device and method of manufacturing the same}

The present invention relates to a three-dimensional structure neuromorphic device, and more particularly, to a transition metal oxide-based three-dimensional structure neuromorphic device having threshold switching characteristics and resistance change memory characteristics depending on the thickness of an electrode and a manufacturing method thereof. will be.

Resistive switching memory (RRAM) enables the smallest cell size and low power, and is an important element replacing conventional charge-based memories or filling a performance gap in computing systems. To maximize memory density and perform various functions such as neuromorphic computing that mimics the brain, RRAM is implemented with a crossbar array architecture in which input and output lines are perpendicular to each other. Since the memory cells are connected to the crossbar array, a selector must be incorporated into each memory. Therefore, the 1S-1R structure including one selector and one RRAM prevents unwanted sneak-path currents in adjacent cells, so that stored data can be read accurately.

A two-terminal electronics exhibiting a nonlinear current-voltage (IV) response was used as the selector. To date, several physical mechanisms have been explored, such as the reversible metal-insulator transition (MIT), tunnel (or Schottky) barrier modulation, trap-related conduction and self-dissolved labile filament dynamics. A recent study demonstrated that a threshold selector that abruptly changes from an off state to an on state at a certain threshold voltage (V _th ) allows sufficient read/write margin. Although the requirement for an additional selector is obvious, the vertically thickened unit cell due to the 1S-1R configuration leads to integration challenges related to the complexity of the process.

An object of the present invention is to provide a transition metal oxide-based three-dimensional structured neuromorphic device having threshold switching characteristics and resistance change memory characteristics according to the size (thickness) of an electrode layer in contact with a transition metal oxide layer and a manufacturing method thereof.

A transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention includes a switching array including one or more switching layers configured to have threshold switching characteristics; a memory array stacked on the switching array and including one or more memory layers configured to have resistance variable memory characteristics; one or more first electrodes formed in a pillar shape in one or more through holes formed through the switching array and the memory array; a plurality of second electrodes including one or more switching electrodes electrically connected to the switching layer and one or more memory electrodes electrically connected to the memory layer; and one or more transition metal oxide layers formed in a ring shape in a region between the first electrode and an inner surface of the through hole and containing a transition metal oxide.

The switching layer includes a first insulating layer and a switching electrode layer laminated on the first insulating layer to have a first thickness and electrically connected to the switching electrode. The memory layer includes a second insulating layer and a memory electrode layer laminated on the second insulating layer to have a second thickness greater than the first thickness and electrically connected to the memory electrode.

The first thickness may be greater than 0 nm and less than or equal to 60 nm, and the second thickness may be greater than or equal to 100 nm and less than or equal to 2 um.

The transition metal oxide may be an oxide of at least one type of transition metal selected from the group consisting of Nb, VO, Ti, and Ta.

The first electrode may be an Al electrode, and the transition metal oxide may include NbO ₂ .

The transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention may further include a current limiting circuit that limits the current flowing through the first electrode to an allowable current value or less. The current limiting circuit may change the memory layer to have threshold switching characteristics by adjusting the allowable current value.

The transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention may further include a hybrid array including one or more hybrid layers stacked on the switching array and the memory array. The hybrid layer may have a third thickness greater than the first thickness and less than the second thickness to have a hybrid threshold switching characteristic and a resistance change memory characteristic.

The first thickness may be greater than 0 nm and less than or equal to 60 nm, the second thickness may be greater than 100 nm and less than or equal to 2 um, and the third thickness may be greater than 60 nm and less than 100 nm.

According to an embodiment of the present invention, a processing-in-memory computing device including the transition metal oxide-based three-dimensional neuromorphic device may be provided.

A method for manufacturing a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention includes forming a switching array including one or more switching layers having threshold switching characteristics; forming a memory array including one or more memory layers having resistance variable memory characteristics to be stacked on the switching array; forming one or more through holes to pass through the switching array and the memory array; forming a transition metal oxide layer containing a transition metal oxide in a ring shape on an inner surface of the through hole; forming one or more first electrodes having a pillar shape in the ring-shaped transition metal oxide layer; and forming a plurality of second electrodes including one or more switching electrodes and one or more memory electrodes to be electrically connected to the switching layer and the memory layer.

Forming the switching array includes stacking a switching electrode layer on the first insulating layer to have a first thickness. The forming of the memory array includes stacking a memory electrode layer on a second insulating layer to have a second thickness greater than the first thickness.

The method of fabricating a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention may further include forming a current limiting circuit that limits the current flowing through the first electrode to an allowable current value or less. there is.

The method for manufacturing a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention may further include forming a hybrid array including one or more hybrid layers to be stacked on the switching array and the memory array. there is.

According to an embodiment of the present invention, a transition metal oxide-based three-dimensional structure neuromorphic device having threshold switching characteristics and resistance change memory characteristics according to the size (thickness) of an electrode layer in contact with a transition metal oxide layer and a manufacturing method thereof are provided. .

1 is a perspective view illustrating a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention.
2 to 7 are exemplary diagrams for explaining a method of manufacturing a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention.
8 is a conceptual diagram illustrating a three-dimensional neuromorphic device based on a transition metal oxide according to another embodiment of the present invention.
9 and 10 are conceptual views illustrating a three-dimensional neuromorphic device based on a transition metal oxide according to various embodiments of the present disclosure.
11 is a transmission electron microscope (TEM) image of a W/NbOx/TiN device.
12 is an X-ray photoelectron spectroscopy (XPS) analysis result of the W/NbOx/TiN device.
13 is a graph showing current-voltage (IV) characteristics of a W/NbOx/TiN device.
14 is a graph showing current-voltage characteristics of an Al/NbOx/TiN device.
15 is a current-voltage characteristic of an Al/NbOx/TiN device having a device size of 70 nm.
16 is a graph showing the cumulative probability characteristics according to the current of the Al/NbOx/TiN device.
17 is a TEM image of an Al/NbOx/TiN device.
18 is an energy dispersive X-ray (EDX) line scan result of an Al/NbOx/TiN device.
19 is an XPS analysis result of an Al/NbOx/TiN device.
20 is a graph illustrating multilevel cell hybrid memory operation according to a reset voltage.
21 is a TEM image of a Cu/NbOx/TiN device.
22 is a graph showing current-voltage characteristics of a Cu/NbOx/TiN device.
23 is a current-voltage characteristic graph showing the development of a hybrid memory after an initial stage of a Cu/NbOx/TiN device.
24 is a conceptual diagram showing the mechanism of observed hybrid memory operation.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited to the following examples. This embodiment is provided to more completely explain the present invention to those skilled in the art. Accordingly, the shapes of elements in the figures are exaggerated to emphasize clearer description.

The configuration of the present invention for clarifying the solution to the problem to be solved by the present invention will be described in detail with reference to the accompanying drawings based on a preferred embodiment of the present invention, but the same reference numerals are assigned to the components of the drawings. For components, even if they are on other drawings, the same reference numerals have been given, and it is made clear in advance that components of other drawings can be cited if necessary in the description of the drawings.

Meanwhile, directional terms such as upper side, lower side, one side, and the other side are used in relation to the orientation of the disclosed drawings. Since components of embodiments of the present invention may be positioned in a variety of orientations, directional terms are used for purposes of illustration and not limitation.

Also, terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention.

1 is a perspective view illustrating a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention. Referring to FIG. 1 , a transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention includes one or more switching arrays 110, one or more memory arrays 120 stacked on the switching array 110, It may include one or more transition metal oxide layers 130 , one or more first electrodes 140 , and a plurality of second electrodes 150 and 160 .

The switching array 110 may include one or more switching layers 111 and 112 configured to have threshold switching characteristics. The switching layers 111 and 112 may include a switching electrode layer 111 and a first insulating layer 112 . The switching electrode layer 111 may be stacked on the first insulating layer 112 to have a first thickness T1. To implement threshold switching characteristics, the switching electrode layer 111 may be formed to have a first thickness T1 of greater than 0 nm and less than 60 nm.

The switching electrode layer 111 may be electrically connected to the switching electrodes constituting the plurality of second electrodes 150 and 160 . The first insulating layer 112 may be formed of, for example, an insulating material such as silicon nitride, but is not limited to this example. The switching electrode layer 111 may be made of a conductive electrode material such as platinum (Pt) or aluminum (Al), but is not limited to these examples.

The memory array 120 may include one or more memory layers 121 and 122 configured to have variable resistance memory characteristics. The memory layers 121 and 122 may include a memory electrode layer 121 and a second insulating layer 122 . The memory electrode layer 121 may be stacked on the second insulating layer 122 to have a second thickness T2 greater than the first thickness T1 of the switching electrode layer 111 . In order to implement resistance-variable memory characteristics, the memory electrode layer 121 may be formed to have a second thickness T2 of 100 nm or more and 2 um or less.

The number of each layer of the switching array 110 and the memory array 120 may be, for example, between 1 and 176 layers. The number of layers may be designed identically or differently. Various combinations of the number of layers and repetitive arrangement structures of the switching array 110 and the memory array 120 are possible according to logic functions (AND, OR, NAND, XOR, etc.) to be implemented.

The memory electrode layer 121 may be electrically connected to memory electrodes constituting the plurality of second electrodes 150 and 160 . The second insulating layer 122 may be formed of, for example, an insulating material such as silicon nitride, but is not limited to this example. The memory electrode layer 121 may be formed of, for example, a conductive electrode material such as platinum (Pt) or aluminum (Al), but is not limited to these examples.

The first electrode 140 may be formed in a pillar shape in one or more through holes formed through the switching array 110 and the memory array 120 . The first electrode 140 may preferably be an Al electrode. When the reactive Al electrode is used as the first electrode 140, the present inventors have found that the thickness of the electrode layer (switching electrode layer, memory electrode layer) in contact with the transition metal oxide layer 130, that is, the width of the transition metal oxide layer 130 in the lateral direction. It was found that threshold switching characteristics and/or resistance change memory characteristics can be implemented according to.

For example, when the first electrode 140 is formed of NbOx transition metal oxide, when the electrode layer is implemented with highly reactive Al electrode, when the size (thickness of the electrode layer) of the electrode layer in contact with the NbOx transition metal oxide is large (for example, , about 2 μm level), when the memory switching (MS) is implemented and operates as a memory layer, and the size of the electrode layer in contact with the NbOx transition metal oxide (electrode layer thickness) becomes small (e.g., 50 nm or less ) Threshold switching (TS) is implemented to operate as a switching layer.

If the size (electrode layer thickness) of the electrode layer in contact with the NbOx transition metal oxide is large, when a voltage is applied to the first electrode or electrode layer, a chemical reaction occurs between the interfaces to form oxygen vacancies, and resistance change memory is affected by the oxygen vacancies. characteristics are implemented. In this way, when the size (thickness) of the electrode layer in contact with the NbOx transition metal oxide is large, the effect of the vacancies formed at the interface dominates, and resistance change memory characteristics are implemented.

In contrast, the size (thickness) of the electrode layer in contact with the NbOx transition metal oxide is small, the influence of vacancies formed at the interface is reduced, and the threshold switching characteristic of NbOx dominates to realize the threshold switching characteristic, and the electrode layer is not a memory. When the voltage is removed, it returns to the original off state. Experimentally, resistance change memory characteristics were observed when the size (thickness) of the electrode layer was 100 nm to 2 um, and threshold switching characteristics were confirmed when the size (thickness) of the electrode layer was 60 nm or less.

When the first electrode 140 is formed of a W or TiN electrode with little chemical reactivity rather than an Al electrode, as described above, hybrid characteristics according to the size (thickness) of the electrode layer in contact with the transition metal oxide layer are not implemented. , Like a switch, it is implemented as a threshold switching characteristic that changes between an off state and an on state according to the voltage applied to the first electrode 140 or the electrode layer regardless of the size (thickness) of the electrode layer.

The transition metal oxide layer 130 may be formed in a ring shape in a region between the first electrode 140 and the inner surface of the through hole. In order to implement threshold switching characteristics and resistance change memory characteristics according to electrode thicknesses of the switching electrode layer 111 and the memory electrode layer 121, the transition metal oxide layer 130 may include a transition metal oxide. In particular, the transition metal oxide layer 130 may include an oxide of at least one type of transition metal selected from the group consisting of Nb, VO, Ti, and Ta.

The second electrodes 150 and 160 may include one or more switching electrodes electrically connected to the switching electrode layer 111 of the switching layer and one or more memory electrodes electrically connected to the memory electrode layer 121 of the memory layer. . The second electrodes 150 and 160 may be made of an electrode material such as, for example, platinum (Pt), but are not limited to this example.

2 to 7 are exemplary diagrams for explaining a method of manufacturing a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention. Hereinafter, a method of manufacturing a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7 .

A method for manufacturing a three-dimensional neuromorphic device based on a transition metal oxide according to an embodiment of the present invention includes forming a switching array 110 including one or more switching layers having threshold switching characteristics, and in the switching array 110 and forming a memory array 120 including one or more memory layers having resistive memory characteristics to be stacked.

As shown in FIG. 2 , the switching array 110 may be formed by repeatedly stacking the first insulating layer 112 and the switching electrode layer 111 . Also, the memory array 120 may be formed by repeatedly stacking the second insulating layer 122 and the memory electrode layer 121 . Although the memory array 120 is stacked on top of the switching array 110 in FIG. 2 , it is also possible to stack the switching array 110 on top of the memory array 120 . Also, the switching array 110 and the memory array 120 may be alternately and repeatedly stacked.

To implement threshold switching characteristics, the switching electrode layer 111 may be formed to have a first thickness T1 of greater than 0 nm and less than 60 nm. In order to implement resistance change memory characteristics, the memory electrode layer 121 may be stacked to have a second thickness T2 greater than the first thickness T1 of the switching electrode layer 111 . Preferably, the memory electrode layer 121 may be formed to have a second thickness T2 of 100 nm or more and 2 um or less.

The first insulating layer 112 and the second insulating layer 122 may be formed by depositing an insulating material such as silicon nitride. The switching electrode layer 111 and the memory electrode layer 121 may be formed by depositing a conductive electrode material such as platinum (Pt) or aluminum (Al). The switching electrode layer 111 and the memory electrode layer 121 may be formed of the same electrode material or different electrode materials.

The memory electrode layer 121 may be electrically connected to memory electrodes constituting the plurality of second electrodes 150 and 160 . The second insulating layer 122 may be formed of, for example, an insulating material such as silicon nitride, but is not limited to this example. The memory electrode layer 121 may be formed of, for example, a conductive electrode material such as platinum (Pt) or aluminum (Al), but is not limited to these examples.

When the switching array 110 and the memory array 120 are stacked, in order to connect the switching electrode and the memory electrode to each switching electrode layer 111 of the switching array 110 and each memory electrode layer 121 of the memory array 120 As shown in FIG. 3 , an etching process may be performed such that a portion of the upper surface of the switching electrode layer 111 on which the second electrodes 150 and 160 are to be formed and a portion of the upper surface of the memory electrode layer 121 are exposed.

In addition, to form the transition metal oxide layer 130 and the first electrode 140 penetrating the switching array 110 and the memory array 120, the transition metal oxide layer 130 and the first electrode 140 are A plurality of through holes 130 penetrating the switching array 110 and the memory array 120 as shown in FIG. ') to form

Next, in order to implement threshold switching characteristics and resistance change memory characteristics according to the thickness of the switching electrode layer 111 and the memory electrode layer 121, as shown in FIG. 5, the switching array 110 and the memory array 120 are formed. A transition metal oxide layer 130 containing a transition metal oxide is formed in a ring shape on inner surfaces of the plurality of through holes 130' passing through. In an embodiment, the transition metal oxide layer 130 may be formed by depositing an oxide of at least one transition metal selected from the group consisting of Nb, VO, Ti, and Ta on the inner surface of the through hole 130'.

Subsequently, as shown in FIG. 6 , a first electrode 140 having a pillar shape is formed in each transition metal oxide layer 130 having a ring shape. The first electrode 140 may be formed in a pillar shape in one or more through holes 130 ′ that pass through the switching array 110 and the memory array 120 . The first electrode 140 may be formed by depositing, for example, an electrode material such as Al in the central groove of the transition metal oxide layer 130 .

Finally, as shown in FIG. 7, slits 170 are formed in units of switching/memory cells (hybrid memory cells), and switching electrodes and memory electrodes are included in the switching electrode layer 111 and the memory electrode layer 121, respectively. By connecting the second electrodes 150 and 160, a transition metal oxide-based three-dimensional neuromorphic device having switching/memory hybrid characteristics can be manufactured. The second electrodes 150 and 160 may be formed by depositing an electrode material such as platinum (Pt). Processes such as deposition or etching of each layer constituting the device may be performed using various deposition and etching methods well known in the art, including photolithography and dry etching. A detailed description will be omitted.

8 is a conceptual diagram illustrating a three-dimensional neuromorphic device based on a transition metal oxide according to another embodiment of the present invention. Referring to FIGS. 1 and 8 , the transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention is different from the above-described embodiment in that it further includes a current limiting circuit 180 .

The current limiting circuit 180 may limit the current flowing through the first electrode 140 of each switching/memory cell to a value less than or equal to an allowable current value. The current limiting circuit 180 may change the memory layers 121 and 122 to have threshold switching characteristics by adjusting the allowable current value. The allowable current value may be adjusted to, for example, around 1 mA, and it is possible to change from memory characteristics to switch characteristics by increasing or decreasing the size of the limiting current.

9 and 10 are conceptual views illustrating a three-dimensional neuromorphic device based on a transition metal oxide according to various embodiments of the present disclosure. The transition metal oxide-based three-dimensional neuromorphic device 100 shown in FIG. 9 is different from the above-described embodiment in that the switching array 110 is stacked on top of the memory array 120 . The transition metal oxide-based three-dimensional neuromorphic device 100 shown in FIG. 10 is different from the above-described embodiment in that the switching array 110 and the memory array 120 are alternately and repeatedly stacked. .

In addition, the transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention includes a hybrid array (not shown) including one or more hybrid layers stacked on the switching array 110 and the memory array 120. may include more. The thickness of the electrode layer of the hybrid layer is a third thickness that is greater than the first thickness of the switching electrode layer 111 of the switching array 110 and smaller than the second thickness of the memory electrode layer 121 of the memory array 120. formed to have hybrid characteristics of threshold switching characteristics and resistance change memory characteristics. The first thickness of the switching electrode layer 111 is greater than 0 nm and less than or equal to 60 nm, the second thickness of the memory electrode layer 121 is greater than or equal to 100 nm and less than or equal to 2 um, and the third thickness, which is the thickness of the electrode layer of the hybrid layer, is 60 nm greater than, but less than 100 nm.

As described above, the transition metal oxide-based three-dimensional neuromorphic device according to the embodiment of the present invention can be applied as a processing-in-memory computing device. The three-dimensional structure neuromorphic device can perform various operations by reading the resistance of each device cell at once, and can be applied to a computing environment that can implement various logic functions by combining a switching array and a memory array. do.

The transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention can transfer only the resistance values of each memory layer of the memory array by controlling the voltage applied to the switching array, and if necessary, the switching array can be switched. A boosting effect may be obtained in which resistance values of each memory layer of the memory array are changed and outputted by controlling the overall resistance value.

The transition metal oxide-based three-dimensional neuromorphic device according to an embodiment of the present invention is applied to artificial intelligence accelerators and artificial intelligence semiconductors in the form of being mounted on, for example, self-driving cars or pattern-recognizable semiconductor chips to improve recognition speed. , can contribute to securing stability, reducing power consumption, and increasing battery efficiency. In addition, neuromorphic and logic functions used for pattern recognition can be implemented in a small area, and processing-in-memory (or logic-in-memory) for neuromorphic or logic functions that read multiple layers of information simultaneously Various functions can be implemented using it.

Hereinafter, the implementation of threshold switching characteristics and resistance change memory characteristics according to the electrode width of a device based on NbOx transition metal oxide will be described. Embodiments of the present invention described below utilize NbOx to demonstrate hybrid memory characteristics in which a resistive switching operation is integrated with a selector operation. For example, thin amorphous NbOx, such as 50 nm thick, exhibits intrinsic volatile threshold switching (TS) properties. To enable memory switching (MS) in NbOx, a device environment capable of supplying oxygen vacancies or positive ions constituting the conductive filament (CF) is configured.

Through various physical analyzes, it was confirmed that in the Al/NbOx/TiN stack, oxygen vacancies may occur internally in the interfacial oxide layer formed by the chemical reaction between the highly reactive Al electrode and NbOx. Hybrid memory properties are observed when the effect of external vacancies is comparable to the intrinsic properties of NbOx. The memory switching (MS) feature is driven by the oxygen vacancy CF, while the threshold switching (TS) feature prevents leakage current, enabling multi-step cell operation.

Also, hybrid switching can be obtained using a Cu/NbOx/TiN stack. However, in this case, the effect of Cu CF dominates because the Cu electrode can provide ions from the outside infinitely. Thus, hybrid memory operation is achieved after memory switching (MS) is performed.

In this regard, a hybrid memory in which a selector (or memory) function is simultaneously implemented in a single memory element (or selector) is considered attractive for simplifying a cell stack. Hybrid switching characteristics based on the Metal-Insulator Transition (MIT) mechanism were demonstrated in NbO ₂ material exhibiting threshold switching (TS) behavior.

The phase and chemical composition of certain parts of NbO ₂ can be transformed using high compliance currents that generate significant amounts of heat in NbO ₂ . As a result, a bilayer structure containing oxygen-deficient NbOx and oxygen-rich Nb ₂ O ₅ was formed. These layers played the roles of threshold switching (TS) and memory switching (MS), respectively. Difficulties with fine-tuning the operating current and maintaining a particular material composition are related to the method used to electrically trigger the hybrid memory.

The present invention presents a design of a device and material stack for integrating a memory with a selector. In particular, the Al/NbOx/TiN and Cu/NbOx/TiN structures were used to create vacancies at interfaces or to provide mobile sources in external ion reservoirs. When the W/NbOx/TiN stack was used as a control device, threshold switching (TS), a unique characteristic of NbOx, was observed even when the device diameter was reduced from 2 μm to 30 nm. However, MS has been observed based on the formation and rupture of local conductive filaments (CFs) when oxygen vacancies or Cu ions are provided in the NbOx layer. In the present invention, the area dependence of the Al/NbOx/TiN stack and the effect of the mobile ion type are analyzed to discuss how hybrid switching characteristics can be achieved.

A pattern wafer in which TiN plugs of various sizes ranging from 2 to 30 nm were formed on a SiO ₂ /W/Si substrate was used. 50 nm thickness on a 3 TiN bottom electrode (BE) at room temperature by reactive sputtering of a 2-inch single Nb metal target in an Ar plasma containing 1.5 sccm of oxygen gas at an RF power of 100 W and an operating pressure of 5×10 ^{−3 .} of NbOx layer was deposited.

A 10 X 10 μm ² pattern was formed on the upper electrode (TE) through photolithography, and then by DC sputtering at room temperature using pure Ar (30 sccm) and a gas of 100 W power using a 2-inch W metal target. A 60 nm thick W upper electrode (TE) was deposited. For comparison, 40 nm-thick Al and Cu upper electrodes (TE) were respectively deposited using an electron beam evaporator with a deposition rate of 1 Å/s. The fabricated device was measured using an HP 4155B semiconductor parameter analyzer.

First, the electrical and physical properties of NbOx surrounded by a relatively stable W upper electrode (TE) and a TiN lower electrode (BE) were investigated. 11 is a transmission electron microscope (TEM) image of a W/NbOx/TiN device. As a result of transmission electron microscopy (TEM) analysis, there was no interfacial oxide layer between the electrode and NbOx, and an amorphous NbOx state was confirmed from the fast Fourier transform image.

12 is an X-ray photoelectron spectroscopy (XPS) analysis result of a W/NbOx/TiN device. The XPS spectrum of the W/NbOx/TiN structure shows the strength of the Nb 3d element. Although NbOx was composed of a mixed oxide containing NbO ₂ and Nb ₂ O ₅ , two peaks were mainly observed at binding energies of 204 and 207 eV representing NbO ₂ .

13 is a graph showing current-voltage (IV) characteristics of a W/NbOx/TiN device. Threshold switching (TS) was achieved when NbO ₂ was dominant, which was consistent with the IV characteristics of FIG. 13 measured through physical analysis for the W/NbOx/TiN structure. The IV measurement using the double sweep mode and the number of voltage steps of 101 was performed by applying a positive (or negative) voltage to the device's W upper electrode (or TiN lower electrode).

The initial isolation state, which was limited by a compliance current of 1 mA at a specific V _th , turned on and turned off as the voltage decreased to less than the hold voltage (V _hold ). In the next second sweep, although V _th was smaller, threshold switching (TS) was still observed. This indicates that a specific phase responsible for the threshold switching (TS) of NbOx is formed locally during the initial voltage sweep, similar to the formation process of the RRAM operation. Then, a small V _th is sufficient since only a local region is needed to induce the phase transition. Threshold switching (TS) was observed for various device sizes from 2 μm to 30 nm.

14 is a graph showing current-voltage characteristics of an Al/NbOx/TiN device. Figure 14 (a) shows the current-voltage characteristics of the relatively wide 2 μm wide Al/NbOx/TiN device, and Figure 14 (b) shows the relatively narrow 30 nm wide Al/NbOx/TiN device. It represents the current-voltage characteristic

Interestingly, in (a) of FIG. 14 and when the W upper electrode was replaced with an Al upper electrode, memory switching (MS) having a set operation was observed in the largest area of 2 μm × 2 μm. The on-state was changed by applying a negative voltage to the Al upper electrode, which can be explained as a filament switching mechanism. However, when the device area was reduced to 30 nm × 30 nm, the initial resistance level increased and threshold switching (TS) began to be observed, as shown in FIG. 14(b).

15 is a current-voltage characteristic of an Al/NbOx/TiN device with an intermediate device size of ~70 nm. In particular, threshold switching (TS) and memory switching (MS) were hybridized in a single Al/NbOx/TiN stack with an intermediate device size of ~70 nm as shown in Fig. 15 under the given measurement conditions. The I-V curve driven by a positive voltage is similar to that of normal threshold switching (TS). However, the direction of counterclockwise switching at negative voltage was opposite to that of threshold switching (TS). 16 is a graph showing the cumulative probability characteristics according to the current of the Al/NbOx/TiN device. Reproducible hybrid switching characteristics were observed for the Al/NbOx/TiN device as shown in FIG. 16 .

17 is a TEM image of an Al/NbOx/TiN device. Oxygen vacancies created at the Al top electrode (TE)/NbOx interface due to chemical reactions played an important role in the switching. A thin interfacial layer, which was not observed in the W/NbOx/TiN stack, was observed in the TEM image.

18 is an EDX (energy dispersive X-ray) line scan result of an Al/NbOx/TiN device. It shows that the Al top electrode (TE) absorbs oxygen more strongly from NbOx than the W top electrode (TE). XPS analysis was performed to confirm the physical properties of the interfacial oxide.

19 is an XPS analysis result of an Al/NbOx/TiN device. Samples were analyzed with a 200 um K-Alpha source and a constant analyzer energy of 151.2. Peaks at specific etch times were extracted from atomic % profiles obtained by single atomic depth profiling. Experimentally detected peaks were deconvolved and fitted using XPS Peak 4.1 software. Referring to FIG. 19, the Al peak in the bulk electrode region shows a binding energy of ~73 eV, which indicates that Al bonds only to other Al atoms.

However, the binding energy peak at 75.5 eV corresponding to the Al-O bond is noticeably closer to that of NbOx. This indicates that Al tends to attract and bind oxygen ions through a thermodynamically favored process, creating vacancies at the NbOx interface. Since this chemical reaction occurred across the interface, the number of pores created is proportional to the device area. Considering a large device area of 2 μm × 2 μm, many vacancies are included in the switching, so NbOx does not show TS, but rather, it is predicted that memory switching (MS) dominates due to vacancies, as shown in FIG. 14 (a) It became.

As the device size decreased, the effect of external vacancies became comparable to the intrinsic properties of NbOx and hybrid properties as shown in FIG. 15 were achieved. As can be seen from the threshold switching (TS) operation, the first positive voltage not only activated the MIT in a specific part of NbOx but also ensured the clustering of vacancies. As a result, a conductive filament (CF) was formed in the remaining area of NbOx to achieve a low-resistance state (LRS).

However, removing the applied voltage turned off the threshold switching (TS). A memory window of 10 or more can be achieved at a read voltage of 1.1 V because the conductive filament (CF) is still connected. Due to the negative voltage, the threshold switching (TS) is turned on again and the conductive filament (CF) is separated and becomes a high-resistance state (HRS).

The current in the low voltage region serving as the sneak path current was suppressed by threshold switching (TS). Assuming that the leakage current is measured at a half lead voltage of 0.55 V, it can be reduced 100 times as shown in FIG. 16 . When the number of vacancies participating in the conductive filament (CF) evolution was further reduced due to the reduced area of less than about 70 nm, the MIT characteristics of NbOx were observed as shown in FIG. 14(b).

These three different region-dependent switching modes indicate that the amount of NbOx vacancies, which is related not only to the device size but also to the film thickness, plays an important role. In the present invention, it was confirmed that a 70 X 70 nm ² device is optimal for a given 50 nm thick NbOx layer by adjusting the device size, which is one of the geometrical factors. Assuming that NbOx is thinner in an Al/NbOx/TiN device with a device size of 30 nm, the effect of memory switching (MS) can be strengthened as the distance between the holes forming the conductive filament (CF) is shortened. Therefore, hybrid switching can be implemented in a large area considering the volume aspect.

20 is a graph illustrating multilevel cell (MLC) hybrid memory operation according to a reset voltage (V _reset ). As shown in Figure 20, memory switching (MS) results from oxygen vacancy conducting filament (CF) evolution, thereby enabling multi-level cell (MLC) operation. At a given compliance current of 1mA, the larger the V _reset , the more conductive filament (CF) ruptures occurred, which suppressed the leakage current while increasing the HRS.

20, the red (or blue) series of the I-V curve in the positive (or negative) voltage region represents the setting (or resetting) operation of the hybrid device. At a given compliance current, the HRS read at 1.3 V, where the memory window was obtained, was continuously changed by reducing the reset voltage from -1.5 V to -2 V to enlarge the gap between the electrode and the separated CF. The leakage current was still significantly suppressed.

These MLC possibilities offer significant opportunities for hybrid memories in neuromorphic synaptic applications. A brain-inspired neuromorphic computing system designed to efficiently perform pattern recognition tasks has been implemented using a crossbar array architecture. Artificial synapses based on memory elements need selectors to work properly. In addition, recent simulation results have reported that using selectors with TS rather than exponential transitions can reduce the degradation of recognition accuracy in terms of system performance. However, demonstrating MLC operation in an integrated 1S-1R device is difficult. Therefore, the MLC hybrid memory according to an embodiment of the present invention is useful for neuromorphic synaptic and high-density memory applications.

Finally, an alternative hybrid memory structure using Cu/NbOx/TiN with a cell diameter of 70 nm to deliver Cu ions from an external reservoir was investigated. 21 is a TEM image of a Cu/NbOx/TiN device. As shown in FIG. 21, when the Cu upper electrode (TE) was used, NbOx was amorphous without interfacial oxide.

22 is a graph showing current-voltage characteristics of a Cu/NbOx/TiN device. As can be seen in FIG. 22, unexpectedly, the I-V curve represents memory switching (MS). The initial formation step at ~4 V induces a large number of Cu ions in the infinite Cu reservoir to migrate through NbOx to form Cu conducting filaments. The symbolic curve represents an initial sweep from 0 V through 5 V to -2 V. The curve represents the next sweep from -2 V to 2 V.

23 is a current-voltage characteristic graph showing the development of a hybrid memory after an initial stage of a Cu/NbOx/TiN device. 24 is a conceptual diagram showing the mechanism of observed hybrid memory operation. LRS was converted to HRS at -1 V during the reset operation. In particular, Cu conductive filaments are rapidly decomposed by thermal effects and electric fields, which is mainly observed when generating conductive filaments (CF) using highly mobile Cu (or Ag) ions, resulting in a rapid reset transition.

In particular, another upward transition was observed at -1.5 V when negative voltage was continuously applied. The changed state dropped as the voltage returned to zero, and the hybrid memory began to appear. That is, the next positive voltage sweep indicates a clockwise shift by increasing the resistance as shown in FIG. 23 .

Here, NbOx was used as the electrolyte to enable ion transport without exhibiting intrinsic threshold switching (TS). As in the conductive bridge RAM, 20 Cu conductive filaments (CF) were formed and separated during the first cycle. During the reset operation, the heat generated by the current flowing through the Cu conductive filament (CF) promotes the radial diffusion of Cu ions, causing some Cu atoms to agglomerate near the lower electrode (BE). At the same time, thermal effects can activate certain parts of NbOx. When the negative voltage is further increased, as shown in FIG. 24 , the dispersed Cu ions tend to reorganize, which corresponds to a negative set behavior.

As the negative voltage was removed, the current dropped rapidly at -1 V, which can be explained by a spontaneous return to the insulating state on metallic NbOx. The V _hold of ~±1V in the IV curve of the hybrid memory, similar to that obtained from the W/NbOx/TiN stack, provides an indirect clue to the formation of the MIT region. Even when the switching direction was reversed, the Cu conductive filament (CF) was still predominantly involved in the memory switching (MS) operation, as evidenced by the abrupt reset behavior at ~1.5 V.

For practical applications, the operating current, which was 1 mA in this work, should be as low as possible. Threshold switching (TS) can be implemented when a current exceeding a minimum threshold current of about several tens of μA is allowed. Therefore, the operating current of the hybrid memory is mainly determined by the compliance current related to the size of the conductive filament (CF). A limited amount CF source enables low operating current of less than 1mA. Therefore, compared to the Cu/NbOx/TiN stack, which can supply unlimited CF sources, the current can be lowered in the Al/NbOx/TiN stack because the degree of void generation can be precisely controlled by interface engineering.

As described above, in the present invention, a hybrid memory is implemented by integrating a conductive filament (CF) source into NbOx representing threshold switching (TS). First, it was confirmed that MIT-based TS was observed in a 50 nm thick amorphous NbOx layer. When using an Al top electrode, physical analysis identified the interfacial AlOx layer at the NbOx interface.

Oxygen vacancies were generated by chemical reactions, but the effect of the vacancies on the electrical behavior of the small size (30 nm) NbOx device was negligible. However, as the device area increases, as a result of vacancies participating in threshold switching (TS), MLC hybrid memories with limited sneak path current at a device size of 70 nm, which is considered to balance the effects of MIT and vacancy CF of NbOx, was created

Hybrid switching is possible even in a very small cell area by considering the balance by adjusting the number of vacancies. In addition, a hybrid memory in which the switching direction is reversed is implemented in a Cu/NbOx/TiN stack. However, since many Cu ions can be provided infinitely, unified memory characteristics are achieved after initial set and reset operations, forming an environment for MIT in NbOx.

The above detailed description is illustrative of the present invention. In addition, the foregoing is intended to illustrate and describe preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, changes or modifications are possible within the scope of the concept of the invention disclosed in this specification, within the scope equivalent to the written disclosure and / or within the scope of skill or knowledge in the art.

The written embodiment describes the best state for implementing the technical idea of the present invention, and various changes required in the specific application field and use of the present invention are also possible. Therefore, the above detailed description of the invention is not intended to limit the invention to the disclosed embodiments. Also, the appended claims should be construed to cover other embodiments as well.

100: transition metal oxide-based three-dimensional structure neuromorphic device
110: switching array
111: switching electrode layer
112: first insulating layer
120: memory array
121: memory electrode layer
122: second insulating layer
130: first electrode
140: transition metal oxide layer
150, 160: second electrode

Claims (15)

a switching array including one or more switching layers configured to have threshold switching characteristics;
a memory array stacked on the switching array and including one or more memory layers configured to have resistance variable memory characteristics;
one or more first electrodes formed in a pillar shape in one or more through holes formed through the switching array and the memory array;
a plurality of second electrodes including one or more switching electrodes electrically connected to the switching layer and one or more memory electrodes electrically connected to the memory layer; and
One or more transition metal oxide layers formed in a ring shape in a region between the first electrode and an inner surface of the through hole and containing a transition metal oxide;
The switching layer includes a first insulating layer and a switching electrode layer laminated on the first insulating layer to have a first thickness and electrically connected to the switching electrode,
The memory layer includes a second insulating layer and a memory electrode layer laminated on the second insulating layer to have a second thickness greater than the first thickness and electrically connected to the memory electrode, transition metal oxide-based 3 Dimensional structural neuromorphic device. The method of claim 1,
The first thickness is greater than 0 nm and less than or equal to 60 nm, and the second thickness is greater than or equal to 100 nm and less than or equal to 2 um. The method of claim 1,
The transition metal oxide is an oxide of at least one transition metal selected from the group consisting of Nb, VO, Ti, and Ta, a transition metal oxide-based three-dimensional structure neuromorphic device. The method of claim 1,
The first electrode is an Al electrode, and the transition metal oxide includes NbO ₂ , a transition metal oxide-based three-dimensional structure neuromorphic device. The method of claim 1,
A current limiting circuit for limiting the current flowing through the first electrode to an allowable current value or less; further comprising,
wherein the current limiting circuit changes the memory layer to have a threshold switching characteristic by adjusting the allowable current value. The method of claim 1,
A hybrid array including one or more hybrid layers stacked on the switching array and the memory array; further comprising;
The hybrid layer is formed to have a third thickness larger than the first thickness and smaller than the second thickness to have a hybrid characteristic of threshold switching characteristics and resistance change memory characteristics, a transition metal oxide-based three-dimensional structure neuromorphic device. The method of claim 6,
The first thickness is greater than 0 nm and less than or equal to 60 nm, the second thickness is greater than 100 nm and less than or equal to 2 um, and the third thickness is greater than 60 nm and less than 100 nm. pick element. A processing-in-memory computing device comprising the three-dimensional structure neuromorphic device based on any one of claims 1 to 7. forming a switching array including one or more switching layers having threshold switching characteristics;
forming a memory array including one or more memory layers having resistance variable memory characteristics to be stacked on the switching array;
forming one or more through holes to pass through the switching array and the memory array;
forming a transition metal oxide layer containing a transition metal oxide in a ring shape on an inner surface of the through hole;
forming one or more first electrodes having a pillar shape in the ring-shaped transition metal oxide layer; and
Forming a plurality of second electrodes including one or more switching electrodes and one or more memory electrodes to be electrically connected to the switching layer and the memory layer;
Forming the switching array includes stacking a switching electrode layer to have a first thickness on the first insulating layer,
Wherein the forming of the memory array comprises stacking a memory electrode layer on a second insulating layer to have a second thickness greater than the first thickness, a transition metal oxide-based three-dimensional structure neuromorphic device manufacturing method. The method of claim 9,
The first thickness is greater than 0 nm and less than or equal to 60 nm, and the second thickness is greater than or equal to 100 nm and less than or equal to 2 um. The method of claim 9,
The transition metal oxide is an oxide of at least one type of transition metal selected from the group consisting of Nb, VO, Ti, and Ta, transition metal oxide-based three-dimensional structure neuromorphic device manufacturing method. The method of claim 9,
wherein the first electrode is an Al electrode, and the transition metal oxide includes NbO ₂ , a transition metal oxide-based three-dimensional structure neuromorphic device manufacturing method. The method according to any one of claims 9 to 12,
Forming a current limiting circuit for limiting the current flowing through the first electrode to an allowable current value or less; further comprising,
Wherein the current limiting circuit changes the memory layer to have a threshold switching characteristic by adjusting the allowable current value. The method according to any one of claims 9 to 12,
forming a hybrid array comprising one or more hybrid layers to be stacked on the switching array and the memory array;
The hybrid layer is formed to have a third thickness larger than the first thickness and smaller than the second thickness to have a hybridized characteristic of threshold switching characteristics and resistance change memory characteristics, transition metal oxide-based three-dimensional structure neuromorphic device manufacturing method . The method of claim 14,
The first thickness is greater than 0 nm and less than or equal to 60 nm, the second thickness is greater than 100 nm and less than or equal to 2 um, and the third thickness is greater than 60 nm and less than 100 nm. Pick element manufacturing method.

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