KR102517217B1 - Memristor device for reducing variations of the device parameters - Google Patents

Abstract

A memristor device according to an embodiment of the present invention includes a lower electrode, an epitaxially grown silicon-germanium layer formed on the lower electrode, a dielectric layer formed on the silicon-germanium layer, and a silicon nitride film layer formed on the A via hole and an upper electrode layer formed on top of the via hole, wherein the silicon-germanium layer is formed through a germanium ion implantation process for inducing low-dimensional defects provided as a passage for metal ions in the upper electrode layer. do. According to the memristor device having the above-described structure, low-dimensional defects are induced in the epitaxially grown silicon-germanium layer, and ions of the upper electrode move along the defects. As a result, the filament formation process performed at high voltage can be omitted, and the operating voltage and operating voltage fluctuations are reduced. In addition, it is possible to implement a memristor device in which linearity of synaptic weight update is greatly improved.

Description

Memristor device with reduced parameter variation {MEMRISTOR DEVICE FOR REDUCING VARIATIONS OF THE DEVICE PARAMETERS}

The present invention relates to a semiconductor device, and more particularly, to a memristor device capable of reducing variations in device parameters.

As the computing paradigm shifts from operations-centric systems to data-centric systems, existing von Neumann systems will face performance limitations in the near future in terms of energy efficiency and scalability. This performance limitation, called the von Neumann bottleneck, is due to the limited throughput of the data bus between the central processor and memory. To address this problem, a brain-inspired neuromimetic computing architecture has been proposed.

A neuromorphic computing architecture does not have a physically separate memory and processor, but they coexist. Loihi, BrainScales, Spinnaker, Truenorth and many other computing chips named Tianjic have been developed by industrial and academic research institutions around the world. However, most of the proven neuromorphic hardware chips are based on CMOS neurons and synapses. Although CMOS-based neuromimetic chips have higher computing efficiency compared to existing von Neumann-based systems, they aim to mimic the human brain and require extensive further improvements.

CMOS-based synaptic devices or transistors are not non-volatile, which limits the power efficiency of neuromimetic computing systems, consuming power to retain information even when idle. In addition, since the unit memory based on the synaptic CMOS circuit includes multiple transistors, the area cost of the CMOS-based synaptic device is high. Replacing CMOS synapses with highly scalable, emerging non-volatile memory devices has been reported as one solution to improve efficiency.

Among non-volatile memories, resistive memory (ReRAM) or memristor devices are one of the most promising synaptic devices in that they meet many requirements to be used as synaptic devices for neuromimetic applications. ReRAM devices have been demonstrated by many research groups to have very promising memristor parameters (long endurance, fast read and write times, high on/off ratio, low synaptic actuation energy and multi-level states). However, all parameters have not yet been realized in a single ReRAM device. Furthermore, variations in device parameters have been an obstacle to implementing ReRAM devices with large-scale crossbar arrays.

A conductive bridging random access memory (hereinafter referred to as CBRAM) is one of representative ReRAM devices composed of an upper electrode, a switching active layer, and a lower electrode. An active metal such as silver (Ag) or copper (Cu) is generally used as an upper electrode, and an inert metal is used as a lower electrode. As an active layer between the upper and lower electrodes, a semiconductor or dielectric thin film layer such as amorphous silicon (a-Si), SiOx, TiOx, WOx, and SiGex is inserted. In general, a virgin device has a high resistance value because there is no conductive path. A conductive filament composed of an active metal is formed by a forming process in which a strong electrical bias is applied to the device. When an electrical bias of opposite polarity is applied, the conductive filament ruptures, resulting in a high resistance state.

Formation and rupture of conductive filaments in ReRAM devices are inherently stochastic. As a result, device parameters such as set and reset voltages and resistance states change greatly. Also, the build process is generally more aggressive than the set and reset process, which can damage the device. Various approaches, such as a multilayer structure, a mixture of nanoparticles, and a nanostructure, have been proposed to reduce device variation and realize a forming-free device.

Recently, several interesting studies have been reported employing low-dimensional defects as conductive pathways for metal ions. Because lower-order defects such as dislocations and grain boundaries are structurally more open, they can serve as fast transport pipelines for metal and oxygen ions in resistive memory devices. In epitaxial SiGe alloy films, SrTiO3 single crystal films, and metal-derived crystalline polysilicon films, threading dislocations at grain boundaries act as conductive filament formation sites. Ion transport is limited along the low-dimensional defects that exist in the virgin state of the device, and therefore, cell-to-cell and cycle-to-cycle changes that occur in stochastic filament formation are SiGe and poly-Si based CBRAM devices can be reduced in

An object of the present invention is to provide a technique capable of forming a memristor device having a small operating voltage and a small change in operating voltage and significantly improved linearity when synaptic weights are updated.

A memristor device according to an embodiment of the present invention includes a lower electrode, an epitaxially grown silicon-germanium layer formed on the lower electrode, a dielectric layer formed on the silicon-germanium layer, and the silicon nitride film layer. A formed via hole, and an upper electrode layer formed on top of the via hole, wherein the silicon-germanium layer is formed through a germanium ion implantation process for inducing low-dimensional defects provided as a passage for metal ions in the upper electrode layer. is formed

In an embodiment, the ion implantation process is performed under conditions for removing interfacial oxide located between the substrate and the silicon-germanium layer.

In an embodiment, the upper electrode layer is composed of at least one reactive metal of silver (Ag), copper (Cu), silver-copper (Ag-Cu) alloy, and nickel (Ni).

In an embodiment, the dielectric layer is made of at least one of a silicon nitride film (SiNx), a silicon oxide film (SiOx), and a silicon oxynitride film (SiOxNy).

In an embodiment, the thickness of the ion composition at half maximum according to the implantation of the germanium ions is 1.5 times the thickness of the silicon-germanium layer.

According to the above-described embodiments of the present invention, it is possible to implement a memristor device having a small operating voltage and a small change in operating voltage and significantly improved linearity when synaptic weights are updated.

1 shows a simplified structure of a memristor array according to an embodiment of the present invention.
FIG. 2 is a view showing a cross section of the memristor device of FIG. 1 .
3 is a flowchart briefly showing a manufacturing method for forming the memristor device of the present invention.
4 is a diagram schematically showing a manufacturing process for forming the memristor device of the present invention.
5a to 5c are views showing a method and characteristics of forming the SPE-SiGe thin film of the present invention.
6 is a diagram showing the growth of solid-phase epitaxy through ion implantation.
7 shows an enlarged HRTEM image of the SPE-SiGe thin film.
8a to 8c are diagrams showing current-voltage behavior and parameters of the memristor device based on the SPE-SiGe thin film of the present invention.
9A to 9C are graphs showing DC voltage-current sweep measurement results for a-Si-based CBRAM devices and SPE-SiGe-based CBRAM devices after a formation process.
10A to 10B are diagrams showing conductive paths formed in the switching layer when voltage is applied to the a-Si device and the SPE-SiGe device.
10c to 10d show the results of strengthening/weakening tests for a-Si-based devices and SPE-SiGe devices.
11 is a diagram briefly showing etching characteristics of an SPE-SiGe thin film.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Also, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

In the present invention, a new approach to form a silicon-germanium (SiGe) epitaxial thin film by a solid-state epitaxial process using ion beam implantation and utilize it as an active layer of a CBRAM device will be proposed. The SiGe epitaxial thin film is formed by sequential processes such as amorphous silicon (a-Si) deposition, germanium (Ge) ion implantation, and high-temperature annealing. The implanted germanium (Ge) ions remove interfacial oxide between the a-Si film and the silicon single crystal wafer, which is helpful for the growth of the SiGe epitaxial thin film. Implantation of Ge ions also induces low-order defects such as dislocation loops near the surface region. The number and location of defects can be controlled by adjusting the implantation ion density (fluence) and selective implantation area. Specifically, the injection region may be selectively adjusted using a finely patterned mask manufactured through an exposure process. In addition, the number and distribution of structural defects can be adjusted by adjusting the acceleration voltage and the fluence of the Ge ion beam. Here, a more reliable device operation of SiGe Epitaxy based CBRAM compared to a-Si based CBRAM will be described. Thanks to the pre-formed defects in the SiGe epitaxial thin film, the SiGe epitaxial CBRAM device has an almost forming-free behavior and can reduce set and reset voltage variations. In addition, SiGe CBRAM devices offer improved linearity in the conductance update curves required to mimic biological synapses compared to a-Si CBRAM.

1 shows a simplified structure of a memristor array according to an embodiment of the present invention. Referring to FIG. 1 , the memristor array 100 may include memristor elements 110 to 190 having induced low-dimensional defects serving as passages for metal ions.

Looking at the cross-section of the memristor device 110, it includes a substrate provided as a lower electrode, a semiconductor layer formed on top of the substrate, a silicon nitride (SiNx) layer, and a reactive metal layer provided as an upper electrode. In an exemplary embodiment, a silicon (Si) layer doped with a high concentration (p++) may be formed as the substrate. The semiconductor layer may consist of an epitaxially grown silicon-germanium (SiGe) layer. The epitaxially grown silicon-germanium (SiGe) layer may be formed through implantation of germanium (Ge) ions into the amorphous silicon layer and heat treatment. And, the reactive metal layer provided as the upper electrode may be composed of silver (Ag). A silicon nitride layer (SiNx) may be deposited on the epitaxially grown silicon-germanium layer, and a via hole may be formed through etching of the silicon nitride layer (SiNx).

According to the memristor device 110 of the present invention, low-dimensional defects are induced in the epitaxially grown silicon-germanium layer, and upper electrode ions move along the defects. As a result, the filament formation process performed at a high voltage can be omitted, and the operating voltage and operating voltage fluctuations can be reduced. In addition, according to the present invention, it is possible to implement a memristor device in which linearity of synaptic weight update is greatly improved.

Here, the lower electrode may be formed of at least one of silicon (Si), platinum (Pt), titanium nitride (TiN), and tungsten (W). The semiconductor layer may include at least one of amorphous silicon (a-Si), amorphous germanium (a-Ge), and amorphous silicon-germanium (a-Si _x Ge _y ). The dielectric layer may include at least one of a silicon nitride layer (SiN _x ), a silicon oxide layer (SiO _x ), and a silicon oxynitride layer (SiO _x N _y ). Also, as the reactive metal layer, at least one of silver (Ag), copper (Cu), a copper-silver (Ag-Cu) alloy, and nickel (Ni) may be used.

FIG. 2 is a view showing a cross section of the memristor device of FIG. 1 . Referring to FIG. 2 , a memristor device 110 having a silicon-germanium (hereinafter, SPE-SiGe) layer grown as a semiconductor layer by solid phase epitaxial (SPE) will be described as an example. The memristor element 110 includes a substrate 111 serving as a lower electrode, an SPE-SiGe layer 112 formed on the substrate 111, a silicon nitride (SiNx) layer 113, and silver (Ag) electrode layer (114).

The substrate 111 may be provided with highly doped p++ type silicon. For example, the substrate 111 may be a silicon wafer. Subsequently, the SPE-SiGe layer 112 is formed through a sequential process of implantation of germanium (Ge) ions and high-temperature annealing after forming an amorphous silicon (a-Si) layer through a low pressure chemical vapor deposition (LPCVD) process on a silicon wafer. It can be. Germanium (Ge) ions implanted to form the SPE-SiGe layer 112 can remove interfacial oxides that hinder the growth of solid-state epitaxy between an amorphous silicon (a-Si) thin film and a silicon monocrystalline wafer. Accordingly, growth of a silicon-germanium (SiGe) epitaxial thin film for forming the SPE-SiGe layer 112 may be activated by the implanted germanium (Ge) ions. Implanted germanium (Ge) ions can also induce low-order defects such as dislocation loops near surface regions.

On top of the SPE-SiGe layer 112, a silicon nitride film (SiNx, 113) is formed. After the silicon nitride film 113 is formed, a via hole structure is formed through an etching process. Thereafter, a silver electrode layer 114 may be formed as a reactive metal layer on top of the silicon nitride film 113 .

In the above, for convenience of description, the memristor device 110 having the SPE-SiGe layer 112 as a semiconductor layer has been described as an example. However, the memristor element 110 of the present invention may be adjusted or changed to various materials. For example, the substrate 111 serving as the lower electrode may be formed of at least one of silicon (Si), platinum (Pt), titanium nitride (TiN), and tungsten (W). The silicon nitride film (SiNx, 113) layer serving as the dielectric layer may be formed of at least one of a silicon nitride film (SiN _x ), a silicon oxide film (SiO _x ), and a silicon oxynitride film (SiO _x N _y ). Also, the silver electrode layer 114 serving as a reactive metal layer may be formed of copper (Cu), a copper-silver (Ag-Cu) alloy, or nickel (Ni). In addition, it will be well understood that silicon (Si), carbon (C), or the like can be used instead of germanium (Ge) as the implanted ion.

3 is a flowchart briefly showing a manufacturing method for forming the memristor device of the present invention. Referring to FIG. 3, the filament formation process performed at a high voltage can be omitted through the SPE-SiGe layer 112 formed by the manufacturing method of the present invention, and fluctuations in operating voltages such as set voltage and reset voltage can be reduced there is. Therefore, ideal analog synaptic characteristics of a memristor device can be implemented.

In step S110, a heavily doped p++ type silicon substrate is provided.

In step S120, an amorphous silicon (a-Si) layer is formed on the heavily doped p++ type silicon substrate. A preferred thickness of the amorphous silicon (a-Si) layer may be formed to, for example, 60 nm. An amorphous silicon (a-Si) layer may be formed on a silicon wafer through a low pressure chemical vapor deposition (LPCVD) process. For a low pressure chemical vapor deposition (LPCVD) process, for example, a deposition temperature of 550° C. and a process pressure of 150 mTorr may be applied.

In step S130 , germanium (Ge) ions are implanted into the amorphous silicon (a-Si) layer. Germanium (Ge) ions may be implanted into an amorphous silicon (a-Si) layer by irradiating an accelerated germanium (Ge) ion beam. The thickness at half maximum of the implanted ion composition through the implantation of germanium (Ge) ions may be 3/2 times the thickness of an amorphous silicon (a-Si) thin film. In addition, the peak composition of the implanted Ge ions may be around 2.6 at% (0.5 at% to 10 at%). The defect peak position due to ion implantation may be similar to the thickness of the thin film. And the defect peak ratio by ion implantation may be 78.5% (50 to 100%). Interfacial oxide can be effectively removed from the interface between the a-Si thin film and the c-Si wafer by the high implantation acceleration voltage of germanium (Ge) ions.

In step S140, annealing is performed following the ion implantation. In order to induce solid phase epitaxy (SPE) on the a-SiGe layer implanted with germanium (Ge) ions, heat treatment under high temperature conditions (eg, 900° C.) may be applied. An SPE-SiGe thin film may be formed through annealing.

In step S150, a silicon nitride film 113 is formed on the SPE-SiGe growth layer.

In step S160 , via holes are formed in the silicon nitride film 113 . For formation of via holes, for example, a silicon nitride film (SiNx, 113) may be selectively etched in a BOE solution using a photoresist mask having a circular hole array patterned by photolithography.

In step S170, an upper electrode is formed on the silicon nitride film 113 in which the via hole is formed. That is, the silver electrode layer 114 may be formed on the via hole. Here, the silver electrode layer 114 may be formed using a lift-off process so that silver is deposited in a cylindrical shape on the silicon nitride film 113 by a thermal evaporator.

4 is a diagram schematically showing a manufacturing process for forming the memristor device of the present invention. Referring to FIG. 4 , low-dimensional defects can be induced in the SPE-SiGe growth layer through the manufacturing method of the present invention, and a path for upper electrode ions to move along the defects can be provided. The memristor device formed according to the manufacturing method of the present invention can implement ideal analog synaptic characteristics.

In process (a), a heavily doped p++ type silicon wafer is provided.

In process (b), an amorphous silicon (a-Si) layer 112a is formed on a heavily doped p++ type silicon wafer. The a-Si layer 112a is an amorphous silicon layer before germanium (Ge) ions are implanted. The a-Si layer 112a may be formed on a silicon wafer through a low pressure chemical vapor deposition (LPCVD) process.

In step (c), germanium (Ge) ions are implanted into the a-Si layer 112a. A germanium (Ge) implanted a-SiGe layer 112b may be formed by implanting germanium (Ge) ions into the a-Si layer 112a by irradiating a germanium (Ge) ion beam accelerated with high energy. .

In the step (d), annealing is performed following the germanium (Ge) ion implantation. In order to induce solid phase epitaxy (SPE) on the a-SiGe layer implanted with germanium (Ge) ions, heat treatment under high temperature conditions (eg, 900° C.) may be applied. An SPE-SiGe thin film may be formed through annealing.

In process (e), a silicon nitride film (SiNx, 113) is formed on the SPE-SiGe layer 112 into which germanium (Ge) ions are implanted. The silicon nitride film 113 may be formed by a plasma chemical vapor deposition (PECVD) technique.

In step (f), via holes are formed in the silicon nitride film (SiNx, 113). For formation of via holes, for example, a silicon nitride film (SiNx, 113) may be selectively etched in a buffered oxide-etchant (BOE) solution using a photoresist mask having a circular hole array patterned by photolithography. there is.

In process (g), an upper electrode layer is formed. That is, the silver electrode layer 114 may be formed on the via hole. Here, the silver electrode layer 114 may be formed using a lift-off process so that silver is deposited in a cylindrical shape on the silicon nitride film 113 by a thermal evaporator.

5a to 5c are views showing a method and characteristics of forming the SPE-SiGe thin film of the present invention. Referring to FIG. 5A, the effect of removing interfacial oxide by ion implantation is shown. Solid-state epitaxy (SPE) is one of the processes for producing an epitaxial thin film by depositing an a-Si layer 112a on a single crystal substrate 111 and subsequent annealing for crystallization. To obtain a high quality epitaxial thin film, the lattice size of the deposited a-Si layer 112a should match that of the substrate 111 . Moreover, the interface between the deposited a-Si layer 112a thin film and the substrate must be controlled so that there are no foreign substances. The native oxide of the silicon wafer is rapidly formed even at room temperature and hinders epithelial growth of the a-Si layer 112a. To remove the native oxide, a hydrogen surface treatment at high temperature in the process chamber is performed prior to the deposition of the amorphous silicon oxide. Ion implantation is one of the techniques for removing the interfacial oxide 115 .

Referring to FIG. 5B , the a-Si layer 112a implanted with Ge ions may be annealed at an appropriate temperature (eg, 900° C.) to induce solid phase epitaxy. Particles injected with a high accelerating voltage collide with the host element, induce a potential in the host element and lose kinetic energy. Interfacial oxides can be reduced by ion bombardment. In addition, it induces densely distributed low-order defects 116 with a [111] crystal orientation from the surface of the SPE-SiGe layer 112 to a certain depth. The low-dimensional defects 116 near the surface of the SPE-SiGe layer 112 are stacked defects surrounded by partial dislocations, which are commonly observed in epitaxial growth. A large number of low-dimensional defects 116 extending to the surface of the SPE-SiGe layer 112 are expected to act as a moving path of silver (Ag) under bias conditions as shown in FIG. 5C.

6 is a diagram showing the growth of solid-phase epitaxy through ion implantation. Referring to FIG. 6, the original interface between the LPCVD a-Si thin film and the c-Si wafer in (a) before annealing is enlarged. 6 are diagrams showing XTEM images of an a-Si thin film on a silicon wafer by high voltage (120 kV) implantation. (a) shows the initial interface between the LPCVD a-Si thin film and the c-Si wafer before annealing. (b) shows the morphology of the initial interface between the LPCVD a-Si thin film and the c-Si wafer after annealing. And (c) is an enlarged view of the interface part of (b).

As shown, in the case of high voltage (eg, 120 kV) implantation, interfacial oxide was not observed even at magnified magnification, and the LPCVD a-Si thin film showed epitaxial growth along the substrate orientation. The amorphized silicon wafer after annealing shows a single crystal diffraction pattern. The implanted Ge ions create a SiGe alloy and increase the lattice size according to the Ge fraction. The lattice parameter of the SiGe alloy changes in proportion to the amount of Ge, and the determined lattice parameter agrees well with the value estimated from 'Vegard's law.

7 shows an enlarged HRTEM image of the SPE-SiGe thin film. Referring to FIG. 7 , as shown, low-dimensional defects may be formed on the surface of SPE-SiGe.

It shows densely distributed defects with the [111] crystal orientation from the surface to a depth of 40 nm, as presented in (a). Low-dimensional defects near the surface are stacking faults (SF) surrounded by partial dislocations, which are commonly observed in epitaxial growth. (b) and (c) show enlarged images of the regions marked '1' and '2' in (a). The X-HRTEM image of (b) indicates that the low-dimensional defects observed near the surface of the epitaxial thin film are stacking defects. Dislocations surround stacking faults near the surface. The number density of defects in SPE-SiGe thin films is experimentally determined by a modified Schimmel etching technique. A large number of defects extending to the surface of the SPE thin film are expected to act as a migration path for silver (Ag).

8a to 8c are diagrams showing current-voltage behavior and parameters of the memristor device based on the SPE-SiGe thin film of the present invention. Referring to FIGS. 8A to 8C , DC current-voltage characteristics and parameter values of CBRAM devices based on SPE-SiGe and a-Si thin films are shown.

8a shows the current-voltage characteristics of a 70 nm thick a-Si based CBRAM device. Referring to FIG. 8A , in an initial state, an a-Si-based CBRAM device requires a forming process for a general resistance switching operation. The forming voltage depends on the active layer thickness and is generally much higher than the set voltage.

8b shows the current-voltage characteristics of a CBRAM device based on SPE-SiGe with the same thickness. CBRAM devices based on SPE-SiGe show much lower formation voltages that are close to the set voltages. In the case of SPE-SiGe-based thin films, low-dimensional defects observed in TEM images are expected to act as conductive pathways. The activation energy of metal migration into stacking faults can be much lower than in an amorphous silicon matrix or crystalline phase. The average formation voltage values of a-Si thin film and SPE-SiGe-based devices were 8.5 V (±1.6) and 2.7 V (±0.3), respectively, summarized in Fig. 8c.

9A to 9C are graphs showing DC voltage-current sweep measurement results for a-Si-based CBRAM devices and SPE-SiGe-based CBRAM devices after a formation process. As can be seen in Figures 9a and 9b, the device based on SPE-SiGe exhibits much less variation in the current-voltage curve. It can be seen that the variation to average ratio of SPE-SiGe-based devices in terms of set and reset voltages is lower than that of a-Si-based devices. The reduced variation of SPE-SiGe-based devices is attributed to the presence of low-order defects. As confirmed from the almost forming-free characteristics as described above, a number of defects are formed before operation of the device. In the case of a-Si based devices, it is well known that conductive filaments form and rupture in a stochastic manner. However, SPE-SiGe-based devices have stacking defects that serve as selective diffusion paths for silver (Ag) ions. Therefore, silver (Ag) migration may occur mainly through low-dimensional defects during repeated switching operations. This may be the reason for the decrease in variation of the set and reset voltages.

One of the important device parameters for implementing memristor neural networks for neuromorphic computing is the nonlinearity of the conductivity change with respect to successive voltage pulses. Consecutive set and reset pulses are forced to mimic synaptic potentiation and attenuation. Nonlinearity in the enhancement and weakening modes shows a simplified structure of the memristor array according to an embodiment of the present invention with a learning accuracy of 1 of the memory neural network. Referring to FIG. 1 , the memristor array 100 may include memristor elements 110 to 190 having induced low-dimensional defects serving as passages for metal ions.

Looking at the cross-section of the memristor device 110, it includes a substrate provided as a lower electrode, a semiconductor layer formed on top of the substrate, a silicon nitride (SiNx) layer, and a reactive metal layer provided as an upper electrode. In an exemplary embodiment, a silicon (Si) layer doped with a high concentration (p++) may be formed as the substrate. The semiconductor layer may consist of an epitaxially grown silicon-germanium (SiGe) layer. The epitaxially grown silicon-germanium (SiGe) layer may be formed through implantation of germanium (Ge) ions into the amorphous silicon layer and heat treatment. And, the reactive metal layer provided as the upper electrode may be composed of silver (Ag). A silicon nitride layer (SiNx) may be deposited on the epitaxially grown silicon-germanium layer, and a via hole may be formed through etching of the silicon nitride layer (SiNx).

According to the memristor device 110 of the present invention, low-dimensional defects are induced in the epitaxially grown silicon-germanium layer, and upper electrode ions move along the defects. As a result, the filament formation process performed at a high voltage can be omitted, and the operating voltage and operating voltage fluctuations can be reduced. In addition, according to the present invention, it is possible to implement a memristor device in which linearity of synaptic weight update is greatly improved.

Here, the lower electrode may be formed of at least one of silicon (Si), platinum (Pt), titanium nitride (TiN), and tungsten (W). The semiconductor layer may include at least one of amorphous silicon (a-Si), amorphous germanium (a-Ge), and amorphous silicon-germanium (a-SixGey). The dielectric layer may include at least one of a silicon nitride layer (SiNx), a silicon oxide layer (SiOx), and a silicon oxynitride layer (SiOxNy). Also, as the reactive metal layer, at least one of silver (Ag), copper (Cu), a copper-silver (Ag-Cu) alloy, and nickel (Ni) may be used.

FIG. 2 is a view showing a cross section of the memristor device of FIG. 1 . Referring to FIG. 2 , a memristor device 110 having a silicon-germanium (hereinafter, SPE-SiGe) layer grown as a semiconductor layer by solid phase epitaxial (SPE) will be described as an example. The memristor element 110 includes a substrate 111 serving as a lower electrode, an SPE-SiGe layer 112 formed on the substrate 111, a silicon nitride (SiNx) layer 113, and silver (Ag) electrode layer (114).

The substrate 111 may be provided with highly doped p++ type silicon. For example, the substrate 111 may be a silicon wafer. Subsequently, the SPE-SiGe layer 112 is formed through a sequential process of implantation of germanium (Ge) ions and high-temperature annealing after forming an amorphous silicon (a-Si) layer through a low pressure chemical vapor deposition (LPCVD) process on a silicon wafer. It can be. Germanium (Ge) ions implanted to form the SPE-SiGe layer 112 can remove interfacial oxides that hinder the growth of solid-state epitaxy between an amorphous silicon (a-Si) thin film and a silicon monocrystalline wafer. Accordingly, growth of a silicon-germanium (SiGe) epitaxial thin film for forming the SPE-SiGe layer 112 may be activated by the implanted germanium (Ge) ions. Implanted germanium (Ge) ions can also induce low-order defects such as dislocation loops near surface regions.

On top of the SPE-SiGe layer 112, a silicon nitride film (SiNx, 113) is formed. After the silicon nitride film 113 is formed, a via hole structure is formed through an etching process. Thereafter, a silver electrode layer 114 may be formed as a reactive metal layer on top of the silicon nitride film 113 .

In the above, for convenience of description, the memristor device 110 having the SPE-SiGe layer 112 as a semiconductor layer has been described as an example. However, the memristor element 110 of the present invention may be adjusted or changed to various materials. For example, the substrate 111 serving as the lower electrode may be formed of at least one of silicon (Si), platinum (Pt), titanium nitride (TiN), and tungsten (W). The silicon nitride layer (SiNx, 113) serving as the dielectric layer may be formed of at least one of a silicon nitride layer (SiNx), a silicon oxide layer (SiOx), and a silicon oxynitride layer (SiOxNy). Also, the silver electrode layer 114 serving as a reactive metal layer may be formed of copper (Cu), a copper-silver (Ag-Cu) alloy, or nickel (Ni). In addition, it will be well understood that silicon (Si), carbon (C), or the like can be used instead of germanium (Ge) as the implanted ion.

3 is a flowchart briefly showing a manufacturing method for forming the memristor device of the present invention. Referring to FIG. 3, the filament formation process performed at a high voltage can be omitted through the SPE-SiGe layer 112 formed by the manufacturing method of the present invention, and fluctuations in operating voltages such as set voltage and reset voltage can be reduced there is. Therefore, ideal analog synaptic characteristics of a memristor device can be implemented.

In step S110, a heavily doped p++ type silicon substrate is provided.

In step S120, an amorphous silicon (a-Si) layer is formed on the heavily doped p++ type silicon substrate. A preferred thickness of the amorphous silicon (a-Si) layer may be formed to, for example, 60 nm. An amorphous silicon (a-Si) layer may be formed on a silicon wafer through a low pressure chemical vapor deposition (LPCVD) process. For a low pressure chemical vapor deposition (LPCVD) process, for example, a deposition temperature of 550° C. and a process pressure of 150 mTorr may be applied.

In step S130 , germanium (Ge) ions are implanted into the amorphous silicon (a-Si) layer. Germanium (Ge) ions may be implanted into an amorphous silicon (a-Si) layer by irradiating an accelerated germanium (Ge) ion beam. The thickness at half maximum of the implanted ion composition through the implantation of germanium (Ge) ions may be 3/2 times the thickness of an amorphous silicon (a-Si) thin film. In addition, the peak composition of the implanted Ge ions may be around 2.6 at% (0.5 at% to 10 at%). The defect peak position due to ion implantation may be similar to the thickness of the thin film. And the defect peak ratio by ion implantation may be 78.5% (50 to 100%). Interfacial oxide can be effectively removed from the interface between the a-Si thin film and the c-Si wafer by the high implantation acceleration voltage of germanium (Ge) ions.

In step S140, annealing is performed following the ion implantation. In order to induce solid phase epitaxy (SPE) on the a-SiGe layer implanted with germanium (Ge) ions, high-temperature conditions (eg, heat treatment at 900 ° C.) may be applied. Through annealing SPE-SiGe thin films can be formed.

In step S150, a silicon nitride film 113 is formed on the SPE-SiGe growth layer.

In step S160 , via holes are formed in the silicon nitride film 113 . For formation of via holes, for example, a silicon nitride film (SiNx, 113) may be selectively etched in a BOE solution using a photoresist mask having a circular hole array patterned by photolithography.

In step S170, an upper electrode is formed on the silicon nitride film 113 in which the via hole is formed. That is, the silver electrode layer 114 may be formed on the via hole. Here, the silver electrode layer 114 may be formed using a lift-off process so that silver is deposited in a cylindrical shape on the silicon nitride film 113 by a thermal evaporator.

4 is a diagram schematically showing a manufacturing process for forming the memristor device of the present invention. Referring to FIG. 4 , low-dimensional defects can be induced in the SPE-SiGe growth layer through the manufacturing method of the present invention, and a path for upper electrode ions to move along the defects can be provided. The memristor device formed according to the manufacturing method of the present invention can implement ideal analog synaptic characteristics.

In process (a), a heavily doped p++ type silicon wafer is provided.

In process (b), an amorphous silicon (a-Si) layer 112a is formed on a heavily doped p++ type silicon wafer. The a-Si layer 112a is an amorphous silicon layer before germanium (Ge) ions are implanted. The a-Si layer 112a may be formed on a silicon wafer through a low pressure chemical vapor deposition (LPCVD) process.

In step (c), germanium (Ge) ions are implanted into the a-Si layer 112a. A germanium (Ge) implanted a-SiGe layer 112b may be formed by implanting germanium (Ge) ions into the a-Si layer 112a by irradiating a germanium (Ge) ion beam accelerated with high energy. .

In the step (d), annealing is performed following the germanium (Ge) ion implantation. In order to induce solid phase epitaxy (SPE) on the a-SiGe layer implanted with germanium (Ge) ions, high-temperature conditions (eg, heat treatment at 900 ° C.) may be applied. Through annealing SPE-SiGe thin films can be formed.

In process (e), a silicon nitride film (SiNx, 113) is formed on the SPE-SiGe layer 112 into which germanium (Ge) ions are implanted. The silicon nitride film 113 may be formed by a plasma chemical vapor deposition (PECVD) technique.

In step (f), via holes are formed in the silicon nitride film (SiNx, 113). For formation of via holes, for example, a silicon nitride film (SiNx, 113) may be selectively etched in a buffered oxide-etchant (BOE) solution using a photoresist mask having a circular hole array patterned by photolithography. there is.

In process (g), an upper electrode layer is formed. That is, the silver electrode layer 114 may be formed on the via hole. Here, the silver electrode layer 114 may be formed using a lift-off process so that silver is deposited in a cylindrical shape on the silicon nitride film 113 by a thermal evaporator.

5a to 5c are views showing a method and characteristics of forming the SPE-SiGe thin film of the present invention. Referring to FIG. 5A, the effect of removing interfacial oxide by ion implantation is shown. Solid-state epitaxial (SPE) growth is one of the processes for producing an epitaxial thin film by deposition of an a-Si layer 112a on a single crystal substrate 111 and subsequent annealing for crystallization. To obtain a high quality epitaxial thin film, the lattice size of the deposited a-Si layer 112a should match that of the substrate 111 . Moreover, the interface between the deposited a-Si layer 112a thin film and the substrate must be controlled so that there are no foreign substances. The native oxide of the silicon wafer is rapidly formed even at room temperature and hinders the epitaxial growth of the a-Si layer 112a. Ion implantation is one of the techniques for removing the interfacial oxide 115 .

Referring to FIG. 5B, the a-Si layer 112a implanted with Ge ions may be annealed at an appropriate temperature (eg, 900° C.) to induce solid-state epitaxy. The implanted particles at a high acceleration voltage may be host Collide with element, induce displacement of host element and lose kinetic energy.Interfacial oxide can be reduced by ion bombardment.In addition, [111] crystal orientation from the surface of SPE-SiGe layer 112 to a certain depth induced densely distributed low-order defects 116. The low-order defects 116 near the surface of the SPE-SiGe layer 112 are stacking faults surrounded by partial dislocations, which are generally Observed in the epitaxial growth, a large number of low-dimensional defects 116 extending to the surface of the SPE-SiGe layer 112 are expected to act as a migration path for silver (Ag) under bias conditions, as shown in FIG.

6 is a diagram showing the growth of solid-phase epitaxy through ion implantation. Referring to FIG. 6, the original interface between the LPCVD a-Si thin film and the c-Si wafer in (a) before annealing is enlarged. 6 are diagrams showing XTEM images of an a-Si thin film on a silicon wafer by high voltage (120 kV) implantation. (a) shows the initial interface between the LPCVD a-Si thin film and the c-Si wafer before annealing. (b) shows the morphology of the initial interface between the LPCVD a-Si thin film and the c-Si wafer after annealing. And (c) is an enlarged view of the interface part of (b).

As shown, in the case of high voltage (eg, 120 kV) implantation, interfacial oxide was not observed even at magnified magnification, and the LPCVD a-Si thin film showed epitaxial growth along the substrate orientation. A crystallized silicon wafer after annealing shows a single crystal diffraction pattern. The implanted Ge ions create a SiGe alloy and increase the lattice size according to the Ge fraction. The lattice parameter of the SiGe alloy changes in proportion to the amount of Ge, and the determined lattice parameter agrees well with the value estimated from 'Vegard's law.

7 shows an enlarged HRTEM image of the SPE-SiGe thin film. Referring to FIG. 7 , as shown, low-dimensional defects may be formed on the surface of SPE-SiGe.

It shows densely distributed defects with the [111] crystal orientation from the surface to a depth of 40 nm, as presented in (a). Low-order defects near the surface are stacking faults (SF) surrounded by partial dislocations, which are commonly observed in epitaxial growth. (b) and (c) show enlarged images of the regions marked '1' and '2' in (a). The X-HRTEM image in (b) indicates that the low-dimensional defects observed near the surface of the epitaxial thin film are stacking defects. Dislocations surround stacking faults near the surface. The number density of defects in SPE-SiGe thin films is experimentally determined by a modified Schimmel etching technique. A large number of defects extending to the surface of the SPE thin film are expected to act as a migration path for silver (Ag).

8a to 8c are diagrams showing current-voltage behavior and parameters of the memristor device based on the SPE-SiGe thin film of the present invention. Referring to FIGS. 8A to 8C , DC current-voltage characteristics and parameter values of CBRAM devices based on SPE-SiGe and a-Si thin films are shown.

8a shows the current-voltage characteristics of a 60 nm thick a-Si based CBRAM device. Referring to FIG. 8A , in an initial state, an a-Si-based CBRAM device requires a forming process for a general resistance switching operation. The formation voltage depends on the active layer thickness and is generally much higher than the set voltage.

8b shows the current-voltage characteristics of a CBRAM device based on SPE-SiGe with the same thickness. In SPE-SiGe-based CBRAM devices, the formation voltage is much lower than the set voltage. In the case of SPE-SiGe-based thin films, low-dimensional defects observed in TEM images are expected to act as conductive pathways. The activation energy of metal migration into stacking faults can be much lower than in an amorphous silicon matrix or crystalline phase. The average formation voltage values of a-Si thin film and SPE-SiGe-based devices were 8.5 V (±1.6) and 2.7 V (±0.3), respectively, summarized in Fig. 8c.

9A to 9C are graphs showing DC voltage-current sweep measurement results for a-Si-based CBRAM devices and SPE-SiGe-based CBRAM devices after a formation process. As can be seen in Figures 9a and 9b, the device based on SPE-SiGe exhibits much less variation in the current-voltage curve. It can be seen that the variation to average ratio of SPE-SiGe-based devices in terms of set and reset voltages is lower than that of a-Si-based devices. The reduced variation of SPE-SiGe-based devices is attributed to the presence of low-order defects. As confirmed from the almost forming-free characteristics as described above, a number of defects are formed before operation of the device. In the case of a-Si based devices, it is well known that conductive filaments form and rupture in a stochastic manner. However, SPE-SiGe-based devices have stacking defects that serve as selective diffusion paths for silver (Ag) ions. Therefore, silver (Ag) migration may occur mainly through low-dimensional defects during repeated switching operations. This may be the reason for the decrease in variation of the set and reset voltages.

One of the important device parameters for implementing memristor neural networks for neuromimetic computing is the nonlinearity of the conductance change with respect to continuous voltage pulses. Consecutive set and reset pulses are forced to mimic the synaptic potentiation and weakening modes. Non-linearity in the strengthening and weakening modes is related to the learning accuracy of the memory neural network. Stacking faults in SPE-SiGe films can operate with many conductive filaments rather than a few strong conductive filaments. Therefore, sudden switching behavior observed in typical resistive memory devices can be suppressed in SPE-SiGe-based memory devices.

10A to 10B are diagrams showing conductive paths formed in the switching layer when voltage is applied to the a-Si device and the SPE-SiGe device. And Figures 10c to 10d are diagrams showing the conductivity update curves for the voltage a-Si device and the SPE-SiGe device.

Referring to FIGS. 10A to 10B , strong conductive filaments 210 exist in a-Si-based devices, but multiple weak filaments 220 exist in SPE-SiGe devices. This is expected to lead to a gradual conductivity update in the enhancement and weakening modes for repetitive equal voltage pulses.

10c to 10d show the results of strengthening/weakening tests for a-Si-based devices and SPE-SiGe devices. As shown, in the case of the a-Si device of FIG. 10C, when the same voltage pulse is continuously applied, rapid increases and decreases in conductivity are observed in both the enhancement mode and the weakening mode after only a few pulses. However, in the case of the SPE-SiGe device of FIG. 10d, a gradual increase and decrease in conductivity were observed in both the enhanced and weakened modes. The nonlinear value of the SPE-SiGe device can be extracted from the rotation equations of Equations 1 to 3 below.

Here, G _P and G _D are conductances for strengthening and weakening, respectively. G _max and G _min are the maximum and minimum conductances extracted from the experimental results. P and P _max are the number of pulses and the maximum number of pulses in each mode. ν _P and ν _D are the nonlinearity of the memristor conductance update in strengthening and weakening, respectively, and will be determined as values satisfying the above equations.

From the above equation, the nonlinearity in the enhancement mode of the SPE-SiGe device is 7.8, and the nonlinearity in the weakening mode is -4.1. In the same way, the nonlinear values of the a-Si device were determined to be 18.9 and -108.4 in the enhanced and weakened modes. This result implies that the SPE-SiGe based CBRAM device with multiple stacking defects has a more gradual conductivity update behavior due to selective Ag migration with low-order defects.

11 is a diagram briefly showing etching characteristics of an SPE-SiGe thin film. Referring to FIG. 11, a result of etching an SPE-SiGe thin film on a silicon (Si) substrate with a Schimmel etchant for 5 seconds is shown. The number of etch pits per unit area generated on the etched surface of the SPE-SiGe thin film shown in (a) can be obtained. In (b), the etch pit density measured after etching with the same etchant for 60 seconds for pure silicon and the etch pit density of the SPE-SiGe thin film are compared. It can be seen that the etch pit of the SPE-SiGe thin film is higher than that of pure silicon (Baer Si). Considering the etch pit, it can be seen that the memristor device using the SPE-SiGe thin film is dense enough to provide uniform defects.

The foregoing are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should be defined by not only the claims to be described later, but also those equivalent to the claims of the present invention.

Claims (5)

For memristor devices:
lower electrode;
an epitaxially grown silicon-germanium layer formed on the lower electrode;
a dielectric layer formed on top of the silicon-germanium layer;
a via hole formed in the dielectric layer; and
Including an upper electrode layer formed on top of the via hole,
The silicon-germanium layer undergoes a germanium ion implantation process and solid phase epitaxy (SPE) for inducing low-dimensional defects in the [111] crystal direction to a specific depth, which are provided as passages for metal ions of the upper electrode layer. A memristor element formed through high-temperature heat treatment for induction. According to claim 1,
The ion implantation process is performed under conditions for removing interfacial oxide located between the lower electrode and the silicon-germanium layer. According to claim 1,
The upper electrode layer is formed of at least one reactive metal of silver (Ag), copper (Cu), silver-copper (Ag-Cu) alloy, and nickel (Ni). According to claim 1,
The dielectric layer is a memristor device formed of at least one of a silicon nitride film (SiNx), a silicon oxide film (SiOx), and a silicon oxynitride film (SiO _x N _y ). According to claim 1,
The memristor device of claim 1 , wherein a thickness of the ion composition at half maximum according to the implantation of the germanium ions is 1.5 times the thickness of the silicon-germanium layer.

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