KR102512678B1 - Electronic device for wirelessly receiving power and method for operating thereof - Google Patents

Abstract

An electronic device according to various embodiments of the present invention includes a receiving circuit for receiving power wirelessly and outputting AC power, and a rectifying circuit for rectifying the AC power output from the power receiving circuit, the rectifying circuit comprising: While the AC power has a positive amplitude, power having the positive amplitude is transmitted to the output terminal of the rectifier circuit, and while the AC power has a negative amplitude, the power having the negative amplitude is transmitted to the output terminal of the rectifier circuit. A first P-MOSFET for disabling power transfer and a forward loss compensation circuit connected to the first P-MOSFET and lowering the threshold voltage of the first P-MOSFET while the AC power has a positive amplitude. can do.

Description

Electronic device receiving power wirelessly and method of operating the same

Various embodiments of the present disclosure relate to an electronic device that wirelessly receives power and an operating method thereof.

For many people living in modern times, portable digital communication devices have become an essential element. Consumers want to be provided with a variety of high-quality services anytime, anywhere. In addition, due to the recent IoT (Internet of Thing), various sensors, home appliances, and communication devices that exist in our lives are being networked into one. In order to smoothly operate these various sensors, a wireless power transmission system is required.

Wireless power transmission includes magnetic induction, magnetic resonance, and electromagnetic wave methods. The magnetic induction or magnetic resonance method is advantageous for charging an electronic device located in a relatively short distance from a wireless power transmission device. The electromagnetic wave method is more advantageous than the magnetic induction or magnetic resonance method for long-distance power transmission up to several meters. The electromagnetic wave method is mainly used for long-distance power transmission, and can transfer power most efficiently by determining the exact location of a power receiver in a long distance.

An electronic device that wirelessly receives power may receive AC waveform power and rectify it. A rectifier circuit included in an electronic device may include a P-MOSFET, and forward loss and reverse leakage loss may occur in the P-MOSFET. For example, when the P-MOSFET is controlled to be in an on state, loss due to the threshold voltage of the P-MOSFET may occur, and this may be referred to as forward loss. For example, although the P-MOSFET should be controlled to be in an off state, current may flow in the reverse direction of the P-MOSFET, and this may be referred to as reverse leakage loss. When an electronic device wirelessly receives a relatively small amount of power, a loss due to a rectifier circuit may have a large effect on overall efficiency.

Various embodiments of the present disclosure may provide an electronic device including a rectifier circuit capable of preventing forward loss and reverse leakage loss, and an operating method thereof.

An electronic device according to various embodiments of the present disclosure includes a receiving circuit that wirelessly receives power and outputs AC power; and a rectifier circuit for rectifying the AC power output from the power receiving circuit, wherein the rectifier circuit outputs power having the positive amplitude to an output terminal of the rectification circuit while the AC power has a positive amplitude. a first P-MOSFET that transmits power having a negative amplitude to an output terminal of the rectifier circuit while the AC power has a negative amplitude; and a forward loss compensation circuit connected to the first P-MOSFET and lowering a threshold voltage of the first P-MOSFET while the AC power has a positive amplitude.

A receiving circuit for receiving power wirelessly and outputting AC power according to various embodiments of the present invention; a plurality of rectifying circuits for rectifying the AC power output from the power receiving circuit; a sensor for sensing the magnitude of the received power; and a control circuit, wherein the control circuit obtains, from the sensor, a magnitude of the received power, and selects a rectifier circuit to perform rectification from among the plurality of rectifier circuits based on the magnitude of the received power. and control to rectify the AC power output from the power receiving circuit using the selected rectifying circuit.

An operating method of an electronic device including a plurality of rectifier circuits according to various embodiments of the present disclosure may include receiving power wirelessly; obtaining a magnitude of the received power; selecting a rectifier circuit to perform rectification from among the plurality of rectifier circuits, based on the magnitude of the received power; and rectifying the received power using the selected rectifying circuit.

According to various embodiments of the present disclosure, an electronic device including a rectifier circuit capable of preventing forward loss and reverse leakage loss and an operating method thereof may be provided. Accordingly, power processing efficiency may be increased, and heat generated from the electronic device may also be reduced.

1 shows a block diagram of a wireless power transmission device and an electronic device according to various embodiments of the present invention.
2 shows a block diagram of a wireless power transmission device and an electronic device according to various embodiments of the present invention.
3A shows a block diagram of a power transmission circuit and a power reception circuit according to an induction method or a resonance method according to various embodiments of the present invention.
3B is a block diagram of a power transmission circuit and a power reception circuit according to an electromagnetic wave method according to various embodiments of the present invention.
4A shows a rectifier circuit according to a comparative example for comparison with various embodiments of the present invention, and FIG. 4B shows a rectifier circuit according to various embodiments of the present invention.
5-9 show rectifier circuits according to various embodiments of the present invention.
10 shows a block diagram of an electronic device according to various embodiments of the present invention.
11 shows a block diagram of an electronic device according to various embodiments of the present invention.
12 is a flowchart illustrating a method of operating an electronic device according to various embodiments of the present disclosure.
13 is a flowchart illustrating a method of operating an electronic device according to various embodiments of the present disclosure.
14 shows a circuit diagram of a resonant circuit and a rectifier circuit according to various embodiments.
15 shows a block diagram of an OLDC circuit in accordance with various embodiments.
16 illustrates signals received or generated according to various embodiments.
17 shows a circuit diagram of a converting circuit according to various embodiments.
18 is a circuit diagram of a zero current detector (ZCD) according to various embodiments.

This study was conducted with the support of the National Research Foundation of Korea's Leading Research Center Support Project (ERC), funded by the Ministry of Science, ICT and Future Planning. (Assignment number: 2014R1A5A1011478)

Hereinafter, various embodiments of this document will be described with reference to the accompanying drawings. Examples and terms used therein are not intended to limit the technology described in this document to specific embodiments, and should be understood to include various modifications, equivalents, and/or substitutes of the embodiments. In connection with the description of the drawings, like reference numerals may be used for like elements. Singular expressions may include plural expressions unless the context clearly dictates otherwise. In this document, expressions such as "A or B" or "at least one of A and/or B" may include all possible combinations of the items listed together. Expressions such as "first," "second," "first," or "second," may modify the corresponding components regardless of order or importance, and are used to distinguish one component from another. It is used only and does not limit the corresponding components. When a (e.g., first) element is referred to as being "(functionally or communicatively) coupled to" or "connected to" another (e.g., second) element, that element refers to the other (e.g., second) element. It may be directly connected to the component or connected through another component (eg, a third component).

In this document, "configured (or configured to)" means "suitable for," "having the ability to," "changed to," depending on the situation, for example, hardware or software. ," can be used interchangeably with "made to," "capable of," or "designed to." In some contexts, the expression "device configured to" can mean that the device is "capable of" in conjunction with other devices or components. For example, the phrase "a processor configured (or configured) to perform A, B, and C" may include a dedicated processor (eg, embedded processor) to perform the operation, or by executing one or more software programs stored in a memory device. , may mean a general-purpose processor (eg, CPU or application processor) capable of performing corresponding operations.

A wireless power transmission device or electronic device according to various embodiments of the present document, for example, a smart phone, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, It may include at least one of a server, a PDA, a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device. A wearable device may be in the form of an accessory (e.g. watch, ring, bracelet, anklet, necklace, eyeglasses, contact lens, or head-mounted-device (HMD)), integrated into textiles or clothing (e.g. electronic garment); may include at least one of a body-attachable (eg, skin pad or tattoo) or bio-implantable circuit In some embodiments, a wireless power transmission device or electronic device may include, for example, a television, a television and a cable Or wirelessly linked set-top box, DVD (digital video disk) player, audio, refrigerator, air conditioner, vacuum cleaner, oven, microwave oven, washing machine, air purifier, set-top box, home automation control panel, security control panel, media box , a game console, an electronic dictionary, an electronic key, a camcorder, an electric vehicle, or an electronic photo frame.

In another embodiment, the wireless power transmission device or electronic device is a variety of medical devices (e.g., various portable medical measuring devices (glucose meter, heart rate monitor, blood pressure monitor, or body temperature monitor, etc.), MRA (magnetic resonance angiography), MRI ( magnetic resonance imaging), CT (computed tomography), camera, or ultrasonicator, etc.), navigation device, GNSS (global navigation satellite system), EDR (event data recorder), FDR (flight data recorder), automotive infotainment devices, marine electronics (e.g. marine navigation systems, gyrocompasses, etc.), avionics, security devices, vehicle head units, industrial or domestic robots, drones, ATMs of financial institutions, Including at least one of a point of sale (POS) in a store or Internet of Things (e.g., light bulbs, various sensors, sprinklers, smoke alarms, thermostats, streetlights, toasters, exercise equipment, hot water tanks, heaters, boilers, etc.) can do. According to some embodiments, the wireless power transmission device or electronic device may be a piece of furniture, a building/structure or a vehicle, an electronic board, an electronic signature receiving device, a projector, or various measuring devices (eg : Water, electricity, gas, or radio wave measuring devices, etc.) may include at least one. In various embodiments, the wireless power transmission device or electronic device may be flexible or a combination of two or more of the various devices described above. A wireless power transmission device or electronic device according to an embodiment of the present document is not limited to the above devices. In this document, the term user may refer to a person using an electronic device, a wireless power transmission device, or a device using an electronic device (eg, an artificial intelligence electronic device).

1 shows a block diagram of a wireless power transmission device and an electronic device according to various embodiments of the present invention.

Referring to FIG. 1 , a wireless power transmitter 100 according to various embodiments of the present disclosure may wirelessly transmit power 161 to an electronic device 150 . The wireless power transmitter 100 may transmit power 161 to the electronic device 150 according to various charging methods. For example, the wireless power transmitter 100 may transmit power 161 according to an induction method. When the wireless power transmission device 100 is inductive, the wireless power transmission device 100 includes, for example, a power source, a DC-AC conversion circuit, an amplifier circuit, an impedance matching circuit, at least one capacitor, and at least one It may include a coil, a communication modulation and demodulation circuit, and the like. At least one capacitor may constitute a resonant circuit together with at least one coil. The wireless power transmission apparatus 100 may be implemented in a manner defined in a wireless power consortium (WPC) standard (or Qi standard). For example, the wireless power transmitter 100 may transmit power 161 according to a resonance method. In the case of the resonance method, the wireless power transmission device 100 includes, for example, a power source, a DC-AC conversion circuit, an amplifier circuit, an impedance matching circuit, at least one capacitor, at least one coil, and an out-of-band communication circuit ( Example: BLE (bluetooth low energy) communication circuit) and the like. At least one capacitor and at least one coil may constitute a resonant circuit. The wireless power transmission apparatus 100 may be implemented in a manner defined in the Alliance for Wireless Power (A4WP) standard (or air fuel alliance (AFA) standard). The wireless power transmitter 100 may include a coil capable of generating an induced magnetic field when a current flows according to a resonance method or an induction method. A process of generating an induced magnetic field by the wireless power transmitter 100 may be expressed as the wireless power transmitter 100 transmitting power 161 wirelessly. In addition, the electronic device 150 may include a coil in which induced electromotive force is generated by a magnetic field whose size changes with time formed around it. A process in which the electronic device 150 generates an induced electromotive force through a coil may be expressed as the electronic device 150 receiving the power 161 wirelessly. For example, the wireless power transmitter 100 may transmit power 161 according to an electromagnetic wave method. When the wireless power transmission device 100 uses an electromagnetic wave method, the wireless power transmission device 100 includes, for example, a power source, a DC-AC conversion circuit, an amplifier circuit, a distribution circuit, a phase shifter, and a plurality of patch antennas. It may include an antenna array for power transmission, an out-of-band communication circuit (eg, a BLE communication module), and the like. Each of the plurality of patch antennas may form a radio frequency (RF) wave (eg, electromagnetic wave). The electronic device 150 may include a patch antenna capable of outputting current using an RF wave formed around it. A process of forming an RF wave by the wireless power transmitter 100 may be expressed as the wireless power transmitter 100 transmitting power 161 wirelessly. A process in which the electronic device 150 outputs current from the patch antenna using RF waves may be expressed as the electronic device 150 receiving power 161 wirelessly.

The wireless power transmitter 100 according to various embodiments of the present invention may communicate with the electronic device 150. For example, the wireless power transmitter 100 may communicate with the electronic device 150 according to an in-band method. The wireless power transmitter 100 or the electronic device 150 may change the load (or impedance) of data to be transmitted, for example, according to an on/off keying modulation scheme. The wireless power transmission device 100 or the electronic device 150 may determine data to be transmitted from the other device by measuring a load change (or impedance change) based on a change in current, voltage, or power of a coil. there is. For example, the wireless power transmitter 100 may communicate with the electronic device 150 according to an out-band method. The wireless power transmitter 100 or the electronic device 150 may transmit and receive data using a communication circuit (eg, a BLE communication module) provided separately from a coil or patch antenna.

In this document, the wireless power transmitter 100 or the electronic device 150 or another electronic device performing a specific operation is included in the wireless power transmitter 100 or the electronic device 150 or another electronic device. It may mean that various hardware, for example, a control circuit such as a processor, a coil or a patch antenna, etc. perform a specific operation. Alternatively, when the wireless power transmitter 100 or the electronic device 150 or another electronic device performs a specific operation, the processor may control other hardware to perform the specific operation. Alternatively, the wireless power transmitter 100 or the electronic device 150, or another electronic device performing a specific operation may cause the wireless power transmitter 100 or the electronic device 150, or the storage circuit of the other electronic device ( It may also mean causing a processor or other hardware to perform a specific operation as an instruction to perform a specific operation stored in memory) is executed.

2 shows a block diagram of a wireless power transmission device and an electronic device according to various embodiments of the present invention.

The wireless power transmission device 100 according to various embodiments of the present invention may include a power transmission circuit 109, a control circuit 102, a communication circuit 103, a memory 105, and a power source 106. there is. The electronic device 150 according to various embodiments of the present disclosure includes a power receiving circuit 159, a control circuit 152, a communication circuit 153, a memory 156, a charger 154, a battery 155, and a PMIC. (power management integrated circuit) 156 and a load 157 may be included.

The power transmission circuit 109 according to various embodiments of the present invention is a power reception circuit 159 and may wirelessly transmit power according to at least one of an induction method, a resonance method, and an electromagnetic wave method. Detailed configurations of the power transmission circuit 109 and the power reception circuit 159 will be described in more detail with reference to FIGS. 3A and 3B. The control circuit 102 can control the amount of power transmitted by the power transmission circuit 109 . For example, as the control circuit 102 controls the size of the power output from the power source 106 or controls the amplification gain of a power amplifier included in the power transmission circuit 109, the power The amount of power transmitted by the transmission circuit 109 can be controlled. The control circuit 102 may adjust the magnitude of the power output from the power source 106 by controlling the duty cycle or frequency of the power output from the power source 106 . The power source 106 may include, for example, a power interface connectable to a wall power source, and may receive AC power having a voltage set for each country from the wall power source and transmit the AC power to the power transmission circuit 109 .

The control circuit 102 may control the magnitude of power applied to the power transmission circuit 109 by controlling the magnitude of the bias voltage of the power amplifier. The control circuit 102 or control circuit 152 includes various circuits capable of performing operations such as a general-purpose processor such as a CPU, a mini computer, a microprocessor, a micro controlling unit (MCU), and a field programmable gate array (FPGA). It can be implemented, and the type is not limited.

The power receiving circuit 159 according to various embodiments of the present invention may wirelessly receive power from the power transmitting circuit 109 according to at least one of an inductive method, a resonance method, and an electromagnetic wave method. The power receiving circuit 159 may perform power processing of rectifying the power of the received AC waveform into a DC waveform, converting a voltage, or regulating the power. The charger 154 may charge the battery 155 of the electronic device 150 . The charger 154 may charge the battery 155 in a constant voltage (CV) mode or a constant current (CC) mode, but the charging mode is not limited. The PMIC 156 may adjust the voltage or current suitable for the load 157 to which it is connected and provide it to the load 157 . The control circuit 152 may control overall operations of the electronic device 150 . The memory 156 may store instructions for performing overall operations of the electronic device 150 . The memory 105 may store instructions for performing an operation of the wireless power transmitter 100 . The memory 105 or the memory 156 may be implemented in various forms such as read only memory (ROM), random access memory (RAM), or flash memory, and there are no limitations on the form of implementation.

3A shows a block diagram of a power transmission circuit and a power reception circuit according to an induction method or a resonance method according to various embodiments of the present invention.

In various embodiments of the present invention, the power transmission circuit 109 may include a power generation circuit 312 and a coil 313 . The power generating circuit 312 may first rectify the AC power received from the outside, invert the rectified power again, and provide the power to the coil. Due to the inverting operation, a maximum voltage or a voltage of 0 may be alternately applied to the coil 313 at a predetermined period, and thus a magnetic field may be generated from the coil 313 . The inverting frequency, that is, the frequency of the AC waveform applied to the coil 313 may be set to 100 to 205 kHz or 6.78 MHz according to standards, but is not limited thereto. When power is applied to the coil 313, an induced magnetic field whose size changes with time may be formed from the coil 313, and thus power may be transmitted wirelessly. Although not shown, capacitors constituting a resonance circuit together with the coil 313 may be further included in the power transmission circuit 109 . In the coil 321 of the power receiving circuit 159, an induced electromotive force may be generated by a magnetic field formed around it and the size of which changes with time, and accordingly, the power receiving circuit 159 may receive power wirelessly. . The rectifying circuit 322 may rectify the power of the received AC waveform. The converting circuit 323 may adjust the voltage of the rectified power and transfer it to hardware. The power receiving circuit 159 may further include a regulator, or the converting circuit 323 may be replaced with a regulator.

3B is a block diagram of a power transmission circuit and a power reception circuit according to an electromagnetic wave method according to various embodiments of the present invention.

In various embodiments of the present invention, the power transmission circuit 109 may include an amplifier circuit 331, a distribution circuit 332, a phase shifter 333, and an antenna array 334 for power transmission. there is. In various embodiments of the present invention, the power receiving circuit 159 may include a power receiving antenna 341 , a rectifying circuit 342 and a converting circuit 343 .

The amplifying circuit 331 may amplify power provided from the power source 106 and provide the amplified power to the distribution circuit 332 . The amplifier circuit 331 may be implemented with various amplifiers such as a drive amplifier (DA), a high power amplifier (HPA), a gain block amplifier (GBA), or a combination thereof, and the implementation is not limited. The distribution circuit 332 may distribute power output from the amplifier circuit 331 to a plurality of paths. Any circuit capable of distributing input power or signals to a plurality of paths is not limited as the distribution circuit 332 . For example, the distribution circuit 332 may distribute power through as many paths as the number of patch antennas included in the power transmission antenna array 334 . The phase shifter 333 may shift the phase (or delay) of each of the plurality of AC powers provided from the distribution circuit 332 . The number of phase shifters 333 may be plural, and may be, for example, the number of patch antennas included in the antenna array 334 for power transmission. For the phase shifter 333, a hardware device such as HMC642 or HMC1113 may be used. The degree of shift of each phase shifter 333 may be controlled by the control circuit 102 . The control circuit 102 may determine the location of the electronic device 150, and the RF wave is generated at the location of the electronic device 150 (or the location of the antenna 314 for power reception of the electronic device 150). The phases of each of the plurality of AC powers may be shifted so as to cause constructive interference, that is, to be beam-formed. Each of the plurality of patch antennas included in the power transmission antenna array 334 may generate sub-RF waves based on the received power. The RF wave in which the sub-RF wave is interfered may be converted into current, voltage, or power at the power reception antenna 341 and then output. The power reception antenna 341 may include a plurality of patch antennas, and may generate AC waveform current, voltage, or power using an RF wave, that is, an electromagnetic wave formed around it, which will be referred to as received power. can The rectifying circuit 342 may rectify the received power into a DC waveform. The converting circuit 343 may increase or decrease the voltage of the DC waveform power to a predetermined value and output the voltage to the PMIC 156 .

At least one of the power transmission circuit 109 or the power reception circuit 159 according to various embodiments of the present invention includes hardware based on the induction method or resonance method shown in FIG. 3A and hardware based on the electromagnetic wave method shown in FIG. 3B. may also include In this case, the control circuit 102 or the control circuit 152 may select a charging method according to various conditions and control hardware corresponding to the selected charging method to be driven. Alternatively, the control circuit 102 or the control circuit 152 may use both an induction method or a resonance method and an electromagnetic wave method, and may transmit and receive power by driving all included hardware.

A coil 321 outputting AC power using a surrounding magnetic field or an antenna 341 for outputting AC power using a surrounding RF wave may be referred to as a receiving circuit.

4A shows a rectifier circuit according to a comparative example for comparison with various embodiments of the present invention, and FIG. 4B shows a rectifier circuit according to various embodiments of the present invention.

Referring to FIG. 4A , the input terminal 401 of the rectifier circuit according to the comparative example may be connected to a power receiving coil (eg, coil 321) or a power receiving antenna (eg, antenna 341). AC power (PRF) output from a coil (eg, the coil 321) or an antenna for receiving power (eg, the antenna 341) may be provided to the input terminal 401. A matching circuit 411 may be connected to the input terminal 401 . The matching circuit 411 may include at least one of at least one capacitor and at least one coil. The matching circuit 411 may perform impedance matching between the electronic device 150 and the wireless power transmission device 100 . The matching circuit 411 may be connected to the capacitor CP, and the node 403 may be connected to the capacitor CP. A source of the first P-MOSFET MP1 and a source of the first N-MOSFET MN1 may be connected to the node 403 . The gate of the first N-MOSFET (MN1) may be connected to the drain of the first N-MOSFET (MN1) to be grounded 412, and the gate of the first P-MOSFET (MP1) may be connected to the first P-MOSFET (MP1). ), it can be connected to the output terminal 402. A capacitor CRF and a resistor RL may be connected in parallel to each other between the first P-MOSFET MP1 and the output terminal 402 , and the capacitor CRF and the resistor RL may be connected to the ground 413 . AC waveform power (eg, sine wave power) may be applied to the input terminal 401 . AC power may be supplied to the input terminal 401 from a power receiving circuit (eg, the coil 321 or the power receiving antenna 341 ). Accordingly, positive power may be applied to the input terminal 401 during the first period, and negative power may be applied during the second period. When positive power is applied to the input terminal 401, the first P-MOSFET MP1 can be controlled to be in an on state, and thus positive power is supplied to the output terminal 402 through the first P-MOSFET MP1. ) can be provided. When negative power is applied to the input terminal 401, the first P-MOSFET (MP1) is controlled to be in an off state and the first N-MOSFET (MN1) is controlled to be in an on state, so that the negative power is grounded ( 412) and may not be provided to the output terminal 402. Accordingly, only positive power can be supplied to the output terminal 402, so that rectification of AC power can be performed. Meanwhile, when positive power is applied to the input terminal 401, forward loss may occur due to the threshold voltage of the first P-MOSFET MP1. In addition, when negative power is applied to the input terminal 401, the first P-MOSFET MP1 must be completely open. However, since the first P-MOSFET MP1 is not completely open, leakage current flowing in the reverse direction from the output terminal 402 through the first P-MOSFET MP1 may occur, and thus reverse leakage loss may occur. this can happen

4B shows a rectifier circuit according to various embodiments of the present invention. Compared to FIG. 4A, the rectifier circuit according to FIG. 4B may further include a forward loss compensation circuit 421 and a reverse loss compensation circuit 422 connected to the gate of the first P-MOSFET MP1. The forward loss compensation circuit 421 may lower the threshold voltage of the first P-MOSFET MP1 when positive power is applied to the input terminal 401, and accordingly, the first P-MOSFET MP1 ), forward loss caused by the threshold voltage can be prevented. For example, the forward loss compensation circuit 421 may control the gate of the first P-MOSFET MP1 to be connected to the source terminal of the first P-MOSFET MP1, thereby lowering the threshold voltage. can lose In this case, the first P-MOSFET MP1 can also be controlled to be turned on by the forward loss compensation circuit 421 . The reverse loss compensation circuit 422 may control the first P-MOSFET MP1 to be turned off when negative power is applied to the input terminal 401 . For example, the reverse loss compensation circuit 422 may control the output terminal 402 to be connected to the first P-MOSFET MP1 so that the first P-MOSFET MP1 is completely off. can As the first P-MOSFET MP1 is controlled to be completely off, the reverse leakage current can be prevented from flowing through the first P-MOSFET MP1. The forward loss compensation circuit 421 and the reverse loss compensation circuit 422 according to various embodiments of the present invention can prevent forward loss and reverse leakage loss without additional control, thereby preventing loss without additional power consumption. can On the other hand, the first P-MOSFET (MP1) is turned on during the first period to transfer positive power to the output terminal 402, and is turned off during the second period to transfer positive power to the output terminal 402. Those skilled in the art will easily understand that it can be implemented with any switch that does not. In the embodiment of FIG. 4, both the forward loss compensation circuit 421 and the reverse loss compensation circuit 422 are shown as being connected to the first P-MOSFET MP1, but a rectifier circuit according to various embodiments of the present invention. may include only one of the forward loss compensation circuit 421 and the reverse loss compensation circuit 422 .

5 shows a rectifier circuit according to various embodiments of the present invention.

Compared to FIG. 4A, the rectifier circuit of FIG. 5 may further include a first switch 501 and a second switch 502. That is, the forward loss compensation circuit 421 of FIG. 4B may be implemented as the first switch 501 and the backward loss compensation circuit 422 may be implemented as the second switch 502 . While positive power is applied to the input terminal 401, the first switch 501 may be in an on state and the second switch 502 may be in an off state. As the first switch 501 is controlled to be in an on state, the gate of the first P-MOSFET MP1 is connected to the node 403, and thus the gate can be connected to the input terminal 401. In addition, as the second switch 502 is controlled to be off, the gate of the first P-MOSFET MP1 receives a voltage (VINN) applied to the node 403 that is lower than the voltage (VRF) at the output terminal 402. ) may be applied, and accordingly, the first P-MOSFET MP1 may be controlled to be in an on state. Also, since the gate of the first P-MOSFET MP1 may be connected to the source of the first P-MOSFET MP1, the threshold voltage of the first P-MOSFET MP1 may also be lowered. As the threshold voltage decreases, forward loss due to the threshold voltage of the first P-MOSFET MP1 may decrease. On the other hand, if the gate of the first P-MOSFET MP1 is fixed to a relatively low voltage (eg, VINN) in consideration of only the compensation of positive power, the reverse leakage loss may increase. The rectifier circuit according to various embodiments of the present disclosure may include a second switch 502 for compensation when negative power is applied to the input terminal 401 . When negative power is applied to the input terminal 401, the first switch 501 can be turned off and the second switch 502 can be turned on. Accordingly, the gate of the first P-MOSFET (MP1) can be connected to the output terminal 402, a relatively high voltage of VRF can be applied to the gate, and the first P-MOSFET (MP1) is in an off state. It can be. VRF may be, for example, greater than or equal to a specified value, and accordingly, the first P-MOSFET MP1 may be reliably turned off. As the first P-MOSFET MP1 is turned off, leakage current flowing in a reverse direction from the output terminal 402 through the first P-MOSFET MP1 may be reduced. Accordingly, reverse leakage loss may be reduced.

6 shows a rectifier circuit according to various embodiments of the present invention.

Compared to FIG. 4A, the rectifier circuit of FIG. 6 may further include a first switch 601 and a second switch 602. The first switch 601 may be implemented with a second N-MOSFET (MN2), and the second switch 602 may be implemented with a third P-MOSFET (MP3). The gate of the second N-MOSFET MN2 may be connected to the node 403 and, accordingly, to the input terminal 401 . The second N-MOSFET MN2 may be connected to the drain of the second N-MOSFET MN2. A source of the second N-MOSFET MN2 may be connected to a gate of the first P-MOSFET MP1. A source of the second N-MOSFET MN2 may be connected to a source of the third P-MOSFET MP3. A source of the third P-MOSFET MP3 may be connected to a gate of the first P-MOSFET MP1. A gate of the third P-MOSFET MP3 may be connected to the gate and node 403 of the second N-MOSFET MN2. A drain of the third P-MOSFET MP3 may be connected to the drain of the first P-MOSFET MP1 and the output terminal 402 . While positive power is applied to the input terminal 401, the second N-MOSFET MN2 may be in an on state and the third P-MOSFET MP3 may be in an off state. As the second N-MOSFET MN2 is controlled to be in an on state, the gate of the first P-MOSFET MP1 may be connected to the node 403 . In addition, as the third P-MOSFET MP3 is controlled to be off, the voltage applied to the node 403 lower than the voltage VRF at the output terminal 402 is applied to the gate of the first P-MOSFET MP1. (VINN) may be applied, and accordingly, the first P-MOSFET MP1 may be controlled to be in an on state. When negative power is applied to the input terminal 401, the second N-MOSFET MN2 can be turned off and the third P-MOSFET MP3 can be turned on. Accordingly, the gate of the first P-MOSFET MP1 may be connected to the output terminal 402, and the voltage of VRF having a relatively high value (eg, a value greater than or equal to a specified value) may be applied to the gate. The P-MOSFET MP1 may be turned off. As the first P-MOSFET MP1 is turned off, leakage current flowing in a reverse direction from the output terminal 402 through the first P-MOSFET MP1 may be reduced. Accordingly, reverse leakage loss may be reduced. As described above, the 2 N-MOSFET (MN2) and the 3 rd P-MOSFET (MP3) of the rectifier circuit according to various embodiments of the present invention simply control the power received through the input terminal 401 without any control signal. can operate by Accordingly, additional power consumption for reducing losses is not required.

7 shows a rectifier circuit according to various embodiments of the present invention.

Compared to FIG. 4A, the rectifier circuit of FIG. 7 may further include a forward loss compensation circuit 701. The forward loss compensation circuit 701 according to various embodiments of the present disclosure may include a second P-MOSFET MP2 and a capacitor CAUX. The drain of the first P-MOSFET MP1 may be connected to the node 404, and the node 404 may be connected to the source of the second P-MOSFET MP2. Node 404 may be coupled to output 402 . The drain of the second P-MOSFET (MP2) may be connected to the gate of the second P-MOSFET (MP2), and the gate of the second P-MOSFET (MP2) together with the gate of the first P-MOSFET (MP1). It may be connected to one end of the capacitor CAUX. The other end of the capacitor CAUX may be connected to ground 414 . In the case of the circuit connection of FIG. 7 , the voltage VRF at the output terminal may be 1/2 (VINN+Vthp1-Vthp2+VAUX). Vthp1 may be a threshold voltage of the first P-MOSFET MP1, and Vthp2 may be a threshold voltage of the second P-MOSFET MP2. As can be seen from the above equation, the threshold voltage (Vthp1) of the first P-MOSFET (MP1) and the threshold voltage (Vthp2) of the second P-MOSFET (MP2) can cancel each other, and thus the input terminal 401 When positive power is applied to , the threshold voltage may decrease. While positive power is applied to the input terminal 401, the second P-MOSFET MP2 may be in an on state. As the threshold voltage decreases, forward loss during positive power application may decrease.

8 shows a rectifier circuit according to various embodiments of the present invention.

Compared to FIG. 7 , the rectifier circuit of FIG. 8 may further include a first switch 601 and a second switch 602 . The first switch 601 may be implemented with a second N-MOSFET (MN2), and the second switch 602 may be implemented with a third P-MOSFET (MP3). As described with reference to FIG. 6, while positive power is applied to the input terminal 401, the second N-MOSFET (MN2) may be in an on state and the third P-MOSFET (MP3) may be in an off state. can As the second N-MOSFET MN2 is controlled to be in an on state, the gate of the first P-MOSFET MP1 may be connected to the node 403 . In addition, as the third P-MOSFET MP3 is controlled to be off, the voltage applied to the node 403 lower than the voltage VRF at the output terminal 402 is applied to the gate of the first P-MOSFET MP1. (VINN) may be applied, and accordingly, the first P-MOSFET MP1 may be controlled to be in an on state. When negative power is applied to the input terminal 401, the second N-MOSFET MN2 can be turned off and the third P-MOSFET MP3 can be turned on. Accordingly, the gate of the first P-MOSFET MP1 may be connected to the output terminal 402, the voltage of VRF may be applied to the gate, and the first P-MOSFET MP1 may be turned off. As the first P-MOSFET MP1 is turned off, leakage current flowing in a reverse direction from the output terminal 402 through the first P-MOSFET MP1 may be reduced. Accordingly, both the forward loss and the reverse leakage loss according to the decrease in the threshold voltage may be reduced.

For example, during the positive period, the first P-MOSFET MP1 and the second P-MOSFET MP2 may be forward-biased. In this case, the threshold voltages of the first P-MOSFET MP1 and the second P-MOSFET MP2 may be reduced, which means that the drain of the second P-MOSFET MP2 connects the second N-MOSFET MN2. may result from being connected to node 403 via In this case, the voltage V _SGP3 between the source and gate of the third P-MOSFET MP3 may be less than the threshold voltage, and the third P-MOSFET MP3 may be maintained in an off state. Meanwhile, during the negative period, the first P-MOSFET MP1 and the second P-MOSFET MP2 may be reverse-biased. In this case, V _SGP3 can be maintained in an on state, and V _SGP1 , which is the voltage between the source and gate of the first P-MOSFET (MP1) and V, which is the voltage between the source and gate of the second P-MOSFET (MP2) _SGP2 can be reduced to zero. Accordingly, since the source of the second P-MOSFET MP2 is connected to the output terminal 402, reverse leakage current can be reduced.

During the positive period, as the voltage (V ₀ ) of the output stage 402 increases, V _SGP2 can continuously increase, resulting from the connection of the source of the second P-MOSFET MP2 to the output stage 402. It can be. The second P-MOSFET MP2 may induce the 1 P-MOSFET MP1 into the convergence region when V _SGP2 becomes equal to the threshold voltage (|V _THP1 |) of the first P-MOSFET MP1. there is. During the negative period, capacitor C _AUX may conserve some of the charge loss during reverse conduction in the rectifier. Equations 1 to 3 are equations expressing the voltage (V ₀ ) at the output terminal 402 as V _INN , V _SDP1 , V _SDP2 , and V _AUX . V _INN is the voltage at node 403 and V _SDP1 is the source-to-drain voltage of the first P-MOSFET MP1 and may be, for example, the voltage drop of the first P-MOSFET MP1. V _SDP2 may be a source-drain voltage of the second P-MOSFET MP2, and may be, for example, a voltage drop of the second P-MOSFET MP2. V _AUX may be a gate voltage of the second P-MOSFET MP2.

When the first P-MOSFET MP1 and the second P-MOSFET MP2 enter the convergence region, V _SDP1 and V _SDP2 are the thresholds of the first P-MOSFET MP1 and the second P-MOSFET MP2. can be voltage. Similarly, since the voltage (V ₀ ) at the output terminal 402 can be expressed as Equations 1 to 3, Equations 4 to 6 can be derived.

By subtracting Equation 5 from Equation 6, Equation 7 can be derived.

From Equation 6, it can be confirmed that V _SGP2 increases in proportion to V ₀ . When V _SGP2 becomes the threshold voltage, the first P-MOSFET MP1 may enter a convergence region. From Equations 3 to 7, V ₀ can be derived as shown in Equations 8 and 9.

In Equation 8, V _SG1 and V _SG2 may be approximated as threshold voltages. |V _THP2 | may be the threshold voltage of the first P-MOSFET MP1.

As described above, the influence of the threshold voltage on the DC output voltage can be reduced.

9 shows a rectifier circuit according to various embodiments of the present invention.

Referring to FIG. 9 , an input terminal 401 may be connected to a plurality of rectifier circuits 901 to 906 . Each of the plurality of rectifier circuits 901 to 906 may be composed of a unit cell. A matching circuit 411 may be connected between the input terminal 401 and the plurality of rectifier circuits 901 to 906 . Each of the plurality of rectifier circuits 901 to 906 may be connected in parallel with each other. Each of the plurality of rectifier circuits 901 to 906 may receive and rectify the AC power received through the input terminal 401 and output the rectified DC power. For example, when 3W of power is input from the input terminal 401, each of the six rectifier circuits 901 to 906 may rectify and output 0.5W of power. Accordingly, one rectifier circuit may be implemented to include elements (eg, MOSFETs) for processing relatively small-sized power, and thus processing efficiency may be increased. Each of the plurality of rectifier circuits 901 to 906 may be a rectifier circuit according to any one of FIGS. 4A, 4B, 5, 6, 7 or 8 . The DC combiner 910 may combine the power received from the plurality of rectifier circuits 901 to 906 and output the combined DC power to the output terminal 402 . The DC combiner 910 may include, for example, a capacitor 911 capable of combining charges and a ground 912 .

10 shows a block diagram of an electronic device according to various embodiments of the present invention.

Referring to FIG. 10, the electronic device 150 includes a power receiving antenna 1001, a matching circuit 1002, a power receiving coil 1011, capacitors 1012 and 1013, a rectifier circuit 1014, a plurality of Rectifier circuits 1021, 1022, 1023, combiner 1031, switch (SW_IN), converting control circuit 1032, transistors 1033, 1034, LDO (linear drop out) regulator 1036, charger 1041 ), battery 1042, communication module 1043, inductor (L1), capacitor (C1), serial peripheral interface (SPI) 1051, PCB board 1070, switch (SW_EX) and capacitor (CRF) can do.

The antenna 1001 for power reception may output AC power using an RF wave formed around it. The matching circuit 1002 may include at least one of at least one capacitor or at least one inductor connected to the antenna 1001 for power reception, and accordingly, an impedance (or , load) can be changed. The plurality of rectifying circuits 1021 , 1022 , and 1023 may receive and rectify AC power output from the antenna 1001 for power reception. Each of the plurality of rectifier circuits 1021, 1022, and 1023 may be a rectifier circuit according to any one of FIGS. 4A, 4B, 5, 6, 7, or 8. The combiner 1031 may receive power from a rectifier circuit to perform rectification among the plurality of rectifier circuits 1021 , 1022 , and 1023 , and disconnect electrical connections to the remaining non-selected rectifier circuits. A capacitor CRF may be connected to the plurality of rectifier circuits 1021 , 1022 , and 1023 , and the capacitor CRF may be connected to the ground 1081 . The combiner 1031 may combine rectified power received from at least one of the plurality of rectifier circuits 1021 , 1022 , and 1023 . The switch SW_IN may be turned on when it is determined that the power receiving antenna 1001 receives power. In addition, when it is determined that another power receiving antenna (not shown) receives power, it may be controlled to be in an off state. AC power from another power reception antenna (not shown) may be rectified through a plurality of external RF rectifier circuits 1071 , 1072 , and 1073 included in the PCB board 1070 . In this case, the switch SW_EX may be controlled to be in an on state. For example, the control circuit may control the on/off state of the switch SW_IN or the switch SW_EX through the SPI 1051 . The coil 1011 and the capacitors 1012 and 1013 may constitute a resonant circuit that receives, for example, 6.78 MHz power. Accordingly, VAC and VACB may be applied to both ends of the resonance circuit. Power received from the resonance circuit may be rectified by the rectifier circuit 1014 and provided to the combiner 1031 . The voltage of Buck IN may be applied to the output terminal of the combiner 1031 . The conversion control circuit 1032 may control on/off states of the transistors 1033 and 1034, and accordingly, an input voltage may be converted (eg, buck-converted) and output. The source of transistor 1034 may be connected to ground 1035 . A voltage of, for example, 5V may be provided to the charger 1041 by the conversion. The transistors 1033 and 1034 are connected to the inductor L1 and the capacitor C1, one end of which is grounded, and connected to the charger 1041 to provide a voltage of 5V. The charger 1041 may charge the battery 1042 . The LDO regulator 1036 may be connected to the inductor 1031 to convert, for example, a voltage of 5V to 3.3V and provide it to the communication module 1043.

11 shows a block diagram of an electronic device according to various embodiments of the present invention.

Referring to FIG. 11, an electronic device 150 includes an antenna array 1101, a control circuit 1102, a sensor 1103, a plurality of switches 1111 to 1116, a plurality of rectifier circuits 1121 to 1126, and a computer. Biner 1130 may be included. Each of the plurality of rectifier circuits 1121 to 1126 may be a rectifier circuit according to any one of FIGS. 4A, 4B, 5, 6, 7, or 8 . The antenna array 1101 may receive an RF wave and output AC power. The sensor 1103 may sense electrical characteristics representing the magnitude of the RF wave received by the antenna array 1101 . For example, the sensor 1103 may sense at least one of voltage, current, or power at an output end of the antenna array 1101 . Alternatively, the sensor 1103 may sense at least one of voltage, current, or power at an output terminal of the combiner 1130 . The control circuit 1102 may receive a sensing result and determine the number of rectification circuits to perform rectification based on the sensing result. For example, the control circuit 1102 may refer to information related to the received power and the switch control signal as shown in Table 1.

switch control signal The amount of received power (V) 1st switch (1111) Second switch (1112) 3rd switch (1113) 4th switch (1114) 5th switch (1115) 6th switch (1116) below a ON OFF OFF OFF OFF OFF more than a and less than or equal to b ON ON OFF OFF OFF OFF More than b and less than or equal to c ON ON ON OFF OFF OFF d more than e or less ON ON ON ON OFF OFF More than e and less than or equal to f ON ON ON ON ON OFF exceeds f ON ON ON ON ON ON

The magnitude (V) of the received power in Table 1 may be, for example, the magnitude of the voltage at the output terminal of the antenna array 1101 in FIG. 11, but as described above, it can represent the magnitude of the received power There is no limitation as far as the electrical characteristics at the points are concerned. For example, if the control circuit 1102 determines that the magnitude of the voltage corresponding to the magnitude of the received power is within the range greater than b and equal to or less than c, three rectifier circuits (eg, 1121, 1122, and 1123) perform rectification. It is possible to control the switches 1111 to 1116 to perform. Accordingly, processing efficiency may increase as an optimal number of rectifier circuits perform rectification according to the magnitude of received power. For example, each of the switches 1111 to 1116 may be implemented as an FET. In this case, the control circuit 1102 turns on/off the switches 1111 to 1116 by controlling the voltage applied to the gate of each of the switches 111 to 1116 based on the determination result of the rectifier circuit to be driven. state can be controlled. Meanwhile, the implementation method of the switches 1111 to 1116 is not limited, and the control circuit 1102 controls the on/off state of each of the switches 1111 to 1116 according to the implementation method of the switches 1111 to 1116. Those skilled in the art will readily understand that this can be done.

12 is a flowchart illustrating a method of operating an electronic device according to various embodiments of the present disclosure.

In operation 1201, the electronic device 150 according to various embodiments of the present disclosure may rectify the received power using a preset number of rectifier circuits. For example, the electronic device 150 may perform rectification using all of the plurality of rectifier circuits 1121 to 1126 in FIG. 11 . The number of rectifier circuits performing initial rectification may be a default value, which may be variously determined according to implementation. In operation 1203, the electronic device 150 may check the received power level. For example, the electronic device 150 measures the magnitude of voltage, current, or power at an output terminal of a coil or antenna array, or measures the magnitude of voltage, current, or power at an output terminal of a combiner to measure the magnitude of power. can be checked. In operation 1205, the electronic device 150 may check the number of rectifier circuits corresponding to the size of the received power. For example, the electronic device 150 may check the number of rectifier circuits or determine the on/off state of a switch connected to each rectifier circuit based on the related information shown in Table 1. In operation 1207, the electronic device 150 may rectify the received power using the identified number of rectifier circuits, and control the remaining rectifier circuits not to perform rectification.

13 is a flowchart illustrating a method of operating an electronic device according to various embodiments of the present disclosure.

In operation 1301, the electronic device 150 according to various embodiments of the present disclosure may rectify the received power using a predetermined number of rectifying circuits. As described in FIG. 12 , for example, the number of rectifier circuits performing initial rectification may be a default value. In operation 1303, the electronic device 150 may measure impedance at a designated point. For example, the electronic device 150 may measure impedance at various points, such as impedance in a coil or antenna array, impedance in a battery, and the like, and there is no limitation on the point where the impedance is measured. In operation 1305, the electronic device 150 may check the number of rectifier circuits corresponding to the measured impedance. For example, the electronic device 150 may store related information as shown in Table 2.

switch control signal The magnitude of the measured impedance (ohm) 1st switch (1111) Second switch (1112) 3rd switch (1113) 4th switch (1114) 5th switch (1115) 6th switch (1116) g or less ON OFF OFF OFF OFF OFF more than g and less than h ON ON OFF OFF OFF OFF More than h and less than or equal to i ON ON ON OFF OFF OFF greater than i and less than or equal to j ON ON ON ON OFF OFF More than j and less than or equal to k ON ON ON ON ON OFF k exceeds ON ON ON ON ON ON

The magnitude (ohm) of the measured impedance in Table 2 may be, for example, the magnitude of the impedance in the antenna 1001 or the coil 1011 in FIG. 10, or the magnitude of the impedance in the battery 1042, There is no limit to the point at which the magnitude of the impedance is measured. For example, when the control circuit determines that the magnitude of the voltage corresponding to the magnitude of the received power is within the range of greater than g and equal to or less than h, the switches allow two rectifier circuits (eg, 1121 and 1122) to perform rectification. (1111 to 1116) can be controlled. Accordingly, processing efficiency may increase as an optimal number of rectifier circuits perform rectification according to the magnitude of received power. In addition, the electronic device according to various embodiments of the present invention may determine the rectifier to perform rectification or the number of rectifiers to perform rectification by using both the magnitude of received power and the magnitude of impedance at a designated point. there is.

14 shows a circuit diagram of a resonant circuit and a rectifier circuit according to various embodiments. For example, FIG. 14 may be an example of a power receiving coil 1011, capacitors 1012 and 1013, and a rectifier circuit 1014 receiving power through a resonance method in FIG. 10 . The coil for receiving power (L _RS ) may constitute a resonant circuit together with the capacitor (C _RS ) and the capacitor (C _LM ). AC power received through the resonance circuit may be rectified through the full-bridge diode. A full-bridge diode can rectify, for example, alternating voltages (V _AC and V _ACB ) to a direct voltage of V _RECT . The rectified voltage (V _{RECT )} may be connected to the rectifying capacitor (C _RECT ), and although not shown, the rectified voltage (V _RECT ) is a combiner ( 1031) can be connected to various types of other circuits. The rectifying capacitor C _RECT may be grounded, and thus, even after rectification, an AC component remaining after rectification may be applied to the ground through the rectifying capacitor C _RECT , so that only a direct current component may be transferred to a circuit connected thereafter.

For example, a full-bridge diode may include four MOSFTETs (MN1, MN2, MN3, and MN4). Among the four MOSTFETs (MN1, MN2, MN3, MN4), MOSFET (MN1) and MOSFET (MN2) can be low side devices, and MOSFET (MN3) and MOSFET (MN4) are high side may be minor. For example, while the MOSFETs MN1 and MN2 are turned on during the first period, the MOSFETs MN3 and MN4 may be turned off. In addition, during the second period after the first period, while the MOSFETs MN3 and MN4 are turned on, the MOSFETs MN1 and MN2 may be turned off. According to the operation of the full-bridge diode described above, AC power may be rectified into DC. On/off of the MOSTFETs (MN1, MN2, MN3, and MN4) may be controlled by gate voltages (VD1, VD2, VD3, and VD4) applied to respective gates. The first open loop delay compensation (OLDC) circuit 1401 may output each of the first driving voltage VD1 and the third driving voltage VD3. Each of the first driver DRV1 and the third driver DRV3 generates a first gate voltage VG1 and a third gate voltage VG3 from the first driving voltage VD1 and the third driving voltage VD3, respectively. and transfer the generated first gate voltage VG1 and third gate voltage VG3 to the gate of the first MOSFET MN1 and the gate of the third MOSFET MN3, respectively. The second OLDC circuit 1402 may output each of the second driving voltage VD2 and the fourth driving voltage VD4. Each of the second driver DRV2 and the fourth driver DRV4 generates a second gate voltage VG2 and a fourth gate voltage VG4 from the second driving voltage VD2 and the fourth driving voltage VD4, respectively. and transfer the generated second gate voltage VG2 and fourth gate voltage VG4 to the gate of the second MOSFET MN2 and the gate of the fourth MOSFET MN4, respectively. In various embodiments, the first OLDC circuit 1401 may adjust the phases of the first driving voltage VD1 and the third driving voltage VD3 outputted using the first gate voltage VG1, and the second OLDC The circuit 1402 may adjust the phases of the output second driving voltage VD2 and the fourth driving voltage VD4 using the second gate voltage VG2. Phase adjustment of the OLDC circuits 1401 and 1402 will be described later in detail.

For example, when a resonant circuit receives power having a resonant frequency of 6.78 MHz, since the frequency of 6.78 MHz is relatively high, parasitic capacitance and consequent internal circuit delay may reduce the efficiency of the rectifier circuit. can For example, the delay generated by the drivers DRV1 to DRV4 may cause a delay in the gate voltages VG1 to VG4, whereby the voltage of the received power (eg, V _AC ) crosses zero. A difference may occur between a zero crossing point and an on/off point of the MOSFETs MN1 to MN4, that is, a rising edge or a falling edge of the gate voltages VG1 to VG4. The difference may cause reverse leakage current in the MOSFET, which reduces the efficiency of the entire rectifier circuit.

Each of the OLDC circuits 1401 and 1402 according to various embodiments receives gate voltages VG1 and VG2 output from drivers (eg, the first driver DRV1 and the second driver DRV2), respectively, and It is possible to adjust the phases of the driving voltages VD1 to VD4 output by using the Accordingly, delays caused by the drivers DRV1 to DRV4 may be compensated for. For example, each of the OLDC circuits 1401 and 1402 converts the falling edge of the output voltage (eg, VG1) from the driver to the received AC power (eg, VAC) of the MOSFET (eg, MOSFET MN1). It can be matched with the time of crossing 0. Accordingly, the point at which the alternating power (eg VAC) crosses zero (eg when the alternating current (eg VAC) transitions from a negative voltage to a positive voltage or when the alternating power (eg VAC) is converted to a positive voltage). At the point at which the voltage is converted to a negative voltage at ), the MOSFET MN1 can be turned off exactly.

15 shows a block diagram of an OLDC circuit in accordance with various embodiments. The embodiment of FIG. 15 will be described in more detail with reference to FIG. 16 . 16 illustrates signals received or generated according to various embodiments.

Referring to FIG. 15, the first OLDC circuit 1401 includes a voltage limiter 1501, a divider (/8 div.) 1502, a digital phase detector 1503, and an edge detector ( An edge detector 1504, a coarse delay adjuster 1505, a fine delay adjusting cell 1506, a mux 1507, and SR latches 1508 and 1509 may be included.

The voltage limiter 1501 may receive an AC voltage (V _AC ) output from a resonance circuit (or a coil for receiving power). For example, as shown in FIG. 16 , the AC voltage V _AC may have a sine wave. The voltage limiter 1501 may generate a square wave limited voltage VL1 from the received AC voltage V _AC . As shown in FIG. 16 , the limiting voltage VL1 may be a rectangular wave having substantially the same phase as the AC voltage V _AC . The limited voltage VL1 may be provided to the divider 1502 and the edge detector 1504. The divider 1502 may divide the limited voltage VL1 to generate the divided voltage VLD1. For example, the divided voltage VLD1 in the form of a square wave having one half wave may be generated at a time corresponding to eight half waves of the limited voltage VL1. For example, when the duty cycles of the first driving voltage VD1 and the fourth driving voltage VD4 are changed, a certain amount of time may be required for internal signals of the rectifier circuit to be stabilized. For stable operation, the divider 1502 may divide the input signal.

Meanwhile, the edge detector 1504 may detect an edge of the limited voltage VL1. The detected edge ED1 may be expressed as an edge voltage ED1 having a delta function waveform at the time of the rising edge of the limited voltage VL1 as shown in FIG. 16 . The edge voltage ED1 may be input to a set (S) terminal of each of the SR latches 1508 and 1509. In addition, the edge voltage ED1 may be transferred to the coarse delay adjuster 1505. The coarse delay adjuster 1505 may delay the received edge voltage ED1 according to a first unit, and the fine delay cell 1506 may delay the first delayed edge voltage ED1 output from the coarse delay adjuster 1505. ) can be delayed according to the second unit. For example, the first unit may be greater than the second unit, and accordingly, the coarse delay adjuster 1505 primarily delays the edge voltage ED1, and the fine delay cell 1506 secondarily delays the edge voltage ED1. The voltage (ED1) can be finely adjusted. For example, the fine delay cell 1506 may consist of 16 cells, and the number of cells to activate the delay may be determined according to the degree of delay.

Meanwhile, the digital phase detector 1503 may receive the divided voltage VLD1 and the gate voltage VG1 already output from the driver. The digital phase detector 1503 may compare (1601 to 1605) the divided voltage VLD1 and the gate voltage VG1, for example, whether the divided voltage VLD1 precedes the gate voltage VG1 ( lead) or whether the divided voltage VLD1 lags behind the gate voltage VG1. In addition, the digital phase detector 1503 may determine the degree of difference between the divided voltage VLD1 and the gate voltage VG1. The digital phase detector 1503 can generate either an up signal or a down signal based on the comparison result. The digital phase detector 1503 may generate the MUX[3:0] signal, and the MUX[3:0] signal may be provided to the mux 1507. The MUX[3:0] signal is controlled to increase by 1, for example, when the divided voltage VLD1 lags behind the first gate voltage VG1, and thus the delay may be increased. Alternatively, when the divided voltage VLD1 precedes the first gate voltage VG1, the MUX[3:0] signal is controlled to decrease by 1, and thus the delay can be reduced. A delayed signal output from the fine delay cell 1506 may be input to the mux 1507, and the delayed signal may be selected by the MUX[3:0] signal. Accordingly, the falling edge of the first gate voltage VG1 and the falling edge of the limited voltage VL1 may be synchronized with each other. This may mean that the received voltage VAC is synchronized with the gate voltage. The low signal RE_L output from the mux 1507 may be a signal in which the edge voltage ED1 is delayed by the coarse delay adjuster 1505 and the fine delay cell 1506. The low signal RE_L is provided to the reset (reset, R) terminal of the SR latches 1508 and 1509, and thus can be used as a reset signal of the SR latches 1508 and 1509. The SR latches 1508 and 1509 may output a first driving voltage VD1 for the first gate voltage VG1 and a fourth driving voltage VD4 for the fourth gate voltage VG4.

Meanwhile, for the high side, the delay of the fourth driver (DRV4) may be longer than that of the first driver (DRV1), which is the effect of the level shifter to make VGS of the fourth MOSFET (MN4) 5V, for example. can be Therefore, the high signal RE_H may be selected to be smaller than the low signal RE_L, for example, may be set to be smaller than “0101”. This may be due to a difference in delay between the low side and the high side. Comparison of the digital phase detector 1503 may be repeated a specified number of times, and may be terminated according to detection of a rising edge of a lock signal (LCK signal). For example, when the falling edges of the divided voltage VLD1 and the first gate voltage VG1 are synchronized, the rising edge of the lock signal may be generated. As described above, since the falling edge of the received voltage VAC and the on/off switching time of the MOSFET can coincide, the reverse leakage current is reduced, and thus the rectification efficiency can be greatly increased.

17 shows a circuit diagram of a converting circuit according to various embodiments. 18 is a circuit diagram of a zero current detector (ZCD) according to various embodiments.

As shown in FIG. 17, the converting circuit according to various embodiments includes a high-side switch M0 and a low-side switch M1, a capacitor C _Buck , and an inductor L _Buck ), and a ground terminal. The switch M0 may be turned on during one period, during the first period, and turned off during the remaining second period. When the switch M0 is turned on, the voltage of V _{X_WPR} may be provided to the inductor L _Buck . The switch M1 is turned on when the switch M0 is turned off, and may be turned off when the switch M0 is turned on. When the switch M1 is turned on, the inductor L _Buck may be connected to the ground terminal. The capacitor (C _Buck ) may supply the charged charging voltage (V _Buck ) to the load (R _L ). The charging/discharging of the capacitor (C _Buck ) and the inductor (L _Buck ) can be performed like a normal buck-converter. Meanwhile, when the voltage required by the load R _L is relatively small, the magnitude of the current to flow through the inductor L _Buck may also be relatively small. Accordingly, it is necessary to be in a zero current state in which current does not flow from the inductor L _Buck to the capacitor C _Buck in some sections of the period.

According to various embodiments, a first process in which an inductor (L _Buck ) receives and stores current, a second process in which current is applied to a capacitor (C _Buck ) by connecting the inductor (L _Buck ) to ground, and an inductor (L _{Buck )} ) is not connected to both the external power supply and the ground, and only the capacitor C _Buck is connected to the ground. A third process may be performed. In the case of the first process, the switch M0 may be turned on and the switch M1 may be turned off. In the case of the second process, the switch M0 may be turned off and the switch M1 may be turned on. In the case of the third process, the switch M0 may be turned off and the switch M1 may be turned off. Since current does not flow in the inductor L _Buck during the above-described third process, it may be referred to as a zero current state, and the above-described converting mode may be referred to as a discontinuous current mode.

According to various embodiments, the zero current detector 1701 may provide a low side input signal L_SIDE_IN for a low side signal L_SIDE capable of controlling on/off of the switch M1. The driver 1707 may provide the low side signal L_SIDE generated using the low side input signal L_SIDE_IN to the switch M1. The zero current detector 1701 may receive a high side signal (H_SIDE), a low side signal (L_SIDE), and a voltage of V _{X _ WPR} . The zero current detector 1701 can sense the duty of the high side signal (H_SIDE), the low side signal (L_SIDE), and V _{X _ WPR} , and can adjust the duty of the low side input signal (L_SIDE_IN). For example, the zero current detector 1701 may adjust the duty of the low side input signal L_SIDE_IN so that the low side signal L_SIDE and the high side signal H_SIDE do not turn on at the same time.

A voltage of V _Buck may be applied to the load (R _L ) of the output stage. The converting circuit may include a resistor R1 and a resistor R2, and a voltage of V _FB may be applied to a node between the resistor R1 and the resistor R2, which is It can be determined according to the load ratio of R2). The first signal generating circuit 1704 may receive the voltage of V _FB and the reference voltage (V _{WPR _ BGR} ), and may output the first signal (V _ERR ) using them. For example, the first signal generating circuit 1704 may generate the first signal V _ERR according to a pulse frequency modulation (PFM) scheme. The second signal generating circuit 1705 may receive the reference voltage (V _{WPR _ BGR} ), and may generate the second signal (V _SAW ) in a pulse width modulation (PWM) method. The second signal generating circuit 1705 may receive V _FB as an input. The comparator 1703 may output a signal of V _PWM based on both input signals V _ERR and V _SAW . The non-overlapping control circuit 1702 may output such that the first output signal Duty_Out and the second output signal Duty_OutB do not turn on at the same time based on the received V _PWM signal. The first output signal (Duty_Out) is input to the driver 1706, and the driver 1706 can output a high side signal (H_SIDE) capable of controlling on/off of the switch M0. The zero current detector 1701 may generate the low side input signal L_SIDE_IN based on the received second output signal Duty_OutB. Referring to FIG. 18 , the first delay circuit 1801 may receive the second output signal Duty_OutB and output a delayed first delay signal DELAY_1. The second delay circuit 1802 receives the first delay signal DELAY_1, generates a delayed second delay signal DELAY_2, and outputs the second delay signal DELAY_2. The first delay signal DELAY_1 may be input to the clock terminal of the first D flip-flop 1803, and the second delay signal DELAY_2 may be input to the clock terminal of the second D flip-flop 1804. A voltage of V _{X _ WPR} may be applied to input terminals of the first D flip-flop 1803 and the second D flip-flop 1804 . Logic values S1 and S2 of voltage V _{X _ WPR} at sampling points may be output from output terminals of the D flip-flops 1803 and 1804, and S1 and S2 may indicate sampling points. The decision circuits 1805 , 1806 , and 1807 may generate a decision signal based on the logic values S1 and S2 . For example, when S1 and S2 are “00”, the decision circuits 1805 , 1806 , and 1807 may generate an UP signal and output it to the counter 1808 . For example, when S1 and S2 are “11”, the decision circuits 1805, 1806, and 1807 may generate a DN signal and output it to the counter 1808. For example, the decision circuits 1805 , 1806 , and 1807 may output a STAY signal when an UP signal or a DN signal is repeatedly generated, for example, a specified number of times or more. The zero current detector 1701 detects the current applied to the inductor at the time of switching off in the previous cycle while monitoring the voltage (V _{X _ WPR} ) at the node for the switching of the switch M1 in every cycle. can do. The zero current detector 1701 may continuously detect the first delay signal DELAY_1 and the second delay signal DELAY_2 and the voltage V _{X _ WPR} at the node. Accordingly, even if the values of S1 and S2 are changed due to load change, the zero current detector 1701, together with the control of the second output signal Duty_OutB and the counter 1808, determines that the current applied to the inductor is 0A at a certain point in time. cognition can be detected. According to the operation of the zero current detector 1701, the counter 1808 can count the UP signal/DN signal and output the duty control signal (DUTY_CONT<7:0>) to the digital control pulse generator 1809 accordingly. there is. The digital control pulse generator 1809 may generate and output the low-side input signal L_SIDE_IN based on the high-side signal H_SIDE and the duty control signal DUTY_CONT<7:0>. An input signal (L_SIDE_IN) may be provided to the driver 1807. As described above, the converting circuit may convert the voltage of the rectified power using relatively low power. In addition, the conversion circuit according to the present embodiment may reduce a loss caused by a zero current sensing timing error due to an offset in the conversion circuit including the conventional comparator.

Each of the aforementioned components of the wireless power transmitter or electronic device may be composed of one or more components, and the name of the corresponding component may vary depending on the type of electronic device. In various embodiments, an electronic device may include at least one of the above-described components, and some components may be omitted or additional components may be further included. In addition, some of the components of the electronic device according to various embodiments are combined to form a single entity, so that the functions of the corresponding components before being combined can be performed the same.

The term "module" used in this document may refer to a unit including one or a combination of two or more of, for example, hardware, software, or firmware. “Module” may be used interchangeably with terms such as, for example, unit, logic, logical block, component, or circuit. A “module” may be a minimum unit or part of an integrally formed part. A “module” may be a minimal unit or part thereof that performs one or more functions. A “module” may be implemented mechanically or electronically. For example, a "module" is any known or future developed application-specific integrated circuit (ASIC) chip, field-programmable gate arrays (FPGAs), or programmable-logic device that performs certain operations. may contain at least one.

At least some of the devices (eg, modules or functions thereof) or methods (eg, operations) according to various embodiments may be stored on computer-readable storage media in the form of, for example, program modules. It can be implemented as a command stored in . When the instruction is executed by a processor, the one or more processors may perform a function corresponding to the instruction. A computer-readable storage medium may be, for example, a memory.

According to various embodiments of the present invention, in a storage medium storing instructions, the instructions are set to cause the at least one processor to perform at least one operation when executed by at least one processor, and the at least one The operation of is an operation of receiving power wirelessly, an operation of obtaining the size of the received power, an operation of selecting a rectifier circuit to perform rectification from among the plurality of rectifier circuits based on the size of the received power, and An operation of rectifying the received power using the selected rectifying circuit may be included.

As described above, the instructions may be stored in an external server or may be downloaded and installed in an electronic device such as a wireless power transmitter. That is, the external server according to various embodiments of the present invention may store commands downloadable by the wireless power transmitter.

The computer-readable recording medium includes a hard disk, a floppy disk, magnetic media (eg, magnetic tape), optical media (eg, CD-ROM (compact disc read only memory), DVD (digital versatile disc), magneto-optical media (such as floptical disk), hardware devices (such as read only memory (ROM), random access memory (RAM), or flash memory) etc.), etc. In addition, program instructions may include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter, etc. The above-described hardware device may include It may be configured to act as one or more software modules to perform the operations of various embodiments, and vice versa.

A module or program module according to various embodiments may include at least one or more of the aforementioned components, some may be omitted, or additional other components may be included. Operations performed by modules, program modules, or other components according to various embodiments may be executed in a sequential, parallel, repetitive, or heuristic manner. Also, some actions may be performed in a different order, omitted, or other actions may be added.

And the embodiments disclosed in this document are presented for explanation and understanding of the disclosed technical content, and do not limit the scope of the present disclosure. Therefore, the scope of the present disclosure should be construed to include all changes or various other embodiments based on the technical spirit of the present disclosure.

Claims (20)

In electronic devices,
a power receiving circuit that wirelessly receives power and outputs AC power; and
A rectifier circuit for rectifying the AC power output from the power receiving circuit
Including,
The rectifier circuit,
While the AC power has a positive amplitude, power having the positive amplitude is transmitted to the output terminal of the rectifier circuit, and while the AC power has a negative amplitude, the power having the negative amplitude is transmitted to the output terminal of the rectifier circuit. a first P-MOSFET that does not transfer power; and
A forward loss compensation circuit connected to the first P-MOSFET and lowering the threshold voltage of the first P-MOSFET while the AC power has a positive amplitude
An electronic device comprising a. According to claim 1,
The forward loss compensation circuit includes a first switch connecting the gate of the first P-MOSFET to the input terminal of the rectifier circuit while the AC power has a positive amplitude. According to claim 2,
The first switch connects the source of the first P-MOSFET to the gate of the first P-MOSFET while the AC power has a positive amplitude. According to claim 3,
The first switch includes a first N-MOSFET whose source is connected to the gate of the first P-MOSFET and whose drain and gate are connected to the input terminal and the source of the first P-MOSFET. According to claim 4,
The first switch does not connect the gate of the first P-MOSFET to the input terminal of the rectifier circuit while the AC power has a negative amplitude. According to claim 1,
A reverse loss compensation circuit connected to the first P-MOSFET and applying a voltage greater than or equal to a specified value to a gate of the first P-MOSFET while the AC power has a negative amplitude.
An electronic device further comprising a. According to claim 6,
The reverse loss compensation circuit includes a second switch connecting the gate of the first P-MOSFET to the output terminal of the rectifier circuit while the AC power has a negative amplitude. According to claim 7,
The second switch connects the drain of the first P-MOSFET to the gate of the first P-MOSFET while the AC power has a negative amplitude. ◈Claim 9 was abandoned when the registration fee was paid.◈ According to claim 8,
The second switch does not connect the drain of the first P-MOSFET to the gate of the first P-MOSFET while the AC power has a positive amplitude. According to claim 7,
The second switch,
A source is connected to the gate of the first P-MOSFET, a gate is connected to the source of the first P-MOSFET and the input terminal of the rectifier circuit, and a drain is connected to the drain and the output terminal of the first P-MOSFET. Electronic device containing 2 P-MOSFETs. According to claim 1,
The forward loss compensation circuit,
a capacitor having one end connected to the gate of the first P-MOSFET and the other end connected to ground; and
A third P-MOSFET having a gate connected to the gate of the first P-MOSFET, a source connected to the drain and the output terminal of the first P-MOSFET, and a drain connected to the gate of the first P-MOSFET
Electronic device comprising a. delete delete delete delete delete delete delete delete delete

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