KR102510147B1 - Liquid crystal display and manufacturing method of the same - Google Patents

Abstract

The present invention provides a liquid crystal display device including a lower structure, a planarization layer, a protrusion and a spacer. The lower structure includes a gate line positioned on the lower substrate. A planarization layer is located on the underlying structure. The protrusion protrudes from the planarization layer and has a closed curve shape. A spacer is positioned on the upper substrate. When the lower substrate and the upper substrate are bonded together, the protrusion surrounds the spacer.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD OF THE SAME}

The present invention relates to a liquid crystal display device and a manufacturing method thereof.

As information technology develops, the market for display devices, which are communication media between users and information, is growing. Accordingly, flat panel displays (FPDs) such as liquid crystal displays (LCDs), organic light emitting diode displays (OLEDs), and plasma display panels (PDPs) ) is increasingly used. Among them, a liquid crystal display capable of realizing high resolution and capable of being large as well as miniaturized is widely used.

A liquid crystal display device displays an image by adjusting light transmittance of a liquid crystal using an electric field. Liquid crystal displays are roughly classified into a vertical electric field method and a horizontal electric field method according to the direction of an electric field driving the liquid crystal.

The liquid crystal display includes a liquid crystal panel and a backlight unit. The liquid crystal panel includes a transistor substrate on which thin film transistors, storage capacitors and pixel electrodes are formed, and a color filter substrate on which color filters and black matrices are formed.

A liquid crystal layer and a spacer are formed between the transistor substrate and the color filter substrate. The spacer serves various purposes, such as maintaining a distance between the transistor substrate and the color filter substrate or preventing problems caused by pressing.

However, in the conventional liquid crystal display device, when a spacer interposed in a liquid crystal panel is moved by an external force, a lower layer thereof (eg, polyimide) is damaged. These problems eventually distort the alignment of the liquid crystal and cause light leakage to the portion, thereby degrading the reliability and display quality of the liquid crystal panel, so improvement is required.

The present invention to solve the problems of the background art described above is to prevent the scratchy light leakage (or CS Disclination phenomenon) problem caused by the movement of the spacer interposed in the liquid crystal panel, the problem of damage to the lower alignment layer, and the problem of misalignment of the liquid crystal.

As a means for solving the above problems, the present invention provides a liquid crystal display device including a lower structure, a planarization layer, a protrusion, and a spacer. The lower structure includes a gate line positioned on the lower substrate. A planarization layer is located on the underlying structure. The protrusion protrudes from the planarization layer and has a closed curve shape. A spacer is positioned on the upper substrate. When the lower substrate and the upper substrate are bonded together, the protrusion surrounds the spacer.

In another aspect, the present invention provides a liquid crystal display device including a spacer having a lower structure, a flattening layer, protrusions, and grooves. The lower structure includes a gate line positioned on the lower substrate. A planarization layer is located on the underlying structure. The protrusions protrude from the planarization layer. The spacer is located on the upper substrate and has a groove. When the lower substrate and the upper substrate are bonded, the protruding portion is inserted into the groove of the spacer.

The spacer may be located in a region corresponding to the gate line.

The protrusion may be selected from at least one of a square, rectangular, circular, or polygonal shape.

The groove of the spacer may correspond to the shape of the protrusion.

In another aspect, the present invention provides a method for manufacturing a liquid crystal display device. A method of manufacturing a liquid crystal display includes forming a lower structure including a gate line on a lower substrate, forming a planarization layer on the lower structure, forming a protrusion protruding from the planarization layer and having a closed curve shape, Forming a spacer on the substrate, and bonding the lower substrate and the upper substrate together. When the lower substrate and the upper substrate are bonded together, the protrusion surrounds the spacer.

In another aspect, the present invention provides a method for manufacturing a liquid crystal display device. A method of manufacturing a liquid crystal display includes forming a lower structure including a gate line on a lower substrate, forming a planarization layer on the lower structure, forming a protrusion protruding from the planarization layer, and forming a groove on the upper substrate. Forming a spacer having , and bonding the lower substrate and the upper substrate together. When the lower substrate and the upper substrate are bonded, the protruding portion is inserted into the groove of the spacer.

The forming of the protrusion may include forming a positive photoresist on the planarization layer, disposing and aligning a first mask having a light blocking layer on the lower substrate, irradiating light through the first mask, and performing exposure and etching.

The step of forming the spacer with grooves is to form a negative photoresist on the upper substrate, place and align a second mask having a light blocking layer on the upper substrate, pass light through the second mask, expose and etch can do.

The groove of the spacer may correspond to the shape of the protrusion.

The present invention has an effect of improving the reliability and display quality of the liquid crystal panel by preventing the scratchy light leakage (or CS Disclination phenomenon) caused by the movement of the spacer interposed in the liquid crystal panel. In addition, the present invention has an effect of preventing damage to a lower alignment layer or misalignment of liquid crystals even when a spacer interposed in a liquid crystal panel is moved by an external force. In addition, the present invention has an effect of improving the aperture ratio by reducing the area of the metal material that serves to prevent light leakage.

1 is a block diagram schematically illustrating a liquid crystal display device;
FIG. 2 is a circuit diagram schematically illustrating a sub-pixel shown in FIG. 1;
3 is a plan view illustrating sub-pixels of a liquid crystal panel implemented in an IPS mode;
4 is a plan view showing a spacer interposed in a conventional liquid crystal panel;
5 is a cross-sectional view of an area A1-A2 in FIG. 4;
6 is a plan view illustrating sub-pixels of a liquid crystal panel implemented in an IPS mode according to the first embodiment of the present invention;
7 is a cross-sectional view showing a method of forming a spacer according to a first embodiment of the present invention.
8 is a cross-sectional view of a region B1-B2 of FIG. 6;
9 is a plan view illustrating sub-pixels of a liquid crystal panel implemented in an IPS mode according to a second embodiment of the present invention;
10 and 11 are cross-sectional views showing a method of forming a spacer according to a second embodiment of the present invention.
12 is an exemplary plan view showing a spacer having a groove;
13 is a cross-sectional view of a region C1-C2 of FIG. 9;

Hereinafter, specific details for the implementation of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a liquid crystal display device, FIG. 2 is a circuit diagram schematically illustrating a subpixel shown in FIG. 1, and FIG. 3 is a plan view illustrating a subpixel of a liquid crystal panel implemented in an IPS mode. .

1 and 2, the liquid crystal display device includes an image supply unit 110, a timing controller 130, a gate driver 140, a data driver 150, a liquid crystal panel 160, a power supply unit 180, and A backlight unit 190 is included.

The image supply unit 110 processes the data signal and outputs it together with a vertical sync signal, a horizontal sync signal, a data enable signal and a clock signal. The image supply unit 110 transmits a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and a data signal through a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface to the timing controller 120. ) to supply

The timing controller 130 outputs a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150 . The timing controller 130 supplies the data signal DATA supplied from the image processing unit 110 to the data driver 150 together with the data timing control signal DDC.

The gate driver 140 outputs a gate signal while shifting the level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller 130 . The gate driver 140 supplies gate signals to the subpixels SP included in the liquid crystal panel 160 through the gate lines GL. The gate driver 140 is formed in the form of an integrated circuit (IC) or formed in the liquid crystal panel 160 in a gate-in-panel method.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 130, converts the data signal DATA into a gamma reference voltage, and outputs the converted gamma reference voltage. The data driver 150 may invert and output the polarity of the data voltage in one frame period. The data driver 150 supplies data voltages (or data signals) to the sub-pixels SP included in the liquid crystal panel 160 through the data lines DL. The data driver 150 is formed in the form of an integrated circuit (IC).

The power supply unit 180 generates and outputs a high potential voltage (VCC), a low potential voltage (GND), and a common voltage (VCOM). The high potential voltage VCC and the low potential voltage GND are supplied to one or more of the timing controller 130 , the gate driver 140 and the data driver 150 . The common voltage VCOM is supplied to the liquid crystal panel 160 . The common voltage VCOM is supplied to the sub-pixels SP through the common voltage line of the liquid crystal panel 160 .

The backlight unit 190 provides light to the liquid crystal panel 160 using a light source that emits light. The backlight unit 190 includes a light emitting diode (LED), an LED driver for driving the LED, an LED substrate on which the LED is mounted, a light guide plate that converts light emitted from the LED into a surface light source, a reflector that reflects light from the bottom of the light guide plate, Optical sheets for condensing and diffusing light emitted from the light guide plate and the like are included.

The liquid crystal panel 160 displays an image in response to a gate signal supplied from the gate driver 140 and a data voltage supplied from the data driver 150 . The liquid crystal panel 160 includes sub-pixels SP that control light provided through the backlight unit 170 .

One sub-pixel includes a switching transistor SW, a storage capacitor Cst, and a liquid crystal layer Clc. The gate electrode of the switching transistor SW is connected to the gate line GL1 and the source electrode is connected to the data line DL1. The storage capacitor Cst has one end connected to the drain electrode of the switching transistor SW and the other end connected to the common voltage line CL1. The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor SW and the common electrode 2 connected to the common voltage line CL1.

The liquid crystal display described above has TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB mode depending on the structure of the pixel electrode and common electrode of the liquid crystal panel. (Electrically Controlled Birefringence) mode. However, for convenience of description, an example implemented in the IPS mode is taken.

Also, in the liquid crystal display device described above, the liquid crystal panel may be implemented with red, green, and blue sub-pixels, or may be implemented with red, green, and blue sub-pixels as well as white sub-pixels to reduce current consumption. However, for convenience of description, an example implemented with red, green, and blue sub-pixels is taken as an example.

As shown in FIG. 3, the gate line GL1, the data line DL1, the pixel electrode PXL, the common electrode Vcom, and the common electrode are included in the Nth sub-pixel SPN of the liquid crystal panel implemented in the IPS mode. A common voltage line CL1 connected to Vcom and disposed parallel to the gate line GL is included. The gate line GL1, the data line DL1, the pixel electrode PXL, the common electrode Vcom, and the common electrode Vcom are formed on a lower substrate (hereinafter referred to as a transistor substrate).

The gate line GL1, the data line DL1, and the common voltage line CL1 are disposed in the non-open area, and the pixel electrode PXL and the common electrode Vcom are disposed in the open area. The gate line GL1 and the common voltage line CL1 are disposed in a horizontal direction (x), and the data line DL1 is disposed in a vertical direction (y). The gate line GL1 and the common voltage line CL1 are disposed side by side adjacent to each other. As the gate line GL1 and the common voltage line CL1 are disposed adjacent to each other, they may also serve as a light shield. The gate line GL1 and the common voltage line CL1 may be formed of the same metal material.

The pixel electrode PXL and the common electrode Vcom may be positioned on the same insulating layer. The pixel electrodes PXL and the common electrode Vcom are alternately disposed to have similar or equal intervals within the opening area OPN. The pixel electrode PXL and the common electrode Vcom are disposed in a bent (eg, < shape) shape with an inclination based on the center line of the opening area OPN.

The pixel electrode PXL and the common electrode Vcom may be a transparent oxide electrode or an opaque metal electrode. The distance between the pixel electrode PXL and the common electrode Vcom may be different depending on the material of the electrode. For example, when the pixel electrode PXL and the common electrode Vcom are selected as transparent oxide electrodes, the space between them is narrower than when the pixel electrodes PXL and the common electrode Vcom are selected as opaque metal electrodes. can

A spacer GCS is disposed in a specific subpixel such as the Nth subpixel SPN. The spacer (GCS) is formed on the upper substrate (hereinafter referred to as a color filter substrate) corresponding to the area where the black matrix is located. The area where the spacer GCS is disposed corresponds to the area where the switching transistor is located on the transistor substrate. Accordingly, the spacer GCS is positioned on the gate line GL1 adjacent to the common voltage line CL1.

The spacer GCS shown in FIG. 3 shows a portion in contact with the transistor substrate, and its shape and size are not limited thereto. For example, the spacer GCS is selected to have a circular shape or a rectangular shape, but is not limited thereto.

The spacer (GCS) maintains the distance between the transistor substrate and the color filter substrate (keeps the thickness of the liquid crystal layer (ie, also referred to as 'cell gap') uniform over the entire area of the substrate) or prevents problems caused by pressing. It serves a variety of purposes, including preventing For example, the spacers GCS may be uniformly arranged at regular intervals so as to be located four by one within a 25 (vertical) X 9 (horizontal) sub-pixel group formed on the liquid crystal panel, but is not limited thereto.

Meanwhile, in the liquid crystal display device having the spacer GCS, the distance (or cell gap) between the transistor substrate and the color filter substrate may be maintained uniformly. However, the spacer (GCS) moves out of its position due to the process of transporting the liquid crystal panel after bonding the transistor substrate and the color filter substrate or the force (i.e., pressure) when the user touches or presses the screen of the liquid crystal panel with his/her hand. The number of occurrences (changes compared to the design position) is also increasing.

In the conventionally proposed liquid crystal display device, when the spacer (GCS) interposed in the liquid crystal panel is moved by an external force, a scratch is generated in which the alignment layer is scratched. In this case, the conventionally proposed liquid crystal display device may cause problems such as light leakage (or CS discrimination phenomenon) and reliability and display quality of the liquid crystal panel due to the liquid crystal having a distorted alignment layer. The light leakage occurring at this time is a phenomenon that occurs when the liquid crystal alignment is distorted due to damage to the lower alignment layer by the spacer (GCS), and is also called a "red eye defect".

Hereinafter, the problems of the conventional structure will be considered and an embodiment of the present invention capable of solving them will be described.

4 is a plan view showing a spacer interposed in a conventional liquid crystal panel, and FIG. 5 is a cross-sectional view of an area A1-A2 in FIG. 4 .

As shown in FIGS. 4 and 5 , the spacer (GCS) interposed in the conventional liquid crystal panel moves in directions y1 and y2 by an external force. When the spacer (GCS) is moved by an external force, scratches (SCR) are generated in the alignment layer (PI) positioned on top of the transistor substrate.

Conventionally, in order to improve the light leakage problem caused by the scratch (SCR), the area is increased (light shield area) by increasing the size in the vertical direction (y) of at least one of the gate line (GL1) and the common voltage line (CL1). reason for the increase). However, in the conventionally proposed method, since the size of at least one of the gate line GL1 and the common voltage line CL1 needs to be increased to prevent light leakage, there is a problem in that the aperture ratio is reduced.

6 is an exemplary plane view showing a sub-pixel of a liquid crystal panel implemented in IPS mode according to the first embodiment of the present invention, and FIG. 7 is a cross-sectional view showing a method of forming a spacer according to the first embodiment of the present invention. , FIG. 8 is a cross-sectional view of the area B1-B2 of FIG. 6 .

As shown in FIG. 6, the gate line GL1, the data line DL1, the pixel electrode PXL, the common electrode Vcom, and the common electrode are included in the Nth sub-pixel SPN of the liquid crystal panel implemented in the IPS mode. A common voltage line CL1 connected to Vcom and disposed parallel to the gate line GL is included. The gate line GL1, data line DL1, pixel electrode PXL, common electrode Vcom, and common electrode Vcom are formed on a transistor substrate.

The gate line GL1, the data line DL1, and the common voltage line CL1 are disposed in the non-opening area, and the pixel electrode PXL and the common electrode Vcom are disposed in the opening area OPN. The gate line GL1 and the common voltage line CL1 are disposed in a horizontal direction (x), and the data line DL1 is disposed in a vertical direction (y). The gate line GL1 and the common voltage line CL1 are disposed side by side adjacent to each other. As the gate line GL1 and the common voltage line CL1 are disposed adjacent to each other, they may also serve as a light shield.

The pixel electrode PXL and the common electrode Vcom may be positioned on the same insulating layer. The pixel electrodes PXL and the common electrode Vcom are alternately disposed to have similar or equal intervals within the opening area OPN. The pixel electrode PXL and the common electrode Vcom are disposed in a bent (eg, < shape) shape with an inclination based on the center line of the opening area OPN.

The pixel electrode PXL and the common electrode Vcom may be a transparent oxide electrode or an opaque metal electrode. The distance between the pixel electrode PXL and the common electrode Vcom may be different depending on the material of the electrode. For example, when the pixel electrode PXL and the common electrode Vcom are selected as transparent oxide electrodes, the space between them is narrower than when the pixel electrodes PXL and the common electrode Vcom are selected as opaque metal electrodes. can

A spacer GCS is disposed in a specific subpixel such as the Nth subpixel SPN. The spacer (GCS) is formed on the color filter substrate to correspond to the region where the black matrix is located. The area where the spacer GCS is disposed corresponds to the area where the switching transistor is located on the transistor substrate. Accordingly, the spacer GCS is positioned on the gate line GL1 adjacent to the common voltage line CL1. The spacer GCS shown in FIG. 6 shows a portion in contact with the transistor substrate, and its shape and size are not limited thereto.

A protrusion BR surrounding the spacer GCS is disposed in the Nth sub-pixel SPN. The protruding portion BR is formed on the transistor substrate. The protruding portion BR is formed in a closed curve shape. For example, the protrusion BR is selected as at least one of a quadrangle, a rectangle, a circle, and a polygon.

As shown in FIG. 7 , the protrusion BR may be formed on the transistor substrate 160a using a positive photoresist PR1. The process of forming the protrusion BR is to form a positive photoresist PR1 on the planarization layer 166, and then goes through an exposure (a in FIG. 7) and an etching (b in FIG. 7) process (photolithography process). In more detail, it is as follows.

A gate line GL1 and a common voltage line CL1 are formed on the transistor substrate 160a. An insulating layer 163 is formed on the gate line GL1 and the common voltage line CL1. Color filter layers (CFR, CFB) are formed on the insulating layer 163 . A planarization layer 166 is formed on the insulating layer 163 . A positive photoresist PR1 is formed on the planarization layer 166 . A first mask MSK1 having a light blocking layer BL is disposed and aligned on the transistor substrate 160a on which the positive photoresist PR1 is formed. Light is irradiated through the first mask MSK1, followed by exposure and etching. Thereafter, exposure and etching processes are performed based on the positive photoresist PR1, and the positive photoresist PR1 is removed.

When the above steps are performed, protrusions BR are formed in the planarization layer 166 located on the upper layer of the transistor substrate 160a. The protruding portion BR may use a horn stepping technique using a mask correction technique (Optical Proximity Correction; OPC).

Meanwhile, a switching transistor, a storage capacitor, and the like are formed in a lower structure positioned below the planarization layer 166 of the transistor substrate 160a. A black matrix or the like is formed on the color filter substrate 160b. A liquid crystal layer is formed between the bonded transistor substrate 160a and the color filter substrate 160b. However, since these structures are different depending on the structure and processing method of the liquid crystal panel, illustration and description thereof are omitted.

As shown in FIG. 8 , protrusions BR are formed on the planarization layer 166 of the transistor substrate 160a. A lower alignment layer PI1 is formed on the protrusion BR. A spacer GCS is formed on the color filter substrate 160b. An upper alignment layer PI2 is formed on the color filter substrate 160b.

When the bonding process of the transistor substrate 160a and the color filter substrate 160b is performed, the spacer GCS is positioned within the region of the protruding portion BR. The protruding portion BR serves as a movement barrier preventing the spacer GCS from invading the opening area OPN even when it moves out of its position due to an external force.

Therefore, in the first embodiment of the present invention, the problem of light leakage (or CS Disclination phenomenon) can be prevented because scratches on the lower alignment layer PI1 occur only within the area of the projection BR, and in addition, the reliability and display of the liquid crystal panel Problems such as deterioration in quality can be improved. In addition, the first embodiment of the present invention can reduce the area of the metal material (gate line, common voltage line) that serves to prevent light leakage, thereby improving the aperture ratio.

9 is an exemplary plan view showing a sub-pixel of a liquid crystal panel implemented in IPS mode according to a second embodiment of the present invention, and FIGS. 10 and 11 show a method of forming a spacer according to a second embodiment of the present invention. 12 is a plan view illustrating a spacer having a groove, and FIG. 13 is a cross-sectional view of the region C1-C2 of FIG. 9 .

As shown in FIG. 9 , the gate line GL1, the data line DL1, the pixel electrode PXL, the common electrode Vcom, and the common electrode are included in the Nth sub-pixel SPN of the liquid crystal panel implemented in the IPS mode. A common voltage line CL1 connected to Vcom and disposed parallel to the gate line GL is included. The gate line GL1, data line DL1, pixel electrode PXL, common electrode Vcom, and common electrode Vcom are formed on a transistor substrate.

The gate line GL1, the data line DL1, and the common voltage line CL1 are disposed in the non-opening area, and the pixel electrode PXL and the common electrode Vcom are disposed in the opening area OPN. The gate line GL1 and the common voltage line CL1 are disposed in a horizontal direction (x), and the data line DL1 is disposed in a vertical direction (y). The gate line GL1 and the common voltage line CL1 are disposed side by side adjacent to each other. As the gate line GL1 and the common voltage line CL1 are disposed adjacent to each other, they may also serve as a light shield.

The pixel electrode PXL and the common electrode Vcom may be positioned on the same insulating layer. The pixel electrodes PXL and the common electrode Vcom are alternately disposed to have similar or equal intervals within the opening area OPN. The pixel electrode PXL and the common electrode Vcom are disposed in a bent (eg, < shape) shape with an inclination based on the center line of the opening area OPN.

The pixel electrode PXL and the common electrode Vcom may be a transparent oxide electrode or an opaque metal electrode. The distance between the pixel electrode PXL and the common electrode Vcom may be different depending on the material of the electrode. For example, when the pixel electrode PXL and the common electrode Vcom are selected as transparent oxide electrodes, the space between them is narrower than when the pixel electrodes PXL and the common electrode Vcom are selected as opaque metal electrodes. can

A spacer GCS is disposed in a specific subpixel such as the Nth subpixel SPN. The spacer (GCS) is formed on the color filter substrate to correspond to the region where the black matrix is located. A groove is formed in the spacer GCS. The area where the spacer GCS is disposed corresponds to the area where the switching transistor is located on the transistor substrate. Accordingly, the spacer GCS is positioned on the gate line GL1 adjacent to the common voltage line CL1. The spacer GCS shown in FIG. 6 shows a portion in contact with the transistor substrate, and its shape and size are not limited thereto.

A protrusion fitted into the groove of the spacer GCS is disposed in the Nth sub-pixel SPN. The protrusion is formed on the transistor substrate. For example, the protrusion is selected to be one of square, rectangular, circular or polygonal.

As shown in FIGS. 10 and 11 , the protrusion BR may be formed on the transistor substrate 160a using a positive photoresist PR1. The process of forming the protrusion BR is to form the positive photoresist PR1 on the planarization layer 166 and to go through exposure (a in FIG. 10) and etching (b in FIG. 10). This will be described in detail as follows. Same as

A gate line GL1 and a common voltage line CL1 are formed on the transistor substrate 160a. An insulating layer 163 is formed on the gate line GL1 and the common voltage line CL1. Color filter layers (CFR, CFB) are formed on the insulating layer 163 . A planarization layer 166 is formed on the insulating layer 163 . A positive photoresist PR1 is formed on the planarization layer 166 . A first mask MSK1 having a light blocking layer BL is disposed and aligned on the transistor substrate 160a on which the positive photoresist PR1 is formed. Light is irradiated through the first mask MSK1, followed by exposure and etching. Thereafter, exposure and etching processes are performed based on the positive photoresist PR1, and the positive photoresist PR1 is removed.

When the above steps are performed, protrusions BR are formed in the planarization layer 166 located on the upper layer of the transistor substrate 160a. The protruding portion BR may use a horn stepping technique using a mask correction technique (Optical Proximity Correction; OPC).

Meanwhile, a switching transistor, a storage capacitor, and the like are formed in a lower structure positioned below the planarization layer 166 of the transistor substrate 160a. A black matrix or the like is formed on the color filter substrate 160b. A liquid crystal layer is formed between the bonded transistor substrate 160a and the color filter substrate 160b. However, since these structures are different depending on the structure and processing method of the liquid crystal panel, illustration and description thereof are omitted.

The spacer GCS having the groove HM may be formed on the color filter substrate 160b using negative photoresist PR2. In the process of forming the spacer GCS having the groove HM, the negative photoresist PR2 is formed on the color filter substrate 160b, and exposure (a in FIG. 11) and etching (b in FIG. 11) are performed. This is explained in more detail as follows.

A negative photoresist PR2 is formed on the color filter substrate 160b. A second mask MSK2 having first and second light blocking layers BL1 and BL2 is disposed and aligned on the color filter substrate 160b on which the negative photoresist PR2 is formed. Light is irradiated through the second mask MSK2, followed by exposure and etching. The first light blocking layer BL1 has a higher ability to block light than the second light blocking layer BL2.

When the above steps are performed, embossed spacers (GCS) and negative grooves (HM) are formed in the upper layer of the color filter substrate (160b) to form spacers (GCS) having grooves (HM). do. The intaglio groove HM formed in the spacer GCS may have a rectangular shape (a) or a circular shape (b) as shown in FIG.

As shown in FIG. 13 , protrusions BR are formed on the planarization layer 166 of the transistor substrate 160a. A lower alignment layer PI1 is formed on the protrusion BR. A spacer GCS having a groove HM is formed on the color filter substrate 160b. An upper alignment layer PI2 is formed on the color filter substrate 160b.

When the bonding process of the transistor substrate 160a and the color filter substrate 160b is performed, the protruding portion BR is located in the groove HM of the spacer GCS. That is, the spacer GCS and the protruding portion BR serve as a fitting structure in which they are coupled so as not to deviate from their positions by an external force.

Therefore, the second embodiment of the present invention can prevent the problem of light leakage (or CS Disclination phenomenon) because the lower alignment layer PI1 is not scratched, and in addition, the problem of deterioration in reliability and display quality of the liquid crystal panel can be solved. can be improved In addition, the second embodiment of the present invention can reduce the area of the metal material (gate line, common voltage line) that serves to prevent light leakage, thereby improving the aperture ratio.

As described above, the present invention has an effect of improving the reliability and display quality of the liquid crystal panel by preventing the scratchy light leakage (or CS Disclination phenomenon) caused by the movement of the spacer interposed in the liquid crystal panel. In addition, the present invention has an effect of preventing damage to a lower alignment layer or misalignment of liquid crystals even when a spacer interposed in a liquid crystal panel is moved by an external force. In addition, the present invention has an effect of improving the aperture ratio by reducing the area of the metal material that serves to prevent light leakage.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: image supply unit 130: timing control unit
140: gate driver 150: data driver
160: liquid crystal panel 180: power supply unit
190: backlight unit 160a: transistor substrate
GCS: Spacer BR: Protrusion
160b: color filter substrate HM: home

Claims (10)

a lower structure including a gate line positioned on a lower substrate, a common voltage line disposed adjacent to and adjacent to the gate line, and a color filter layer disposed on the gate line and the common voltage line;
a planarization layer positioned on the lower structure;
a protrusion protruding from the planarization layer and having a closed curve shape;
a lower alignment layer formed on the protrusion;
a spacer located on the upper substrate; and
Including an upper alignment layer formed on the upper substrate,
The spacer is located in an area overlapping the color filter layer,
When the lower substrate and the upper substrate are bonded, the protrusion surrounds the spacer,
the gate line and the common voltage line are disposed in a non-opening area;
the spacer is located on a gate line adjacent to the common voltage line disposed in the non-opening region;
The protruding portion is located on the common voltage line and the gate line disposed side by side in the non-opening area. a lower structure including a gate line positioned on a lower substrate, a common voltage line disposed adjacent to and adjacent to the gate line, and a color filter layer disposed on the gate line and the common voltage line;
a planarization layer positioned on the lower structure;
a protrusion protruding from the planarization layer;
a lower alignment layer formed on the protrusion;
a spacer located on the upper substrate and having a groove; and
Including an upper alignment layer formed on the upper substrate,
The spacer is located in an area overlapping the color filter layer,
When the lower substrate and the upper substrate are bonded, the protruding portion is inserted into the groove of the spacer,
the gate line and the common voltage line are disposed in a non-opening area;
the spacer is located on a gate line adjacent to the common voltage line disposed in the non-opening region;
The protruding portion is located on the common voltage line and the gate line disposed side by side in the non-opening area. delete According to claim 1 or 2,
the protrusion
A liquid crystal display device selected from at least one of square, rectangular, circular, or polygonal. According to claim 2,
The groove of the spacer is
A liquid crystal display device corresponding to the shape of the protrusion. forming a lower structure on a lower substrate including a gate line, a common voltage line disposed adjacent to and adjacent to the gate line, and a color filter layer disposed on the gate line and the common voltage line;
forming a planarization layer on the lower structure;
forming a protrusion having a closed curve shape by protruding from the planarization layer;
forming a lower alignment layer on the protrusion;
Forming a spacer on an upper substrate;
forming an upper alignment layer on the upper substrate; and
Including the step of bonding the lower substrate and the upper substrate,
The spacer is located in an area overlapping the color filter layer,
When the lower substrate and the upper substrate are bonded, the protrusion surrounds the spacer,
the gate line and the common voltage line are disposed in a non-opening area;
the spacer is located on a gate line adjacent to the common voltage line disposed in the non-opening region;
The protruding part is located on the common voltage line and the gate line disposed side by side in the non-opening area. forming a lower structure on a lower substrate including a gate line, a common voltage line disposed adjacent to and adjacent to the gate line, and a color filter layer disposed on the gate line and the common voltage line;
forming a planarization layer on the lower structure;
forming protrusions protruding from the planarization layer;
forming a lower alignment layer on the protrusion;
Forming a spacer having a groove on an upper substrate;
forming an upper alignment layer on the upper substrate; and
Including the step of bonding the lower substrate and the upper substrate,
The spacer is located in an area overlapping the color filter layer,
When the lower substrate and the upper substrate are bonded, the protruding portion is inserted into the groove of the spacer,
the gate line and the common voltage line are disposed in a non-opening area;
the spacer is located on a gate line adjacent to the common voltage line disposed in the non-opening region;
The protruding part is located on the common voltage line and the gate line disposed side by side in the non-opening area. According to claim 6 or 7,
The step of forming the protrusion is
A method of manufacturing a liquid crystal display device comprising forming a positive photoresist on the planarization layer, disposing and aligning a first mask having a light blocking layer on the lower substrate, irradiating light through the first mask, and exposing and etching the light. . According to claim 7,
The step of forming the spacer having the groove is
Manufacturing of a liquid crystal display device comprising forming a negative photoresist on the upper substrate, arranging and aligning a second mask having a light blocking layer on the upper substrate, and exposing and etching light through the second mask. method. According to claim 7,
The groove of the spacer is
A method of manufacturing a liquid crystal display device corresponding to the shape of the protrusion.

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