KR102505920B1 - Memory controller, memory system having the same and operating method thereof - Google Patents

Abstract

The present invention includes a state check command determining unit that checks a state check command supported by a memory device among a plurality of state check commands; and a memory controller including a state check performer configured to perform a state check operation on the memory device using the checked state check command, a memory system including the same, and an operating method thereof.

Description

Memory controller, memory system including the same and operating method thereof

The present invention relates to a memory controller, a memory system including the same, and an operating method thereof, and more particularly, to a memory controller capable of performing a status check according to a type of a memory device, a memory system including the same, and an operating method thereof. it's about

A memory system may include a memory device and a memory controller.

The memory device may store data or output stored data under the control of the memory controller. For example, the memory device may include a volatile memory device in which stored data is lost when power supply is cut off, or a non-volatile memory device in which stored data is maintained even when power supply is cut off.

The memory controller may control data communication between a host and a memory device.

The host communicates with the memory system using interface protocols such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or serial attached SCSI (SAS) can be performed. Interface protocols between the host and the memory system are not limited to the above examples. For example, the host may communicate with the memory system using various interfaces such as USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics). .

Embodiments of the present disclosure provide a memory controller capable of performing a state check according to a type of memory device, a memory system including the same, and an operating method thereof.

A memory controller according to an embodiment of the present invention includes a state check command determiner configured to check a state check command supported by a memory device among a plurality of state check commands; and a state check performer performing a state check operation on the memory device using the checked state check command.

A memory system according to an embodiment of the present invention includes a memory device that outputs state information in response to a state check command; and a memory controller configured to check a status check command supported by the memory device among a plurality of status check commands and perform a status check on the memory device using the checked status check command.

A method of operating a memory controller according to an embodiment of the present disclosure includes receiving type information of a memory device from a host; Checking a status check command supported by the memory device based on a first table in which the received type information of the memory device and type information of a memory device supporting the corresponding status check command are mapped with respect to each of the plurality of status check commands step; and performing a state check on the memory device using the checked state check command.

According to the present technology, since a state check can be performed according to the type of a memory device, reliability of a memory system can be improved.

1 is an exemplary diagram for describing a memory system according to an exemplary embodiment of the present invention.
FIG. 2 is an exemplary diagram for explaining the memory controller shown in FIG. 1 .
FIG. 3 is an exemplary diagram for explaining the memory device shown in FIGS. 1 and 2 .
4 is an exemplary view for explaining a memory block having a two-dimensional structure.
5 is an exemplary diagram for explaining an example of a memory block having a 3D structure.
6 is an exemplary view for explaining another example of a memory block having a 3D structure.
7 is a flowchart illustrating a method for performing a status check according to an embodiment of the present invention.
8 is an exemplary diagram for explaining a first table according to an embodiment of the present invention.
9 is an exemplary diagram for explaining a second table according to an embodiment of the present invention.
10 is an exemplary view for explaining a third table according to an embodiment of the present invention.
FIG. 11 is an exemplary diagram for explaining in detail the state information shown in FIG. 9 .
FIG. 12 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .
FIG. 13 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .
FIG. 14 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .
FIG. 15 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .

Advantages and features of the present invention, and methods for achieving them, will be explained in detail through the following embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the present embodiments are provided to explain in detail enough to easily implement the technical idea of the present invention to those skilled in the art to which the present invention belongs.

Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element interposed therebetween. . Throughout the specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is an exemplary diagram for describing a memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a memory system 2000 includes a memory device 2200 in which data is stored and a memory controller controlling the memory device 2200 under the control of a host 1000 ( memory controller; 2100).

The host 1000 uses an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or serial attached SCSI (SAS) to access memory. It can communicate with system 2000. Interface protocols used between the host 1000 and the memory system 2000 are not limited to the above examples, and USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface) or IDE (Integrated Drive Electronics) or the like may be used.

Various types of memory devices 2200 may be mounted in the memory system 2000 . For example, an A-type memory device 2200 or a B-type memory device 2200 may be mounted in the memory system 2000 . Here, the status check ("READ STATUS") command supported by the A-type memory device 2200 may be different from the status check command supported by the B-type memory device 2200 . That is, different types of memory devices 2200 may support different state check commands.

When a specific type of memory device 2200 is mounted in the memory system 2000 , the host 1000 may transmit type information of the corresponding memory device 2200 to the memory controller 2100 . The type information of the memory device 2200 may be, for example, a product name, serial number, or package information of the memory device 2200 . However, the type information of the memory device 2200 is not limited thereto, and various pieces of information capable of identifying the memory device 2200 may be used as the type information.

The memory controller 2100 controls overall operations of the memory system 2000 and may control data exchange between the host 1000 and the memory device 2200 . For example, the memory controller 2100 converts received information so that commands, addresses, and data can be communicated between the host 1000 and the memory device 2200, and converts the converted information. can be saved and printed. For example, during a program operation, the memory controller 2100 may transmit commands, addresses, and data to the memory device 2200 .

The memory controller 2100 may perform a state check on the memory device 2200 . For example, the memory controller 2100 may generate and transmit a state check command to the memory device 2200 and receive state information from the memory device 2200 in response to the state check command. For example, the memory controller 2100 may check the state of the memory device 2200 according to state information received from the memory device 2200 . That is, the memory controller 2100 may check information such as whether the memory device 2200 is currently operating or in an idle state. State information output from the memory device 2200 may include various types of information. For example, the state information includes information about whether a state check command output from the memory controller 2100 is normally received, information about whether the memory device 2200 is currently in an idle state, and whether the memory device 2200 is in an idle state. It may include information about whether it is currently busy. Also, when the state check operation is performed after the program operation of the memory device 2200, the memory controller 2100 checks the state information received from the memory device 2200 so that the program operation of the memory device 2200 is normally performed. You can check if it has been done. For example, when a state check operation is performed after a read operation of the memory device 2200, the memory controller 2100 checks state information received from the memory device 2200 and performs a read operation of the memory device 2200. You can check whether this was performed normally.

The memory controller 2100 may check a state check command supported by the memory device 2200 and perform a state check on the memory device 2200 using the checked state check command. For example, the memory controller 2100 receives type information of the memory device 2200 from the host 1000, and based on the received type information of the memory device 2200, the memory device 2200 supports a state. You can check the check command. The confirmation of the status check command supported by the memory device 2200 is based on a table (hereinafter, a first table) in which type information of the memory device 2200 supporting the corresponding status check command is stored for each of a plurality of status check commands. can be made with For example, the memory controller 2100 may check a state check command corresponding to type information of the memory device 2200 received from the host 1000 by referring to the first table.

The memory controller 2100 may perform a state check on the memory device 2200 using the checked state check command. For example, the memory controller 2100 may generate a confirmed state check command and transmit the generated state check command to the memory device 2200 . The memory controller 2100 may receive state information from the memory device 2200 in response to the state check command. The memory controller 2100 may check the status information received from the memory device 2200 and check the status check result. Confirmation of the status check result may be performed based on a table (hereinafter, a second table) in which a definition of status information corresponding to a corresponding status check command is recorded for each of a plurality of status check commands. For example, the memory controller 2100 may check the status check result by referring to the second table and confirming meanings of the bits of the status information received from the memory device 2200 .

When performing the status check, the memory controller 2100 may determine a bit to be checked among status information received from the memory device 2200 and check a status check result for the memory device 2200 according to the determined bit. there is. Bits to be checked may be determined based on a table (hereinafter referred to as a third table) in which information on reference bits to be checked among state information corresponding to each of a plurality of state check commands is stored. For example, the memory controller 2100 may check the state check result of the memory device 2200 according to bits corresponding to reference bits among the state information received from the memory device 2200 by referring to the third table. . Confirmation of the status check result may be performed based on the second table. For example, the memory controller 2100 may check a state check result of the memory device 2200 by checking a bit corresponding to a reference bit among state information received from the memory device 2200 by referring to the second table. .

The memory controller 2100 may determine state information to be checked by further considering the type of operation to be checked. For example, reference bits corresponding to each operation may be stored in the third table. That is, a plurality of status check commands may be stored in the third table, and a reference bit to be checked among status information for each status check command may be stored. In this case, the memory controller 2100 should check a bit corresponding to a reference bit mapped to an operation targeted for status check among status information received from the memory device 2200 by referring to the third table. It can be determined by status information.

Meanwhile, the number of status check commands supported by the memory device 2200 may be plural. In this case, the memory controller 2100 may perform a state check on the memory device 2200 by selecting one state check command from among a plurality of state check commands. According to an embodiment, the memory controller 2100 performs a state check using any one state check command among a plurality of state check commands supported by the memory device 2200 and checks another state according to the result. A status check using a command can be further performed.

The memory device 2200 may perform an operation under the control of the memory controller 2100 . For example, the memory device 2200 may perform a program operation, a read operation, an erase operation, a suspend operation, and a copyback operation.

The memory device 2200 may store status information in a status register while performing an operation under the control of the memory controller 2100 . When a state check command is received from the memory controller 2100 , the memory device 2200 may transmit state information stored in a state register to the memory controller 2100 .

The memory device 2200 may include a volatile memory device in which stored data is lost when power supply is cut off, or a non-volatile memory device in which stored data is maintained even when power supply is cut off. In the embodiments described below, a flash memory included in a non-volatile memory device will be described as an example.

FIG. 2 is an exemplary diagram for explaining the memory controller shown in FIG. 1 .

Referring to FIG. 2 , the memory controller 2100 includes a host interface 2110, an Error Correcting Code unit (ECC) 2120, a memory interface 2130, and a buffer memory 2140. , a central processing unit (CPU) 2150 and a static random-access memory (SRAM) 2160. The host interface 2110, the ECC unit 2120, the memory interface 2130, the buffer memory 2140, and the SRAM 2160 may be controlled by the CPU 2150.

The host interface 2110 may exchange data with the host 1000 using a communication protocol.

The ECC unit 2120 may detect an error during a program operation or a read operation and may correct the detected error.

The memory interface 2130 may communicate with the memory device 2200 using a communication protocol.

The buffer memory 2140 may temporarily store data while the memory controller 2100 controls the memory device 2200 . For example, data received from the host may be temporarily stored in the buffer memory 2140 until the program operation is completed. Also, during a read operation, data read from the memory device 2200 may be temporarily stored in the buffer memory 2140 .

The CPU 2150 may perform various operations or generate commands and addresses to control the memory device 2200 . For example, the CPU 2150 may generate various commands necessary for program operation, read operation, erase operation, suspend operation, and copyback operation.

The CPU 2150 may perform a state check on the memory device 2200 using a state check command corresponding to the type of the memory device. Type information of the memory device 2200 may be received from the host 1000 .

The CPU 2150 may include a state check command determination unit 2151 and a state check execution unit 2155.

The state check command determiner 2151 may check a state check command supported by the memory device 2200 among a plurality of state check commands. For example, the state check command determiner 2151 may check the state check command corresponding to the type information of the memory device 2200 received from the host 1000 by referring to the first table 2152 . The status check command determiner 2151 may provide information on the confirmed status check command to the status check performer 2155 . Information on the status check command may mean information capable of identifying the corresponding status check command.

The state check performer 2155 receives information about the state check command supported by the memory device 2200 from the state check command determiner 2151, and uses the state check command to determine information about the memory device 2200. A health check can be performed. For example, the status check performer 2155 may generate the status check command confirmed by the status check command determiner 2151 and transmit the generated status check command to the memory device 2200 .

The state check performer 2155 may check the state information received from the memory device 2200 in response to the state check command to check the state check result. Confirmation of the state check result may be performed based on at least one of the second table 2156 and the third table 2158 . For example, the state check performer 2155 may refer to the second table 2156 to check what each bit of the state information received from the memory device 2200 represents. For example, the status check performer 2155 may refer to the third table 2158 and check a bit corresponding to a reference bit among the status information received from the memory device 2200 to check the status check result. .

When there are a plurality of status check commands supported by the memory device 2200, the status check performer 2155 selects one of the plurality of status check commands to check the status of the memory device 2200. can be performed. According to an embodiment, the state check performer 2155 performs a state check using any one state check command among a plurality of state check commands supported by the memory device 2200, and performs a state check according to the result. A state check using a state check command may be further performed.

The SRAM 2160 may be used as a storage unit for storing various pieces of information necessary for the operation of the memory controller 2100 .

FIG. 3 is an exemplary diagram for explaining the memory device shown in FIGS. 1 and 2 .

The memory device 2200 may include a control logic 2210 , peripheral circuits 2220 , and a memory cell array 2240 . The peripheral circuits 2220 include a voltage generation circuit 2222, a row decoder 2224, an input/output circuit 2226, a column decoder 2228, and a page buffer. A page buffer group 2232 and a current sensing circuit 2234 may be included.

The control logic 2210 may control the peripheral circuits 2220 under the control of the memory controller 2100 shown in FIG. 2 . The control logic 2210 may control the peripheral circuits 2220 in response to the command CMD and address ADD received from the memory controller 2100 through the input/output circuit 2226 . For example, the control logic 2210 controls the operation signal OP_CMD, the row address RADD, the page buffer control signals PBSIGNALS, and the allow bit VRY_BIT<# in response to the command CMD and the address ADD. >) can be printed. The control logic 2210 may determine whether the verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL received from the current sensing circuit 2234 .

The command CMD received from the memory controller 2100 may include an operation command and a state check command. The operation command may include a program operation command, an erase operation command, a read operation command, a suspend operation command, and a copyback operation command.

The control logic 2210 may record the state of the memory device 2200 in the state register 2212 while performing an operation according to a command received from the memory controller 2100 . For example, when the command received from the memory controller 2100 is a program operation command, information on whether the corresponding program operation command has been successfully executed or failed may be recorded in the status register 2212 .

The control logic 2210 may transmit the status check bits stored in the status register 2212 to the memory controller 2100 when a status check command is received from the memory controller 2100 .

The peripheral circuits 2220, under the control of the control logic 2210, perform a program operation for storing data in the memory cell array 2240 and a lead for outputting data stored in the memory cell array 2240. A read operation and an erase operation for erasing data stored in the memory cell array 2240 may be performed. Also, the peripheral circuits 2220 may perform a suspend operation to stop an operation currently being performed or a copy-back operation to copy data to another memory block.

The voltage generation circuit 2222 may generate various operating voltages Vop used for program operation, read operation, and erase operation in response to the operation signal OP_CMD received from the control logic 2210 . For example, the voltage generator circuit 2222 may generate a program voltage, a verify voltage, a pass voltage, a compensated program voltage, a read voltage, an erase voltage, and a turn-on voltage.

The row decoder 2224 generates local lines (LL) connected to a selected memory block among memory blocks included in the memory cell array 2240 in response to the row address RADD received from the control logic 2210. The operating voltages Vop may be transferred to . The local lines LL may include local word lines, local drain select lines, and local source select lines. In addition to this, the local lines LL may include various lines connected to the memory block, such as a source line.

The input/output circuit 2226 may transfer the command CMD and address ADD received from the memory controller to the control logic 2210 through the input/output lines DQ, or exchange data with the column decoder 2228. there is.

The column decoder 2228 may transfer data between the input/output circuit 2226 and the page buffer group 2232 in response to the column address CADD received from the control logic 2210 . For example, the column decoder 2228 exchanges data with the page buffers PB1 to PBI through data lines DL, or exchanges data with the input/output circuit 2226 through column lines CL. can receive

The page buffer group 2232 may be connected to bit lines BL1 to BLI commonly connected to memory blocks included in the memory cell array 2240 . The page buffer group 2232 may include a plurality of page buffers PB1 to PBI connected to the bit lines BL1 to BLI. For example, one page buffer may be connected to each bit line. The page buffers PB1 to PBI may operate in response to page buffer control signals PBSIGNALS received from the control logic 2210 . For example, the page buffers PB1 to PBI may temporarily store program data received from the memory controller during a program operation and adjust voltages applied to the bit lines BL1 to BLI according to the program data. . In addition, the page buffers PB1 to PBI may temporarily store data received through the bit lines BL1 to BLI during a read operation, or may sense the voltage or current of the bit lines BL1 to BLI. there is. The current sensing circuit 2234 generates a reference current in response to the allow bit (VRY_BTI<#>) received from the control logic 2210 during a read operation or a verify operation, and generates a reference voltage generated by the reference current and a page buffer. A pass signal PASS or a fail signal FAIL may be output by comparing the sensing voltage VPB received from the group 2232 .

The memory cell array 2240 may include a plurality of memory blocks MB1 to MBk in which data is stored. User data and various information necessary for the operation of the memory device 2200 may be stored in the memory blocks MB1 to MBk. The memory blocks MB1 to MBk may be implemented in a 2D structure or a 3D structure, and may be configured identically to each other.

4 is an exemplary view for explaining a memory block having a two-dimensional structure.

The memory cell array may include a plurality of memory blocks, and FIG. 4 illustrates one memory block MBk among the plurality of memory blocks for convenience of description.

The memory block MBk may include a plurality of cell strings (ST) connected between bit lines BL1 to BLI and source lines (SL). Cell strings (ST) may be connected to bit lines BL1 to BLI, respectively, and may be commonly connected to source line SL. Since the cell strings ST have structures similar to each other, the cell string ST connected to the first bit line BL1 will be described as an example.

The cell string ST includes a source select transistor (SST) connected in series between the source line SL and the first bit line BL1, first through n-th memory cells F1- Fn (n is a positive integer) and a drain select transistor (DST). The number of source select transistors SST and drain select transistors DST is not limited to the number shown in FIG. 4 .

The source select transistor SST may be connected between the source line SL and the first memory cell F1. The first to nth memory cells F1 to Fn may be connected in series between the source select transistor SST and the drain select transistor DST. The drain select transistor DST may be connected between the nth memory cell Fn and the first bit line BL1. Although not shown in the drawing, dummy cells may be further connected between the memory cells F1 to Fn or between the source select transistor SST and the drain select transistor DST.

Gates of the source select transistors SST included in the cell strings ST may be connected to a source select line (SSL). Gates of the first to nth memory cells F1 to Fn may be connected to first to nth word lines WL1 to WLn. Gates of the drain select transistors DST may be connected to drain select lines (DSL). Here, a group of memory cells connected to each of the word lines WL1 to WLn may be referred to as a physical page (PPG). For example, a group of first memory cells F1 connected to a first word line WL1 among memory cells F1 to Fn included in different cell strings ST has one physical page PPG. It can be. When a multi-level cell (MLC) method is used, a plurality of logical pages may be included in one physical page (PPG).

5 is an exemplary diagram for explaining an example of a memory block having a 3D structure.

The memory cell array may include a plurality of memory blocks, and FIG. 5 illustrates one memory block MBk among the plurality of memory blocks for convenience of explanation.

Referring to FIG. 5 , the three-dimensional memory block MBk may be formed in an I shape on a substrate in a direction perpendicular to the substrate (Z direction). The memory block MBk may include a plurality of cell strings ST arranged between bit lines BL and source lines SL. Depending on the embodiment, a well may be formed instead of the source line SL. This structure may be referred to as Bit Cost Scalable (BiCS). For example, when the source line SL is formed parallel to the substrate on top of the substrate, the cell strings ST having the BiCS structure are formed on the top of the source line SL in a direction (Z direction) perpendicular to the substrate. It can be.

Specifically, the cell strings ST may be arranged in a first direction (X direction) and a second direction (Y direction). The cell strings ST may include stacked source select lines SSL, word lines WL, and drain select lines DSL spaced apart from each other. The number of source select lines (SSL), word lines (WL), and drain select lines (DSL) is not limited to the number shown in the drawing and may vary according to exemplary embodiments. The cell strings ST may include vertical channel films CH and bit lines BL. The vertical channel layers CH may vertically pass through source select lines SSL, word lines WL, and drain select lines DSL. The bit lines BL contact upper portions of the vertical channel layers CH protruding above the drain select lines DSL and may extend in a second direction (Y direction). Memory cells may be formed between the word lines WL and the vertical channel films CH. A contact plug (CT) may be further formed between the bit lines BL and the vertical channel films CH.

6 is an exemplary view for explaining another example of a memory block having a 3D structure.

The memory cell array may include a plurality of memory blocks, and FIG. 6 illustrates one memory block MBk among the plurality of memory blocks for convenience of description.

Referring to FIG. 6 , the three-dimensional memory block MBk may be formed in a U shape on a substrate in a direction (Z direction) perpendicular to the substrate. The memory block MBk may include paired source strings ST_S and drain strings ST_D connected between bit lines BL and source lines SL. The source strings ST_S and the drain strings ST_D may be connected to each other through a pipe gate (PG) to form a U-shaped structure. The pipe gate PG may be formed in a pipe line PL. Specifically, the source strings ST_S may be formed perpendicular to the substrate between the source lines SL and the pipeline PL, and the drain strings ST_D may be formed between the bit lines BL and the pipeline. (PL) can be formed perpendicularly to the substrate. This structure may be referred to as P-BiCS (Pipe-shaped Bit Cost Scalable).

Specifically, the drain strings ST_D and the source strings ST_S may be arranged in a first direction (X direction) and a second direction (Y direction), respectively. The drain strings ST_D and the source strings ST_S may be alternately arranged along the second direction (Y direction). The drain strings ST_D may include stacked word lines WL and drain select lines DSL spaced apart from each other. The drain strings ST_D may include drain vertical channel films D_CH vertically penetrating the word lines WL and the drain select line DSL. The source strings ST_S may include word lines WL and source select lines SSL stacked apart from each other. The source strings ST_S may include source vertical channel films S_CH vertically penetrating the word lines WL and the source select line SSL. The drain vertical channel films D_CH and the source vertical channel films S_CH may be connected to each other by the pipe gate PG in the pipeline PL. The bit lines BL may extend in a second direction (Y direction) while contacting upper portions of the drain vertical channel layers D_CH protruding above the drain select line DSL.

7 is a flowchart illustrating a method for performing a status check according to an embodiment of the present invention.

The embodiment described with reference to FIG. 7 may be applied to the memory system described with reference to FIGS. 1 to 6 . Depending on embodiments, at least one of the steps shown in FIG. 7 may be omitted. Depending on the embodiment, the order of steps shown in FIG. 7 may be changed.

In operation 701 , the state check command determiner may check a state check command supported by the memory device. For example, the state check command determiner may determine a state check command supported by the corresponding memory device based on the type information of the memory device received from the host and the first table.

In steps 703 to 711 , the state check performer may perform a state check on the memory device using the state check command confirmed by the state check command determiner.

In operation 703 , the state check execution unit may generate a state check command supported by the memory device and transmit the generated state check command to the memory device. When a plurality of state check commands are supported by the memory device, one state check command among the plurality of state check commands may be selected and the selected state check command may be transmitted to the memory device.

In operation 705 , the state check performing unit may receive state information from the memory device in response to the state check command.

In step '707', the status check performer may determine status information to be checked among the received status information. For example, the state check performer may determine state information to be checked among state information corresponding to a state check command transmitted to the memory device with reference to the third table. Depending on the embodiment, the state check performer may determine state information to be checked by further considering the type of operation that is a target of the state check. For example, the status check performer may check the type of operation command transmitted to the memory device by referring to an operation command queue before transmitting the status check command. Subsequently, the state check performing unit may refer to the third table to determine state information to be checked in correspondence with the corresponding operation.

In step '709', the status check performer may confirm the status check result by checking the determined status information. For example, the state check performer may check the state check result of the memory device by checking the definition of a bit corresponding to a reference bit among the state information received from the memory device with reference to the second table.

Meanwhile, as described above, when a plurality of status check commands are supported by the memory device, the status check execution unit performs a status check on the memory device using any one status check command among the plurality of status check commands. can do. In this case, the status check execution unit may perform a status check on the memory device using another status check command according to a result of performing the status check using the corresponding one status check command. This will be described later with reference to FIG. 11 .

8 is an exemplary diagram for explaining a first table according to an embodiment of the present invention.

In the first table, information on the type of memory device supporting the corresponding state check command may be mapped to each of the plurality of state check commands.

Referring to FIG. 8 , a memory device corresponding to type A supports a first state check command 70h, a second state check command 78h, and an Nth state check command 7Ah, and a memory device corresponding to type B It can be seen that the device supports the second status check command 78h.

If the type information of the memory device received from the host indicates type A, the state check command determiner determines the first state check command 70h, the second state check command 78h, and the Nth state check command 7Ah. A state check command to be applied to the corresponding memory device may be determined, and a state check of the memory device may be performed using at least one state check command among the corresponding state check commands.

9 is an exemplary diagram for explaining a second table according to an embodiment of the present invention.

In the second table, definitions of state information corresponding to a corresponding state check command may be recorded for each of a plurality of state check commands.

In the embodiment described with reference to FIG. 9 , it is assumed that a memory device includes four planes.

Among the state information corresponding to the first state check command 70h, the bit received through the first input/output line DQ0 indicates the pass of the most recently performed operation on at least one plane among the four planes, or May indicate a fail.

Among the state information corresponding to the first state check command 70h, a bit received through the second input/output line DQ1 may indicate pass or fail of a previous operation performed on at least one plane among the four planes. .

Among the state information corresponding to the first state check command 70h, bits received through the third input/output line DQ2 and the fourth input/output line DQ3 may be reserved for future use.

Among the state information corresponding to the first state check command 70h, a bit received through the fifth input/output line DQ4 may indicate whether a program operation or an erase operation is in a suspended state.

Among the state information corresponding to the first state check command 70h, the bit received through the sixth input/output line DQ5 indicates whether an array operation is being performed on at least one of the four planes. can

Among the state information corresponding to the first state check command 70h, a bit received through the seventh input/output line DQ6 may indicate whether the memory device is ready to receive a new operation command.

Among the state information corresponding to the first state check command 70h, a bit received through the eighth input/output line DQ7 may indicate whether the One Time Programmable (OTP) area is protected.

Detailed descriptions of the second status check command 78h and the Nth status check command 7Ah are omitted.

Meanwhile, status information corresponding to each status check command may indicate different status check results. For example, the bit received through the first input/output line DQ0 in response to the first status check command 70h and the bit received through the first input/output line DQ0 in response to the second status check command 78h Bits can indicate different status check results. For example, as described above, the bit received through the first input/output line DQ0 in response to the first state check command 70h indicates the most recent operation performed on at least one of the planes of the memory device. It can indicate whether this succeeded or failed. On the other hand, the bit received through the first input/output line DQ0 in response to the second state check command 78h indicates whether the most recent operation performed on the selected plane among the planes of the memory device succeeded or failed. can That is, even with the same status check bit, the meaning of the status check result may be different according to the type of status check command.

Accordingly, the state check performer may check the state check result by referring to the second table and confirming the meaning of the state information received from the memory device.

10 is an exemplary view for explaining a third table according to an embodiment of the present invention.

In the third table, operations may be mapped for each of a plurality of status check commands, and reference bits to be checked may be mapped corresponding to each operation.

For example, it is assumed that the first status check command 70h is issued after a program operation. In this case, the third table includes the bits received through the first input/output line DQ0, the bits received through the second input/output line DQ1, the bits received through the fourth input/output line DQ5, and the fifth input/output lines. A bit received through line DQ6 is defined as a reference bit. Accordingly, the memory controller determines the bit received through the first input/output line DQ0 and the bit received through the second input/output line DQ1 among the status information received from the memory device in response to the first status check command 70h. , It is possible to check the status check result corresponding to the program operation by checking the bit received through the fourth input/output line DQ5 and the bit received through the fifth input/output line DQ6.

For example, it is assumed that the first status check command 70h is issued after a read operation. In this case, the third table defines bits received through the fifth input/output line DQ6 as reference bits. Accordingly, the memory controller checks the state check result corresponding to the read operation by checking the bit received through the fifth input/output line DQ6 among the state information received from the memory device in response to the first state check command 70h. can

For example, it is assumed that the first status check command 70h is issued after a suspend operation. In this case, the third table defines bits received through the third input/output line DQ4 as reference bits. Accordingly, the memory controller checks the bit received through the third input/output line DQ4 among the state information received from the memory device in response to the first state check command 70h to determine the state check result corresponding to the suspend operation. can

Detailed descriptions of the second status check command 78h and the Nth status check command 7Ah are omitted.

Meanwhile, as described above, a plurality of status check commands supported by one memory device may be provided. In this case, the memory controller selects one of the plurality of status check commands supported by the memory device to determine the state of the memory device. check can be performed. This selection may be made randomly or according to a pre-determined priority. For example, the memory device supports the first status check command 70h and the second status check command 78h, and the priority of the first status check command 70h is the priority of the second status check command 78h. Let's assume a case where it is set higher than the rank. In this case, the memory controller may check the state of the memory device using the first state check command 70h. In this case, the memory controller may determine whether to further perform a state check using the second state check command 78h according to a result of performing the state check using the first state check command 70h. This will be examined with reference to FIG. 11 .

FIG. 11 is an exemplary diagram for explaining in detail the state information shown in FIG. 9 .

For convenience of description, only a part of the state information shown in FIG. 9 is shown in FIG. 11 .

The bit received through the first input/output line DQ0 in response to the first status check command 70h is performed in at least one of the planes (plane 0, plane 1, plane 2, and plane 3) of the memory device. It may indicate whether the most recent operation performed successfully or failed. For example, when the bit received through the first input/output line DQ0 in response to the first state check command 70h is '0', it indicates that the most recent operation performed on the planes of the memory device succeeded. indicate For example, when the bit received through the first input/output line DQ0 in response to the first state check command 70h is '1', the most recent It may indicate that the operation has failed.

A bit received through the second input/output line DQ1 in response to the first status check command 70h is performed in at least one of the planes (plane 0, plane 1, plane 2, and plane 3) of the memory device. It may indicate whether the previous operation performed successfully or failed. For example, if the bit received through the second input/output line DQ1 in response to the first state check command 70h is '0', it indicates that the previous operation performed on the planes of the memory device succeeded. . For example, when the bit received through the second input/output line DQ1 in response to the first status check command 70h is '1', the previous operation performed in at least one of the planes of the memory device This may indicate failure.

The bit received through the first input/output line DQ0 in response to the second state check command 78h is the most performed on the selected plane among the planes (plane 0, plane 1, plane 2, and plane 3) of the memory device. It may indicate whether the latest operation succeeded or failed. That is, the bit received through the first input/output line DQ0 in response to the second status check command 78h is the bit received through the first input/output line DQ0 in response to the first status check command 70h. Unlike , it can indicate the status check result corresponding to one plane. For example, when the bit received through the first input/output line DQ0 in response to the second status check command 78h is '0', it indicates that the most recent operation performed on the selected plane of the memory device succeeded. indicate For example, if the bit received through the first input/output line DQ0 in response to the second status check command 78h is '1', it indicates that the most recent operation performed on the selected plane of the memory device has failed. can indicate

The bit received through the second input/output line DQ1 in response to the second state check command 78h indicates the previous state performed in the selected plane among the planes (plane 0, plane 1, plane 2, and plane 3) of the memory device. It may indicate whether the operation of has succeeded or failed. That is, the bit received through the second input/output line DQ1 in response to the second status check command 78h is the bit received through the second input/output line DQ1 in response to the first status check command 70h. Unlike , it can indicate the status check result corresponding to one plane. For example, if the bit received through the second input/output line DQ1 in response to the second status check command 78h is '0', it indicates that the previous operation performed in the selected plane of the memory device succeeded. . For example, if the bit received through the second input/output line DQ1 in response to the second status check command 78h is '1', it indicates that the previous operation performed on the selected plane of the memory device failed. can

As shown in FIG. 11 , in a state in which state information corresponding to the first state check command 70h and the second state check command 78h is defined, the memory device receives the first state check command 70h and the second state check command 70h. Assume that the second status check command 78h is supported. In this case, the memory controller may check the state of the memory device using the first state check command 70h. If the bit received through the first input/output line DQ0 is '1' as a result of performing the status check using the first status check command 70h, that is, the operation performed in at least one of the planes of the memory device Suppose the operation fails. In this case, the memory controller needs to check whether an operation performed on a plane has failed and perform error processing. Accordingly, in this case, the memory controller may further perform a state check using the second state check command 78h to determine whether an operation performed on a plane among planes of the memory device has failed.

FIG. 12 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .

Referring to FIG. 12, a memory system (Memory System; 30000) is a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), or a wireless communication device. can be implemented as The memory system 30000 may include a memory device 2200 and a memory controller 2100 capable of controlling operations of the memory device 2200 . The memory device 2200 illustrated in FIG. 12 may correspond to the memory device 2200 illustrated in FIGS. 1 and 2 . The memory controller 2100 illustrated in FIG. 12 may correspond to the memory controller 2100 illustrated in FIGS. 1 and 2 .

The memory controller 2100 may control a data access operation of the memory device 2200, such as a program operation, an erase operation, or a read operation, under the control of a processor 3100. there is.

Data programmed in the memory device 2200 may be output through a display 3200 under the control of the memory controller 2100 .

The radio transceiver (RADIO TRANSCEIVER) 3300 may transmit and receive radio signals through an antenna (ANT). For example, the wireless transceiver 3300 may change a radio signal received through the antenna ANT into a signal that can be processed by the processor 3100 . Accordingly, the processor 3100 may process a signal output from the wireless transceiver 3300 and transmit the processed signal to the memory controller 2100 or the display 3200 . The memory controller 2100 may transmit a signal processed by the processor 3100 to the memory device 2200 . In addition, the wireless transceiver 3300 may change the signal output from the processor 3100 into a wireless signal and output the changed wireless signal to an external device through the antenna ANT. An input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and includes a touch pad and It may be implemented with a pointing device such as a computer mouse, a keypad, or a keyboard. The processor 3100 displays the display 3200 so that data output from the memory controller 2100, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output through the display 3200. ) can be controlled.

According to an embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 3100 or as a separate chip from the processor 3100 .

FIG. 13 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .

Referring to FIG. 13, a memory system (Memory System) 40000 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, and a personal digital assistant (PDA). ), portable multimedia player (PMP), MP3 player, or MP4 player.

The memory system 40000 may include a memory device 2200 and a memory controller 2100 capable of controlling a data processing operation of the memory device 2200 . The memory device 2200 illustrated in FIG. 13 may correspond to the memory device 2200 illustrated in FIGS. 1 and 2 . The memory controller 2100 illustrated in FIG. 13 may correspond to the memory controller 2100 illustrated in FIGS. 1 and 2 .

The processor 4100 may output data stored in the memory device 2200 through the display 4300 according to data input through the input device 4200 . For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and the operation of the memory controller 2100 . According to an embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 4100 or as a separate chip from the processor 4100 .

FIG. 14 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .

Referring to FIG. 14 , the memory system 50000 may be implemented as an image processing device such as a digital camera, a mobile phone with a digital camera, a smart phone with a digital camera, or a tablet PC with an attached digital camera. .

The memory system 50000 includes a memory device 2200 and a memory controller 2100 capable of controlling a data processing operation of the memory device 2200, such as a program operation, an erase operation, or a read operation. The memory device 2200 illustrated in FIG. 14 may correspond to the memory device 2200 illustrated in FIGS. 1 and 2 . The memory controller 2100 illustrated in FIG. 14 may correspond to the memory controller 2100 illustrated in FIGS. 1 and 2 .

The image sensor 5200 of the memory system 50000 may convert optical images into digital signals, and the converted digital signals may be transmitted to the processor 5100 or the memory controller 2100. . Under the control of the processor 5100, the converted digital signals may be output through a display 5300 or stored in the memory device 2200 through the memory controller 2100. Also, data stored in the memory device 2200 may be output through the display 5300 under the control of the processor 5100 or the memory controller 2100 .

According to an embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 5100 or as a separate chip from the processor 5100 .

FIG. 15 is a diagram for explaining another example of a memory system including the memory controller shown in FIGS. 1 and 2 .

Referring to FIG. 15 , a memory system (70000) may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200 , a memory controller 2100 , and a card interface 7100 . The memory device 2200 illustrated in FIG. 15 may correspond to the memory device 2200 illustrated in FIGS. 1 and 2 . The memory controller 2100 illustrated in FIG. 15 may correspond to the memory controller 2100 illustrated in FIGS. 1 and 2 .

The memory controller 2100 may control data exchange between the memory device 2200 and the card interface 7100 . According to embodiments, the card interface 7100 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto.

The card interface 7100 may interface data exchange between the host 60000 and the memory controller 2100 according to the protocol of the host 60000 (HOST). According to an embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol or an InterChip (IC)-USB protocol. Here, the card interface 7100 may mean hardware capable of supporting a protocol used by the host 60000, software loaded in the hardware, or a signal transmission method.

When the memory system 70000 is connected with the host interface 6200 of the host 60000, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the host The interface 6200 may perform data communication with the memory device 2200 through the card interface 7100 and the memory controller 2100 under the control of a microprocessor (μP) 6100 .

Although specific embodiments have been described in the detailed description of the present invention, various changes are possible within the limits that do not deviate from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined, but should be defined by those equivalent to the claims of this invention as well as the claims to be described later.

Host: 1000 Memory System: 2000
Memory Controller: 2100 Memory Device: 2200
CPU: 2150 State check command determining unit: 2151
Status check execution unit: 2155

Claims (19)

a state check command determiner determining a state check command supported by the memory device among a plurality of state check commands; and
a state check performer performing a state check operation on the memory device using the checked state check command;
The state check performing unit,
Checking a state check result by checking a bit corresponding to a reference bit among the state information received from the memory device;
The reference bit is
A memory controller mapped to the state check command.
◈Claim 2 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the state check command determining unit,
Checking the status check command supported by the memory device based on type information of the memory device received from a host
memory controller.
◈Claim 3 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the state check command determining unit,
For each of the plurality of status check commands, a first table in which type information of a memory device supporting the corresponding status check command is mapped is stored;
Checking the status check command supported by the memory device based on the first table and type information of the memory device received from a host
memory controller.
◈Claim 4 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the state check performing unit,
Stores a second table in which a definition of state information corresponding to each of the plurality of state check commands is recorded;
Checking a state check result based on the second table and the state information received from the memory device
memory controller.
◈Claim 5 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the state check performing unit,
Storing a third table in which reference bits to be checked among state information corresponding to the corresponding state check command are mapped for each of the plurality of state check commands
memory controller.
◈Claim 6 was abandoned when the registration fee was paid.◈ According to claim 5,
In the third table, the reference bits are mapped further corresponding to each operation,
The status check performing unit checks a bit corresponding to a reference bit mapped to an operation that is a target of the status check among the status information received from the memory device to confirm a status check result.
memory controller.
◈Claim 7 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the state check performing unit,
If there are a plurality of the confirmed status check commands, a status check is performed using any one status check command among the identified plurality of status check commands, and according to the result of the status check using the one status check command Determining whether to further perform a status check using another status check command among the identified plurality of status check commands
memory controller.
a memory device outputting status information in response to a status check command; and
a memory controller configured to check a status check command supported by the memory device among a plurality of status check commands and perform a status check on the memory device using the checked status check command;
The memory controller,
Checking a state check result by checking a bit corresponding to a reference bit among the state information received from the memory device;
The reference bit is
A memory system mapped to the state check command.
◈Claim 9 was abandoned when the registration fee was paid.◈ The method of claim 8 , wherein the memory controller comprises:
Checking a state check command supported by the memory device based on type information of the memory device received from a host
memory system.
◈Claim 10 was abandoned when the registration fee was paid.◈ The method of claim 8 , wherein the memory controller comprises:
For each of the plurality of status check commands, a first table to which type information of a memory device supporting the corresponding status check command is mapped is stored, and based on the first table and the type information of the memory device received from the host, Check the status check command supported by the memory device.
memory system.
◈Claim 11 was abandoned when the registration fee was paid.◈ The method of claim 8 , wherein the memory controller comprises:
For each of the plurality of status check commands, a second table in which a definition of status information corresponding to the corresponding status check command is recorded is stored, and a status is determined based on the second table and the status information received from the memory device. check the check result
memory system.
◈Claim 12 was abandoned when the registration fee was paid.◈ The method of claim 8 , wherein the memory controller comprises:
Storing a third table in which reference bits to be checked among state information corresponding to the corresponding state check command are mapped for each of the plurality of state check commands
memory system.
◈Claim 13 was abandoned when the registration fee was paid.◈ According to claim 12,
In the third table, the reference bits are mapped further corresponding to each operation,
The memory controller checks a state check result by checking a bit corresponding to a reference bit mapped to an operation that is a target of state check among state information received from the memory device.
memory system.
◈Claim 14 was abandoned when the registration fee was paid.◈ The method of claim 8 , wherein the memory controller comprises:
If there are a plurality of the confirmed status check commands, a status check is performed using any one status check command among the identified plurality of status check commands, and according to the result of the status check using the one status check command Determining whether to further perform a status check using another status check command among the identified plurality of status check commands
memory system.
Receiving type information of a memory device from a host;
Checking a status check command supported by the memory device based on a first table in which the received type information of the memory device and type information of a memory device supporting the corresponding status check command are mapped with respect to each of the plurality of status check commands step; and
Performing a state check on the memory device using the checked state check command;
The step of performing the status check is,
receiving state information in response to the state check command from the memory device; and
Checking a state check result by checking a bit corresponding to a reference bit among the state information received from the memory device;
The reference bit is mapped to the state check command.
◈Claim 16 was abandoned when the registration fee was paid.◈ 16. The method of claim 15, wherein checking the state check result comprises:
and checking a state check result based on the received state information and a second table in which a definition of state information corresponding to a corresponding state check command is recorded for each of the plurality of state check commands. how it works.
◈Claim 17 was abandoned when the registration fee was paid.◈ 16. The method of claim 15, wherein checking the state check result comprises:
The operating method of the memory controller is performed by referring to a third table in which reference bits to be checked among state information corresponding to the state check command are mapped for each of the plurality of state check commands.
◈Claim 18 was abandoned when the registration fee was paid.◈ 18. The method of claim 17,
In the third table, the reference bits are mapped further corresponding to each operation,
The checking of the state check result includes checking a state check result by checking a bit corresponding to a reference bit mapped to an operation that is a target of the state check among state information received from the memory device.
How the memory controller works.
◈Claim 19 was abandoned when the registration fee was paid.◈ 16. The method of claim 15, wherein performing the status check comprises:
performing a status check using one of the identified status check commands when there are a plurality of status check commands; and
Determining whether or not to further perform a status check using another status check command among the identified plurality of status check commands according to a result of performing the status check using the one status check command.
A method of operating a memory controller including a.

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