KR102492602B1 - Method and apparatus for detecting resolver error - Google Patents

Abstract

The present invention relates to a method and apparatus for detecting an error in a resolver output. An apparatus for detecting a resolver error according to an embodiment of the present invention includes a comparator outputting a digital signal based on a difference between a resolver output and a reference voltage, inputting the digital signal to an AND gate, and It may include a duty value calculator that calculates a duty value of the gate output and a phase error detector that detects a phase error of the resolver output based on a difference between the calculated duty value and a reference value.

Description

Resolver error detection device and method {METHOD AND APPARATUS FOR DETECTING RESOLVER ERROR}

The present invention relates to a method and apparatus for detecting an error in a resolver output. More specifically, the present invention relates to a method and apparatus for detecting a phase error and an amplification ratio error of a resolver output.

The resolver is a type of rotary electric transformer device that measures the rotational angle of a rotor, and is a device used throughout the industry. In particular, in order to drive the AC motor of an eco-friendly vehicle with maximum torque, it is necessary to precisely measure the angle of the AC motor rotor. At this time, a resolver is used. Hereinafter, a resolver device and a resolver output that may be referred to in some embodiments of the present invention will be described with reference to FIGS. 1 and 2 .

Referring to FIGS. 1 and 2 , an excitation signal 11 is input to the input coil 10 . Accordingly, the first output coil 21 whose envelope is a sine wave is output to the first output coil 20, and the second output coil 30 orthogonal to the first output coil 20 at an angle of 90 degrees. ), the second output 31 whose envelope is a cosine waveform is output. In this resolver device, since the amplitudes of the first output 21 and the second output 31 vary according to the position of the rotor 40, each An envelope of the output is formed.

In this resolver device, the angles of the first output 21, the second output 31, and the rotor 40 according to the input of the excitation signal 11 can be calculated by the following formula.

은 여자 신호(11)이고,

은 제1 출력(21)이고,

은 제2 출력(31)이고,

는 회전자(40)의 각도이다. 또한,

는 캐리어 주파수이고,

는 출력 비율이다. 이하, 도 3 내지 도 5를 참조하여, 레졸버 출력에 따라 산출된 회전자(40)의 각도를 설명하기로 한다.here,

is the excitation signal (11),

is the first output 21,

is the second output 31,

is the angle of the rotor 40. also,

is the carrier frequency,

is the output ratio. Hereinafter, the angle of the rotor 40 calculated according to the resolver output will be described with reference to FIGS. 3 to 5 .

Referring to FIG. 3 , an angular graph 41 of the rotor 40 in a steady state is shown. Referring to FIG. 4 , an angle graph 43 of the rotor 40 in a state in which a phase error occurs is shown. Referring to FIG. 5 , an angle graph 45 of the rotor 40 in a state in which an amplification ratio error occurs is shown. As can be seen in FIGS. 4 and 5 , when an error in the resolver output occurs, it is difficult to precisely calculate the angle of the rotor 40 .

Therefore, in order to accurately calculate the angle of the rotor 40, a method for detecting an error in the resolver output is required. In particular, a method for detecting a phase error of a resolver output and an amplification ratio error of a resolver output is required.

A technical problem to be solved by some embodiments of the present invention is to provide a method and apparatus for detecting a phase error of a resolver output.

Another technical problem to be solved by some embodiments of the present invention is to provide a method and apparatus for detecting an amplification ratio error of a resolver output.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

An apparatus for detecting a resolver error according to an embodiment of the present invention for solving the above technical problem is a comparator for outputting a digital signal based on a difference between a resolver output and a reference voltage, and an end gate (AND of the digital signal) gate), a duty value calculation unit that calculates a duty value of an end gate output, and a phase error detection unit that detects a phase error of the resolver output based on a difference between the calculated duty value and a reference value. wealth may be included.

In one embodiment, the resolver output includes a first output and a second output having a phase difference between the first output and a reference angle, and the comparison unit is based on a difference between the first output and the reference voltage. Thus, a first digital signal may be output, and a second digital signal may be output based on a difference between the second output and the reference voltage. In this case, the duty value calculating unit calculates the duty value based on a period in which the first digital signal and the second digital signal have the same phase, or the logic value of the first digital signal and the second digital signal. The duty value may be calculated based on a section in which the logical value of is 1.

In an embodiment, the duty value calculating unit may calculate the duty value by counting the end gate output using an oscillator. Here, the frequency of the oscillator may be greater than the frequency of the resolver output.

In one embodiment, based on the sensed phase error, it may further include a phase error correction unit correcting the phase error of the resolver output.

In an embodiment, the apparatus may further include a sampling unit to sample the resolver output and an amplification ratio error detection unit to detect an amplification ratio error of the resolver output based on a voltage sampled from the sampling unit. Here, the resolver output includes a first output and a second output having a phase difference between the first output and a reference angle, and the sampling unit performs a first sampling of the first output, and after a reference time has elapsed, the second output The second output may be second sampled. Here, the amplification ratio error detector may sense the amplification ratio error of the resolver output based on a difference between a result of the first sampling and a result of the second sampling. Also, based on the sensed amplification ratio error, it may further include an amplification ratio error correction unit for correcting the amplification ratio error of the resolver output.

A method for detecting a resolver error according to another embodiment of the present invention is a method performed by a resolver error detection device, the step of outputting a digital signal based on a difference between a resolver output and a reference voltage, the digital signal to an AND gate, calculating a duty value of an end gate output, and detecting a phase error of the resolver output based on a difference between the calculated duty value and a reference value. can include The method may further include sampling the resolver output and detecting an amplification ratio error of the resolver output based on the sampled voltage.

1 is a diagram for explaining a resolver device that may be referred to in some embodiments of the present invention.
FIG. 2 is a diagram for explaining a resolver output of the resolver device described with reference to FIG. 1 .
3 to 5 are diagrams for explaining an error of the resolver output described with reference to FIG. 2 .
6 is a diagram for explaining an apparatus for detecting a resolver error according to an embodiment of the present invention.
FIG. 7 is a diagram for explaining the resolver error detection device described with reference to FIG. 6 in more detail.
8 to 10 are diagrams for explaining a phase error detection operation of the resolver error detection device described with reference to FIG. 7 in more detail.
11 is a diagram for explaining an apparatus for detecting a resolver error according to another embodiment of the present invention.
FIG. 12 is a diagram for explaining the resolver error detection device described with reference to FIG. 11 in more detail.
13 and 14 are diagrams for explaining an amplification ratio error detection operation of the resolver error detection device described with reference to FIG. 12 in more detail.
15 and 16 are views for explaining a resolver error detection method according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the technical idea of the present invention is not limited to the following embodiments and can be implemented in various different forms, only the following embodiments complete the technical idea of the present invention, and in the technical field to which the present invention belongs It is provided to fully inform those skilled in the art of the scope of the present invention, and the technical spirit of the present invention is only defined by the scope of the claims.

In adding reference numerals to components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless explicitly specifically defined. Terminology used herein is for describing the embodiments and is not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, order, or order of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is directly connected or connectable to the other element, but there is another element between the elements. It will be understood that elements may be “connected”, “coupled” or “connected”.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. 6 is a diagram for explaining an apparatus for detecting a resolver error according to an embodiment of the present invention.

Referring to FIG. 6 , the resolver system may include a uC 100 and a resolver interface 200 . Each component of the resolver system shown in FIG. 6 represents functionally differentiated functional elements, and any one or more components may be integrated and implemented in an actual physical environment. Hereinafter, components of the resolver system will be described in more detail.

The uC 100 may transmit a signal to the resolver interface 200 so that an excitation signal is input to the resolver input terminal coil 10 . In addition, the uC 100 may calculate the angle of the rotor by receiving the first output output from the first output coil 20 of the resolver and the second output output from the second output coil 30 of the resolver.

The uC 100 may include a phase error correction unit that corrects a phase error of a resolver output based on a phase error detected by a phase error detection unit, which will be embodied in some embodiments to be described later. In addition, the uC 100 may include an amplification ratio error correction unit for correcting an amplification ratio error of a resolver output based on an amplification ratio error detected by an amplification ratio error detector to be embodied in some embodiments to be described later. That is, it should be noted that the uC 100 is not limited to the components of the uC 100 shown in FIG. 6 .

Next, the resolver interface 200 may receive a signal for generating an excitation signal from the uC 100 and input the excitation signal to the input coil 100 . For example, the excitation signal may refer to a sine wave having a carrier frequency. However, it is not limited thereto. The first output stage coil 20 outputs a first output caused by an excitation signal. For example, the first output may have an envelope of a sine wave. The second output stage coil 30 outputs a second output caused by the excitation signal. For example, the envelope of the second output may be a cosine wave. However, it should be noted that it is not limited thereto. Equations related to the excitation signal, the first output, and the second output may be embodied by referring to the background art described above.

The resolver interface 200 may amplify outputs outputted by the first output coil 20 and the second output coil 30 and transmit the amplified output to the uC 100 .

The resolver interface 200 may include a resolver phase error detection device 300 that detects a phase error of the resolver output. Hereinafter, a resolver phase error detection device 300 for detecting a phase error of a resolver output will be described with reference to FIG. 7 .

Referring to FIG. 7 , the resolver phase error detection device 300 may include a comparison unit 310 , a duty value calculator 330 and a phase error detection unit 350 . The components of the resolver phase error detection device 300 shown in FIG. 7 represent functionally differentiated functional elements, and any one or more components may be integrated and implemented in an actual physical environment. In addition, it should be noted that the resolver phase error detection device 300 is not limited to the components of the resolver phase error detection device 300 shown in FIG. 7 . Hereinafter, components of the resolver phase error detection device 300 will be described in more detail.

The comparator 310 outputs a digital signal based on the difference between the resolver output and the reference voltage 311 . A general comparator circuit may be applied to Comp_S and Comp_C included in the comparator 310 . Since the content related to the comparator circuit is obvious to those skilled in the art, a detailed description thereof will be omitted.

In some embodiments, the resolver output may include a first output and a second output out of phase with the first output at a reference angle. For example, the first output may be a sine wave and the second output may be a cosine wave. Here, the reference angle is 90 degrees. Referring to FIG. 7 , a first output may be measured at a first node 313 and a second output may be measured at a second node 315 .

Also, in some embodiments, the comparator 310 outputs a first digital signal based on a difference between the first output and the reference voltage 311 and based on a difference between the second output and the reference voltage 311 , it is possible to output the second digital signal. Referring to FIG. 7 , a first digital signal may be measured at a third node 331 and a second digital signal may be measured at a fourth node 333 .

Next, the duty value calculator 330 inputs the digital signal output from the comparator 310 to the end gate and calculates a duty value of the end gate output. Here, the end gate means a basic digital logic gate that implements logical product. In addition, the duty value means the ratio of the conduction period to one period in the semiconductor device, and means the ratio of the conduction period to one period of the end gate output.

In some embodiments, the duty value calculator 330 may calculate a duty value based on a period in which the first digital signal and the second digital signal have the same phase. Also, in some other embodiments, the duty value calculator 330 may calculate a duty value based on a section in which the logic value of the first digital signal and the logic value of the second digital signal are 1.

In some other embodiments, the duty value calculator 330 may calculate the duty value by counting the output of the end gate using an oscillator. Here, an oscillator is a functional element that vibrates at a required frequency, and is often a functional element that generates a clock. All known techniques related to oscillators can be applied to count the output of the end gate. Here, the frequency of the oscillator may be greater than the frequency of the resolver output. For example, the frequency of the resolver output may be 10 KHz while the oscillator frequency is 5 MHz.

Referring to FIG. 7 , information about the duty value of the end gate output may be measured at the fifth node 351 . Also, information obtained by counting the output of the end gate by the oscillator may be measured. Also, the output of the end gate may be measured.

Next, the phase error detector 350 may detect a phase error of the resolver output based on the difference between the duty value calculated by the duty value calculator 330 and the reference value. Here, the reference value refers to a value previously determined by reference angles formed by coils of the output stage and rotational speed of the rotor.

The phase error detecting unit 350 may determine that a phase error has occurred when a difference from a predetermined reference value occurs when the signal output from the duty value calculating unit 330 is information about the duty value. In addition, when the signal output by the duty value calculation unit 330 is information counted by the oscillator, the phase error detection unit 350 calculates a duty value that is a conduction rate for one period, and calculates a duty value corresponding to a predetermined reference value. If a difference occurs, it may be determined that a phase error has occurred. In addition, when the signal output from the duty value calculator 330 is the output of the end gate, the phase error detection unit 350 counts the output of the end gate by the oscillator and calculates the duty value, which is the conduction rate for one cycle. It may be determined that a phase error has occurred when a difference from a predetermined reference value is calculated.

It should be noted that in some embodiments, the duty value may be substituted into a convertible form. It is obvious that the reference value is also replaced according to the conversion of the duty value. For example, whether or not a phase error occurs may be determined based on the length of the conduction section rather than the same ratio as the duty value. However, it is not limited thereto.

Hereinafter, a phase error detection operation will be described in more detail with reference to FIGS. 8 to 10 . 8 is a graph showing the output measured at the main node in a steady state, and FIG. 9 is a graph of the measured output at the main node in the case of the first output shifted in the x-axis (+) direction according to the occurrence of the phase error. 10 is a graph showing the output measured at the main node in the case of the first output shifted in the (-) direction of the x-axis according to the occurrence of the phase error. It should be noted that FIGS. 8 to 10 are only exemplary drawings for explaining a phase error detection operation, and the present invention is not limited thereto.

Referring to FIG. 8 , a first output 21 , a first digital signal 22 , a second output 31 and a second digital signal 33 are shown. An end gate normal output 50 output by inputting the first digital signal 22 and the second digital signal 33 to the end gate is also shown.

On the other hand, referring to FIG. 9 , the first output 23 shifted in the x-axis (+) direction and the first digital signal 24 shifted in the x-axis (+) direction are shown. With the first digital signal 24 shifted in the x-axis positive direction, the end gate positive phase error output 51 is also shown. Also, referring to FIG. 10 , the first output 25 shifted in the (-) x-axis direction and the first digital signal 26 shifted in the (-) x-axis direction are shown. With the first digital signal 26 shifted in the negative x-axis direction, the end gate negative phase error output 53 is also shown.

Referring to FIGS. 8 to 10 , when a phase error occurs in the resolver output, whether or not a phase error occurs can be determined based on the output of the end gate. In addition, the phase error may be corrected based on the degree of difference from the reference value.

Hereinafter, an apparatus for detecting a resolver error according to another embodiment of the present invention will be described with reference to FIG. 11 . Referring to FIG. 11 , the resolver system may include a uC 100 and a resolver interface 200 . Each component of the resolver system shown in FIG. 11 represents functionally differentiated functional elements, and any one or more components may be integrated and implemented in an actual physical environment. The configurations shown in FIG. 11 may be understood through the description with reference to FIG. 6 except for the resolver amplification ratio error sensing device 400 . Hereinafter, with reference to FIG. 12, the resolver amplification ratio error sensing device 400 will be described in more detail.

Referring to FIG. 12 , the resolver amplification ratio error detection device 400 may include a sampling unit 410 and an amplification ratio error detection unit 430 . Components of the resolver amplification ratio error detection device 400 shown in FIG. 12 represent functionally differentiated functional components, and any one or more components may be integrated and implemented in an actual physical environment. In addition, it should be noted that the resolver amplification ratio error sensing device 400 is not limited to the components of the resolver amplification ratio error sensing device 400 shown in FIG. 12 . Hereinafter, components of the resolver amplification ratio error sensing device 400 will be described in more detail.

The sampling unit 410 may sample the resolver output.

In some embodiments, the resolver output may include a first output and a second output out of phase with the first output at a reference angle. For example, the first output may be a sine wave and the second output may be a cosine wave. Here, the reference angle is 90 degrees. Referring to FIG. 12 , a first output may be measured at a sixth node 411 and a second output may be measured at a seventh node 413 .

Also, in some embodiments, the sampling unit 410 may first sample the first output and second sample the second output after the elapse of the reference time. Here, the reference time may be a time previously determined by a reference angle formed by coils of the output stage and a rotational speed of the rotor. Such a sampling unit 410 may be implemented by a MUX and an ADC as shown in FIG. 12 . However, it should be noted that what is shown in FIG. 12 is only illustrative and does not limit the present invention.

Next, the amplification ratio error detection unit 430 may detect an amplification ratio error of the resolver output based on the voltage sampled from the sampling unit 410 .

Hereinafter, an amplification ratio error detection operation will be described in more detail with reference to FIGS. 13 and 14 . 13 is a diagram for explaining sampling of a resolver output in a steady state, and FIG. 14 is a diagram for explaining sampling of a first output in which an amplification ratio error occurs. 13 and 14 are exemplary diagrams for explaining an amplification ratio error sensing operation, and it should be noted that the present invention is not limited thereto.

Referring to FIG. 13 , a first output 21 and a second output 31 are shown. Second sampling 31a of the second output 31 is performed after the reference time 31 elapses after the first sampling 21a of the first output 21 . At this time, in the steady state, the result of the first sampling 21a and the result of the second sampling 31a have the same value by a predetermined reference time.

On the other hand, referring to FIG. 14, a first output 27 with an amplification ratio error is shown. At this time, first sampling 27a is performed on the first output 27 in which the amplification ratio error has occurred. As shown in FIG. 14 , when an amplification ratio error occurs, a difference between a result of the first sampling and a result of the second sampling occurs.

Referring to FIGS. 13 and 14 , when an amplification ratio error of the resolver output occurs, a difference between a result of the first sampling and a result of the second sampling occurs. Therefore, it is possible to determine whether an amplification ratio error occurs based on the difference between the sampling results. In addition, the amplification ratio error may be corrected based on the degree of difference between the sampling results.

According to the resolver error detection apparatus according to the embodiments described above with reference to FIGS. 6 to 14 , it is possible to detect a phase error and an amplification ratio error of a resolver output. Also, the resolver error detection device may correct the resolver output based on the detected phase error and amplification ratio error. Hereinafter, a resolver error detection method according to another embodiment of the present invention will be described in more detail with reference to FIGS. 14 and 15 .

15 and 16 are views for explaining a resolver error detection method according to another embodiment of the present invention. The resolver error detection method according to the present embodiments may be performed by a resolver error detection device. Also, the method according to the present embodiments may be performed separately by the first resolver error detection device and the second resolver error detection device. Hereinafter, in performing each operation of the method according to the present embodiment, if the description of the subject is omitted, the subject may be interpreted as a resolver error detection device.

Referring to FIG. 15 , a digital signal is output based on the difference between the resolver output and the reference voltage in step S110. This step S110 may be performed by the comparator of the resolver error detection device. Next, in step S120, a digital signal is input to an AND gate to calculate a duty value. This step S120 may be performed by the duty value calculator of the resolver error detection device. Next, based on the difference between the duty value calculated in step S130 and the reference value, a phase error of the resolver output is detected. This step S130 may be performed by the phase error detection unit of the resolver error detection device. Next, based on the phase error detected in step S140, the phase error of the resolver output is corrected. This step S140 may be performed by the phase error correction unit of the resolver error detection device.

The resolver error detection method according to the present embodiment described with reference to FIG. 15 may be performed by functionally separated elements of the resolver error detection device. Operations performed by elements of the resolver error detection device described above with reference to FIGS. 6 to 10 may also be applied to the present embodiment.

Referring to FIG. 16, the resolver output is sampled in step S210. This step S210 may be performed by the sampling unit of the resolver error detection device. Next, based on the voltage sampled in step S220, an amplification ratio error of the resolver output is detected. This step S220 may be performed by an amplification ratio error detection unit of the resolver error detection device. Next, based on the amplification ratio error detected in step S230, the amplification ratio error of the resolver output is corrected. This step S230 may be performed by an amplification ratio error correction unit of the resolver error detection device.

The resolver error detection method according to the present embodiment described with reference to FIG. 16 may be performed by functionally separated elements of the resolver error detection device. Operations performed by elements of the resolver error detection device described above with reference to FIGS. 11 to 14 may also be applied to the present embodiment.

So far, various embodiments of the present invention and effects according to the embodiments have been described with reference to FIGS. 1 to 16 . Effects according to the technical idea of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

In the above, even though all the components constituting the embodiment of the present invention have been described as being combined or operated as one, the technical idea of the present invention is not necessarily limited to these embodiments. That is, within the scope of the object of the present invention, all of the components may be selectively combined with one or more to operate.

Although actions are shown in a specific order in the drawings, it should not be understood that the actions must be performed in the specific order shown or in a sequential order, or that all depicted actions must be performed to obtain a desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of the various components in the embodiments described above should not be understood as requiring such separation, and the described program components and systems may generally be integrated together into a single software product or packaged into multiple software products. It should be understood that there is

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing the technical spirit or essential features. can understand that there is Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the technical ideas defined by the present invention.

Claims (13)

a comparator outputting a digital signal based on a difference between the resolver output and the reference voltage;
a duty value calculation unit inputting the digital signal to an AND gate and calculating a duty value of an end gate output; and
Based on the difference between the calculated duty value and a reference value, a phase error detector detecting a phase error of the resolver output,
Resolver error detection device. According to claim 1,
The resolver output is,
A first output and a second output having a phase difference between the first output and a reference angle,
The comparison unit,
Outputting a first digital signal based on a difference between the first output and the reference voltage, and outputting a second digital signal based on a difference between the second output and the reference voltage.
Resolver error detection device. According to claim 2,
The duty value calculator,
Calculating the duty value based on a period in which the first digital signal and the second digital signal have the same phase,
Resolver error detection device. According to claim 2,
The duty value calculator,
calculating the duty value based on a period in which the logic value of the first digital signal and the logic value of the second digital signal are 1;
Resolver error detection device. According to claim 1,
The duty value calculator,
Calculating the duty value by counting the end gate output using an oscillator,
Resolver error detection device. According to claim 5,
The frequency of the oscillator is
Which is greater than the frequency of the resolver output,
Resolver error detection device. According to claim 1,
Further comprising a phase error correction unit correcting the phase error of the resolver output based on the detected phase error.
Resolver error detection device. According to claim 1,
a sampling unit sampling the resolver output; and
Further comprising an amplification ratio error detection unit for sensing an amplification ratio error of the resolver output based on the voltage sampled from the sampling unit.
Resolver error detection device. According to claim 8,
The resolver output is,
A first output and a second output having a phase difference between the first output and a reference angle,
The sampling unit,
First sampling the first output and second sampling the second output after a reference time has elapsed.
Resolver error detection device. According to claim 9,
The amplification ratio error detection unit,
sensing the amplification ratio error of the resolver output based on a difference between a result of the first sampling and a result of the second sampling;
Resolver error detection device. According to claim 8,
Based on the sensed amplification ratio error, further comprising an amplification ratio error correction unit for correcting the amplification ratio error of the resolver output.
Resolver error detection device. In the method performed by the resolver error detection device,
outputting a digital signal based on the difference between the resolver output and the reference voltage;
calculating a duty value of an end gate output by inputting the digital signal to an AND gate; and
Based on the difference between the calculated duty value and a reference value, detecting a phase error of the resolver output,
Resolver error detection method. According to claim 12,
sampling the resolver output; and
Further comprising detecting an amplification ratio error of the resolver output based on the sampled voltage.
Resolver error detection method.

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