KR102491112B1 - Msr 코드를 위한 fpga 가속 시스템 - Google Patents
Msr 코드를 위한 fpga 가속 시스템 Download PDFInfo
- Publication number
- KR102491112B1 KR102491112B1 KR1020190126494A KR20190126494A KR102491112B1 KR 102491112 B1 KR102491112 B1 KR 102491112B1 KR 1020190126494 A KR1020190126494 A KR 1020190126494A KR 20190126494 A KR20190126494 A KR 20190126494A KR 102491112 B1 KR102491112 B1 KR 102491112B1
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- error correction
- data elements
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- correction code
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
- G06F11/1096—Parity calculation or recalculation after configuration or reconfiguration of the system
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1032—Simple parity
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/3009—Thread control instructions
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Probability & Statistics with Applications (AREA)
- Human Computer Interaction (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862780185P | 2018-12-14 | 2018-12-14 | |
| US62/780,185 | 2018-12-14 | ||
| US16/271,777 US11061772B2 (en) | 2018-12-14 | 2019-02-08 | FPGA acceleration system for MSR codes |
| US16/271,777 | 2019-02-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20200073978A KR20200073978A (ko) | 2020-06-24 |
| KR102491112B1 true KR102491112B1 (ko) | 2023-01-20 |
Family
ID=71072501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020190126494A Active KR102491112B1 (ko) | 2018-12-14 | 2019-10-11 | Msr 코드를 위한 fpga 가속 시스템 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US11061772B2 (https=) |
| JP (1) | JP7356887B2 (https=) |
| KR (1) | KR102491112B1 (https=) |
| CN (1) | CN111324479B (https=) |
| TW (1) | TWI791891B (https=) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10949301B2 (en) * | 2011-06-06 | 2021-03-16 | Pure Storage, Inc. | Pre-positioning pre-stored content in a content distribution system |
| WO2018176238A1 (en) | 2017-03-28 | 2018-10-04 | Intel Corporation | Technologies for hybrid field-programmable gate array-application-specific integrated circuit code acceleration |
| US11061772B2 (en) * | 2018-12-14 | 2021-07-13 | Samsung Electronics Co., Ltd. | FPGA acceleration system for MSR codes |
| US11934330B2 (en) * | 2020-05-08 | 2024-03-19 | Intel Corporation | Memory allocation for distributed processing devices |
| US11568089B2 (en) * | 2020-08-31 | 2023-01-31 | Frontiir Pte Ltd. | Offloading operations from a primary processing device to a secondary processing device |
| US11868777B2 (en) | 2020-12-16 | 2024-01-09 | Advanced Micro Devices, Inc. | Processor-guided execution of offloaded instructions using fixed function operations |
| US12073251B2 (en) * | 2020-12-29 | 2024-08-27 | Advanced Micro Devices, Inc. | Offloading computations from a processor to remote execution logic |
| US11625249B2 (en) | 2020-12-29 | 2023-04-11 | Advanced Micro Devices, Inc. | Preserving memory ordering between offloaded instructions and non-offloaded instructions |
| US12468474B2 (en) * | 2021-11-15 | 2025-11-11 | Samsung Electronics Co., Ltd. | Storage device and method performing processing operation requested by host |
| US12197378B2 (en) | 2022-06-01 | 2025-01-14 | Advanced Micro Devices, Inc. | Method and apparatus to expedite system services using processing-in-memory (PIM) |
| US12050531B2 (en) | 2022-09-26 | 2024-07-30 | Advanced Micro Devices, Inc. | Data compression and decompression for processing in memory |
| US12147338B2 (en) | 2022-12-27 | 2024-11-19 | Advanced Micro Devices, Inc. | Leveraging processing in memory registers as victim buffers |
| US12265470B1 (en) | 2023-09-29 | 2025-04-01 | Advanced Micro Devices, Inc. | Bypassing cache directory lookups for processing-in-memory instructions |
| US12596650B2 (en) | 2023-09-29 | 2026-04-07 | Advanced Micro Devices, Inc. | Preemptive flushing of processing-in-memory data structures |
| US12455826B2 (en) | 2024-03-29 | 2025-10-28 | Advanced Micro Devices, Inc. | Dynamic caching policies for processing-in-memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1040698A (zh) | 1988-09-02 | 1990-03-21 | 三菱电机株式会社 | 错误校正电路 |
| CN101740135A (zh) | 2008-11-18 | 2010-06-16 | 富士通株式会社 | 错误判断电路和共享的存储器系统 |
| US20140317222A1 (en) | 2012-01-13 | 2014-10-23 | Hui Li | Data Storage Method, Device and Distributed Network Storage System |
| US20160110254A1 (en) | 2014-10-15 | 2016-04-21 | Empire Technology Development Llc | Partial Cloud Data Storage |
| US20170179979A1 (en) | 2015-12-18 | 2017-06-22 | Netapp, Inc. | Systems and Methods for Minimum Storage Regeneration Erasure Code Construction Using r-Ary Trees |
| US20180300201A1 (en) | 2017-04-17 | 2018-10-18 | Intel Corporation | Bypassing error correction code (ecc) processing based on software hint |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7673222B2 (en) * | 2005-07-15 | 2010-03-02 | Mediatek Incorporation | Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method |
| CN102272730B (zh) * | 2008-10-09 | 2017-05-24 | 美光科技公司 | 经虚拟化错误校正码nand |
| US8356137B2 (en) | 2010-02-26 | 2013-01-15 | Apple Inc. | Data storage scheme for non-volatile memories based on data priority |
| US8650446B2 (en) | 2010-03-24 | 2014-02-11 | Apple Inc. | Management of a non-volatile memory based on test quality |
| WO2014131148A1 (zh) | 2013-02-26 | 2014-09-04 | 北京大学深圳研究生院 | 一种最小存储再生码的编码和存储节点修复方法 |
| US8996796B1 (en) | 2013-03-15 | 2015-03-31 | Virident Systems Inc. | Small block write operations in non-volatile memory systems |
| US9547458B2 (en) | 2014-12-24 | 2017-01-17 | International Business Machines Corporation | Intra-rack and inter-rack erasure code distribution |
| US10007587B2 (en) | 2015-09-18 | 2018-06-26 | Qualcomm Incorporated | Systems and methods for pre-generation and pre-storage of repair fragments in storage systems |
| US10452477B2 (en) | 2016-08-26 | 2019-10-22 | Netapp, Inc. | Multiple node repair using high rate minimum storage regeneration erasure code |
| US11061772B2 (en) * | 2018-12-14 | 2021-07-13 | Samsung Electronics Co., Ltd. | FPGA acceleration system for MSR codes |
-
2019
- 2019-02-08 US US16/271,777 patent/US11061772B2/en active Active
- 2019-09-18 TW TW108133489A patent/TWI791891B/zh active
- 2019-10-11 KR KR1020190126494A patent/KR102491112B1/ko active Active
- 2019-11-20 CN CN201911143197.3A patent/CN111324479B/zh active Active
- 2019-12-10 JP JP2019222969A patent/JP7356887B2/ja active Active
-
2021
- 2021-07-02 US US17/367,315 patent/US11726876B2/en active Active
-
2023
- 2023-07-17 US US18/223,019 patent/US12117903B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1040698A (zh) | 1988-09-02 | 1990-03-21 | 三菱电机株式会社 | 错误校正电路 |
| CN101740135A (zh) | 2008-11-18 | 2010-06-16 | 富士通株式会社 | 错误判断电路和共享的存储器系统 |
| US20140317222A1 (en) | 2012-01-13 | 2014-10-23 | Hui Li | Data Storage Method, Device and Distributed Network Storage System |
| US20160110254A1 (en) | 2014-10-15 | 2016-04-21 | Empire Technology Development Llc | Partial Cloud Data Storage |
| US20170179979A1 (en) | 2015-12-18 | 2017-06-22 | Netapp, Inc. | Systems and Methods for Minimum Storage Regeneration Erasure Code Construction Using r-Ary Trees |
| US20180300201A1 (en) | 2017-04-17 | 2018-10-18 | Intel Corporation | Bypassing error correction code (ecc) processing based on software hint |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI791891B (zh) | 2023-02-11 |
| TW202026871A (zh) | 2020-07-16 |
| KR20200073978A (ko) | 2020-06-24 |
| JP2020095722A (ja) | 2020-06-18 |
| US20230367675A1 (en) | 2023-11-16 |
| US11726876B2 (en) | 2023-08-15 |
| CN111324479A (zh) | 2020-06-23 |
| US20200192757A1 (en) | 2020-06-18 |
| JP7356887B2 (ja) | 2023-10-05 |
| CN111324479B (zh) | 2022-08-09 |
| US11061772B2 (en) | 2021-07-13 |
| US20210334162A1 (en) | 2021-10-28 |
| US12117903B2 (en) | 2024-10-15 |
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