KR102486404B1 - Liquid Crystal Display Device And Method Of Fabricating The Same - Google Patents

Abstract

The present invention relates to first and second substrates facing each other and spaced apart from each other, a thin film transistor disposed on an inner surface of the first substrate, a protective layer disposed on the upper portion of the thin film transistor, and an upper portion of the protective layer corresponding to the thin film transistor. A first column spacer disposed on the protective layer, a first alignment layer disposed on the protective layer and exposing an upper surface of the first column spacer, and a plurality of alignment layers disposed on the inner surface of the second substrate and corresponding to the first column spacer. Provided is a liquid crystal display device including an overcoat layer including a first groove of, a second alignment layer disposed under the overcoat layer, and a liquid crystal layer disposed between the first and second alignment layers. Formation and damage of the alignment layer on the upper surface of the column spacer are minimized by forming the layer in the stepped region, and bright spot defects and display quality deterioration are prevented.

Description

Liquid Crystal Display Device And Method Of Fabricating The Same}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which bright point defects due to damage to an alignment layer are prevented, and a manufacturing method thereof.

As society entered the information age in earnest, the display field, which processes and displays a large amount of information, has developed rapidly. Various flat panel display devices such as panel (PDP), field emission display device (FED), and organic light emitting diode display device (OELD) have been developed and are in the spotlight.

Among them, the liquid crystal display device is driven by using the optical anisotropy and polarization of the liquid crystal layer. Since the structure of the liquid crystal molecules is thin and long, the liquid crystal molecules have a directivity in alignment, and an electric field is artificially applied to the liquid crystal layer to change the alignment direction of the liquid crystal molecules. can control. Therefore, when an arbitrary electric field is applied to the liquid crystal layer, the arrangement direction of the liquid crystal molecules is changed, and light is refracted in the arrangement direction of the liquid crystal molecules due to optical anisotropy, thereby displaying image information.

In general, a liquid crystal display device includes two substrates facing each other and a liquid crystal layer interposed between the two substrates. A spacer is used to maintain a constant thickness of the liquid crystal layer (ie, a separation distance between the two substrates). (spacer) is used.

Conventionally, a spacer in the form of scattering has been used, but recently, a column spacer having an advantage of improving an aperture ratio by forming at a specific position by patterning has been widely used.

This conventional liquid crystal display device will be described with reference to the drawings.

1 is a cross-sectional view showing a conventional liquid crystal display device.

As shown in FIG. 1, the conventional liquid crystal display device 10 is formed between first and second substrates 20 and 50 facing each other and spaced apart from each other, and between the first and second substrates 20 and 50. It includes a liquid crystal layer 70 to be.

A gate electrode 22 is formed on the inner surface of the first substrate 20 , and a gate insulating layer 24 is formed on the entire surface of the first substrate 20 above the gate electrode 22 .

A semiconductor layer 26 is formed on the top of the gate insulating layer 24 corresponding to the gate electrode 22, and a source electrode 28 and a drain electrode 30 spaced apart from each other are formed on both ends of the top of the semiconductor layer 26. However, the gate electrode 22, the semiconductor layer 26, the source electrode 28, and the drain electrode 30 constitute a thin film transistor (T).

An interlayer insulating layer 32 is formed on the entire surface of the first substrate 20 above the thin film transistor T, and a common electrode 34 is formed in a pixel region above the interlayer insulating layer 32 .

A passivation layer 36 is formed on the entire surface of the first substrate 20 above the common electrode 34, and a pixel electrode 38 connected to the drain electrode 30 is formed on the passivation layer 36. (38) includes a number of openings.

A first alignment layer 40 is formed on the entire surface of the first substrate 20 above the pixel electrode 38 .

In addition, a black matrix 52 corresponding to the thin film transistor T is formed on the inner surface of the second substrate 50, and the inner surface of the second substrate 50 between the bottom of the black matrix 52 and the black matrix 52 has a color A filter layer 54 is formed.

An overcoat layer 56 is formed on the entire surface of the second substrate 50 below the color filter layer 54, and first and second column spacers 58 and 60 are formed below the overcoat layer 56. The spacer 58 is disposed below the overcoat layer 56 corresponding to the black matrix 52 , and the second column spacer 60 is disposed spaced apart from the first column spacer 58 .

A second alignment layer 62 is formed on the entire surface of the second substrate 50 below the first and second column spacers 58 and 60 .

In such a liquid crystal display device 10, the first column spacer 58 serves to maintain a cell gap in a general environment without external pressure, and the second column spacer 60 serves to maintain a special external pressure such as manufacturing process and reliability test. It plays a role in maintaining the cell gap in the environment.

However, when a specific point of the first or second substrates 58 and 60 is pressed by an external pressure, the first and second column spacers 58 and 60 may move left and right along the horizontal direction. At this time, the protective layer ((36) The upper first alignment layer 38 and the lower second alignment layer 62 of the first and second column spacers 58 and 60 may be partially damaged by friction.

This phenomenon is particularly caused by the first alignment layer 38 and the first and second column spacers 58 and 60 in the region corresponding to the thin film transistor T having the largest step A on the first substrate 20. It is highly likely to occur between the second alignment layer 62 on the lower surface. The damaged alignment layer becomes a foreign substance in the form of debris, floats, and then adheres to a specific area, causing a milky way-shaped bright point defect, resulting in deterioration in display quality of the liquid crystal display device 10. there is a problem

Recently, in order to improve scratch defects, diagonal viewing angle, color imbalance, and improve the uniformity of liquid crystal alignment to improve the contrast ratio of the front, a technology for completing an alignment film by photo-alignment instead of rubbing alignment has been widely studied.

However, since the photo-alignment layer has a lower hardness than the rubbing alignment layer, the first and second alignment layers 38 and 62 are damaged by the first and second column spacers 58 and 60 and the resulting bright spot defects and Deterioration in display quality is further intensified in the photo-alignment layer, and as a result, it is difficult to apply the photo-alignment layer to the liquid crystal display device 10 despite various advantages.

The present invention has been proposed to solve these problems, and provides a liquid crystal display device in which the formation and damage of an alignment layer on the upper surface of the column spacer is minimized and the bright point defect and display quality deterioration are prevented by forming the column spacer in the region having the largest step difference. aims to do

In addition, the present invention provides a liquid crystal display device in which the formation and damage of an alignment film on the lower surface of the area facing the column spacer is minimized, and defective bright spots and deterioration of display quality are prevented by forming a plurality of grooves in the area facing the column spacer. to do for a different purpose.

In order to solve the above problems, the present invention, first and second substrates facing each other and spaced apart, a thin film transistor disposed on the inner surface of the first substrate, a protective layer disposed on the upper portion of the thin film transistor, and the thin film A first column spacer disposed on the protective layer corresponding to the transistor, a first alignment layer disposed on the protective layer and exposing an upper surface of the first column spacer, and disposed on an inner surface of the second substrate, A liquid crystal display device including an overcoat layer including a plurality of first grooves corresponding to the first column spacer, a second alignment layer disposed under the overcoat layer, and a liquid crystal layer disposed between the first and second alignment layers. provides

Also, the second alignment layer may expose a lower surface of the overcoat layer between the plurality of first grooves.

Also, an area obtained by summing the plurality of first grooves and the lower surface of the overcoat layer between the plurality of first grooves may be greater than or equal to the area of the upper surface of the first column spacer.

In addition, the plurality of first grooves may have a shape in which a plurality of vertical rows of squares are arranged in a horizontal direction, a form in which a plurality of vertical rows of regular hexagons are arranged in a horizontal direction, and a plurality of rectangles in a horizontal direction. It may be one of the shapes arranged parallel to the direction.

In addition, the liquid crystal display device may further include a second column spacer spaced apart from the first column spacer.

The overcoat layer may further include a plurality of second grooves corresponding to the second column spacer.

In addition, the liquid crystal display device includes an interlayer insulating layer covering the thin film transistor, a plate-shaped common electrode disposed between the interlayer insulating layer and the passivation layer, and disposed above the passivation layer, corresponding to the common electrode. The pixel electrode may further include a pixel electrode including a plurality of openings exposing the passivation layer, and a black matrix and a color filter layer disposed between the second substrate and the overcoat layer.

Meanwhile, the present invention includes forming a thin film transistor on a first substrate, forming a protective layer on the thin film transistor, and forming a first column spacer on the protective layer corresponding to the thin film transistor. The steps of: forming a first alignment layer on the first column spacer; forming an overcoat layer including a plurality of first grooves corresponding to the first column spacer on a second substrate; A manufacturing method of a liquid crystal display device comprising the steps of forming a second alignment layer on an upper layer and forming a liquid crystal layer between the first and second alignment layers is provided.

The first alignment layer may expose an upper surface of the first column spacer, and the second alignment layer may expose an upper surface of the overcoat layer between the plurality of first grooves.

Also, an area obtained by summing the plurality of first grooves and the upper surface of the overcoat layer between the plurality of first grooves may be greater than or equal to the area of the upper surface of the first column spacer.

In the present invention, by forming the column spacer in the region having the largest step difference, the formation and damage of the alignment layer on the top surface of the column spacer is minimized, and bright spot defects and display quality degradation are prevented.

Further, according to the present invention, by forming a plurality of grooves in the area facing the column spacer, formation and damage of the alignment layer on the lower surface of the area facing the column spacer is minimized, and defects in bright spots and deterioration in display quality are prevented.

1 is a cross-sectional view showing a conventional liquid crystal display device.
2 is a plan view showing an array substrate of a liquid crystal display device according to a first embodiment of the present invention.
3 is a plan view showing a color filter substrate of a liquid crystal display device according to a first embodiment of the present invention.
4 is a cross-sectional view of a liquid crystal display device according to a first embodiment of the present invention.
5 is a plan view showing a plurality of first grooves of a liquid crystal display device according to a second embodiment of the present invention;
6 is a plan view showing a plurality of first grooves of a liquid crystal display device according to a third embodiment of the present invention;

A liquid crystal display device and a manufacturing method thereof according to the present invention will be described with reference to the accompanying drawings.

2 is a plan view showing an array substrate of a liquid crystal display device according to a first embodiment of the present invention, and FIG. 3 is a plan view showing a color filter substrate of a liquid crystal display device according to a first embodiment of the present invention. 4 is a cross-sectional view of the liquid crystal display device according to the first embodiment of the present invention, and is a cross-sectional view taken along the line IV-IV of FIGS. 2 and 3 .

As shown in FIGS. 2, 3 and 4, the liquid crystal display device 110 according to the first embodiment of the present invention includes first and second substrates 120 and 150 facing each other and spaced apart from each other, and A liquid crystal layer 170 formed between the first and second substrates 120 and 150 is included.

A gate line GL and a gate electrode 122 connected to the gate line GL are formed on the inner surface of the first substrate 120, and the first substrate 120 above the gate line GL and the gate electrode 122 A gate insulating layer 124 is formed on the front surface.

A semiconductor layer 126 is formed on the top of the gate insulating layer 124 corresponding to the gate electrode 122, and a source electrode 128 and a drain electrode 130 spaced apart from each other are formed on both ends of the top of the semiconductor layer 126. do.

A data line DL is formed on the gate insulating layer 124 to cross the gate line GL to define the pixel region P, and the source electrode 128 is connected to the data line DL.

Here, the gate electrode 122, the semiconductor layer 126, the source electrode 128, and the drain electrode 130 constitute a thin film transistor (T).

An interlayer insulating layer 132 is formed on the entire surface of the first substrate 120 above the thin film transistor T, and a plate-shaped common electrode 134 is formed in the pixel region P above the interlayer insulating layer 132. is formed

A protective layer 136 is formed on the entire surface of the first substrate 120 above the common electrode 134 , and a pixel electrode 138 is formed on the protective layer 136 .

Here, the interlayer insulating layer 132 and the protective layer 136 include a contact hole exposing the drain electrode 130, the pixel electrode 138 is connected to the drain electrode 130 through the contact hole, and the common electrode (134) includes a plurality of openings exposing the upper protective layer 136.

In addition, first and second column spacers 158 and 160 are formed on the protective layer 136, and the first column spacer 158 is disposed on the protective layer 136 corresponding to the thin film transistor T, , The second column spacer 160 is spaced apart from the first column spacer 158.

A first alignment layer 140 is formed on the first and second column spacers 158 and 160 and the pixel electrode 138 and the protective layer 136 exposed to the outside of the first and second column spacers 158 and 160 . do.

Here, the first alignment layer 140 is selectively formed on the side surfaces of the first and second column spacers 158 and 160, and is not formed on the upper surfaces of the first and second column spacers 158 and 160 or has a minimized thickness. is partially formed to expose the upper surfaces of the first and second column spacers 158 and 160.

The first column spacer 158, also called a gap spacer, serves to maintain a cell gap (ie, the separation distance between the first and second substrates 120 and 150) in a general environment without external pressure, and push The second column spacer 160, also called a push spacer, serves to maintain a cell gap in a special environment where the cell gap is reduced by vibration and external pressure, such as in a manufacturing process or reliability test.

To this end, in a general environment, the top surface s1 of the first column spacer 158 above the first substrate 120 should be located closer to the second substrate 150 than the top surface of the second column spacer 160.

However, since the first column spacer 158 is disposed at a higher position than the second column spacer 160 by the level difference A due to the thin film transistor T, the height B of the first column spacer 158 When formed to be higher than the height of the second column spacer 160, the upper surface s1 of the first column spacer 158 may be disposed closer to the second substrate 150 than the upper surface of the second column spacer 160. there is.

That is, the height of the first column spacer 158 may be greater than or equal to the height of the second column spacer 160 .

Meanwhile, the first column spacer 158 is formed on the top of the thin film transistor T (in particular, directly above the channel region between the source electrode 128 and the drain electrode 130 of the semiconductor layer 126 of the thin film transistor T). Therefore, the height (C) from the protective layer 136 to the top surface (s1) of the first column spacer 158 is the step (A) by the thin film transistor (T) and the height of the first column spacer 158 ( B), it is possible to maximize the height difference between the protective layer 136 and the upper surface s1 of the first column spacer 158, and as a result, the height difference between the upper surface of the first column spacer 158 Formation of the first alignment layer 140 may be prevented or minimized.

Specifically, in the manufacturing process of the array substrate of the liquid crystal display device 110, the thin film transistor T, the common electrode 134, the pixel electrode 138 and the first column spacer 158 are formed on the first substrate 120. After forming, an alignment layer material is coated on the upper portion of the first substrate 120 on which the first column spacer 158 is formed. ), the thickness of the alignment layer material applied decreases from the lower side of the side surface of the first column spacer 158 to the upper side, and then the alignment layer material on the upper surface (s1) of the first column spacer 158 will not remain.

That is, since the alignment layer material has a limited step coverage characteristic, when the first column spacer 158 has a step difference greater than a critical value, the alignment layer material on the upper surface s1 of the first column spacer 158 retention can be prevented.

In the first embodiment of the present invention, the step of the first column spacer 158 is reduced by forming the first column spacer 158 directly above the thin film transistor (T) having the maximum step on the top of the first substrate 120. As a result, the formation of the first alignment layer 140 on the upper surface s1 of the first column spacer 158 can be prevented or minimized.

At this time, the second column spacer 158 has a smaller step than the first column spacer 160, but the step is increased by the drain electrode 130, the common electrode 134, and the pixel electrode 138, so that the second column spacer Formation of the first alignment layer 140 on the upper surface of (158) can also be prevented or minimized.

Therefore, damage to the first alignment layer 140 on the upper surfaces of the first and second column spacers 158 and 160 due to friction is minimized, and bright point defects and display quality degradation of the liquid crystal display device 110 are prevented.

Meanwhile, a black matrix 152 corresponding to the thin film transistor (T) is formed on the inner surface of the second substrate 150, and on the inner surface of the second substrate 150 between the bottom of the black matrix 152 and the black matrix 152, a color A filter layer 154 is formed.

An overcoat layer 156 is formed on the entire surface of the second substrate 150 below the color filter layer 154 , and a second alignment layer 162 is formed below the overcoat layer 156 .

Here, the overcoat layer 156 includes a plurality of first grooves 164 and a plurality of second grooves 166 corresponding to the first and second column spacers 158 and 160, respectively. 164 and the plurality of second grooves 166 may each have a shape in which a plurality of vertical rows of squares are alternately arranged in a horizontal direction.

Also, the second alignment layer 162 is not formed on the lower surface s2 of the overcoat layer 156 between the plurality of first grooves 164 or is formed with a minimized thickness.

Specifically, in the manufacturing process of the color filter substrate of the liquid crystal display device 110 (a process performed with the second substrate 150 turned upside down in FIG. 4), a black matrix 152 is formed on the upper part of the second substrate 150. After forming the color filter layer 154 and the overcoat layer 156, an alignment layer material is applied on the second substrate 150 on which the overcoat layer 156 is formed, and the alignment layer material is applied near the plurality of first grooves 164. Since it flows into the plurality of first grooves 164, the alignment layer material remains on the upper surface of the overcoat layer 156 between the plurality of first grooves 164 (the lower surface s2 of the overcoat layer 156 in FIG. 4). Instead, the alignment layer material remains only on the bottom surface of the plurality of first grooves 164 (upper surface s3 of the plurality of first grooves 164 in FIG. 4 ).

At this time, the plurality of second grooves 166 corresponding to the second column spacer 158 are also formed through the same process as the plurality of first grooves 164, and the second alignment layer 162 has a plurality of second grooves ( 166) is not formed on the lower surface of the overcoat layer 156 or is partially formed with a minimized thickness to expose the lower surface of the overcoat layer 156 between the plurality of second grooves 166.

Therefore, damage to the second alignment layer 162 on the lower surface of the overcoat layer 156 corresponding to the first and second column spacers 158 and 160 due to friction is minimized, and bright point defects and display of the liquid crystal display device 110 are minimized. Deterioration of quality is prevented.

Here, in order to prevent damage to the second alignment layers 140 and 162 due to friction with the upper surfaces of the first and second column spacers 158 and 160, the area occupied by the plurality of first grooves 164 (the number of first grooves 164) The total area of one groove 164 and the lower surface of the overcoat layer therebetween (s2+s3) is greater than or equal to the area of the upper surface s1 of the first column spacer 158, and a plurality of second grooves 166 The area occupied by this may be greater than or equal to the area of the upper surface of the second column spacer 160 .

That is, when the plurality of first grooves 164 form a circular shape or a square shape and the upper surface of the first column spacer 158 is circular or square shape, the second width w2 of the plurality of first grooves 164 is the first It may be greater than or equal to the first width w1 of the upper surface s1 of the column spacer 158 .

For example, the first width w1 may be about 10 μm to about 12 μm, and the second width w2 may be about 15 μm or more.

And, when the depth (d) of the plurality of first grooves 164 is smaller than about 10% of the thickness (t) of the overcoat layer 156, the alignment layer material sufficiently flows into the plurality of first grooves 164. Alignment layer material may remain on the upper surface (s2) of the overcoat layer 156 between the plurality of first grooves 164, and the depth (d) of the plurality of first grooves 164 is the thickness of the overcoat layer 156. When it is greater than about 90% of the thickness t, the lower part of the overcoat layer 156 (the upper part of the overcoat layer 156 in FIG. 4) in the process of forming a plurality of first grooves 164 or the second alignment layer 162 The color filter layer 154 of may be damaged.

Therefore, the depth d of the plurality of first grooves 164 may be about 10% to about 90% of the thickness t of the overcoat layer 156, preferably about 20% to about 80%. there is.

In addition, the area occupied by the plurality of first grooves 164 (the sum of the plurality of first grooves 164 and the lower surface of the overcoat layer 156 therebetween) so that the alignment layer material can sufficiently flow in (s2+ A ratio of the area s3 of the plurality of first grooves 164 to s3 may be 50% or more.

In the first embodiment, the first and second alignment layers 140 and 162 may be formed by rubbing alignment or optical alignment, and in the case of optical alignment, the first and second alignment layers 140 and 162 are decomposable polyimide ( polyimide) type may be used, and polarized ultraviolet (UV) having a wavelength range of about 254 nm to about 300 nm may be used as a light source.

Then, after completing the manufacturing process of the array substrate and the color filter substrate by the alignment of the first and second alignment films 140 and 162, the first and second substrates 120 and 150 are formed by liquid crystal dispensing. The liquid crystal display device 110 is completed by forming the liquid crystal layer 170 on one upper part and bonding the first and second substrates 120 and 150, or by liquid crystal injection method to the first and second substrates ( 120 and 150) are bonded together and a liquid crystal layer is formed between the bonded first and second substrates 120 and 150 to complete the liquid crystal display device 110.

Meanwhile, since the step difference of the second substrate 120 is minimized by the overcoat layer 156 under the second substrate 120, the first and second column spacers 158 and 160 of the first substrate 120 and the second substrate 120 The possibility of friction between the second substrate 120 is minimized, and as a result, damage to the first and second alignment layers 140 and 162 due to friction is further minimized, and bright point defects and display quality deterioration of the liquid crystal display device 110 are minimized. is further prevented.

As described above, in the liquid crystal display device 110 according to the first embodiment of the present invention, the first column spacer 158 is formed on the top of the thin film transistor T having the largest step above the first substrate 120, , By forming a plurality of first grooves 164 corresponding to the first column spacer 158 in the overcoat layer 156 under the second substrate 150, the upper surface of the first column spacer 158 and the first column spacer Formation of the first and second alignment layers 140 and 162 on the lower surface of the overcoat layer 156 corresponding to (158) can be prevented or minimized.

Accordingly, damage to the first and second alignment layers 140 and 162 caused by friction and thus defective bright spots are prevented, and display quality of the liquid crystal display device 110 is improved.

In the first embodiment, a liquid crystal display of a fringe field switching (FFS) mode, which is one of the horizontal electric field type liquid crystal displays, was taken as an example, but in another embodiment, a bar-shaped pixel electrode and a common electrode are The present invention can be applied to an in-plane switching (IPS) mode liquid crystal display, a twisted nematic (TN) mode, or a vertical alignment (VA) mode liquid crystal display.

Meanwhile, in another embodiment, the shapes of the plurality of first grooves and the plurality of second grooves may be changed, which will be described with reference to the drawings.

5 is a plan view showing a plurality of first grooves of a liquid crystal display device according to a second embodiment of the present invention, and FIG. 6 illustrates a plurality of first grooves of a liquid crystal display device according to a third embodiment of the present invention. As a plan view, configurations other than the plurality of first grooves are the same as those of the first embodiment, so description thereof is omitted.

As shown in FIG. 5, the overcoat layer of the second substrate of the liquid crystal display device according to the second embodiment of the present invention includes a plurality of first grooves 264, and the plurality of first grooves 264 include a plurality of first grooves 264. It may be arranged so that the vertical columns of regular hexagons are staggered in the horizontal direction.

Even in this case, the area occupied by the plurality of first grooves 264 (the sum of the plurality of first grooves 264 and the lower surface of the overcoat layer therebetween) may be greater than or equal to the area of the upper surface of the first column spacer. The depth of the plurality of first grooves 264 may be about 10% to about 90% of the thickness of the overcoat layer, and the plurality of first grooves 264 relative to the area occupied by the plurality of first grooves 264 The area ratio of may be 50% or more.

As shown in FIG. 6, the overcoat layer of the second substrate of the liquid crystal display device according to the third embodiment of the present invention includes a plurality of first grooves 364, and the plurality of first grooves 364 include a plurality of first grooves 364. The rectangles of may be arranged in parallel in the horizontal direction.

Even in this case, the area occupied by the plurality of first grooves 364 (the sum of the bottom surfaces of the plurality of first grooves 364 and the overcoat layer therebetween) may be greater than or equal to the area of the upper surface of the first column spacer. The depth of the plurality of first grooves 364 may be about 10% to about 90% of the thickness of the overcoat layer, and the plurality of first grooves 364 relative to the area occupied by the plurality of first grooves 364 The area ratio of may be 50% or more.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the technical spirit and scope of the present invention described in the claims below. You will understand that it can be done.

110: liquid crystal display device 120: first substrate
150: second substrate 170: liquid crystal layer
T: thin film transistor 158: first column spacer
160: second column spacer 140: first alignment layer
164: a plurality of first grooves 166: a plurality of second grooves
162: second alignment layer

Claims (12)

first and second substrates facing each other and spaced apart from each other;
a thin film transistor disposed on an inner surface of the first substrate;
a protective layer disposed over the thin film transistor;
a first column spacer disposed above the passivation layer corresponding to a portion directly above the channel region of the semiconductor layer between the source and drain electrodes of the thin film transistor;
a second column spacer spaced apart from the first column spacer;
a first alignment layer disposed on the protective layer, selectively disposed on a side surface of the first column spacer, and exposing an upper surface of the first column spacer;
an overcoat layer disposed on an inner surface of the second substrate and including a plurality of first grooves corresponding to the first column spacer;
a second alignment layer disposed under the overcoat layer;
A liquid crystal layer disposed between the first and second alignment layers
including,
The first column spacer is disposed at a higher position than the second column spacer by a level difference due to the thin film transistor, the height of the first column spacer is equal to or greater than that of the second column spacer, and the top surface of the first column spacer. Is disposed closer to the second substrate than the upper surface of the second column spacer,
The upper surface of the first column spacer is disposed below the lower surface of the overcoat layer.
According to claim 1,
The second alignment layer exposes a lower surface of the overcoat layer between the plurality of first grooves.
According to claim 1,
An area obtained by summing the plurality of first grooves and the lower surface of the overcoat layer between the plurality of first grooves is greater than or equal to the area of the upper surface of the first column spacer.
According to claim 1,
The plurality of first grooves may have a shape in which a plurality of vertical rows of squares are arranged to cross each other in a horizontal direction, or a form in which a plurality of vertical rows of regular hexagons are arranged to alternate in a horizontal direction, in plan view.
delete According to claim 1,
The overcoat layer further comprises a plurality of second grooves corresponding to the second column spacer.
According to claim 1,
an interlayer insulating layer covering the thin film transistor;
a plate-shaped common electrode disposed between the interlayer insulating layer and the passivation layer;
a pixel electrode disposed on the passivation layer and including a plurality of openings exposing the passivation layer corresponding to the common electrode;
A black matrix and color filter layer disposed between the second substrate and the overcoat layer
A liquid crystal display device further comprising a.
forming a thin film transistor on the first substrate;
forming a protective layer on the thin film transistor;
forming a first column spacer on an upper portion of the passivation layer corresponding to a portion directly above a channel region of a semiconductor layer between a source electrode and a drain electrode of the thin film transistor;
forming a second column spacer spaced apart from the first column spacer;
forming a first alignment layer on the first column spacer, selectively disposed on a side surface of the first column spacer, and exposing an upper surface of the first column spacer;
forming an overcoat layer including a plurality of first grooves corresponding to the first column spacer on an upper portion of a second substrate;
forming a second alignment layer on the overcoat layer;
Forming a liquid crystal layer between the first and second alignment layers
including,
The first column spacer is disposed at a higher position than the second column spacer by a level difference due to the thin film transistor, the height of the first column spacer is equal to or greater than that of the second column spacer, and the top surface of the first column spacer. Is disposed closer to the second substrate than the upper surface of the second column spacer,
The upper surface of the first column spacer is disposed below the upper surface of the overcoat layer.
According to claim 8,
The second alignment layer exposes an upper surface of the overcoat layer between the plurality of first grooves.
According to claim 8,
The method of manufacturing a liquid crystal display device wherein the sum of the plurality of first grooves and the upper surface of the overcoat layer between the plurality of first grooves is greater than or equal to the area of the upper surface of the first column spacer.
According to claim 1,
A thickness of the overcoat layer between the plurality of first grooves and a thickness of the overcoat layer outside the plurality of first grooves are equal to each other.
According to claim 1,
The depth of the plurality of first grooves is 20% to 80% of the thickness of the overcoat layer,
The liquid crystal display device of claim 1 , wherein a ratio of an area of the plurality of first grooves to an area obtained by summing the bottom surface of the overcoat layer between the plurality of first grooves is 50% or more.

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