KR102482006B1 - Display device - Google Patents

Abstract

Embodiments of the present invention relate to a display device, and more particularly, an overcoat layer positioned on a substrate, a common electrode positioned on the overcoat layer in an active area where an image is displayed, and a pixel electrode positioned on the common electrode and a data link line, a data voltage connection pattern, and a common voltage jumping pattern positioned below the overcoat layer in a non-active area, which is an outer area of the active area, and located between the data link line and the data voltage connection pattern, and forming the upper part of the overcoat layer. It includes a first bank made of a material and a second bank positioned between the data voltage connection pattern and the common voltage jumping pattern and made of the material of the overcoat layer. Through this, it is possible to provide a display device capable of simplifying a process.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

Demand for a display device for displaying an image is increasing in accordance with the gradual development of technology, and in recent years, various display devices such as a liquid crystal display device and an organic light emitting display device have been utilized.

These display devices include thin film transistor array substrates.

The thin film transistor array substrate may include an active area displaying an image and a non-active area located outside the active area.

In the active region, a plurality of gate lines and data lines defining a plurality of subpixel regions, thin film transistors disposed at intersections of the gate lines and data lines, a common electrode, and a pixel electrode may be disposed.

A pad portion, which is an area connected to other elements (eg, driving circuits) supplying signals to the plurality of gate lines and data lines disposed in the active area, may be provided in the non-active area.

In order to form such a thin film transistor array substrate, six to seven mask processes (photolithography processes) are usually required.

In particular, electrodes having various functions are disposed on the pad portion. While the types of these electrodes are diverse, the type of material is limited, resulting in a complicated laminated structure.

Therefore, the process of forming the pad portion of the non-active region, the thin film transistor, the common electrode, and the pixel electrode of the active region becomes complicated, and thus, a plurality of mask processes are required, which complicates the panel manufacturing process and takes time to manufacture the panel. There has also been a problem with lengthening.

As described above, since a plurality of mask processes are required to form a thin film transistor array substrate, a method for reducing the number of mask processes is required in terms of productivity, but it is not easy to reduce the number of mask processes due to various constraints. .

On the other hand, when manufacturing a panel through a mask process, some of the components formed by the mask process may have unnecessary protrusions due to errors in the process. Due to these protrusions, damage such as shorting or breaking of electrodes or wires around the protrusions may occur. Due to this, abnormal images may be displayed or problems in which the display itself may not function may occur.

Against this background, an object of embodiments of the present invention is to provide a display device having a structure capable of simplifying a mask process by reducing a mask process.

Another object of the embodiments of the present invention is to provide a display device having a structure capable of improving image quality by preventing disconnection or cracking of electrodes or signal wires.

In one aspect, embodiments of the present invention, a substrate including an active region and a non-active region that is an outer region of the active region, and a data line and a common voltage for transmitting data voltages to pixel electrodes in each subpixel in the active region A common electrode to be applied is disposed.

In the non-active region, a data link line connected to the data line, a data voltage connection pattern connected to the data link line, a data voltage jumping pattern connecting the data link line and the data voltage connection pattern, and a first connected to the common electrode. A common voltage jumping pattern, a common voltage connection pattern connecting the common electrode and the first common voltage jumping pattern, and a second common voltage jumping pattern connected to the first common voltage jumping pattern are disposed.

The data link line and the second common voltage jumping pattern are located on the first layer, the data voltage connection pattern is located on the second layer on the first layer with the first insulating layer interposed therebetween, and the overcoat layer is located on the second layer. And, the common voltage connection pattern may be connected to the common electrode located in the third layer on the overcoat layer.

The data voltage jumping pattern is located on the fourth layer on the third layer with the second insulating layer interposed therebetween, and connects the data link line and data through the first and second contact holes of the second insulating layer and the overcoat layer. It can be connected with the voltage connection pattern. In addition, the first common voltage jumping pattern is located on the fourth layer and is connected to the second common voltage jumping pattern through third contact holes of the second insulating layer and the overcoat layer. It may be connected to a common voltage connection pattern located on the layer.

On the other hand, embodiments of the present invention provide a first pattern on a substrate, a first insulating layer on the first pattern, a second pattern on the first insulating layer, and an overcoat layer on the second pattern. includes

A third pattern located on the overcoat layer, connected to the first pattern through the first contact hole of the overcoat layer and the first insulating layer, and connected to the second pattern through the second contact hole of the overcoat layer; A common electrode located on the overcoat layer is connected to the fourth pattern through a contact hole of the overcoat layer and the fourth pattern located on the same layer as the first pattern and located in the lateral direction of the pattern, and the second pattern and the fourth pattern are connected. and a fifth pattern located on the side of the overcoat layer located therebetween.

The first to fifth patterns may be located outside the image display area.

In another aspect, embodiments of the present invention, an overcoat layer positioned on a substrate, a common electrode positioned on the overcoat layer in an active area where an image is displayed, a pixel electrode positioned on the common electrode, and a pixel electrode positioned on the common electrode and under the overcoat layer , a data link line, a data voltage connection pattern, and a common voltage jumping pattern located in a non-active area outside the active area.

In addition, a first bank positioned between the data link line and the data voltage connection pattern and made of an overcoat layer material, and a second bank positioned between the data voltage connection pattern and the common voltage jumping pattern and made of an overcoat layer material.

In addition, a data voltage jumping pattern electrically connecting the data link line and the data voltage connection pattern is included, and the data voltage jumping pattern electrically connects the data link line and the data voltage connection pattern along the side surface and upper surface of the first bank. can do it

In addition, another common voltage jumping pattern connecting the common electrode on the overcoat layer and the common voltage jumping pattern under the overcoat layer is further included, and the other common voltage jumping pattern extends along the side surface of the second bank to the upper surface of the second bank. can

According to the embodiments of the present invention described above, a display device having a structure capable of simplifying a process by reducing a mask process can be provided.

According to embodiments of the present invention, it is possible to provide a display device having a structure capable of improving image quality by preventing disconnection or cracking of electrodes or signal wires.

1 is a system configuration diagram of a display device according to embodiments of the present invention.
2 is a diagram schematically illustrating a display panel of a display device according to example embodiments.
3 is a plan view illustrating one subpixel disposed in an active area.
FIG. 4A is a plan view of area A of FIG. 2 .
Figure 4b is a cross-sectional view taken along XY of Figure 4a.
FIG. 5 is a plan view of region B of FIG. 4 .
6 is a CD area of 5;
FIG. 7 is a plan view of area E of FIG. 4 .
8 is an FG region of FIG. 7 .
9 is an enlarged view of region H of FIG. 3 .
10 is a cross-sectional view taken along line IJ of FIG. 3 .
11 is a diagram illustrating a conceptual structure of an arrangement relationship of components of a display panel according to embodiments of the present invention.
12 to 19 are views of a manufacturing process of a display device according to embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention may be embodied in other shapes without being limited to the embodiments described below. And in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numbers indicate like elements throughout the specification.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numbers designate like elements throughout the specification. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of explanation.

When an element or layer is referred to as “on” or “on” another element or layer, it includes both cases where another element or layer is intervening as well as directly on another element or layer. do. On the other hand, when an element is referred to as “directly on” or “directly on”, it indicates that no other element or layer is intervening.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc., refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between and other elements or components. Spatially relative terms should be understood as terms that include different orientations of elements in use or operation in addition to the directions shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions both below and above.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term.

1 is a system configuration diagram of a display device according to embodiments of the present invention.

Referring to FIG. 1 , in a display device 100 according to example embodiments, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of data lines DL and a plurality of gate lines GL are disposed. A display panel 110 in which a plurality of subpixels SP defined by a gate line GL are arranged, a data driving circuit 120 driving a plurality of data lines DL, and a plurality of gate lines GL ), and a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

The controller 140 controls the data driving circuit 120 and the gate driving circuit 130 by supplying various control signals DCS and GCS to the data driving circuit 120 and the gate driving circuit 130 .

The controller 140 starts scanning according to the timing implemented in each frame, and converts input image data input from the outside to suit the data signal format used in the data driving circuit 120 to convert the converted image data (Data ), and controls data drive at an appropriate time according to the scan.

The above-described controller 140 includes various types of input image data, including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, a clock signal (CLK), and the like. Receive timing signals from outside (e.g. host system).

The controller 140 converts the input video data input from the outside to suit the data signal format used by the data driving circuit 120 and outputs the converted video data, as well as the data driving circuit 120 and the gate driving circuit. In order to control the 130, the data driving circuit 120 and the gate receive timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal to generate various control signals. output to the drive circuit 130.

For example, in order to control the gate driving circuit 130, the controller 140 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Gate Output Enable) and various gate control signals (GCS: Gate Control Signal) are output.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 130 . The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits and controls shift timing of scan signals (gate pulses). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140, in order to control the data driving circuit 120, a source start pulse (SSP: Source Start Pulse), a source sampling clock (SSC: Source Sampling Clock), a source output enable signal (SOE: Source It outputs various data control signals (DCS: Data Control Signal) including Output Enable) and the like.

Here, the source start pulse SSP controls data sampling start timing of one or more source driver integrated circuits constituting the data driving circuit 120 . The source sampling clock (SSC) is a clock signal that controls sampling timing of data in each source driver integrated circuit. The source output enable signal SOE controls output timing of the data driving circuit 120 .

The controller 140 may be a timing controller used in a typical display technology or a control device that further performs other control functions including a timing controller.

The controller 140 may be implemented as a component separate from the data driving circuit 120, or integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 drives the plurality of data lines DL by receiving the image data Data from the controller 140 and supplying the data voltage Vdata to the plurality of data lines DL. Here, the data driving circuit 120 is also referred to as a source driving circuit.

The data driving circuit 120 may be implemented by including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like.

In some cases, each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC).

Each source driver integrated circuit (SDIC) is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method. , may be directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110 in some cases. In addition, each source driver integrated circuit (SDIC) may be implemented in a Chip On Film (COF) method mounted on a film connected to the display panel 110 .

The gate driving circuit 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 is also referred to as a scan driving circuit.

The gate driving circuit 130 may be implemented by including at least one gate driver integrated circuit (GDIC).

Each gate driving circuit integrated circuit (GDIC) may include a shift register, a level shifter, and the like.

Each gate driver integrated circuit (GDIC) is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or a GIP (Gate In Panel) type , and may be directly disposed on the display panel 110 or may be integrated and disposed on the display panel 110 in some cases. In addition, each gate driver integrated circuit (GDIC) may be implemented in a chip on film (COF) method mounted on a film connected to the display panel 110 .

The gate driving circuit 130 sequentially supplies scan signals of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller 140 .

When a specific gate line is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data DATA received from the controller 140 into an analog data voltage to generate a plurality of data lines DL. supplied with

The data driving circuit 120 may be located on only one side (eg, upper or lower side) of the display panel 110, or in some cases, both sides (eg, upper or lower side) of the display panel 110 depending on a driving method or a panel design method. : upper side and lower side) may be located both.

The gate driving circuit 130 may be located on only one side (eg, the left or right side) of the display panel 110, and in some cases, both sides of the display panel 110 ( Example: left and right) may be located on both sides.

2 is a diagram schematically illustrating a display panel of a display device according to example embodiments.

Referring to FIG. 2 , the display panel 110 of the display device 100 according to embodiments of the present invention includes an active area AA displaying an image and a non-active area positioned outside the active area AA. area (NA).

Meanwhile, in FIG. 2 , a structure in which the non-active area NA surrounds the active area AA is shown as a center, but the present invention is not limited thereto. In the present invention, it is sufficient if the non-active area NA exists outside at least one side of the active area AA.

A plurality of subpixels SP defined by crossing a plurality of gate lines GL and a plurality of data lines DL are arranged in the active area AA.

A data pad unit to which the source driver integrated circuit (SDIC) is connected is located in a part of the non-active area NA. A plurality of data pads DP and a plurality of common voltage pads CP are positioned in the data pad unit.

Each of the plurality of data pads DP is connected to a data link line DLL located in the non-active area NA. Each of the plurality of common voltage pads CP is connected to a common voltage link line CLL located in a non-active region.

Each data link line DLL is connected to the data line DL located in the active area AA, and each common voltage link line CLL is connected to the common electrode COM located in the active area AA. .

The data voltage supplied from the source driver integrated circuit (SDIC) is applied to the data line (DL) via the data pad (DP) and the data link line (DLL). The data line DL transfers the data voltage to the pixel electrode PXL located in the subpixel SP.

Also, the common voltage supplied from the source driver integrated circuit (SDIC) is applied to the common electrode (COM) via the common voltage pad (CP) and the common voltage link line (CLL).

Meanwhile, the plurality of subpixels SP arranged in the active area AA include at least one thin film transistor TR. The thin film transistor TR includes a gate node G, a source node S, and a drain node D.

A source node S of the thin film transistor TR may be electrically connected to the pixel electrode PXL.

Also, a capacitance Cst is formed between the common electrode COM and the pixel electrode PXL so that the display device 100 can be driven.

Meanwhile, in FIG. 2 , the pixel electrode PXL has a plate shape, but the present invention is not limited thereto.

For example, as shown in FIG. 3 , the pixel electrode PXL may have a shape having a plurality of slits.

3 is a plan view illustrating one subpixel disposed in an active area.

Referring to FIG. 3 , the subpixel SP disposed in the active area AA may be defined as an area where the gate line GL and the data line DL intersect.

Each subpixel SP includes at least one thin film transistor TFT. The thin film transistor TFT includes a gate electrode GE, an active layer, a source electrode SE, and a drain electrode DE.

The source electrode SE of the thin film transistor TFT may be electrically connected to the pixel electrode PXL through a contact hole.

Meanwhile, although FIG. 3 shows a configuration in which the source electrode SE of the thin film transistor TFT is electrically connected to the pixel electrode PXL, the present invention is not limited thereto, and the drain electrode DE is connected to the pixel electrode PXL. ) and electrically connected.

The pixel electrode PXL may have a plurality of slits, and the common electrode COM overlapping the pixel electrode PXL may have a plate shape, but the present invention is not limited thereto.

As shown in FIG. 3 , the common electrode COM and the pixel electrode PXL overlap each other, and the display device 100 can be driven by an electric field applied therebetween.

In this structure, a voltage may be applied to the pixel electrode PXL by the data line DL located in the active area AA, and the common electrode COM may be connected to the common line CL located in the active area AA. Voltage can be applied by

Meanwhile, in the display device 100 according to embodiments of the present invention, one subpixel SP may have multiple domains.

Referring to FIG. 3 , the data line DL, the common electrode COM, and the pixel electrode PXL have a bent shape, and the first and second domains D1 and D2 are determined based on the bent areas.

On the other hand, a liquid crystal layer may be interposed between the common electrode COM and the pixel electrode PXL. In this way, the common electrode COM and the pixel electrode PXL are formed in a bent shape, thereby forming a liquid crystal layer according to the alignment direction of the liquid crystal. By offsetting birefringence, a color shift phenomenon can be minimized.

However, the shapes of the data line DL, the common electrode COM, and the pixel electrode PXL of the present invention are not limited thereto.

Next, planar and cross-sectional structures of area A of FIG. 2 , that is, a partial area of the active area AA and a partial area of the non-active area NA of the display panel 110 will be reviewed.

FIG. 4A is a plan view of area A of FIG. 2 , and FIG. 4B is a cross-sectional view taken along line X-Y of FIG. 4A .

Referring to FIGS. 4A and 4B , the display device 100 includes a substrate (SUB, thin film transistor array substrate) having an active area AA and a non-active area NA, which is an area outside the active area AA. include

A thin film transistor TR, a pixel electrode PXL electrically connected to the thin film transistor TR, and a common electrode COM overlapping the pixel electrode PXL are disposed in the active area AA.

A data link line (DLL) connected to the data pad (DP), a data voltage jumping pattern (DJP), and a data voltage connection pattern (DCP) connected to the data pad (DP) are positioned in the non-active area (NA) and connected to the common voltage pad (CP). A first common voltage jumping pattern CJP1 and a second common voltage jumping pattern CJP2 are included.

A specific arrangement relationship of the above-described components is as follows.

In the active area AA, a gate electrode GE is positioned on the substrate 100 . Also, in the non-active area NA, the data link line DLL and the second common voltage jumping pattern CJP2 are positioned on the substrate SUB.

The gate electrode GE, the data link line DLL, and the second common voltage jumping pattern CJP2 may be positioned on the same layer and made of the same material. For example, the gate electrode GE, the data link line DLL, and the second common voltage jumping pattern CJP2 may be formed of a gate material.

A gate insulating layer GI is disposed on the gate electrode GE, the data link line DLL, and the second common voltage jumping pattern CJP2. The gate insulating layer GI is disposed in the active area AA and the non-active area NA. In addition, the gate insulating layer GI includes a first contact hole exposed to the data link line DLL in the non-active region NA, and a second contact hole exposing a portion of the upper surface of the second common voltage jumping pattern CJP2. Provide a contact hole.

In the active area AA, an active layer ACT, and a source electrode SE and a drain electrode DE disposed on the active layer are disposed on the gate insulating layer GI.

In the non-active region NA, a data voltage connection pattern DCP including a first layer made of an active layer (ACT) material and a second layer made of a source-drain material is disposed on the gate insulating layer GI. .

A first insulating layer PAS1 is positioned on the source electrode SE, the drain electrode DE, and the data voltage connection pattern DCP. An overcoat layer OC is disposed on the first insulating layer PAS1. The first insulating layer PAS1 and the overcoat layer OC are disposed in the active area AA and the non-active area NA.

In the non-active area NA, the first insulating layer PAS1 and the overcoat layer OC have a first contact hole CNT1 exposing a part of the upper surface of the data link line DLL, and are connected to a data voltage. A second contact hole CNT2 exposing a part of the upper surface of the pattern DCP is provided, and a third contact hole CNT3 exposing a part of the upper surface of the second common voltage jumping pattern CJP2 is provided.

Also, in the active area AA, the first insulating layer PAS1 and the overcoat layer OC have a fourth contact hole CNT2 exposing a part of the upper surface of the source electrode SE.

Here, the first contact hole CNT1 and the third contact hole CNT3 of the first insulating layer PAS1 and the overcoat layer OC may be located at positions corresponding to the contact hole of the gate insulating layer GI.

In the active area AA, a common electrode COM is disposed on the overcoat layer OC (excluding the fourth contact hole of the overcoat layer). Meanwhile, the common electrode COM may be further positioned in a part of the non-active area NA or at a boundary between the active area AA and the non-active area NA, and in this area, a common voltage is applied. can

In the non-active area NA, the floating pattern FP is disposed on the overcoat layer OC (excluding the first to third contact holes of the overcoat layer).

The common electrode COM and the floating pattern FP may be positioned on the same layer and made of the same material. For example, the common electrode COM and the floating pattern FP may be made of a transparent electrode material.

However, the common electrode COM is electrically connected to other elements (eg, the common voltage pad CP), but the floating pattern FP may be electrically isolated.

A common voltage connection pattern CCP is positioned on the common electrode COM. The common voltage connection pattern CCP may be located in the active area AA, and in addition, a part of the non-active area NA or a boundary between the active area AA and the non-active area NA. can be located

The common voltage connection pattern (CCP) located in the active area (AA) may be electrically isolated, but may be in an electrical isolation state, but in some cases, other components (for example, a component capable of applying a common voltage to the common electrode COM) and may be connected.

The common voltage connection pattern CCP may serve to lower the resistance of the common electrode COM, and may be disposed on a portion of an upper surface of the common electrode COM.

Also, the common voltage connection pattern CCP may be formed of a material different from that of the common electrode COM. For example, it may be made of copper (Cu), but the present invention is not limited thereto, and may be made of a conductive material different from the common electrode (COM) material. For example, any one of aluminum (Al), aluminum alloy (AlNd), gold (Au), silver (Ag), copper alloy, chromium (Cr), and molybdenum (Mo) may be selected.

A second insulating layer PAS2 is disposed on the common voltage connection pattern CCP, the common electrode COM, and the floating pattern FP. The second insulating layer PAS2 is disposed in the active area AA and the non-active area NA.

In the non-active area NA, the second insulating layer PAS2 has a first contact hole CNT1 exposing a part of the upper surface of the data link line DLL, and the upper surface of the data voltage connection pattern DCP. A second contact hole CNT2 exposing a part of the second common voltage jumping pattern CJP2 is provided, and a third contact hole CNT3 exposing a part of the upper surface of the second common voltage jumping pattern CJP2 is provided.

In the active area AA, the second insulating layer PAS2 includes a fourth contact hole CNT2 exposing a part of the top surface of the source electrode SE.

Here, the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 of the second insulating layer PAS2 are the first to fourth contact holes CNT1 of the first insulating layer PAS1 and the overcoat layer OC. , CNT2, CNT3, CNT4) are provided in corresponding positions.

Meanwhile, in the region where the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 are present, the entrance width of the opening of the second insulating layer PAS2 corresponds to the entrance width of the opening of the overcoat layer. Here, the meaning of corresponding means the same or similar. The meaning of being the same or similar may be a concept including a level at which a difference occurs within a tolerance range. In this case, the allowable error range may be approximately 2% to 3%.

In this structure, as shown in FIG. 4B , the overcoat layer OC may be located in all areas except for areas where the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 are present.

In the active area AA, a pixel electrode PXL is disposed on the second insulating layer PAS2. In the active area AA, the pixel electrode PXL may be disposed to overlap with the second insulating layer PAS2 interposed therebetween.

The pixel electrode PXL may be connected to the source electrode DE through the fourth contact hole CNT4 to receive a data voltage.

Also, in the non-active area NA, the data voltage jumping pattern DJP and the first common voltage jumping pattern CJP1 are disposed on the second passivation layer PAS2.

The data voltage jumping pattern DJP is connected to the data link line DLL through the first contact hole CNT1 and the first contact hole of the gate insulating layer GI, and the data voltage through the second contact hole CNT2. It can be connected to the connection pattern (DCP).

Meanwhile, the data voltage jumping pattern DJP connects the data link line DLL and the data voltage connection pattern DCP, and may be disposed along the side surface and upper surface of the overcoat layer OC.

In this case, the data voltage jumping pattern DJP may contact side surfaces of the overcoat layer OC exposed by the first and second contact holes CNT1 and CNT2. That is, the data voltage jumping pattern DJP may directly contact the side surface of the overcoat layer OC without intervening an insulating layer.

Meanwhile, although not shown in FIGS. 4A and 4B, one of the data link line (DLL), the data voltage jumping pattern (DJP), and the data voltage connection pattern (DCP) is connected to the data pad (DP) and is connected to the source driver integrated circuit. A data voltage supplied from (SDIC) may be applied.

For example, a data voltage is applied to the data voltage jumping pattern DJP, and the data voltage jumping pattern DJP has a data line DL located in the active area AA and a drain electrode connected to the data line DL. The data voltage is transferred to DE, and the data voltage may be transferred to the source electrode SE and the pixel electrode PXL connected to the source electrode SE through a channel region of the active layer ACT.

Also, the first common voltage jumping pattern CJP1 may be connected to the second common voltage jumping pattern CJP2 through the third contact hole CNT3 and the second contact hole of the gate insulating layer GI.

Also, the first common voltage jumping pattern CJP1 may be connected to the above-described common voltage connection pattern CCP.

In this case, the first common voltage jumping pattern CJP1 may be positioned on a side surface of the overcoat layer OC. Specifically, in the non-active region NA, the first common voltage jumping pattern CJP1 may contact side surfaces of the overcoat layer OC exposed by the first and second contact holes CNT1 and CNT2. That is, the first common voltage jumping pattern CJP1 may directly contact the side surface of the overcoat layer OC without intervening an insulating layer.

Meanwhile, although not shown in FIGS. 4A and 4B , one of the first common voltage jumping pattern CJP1 and the second common voltage jumping pattern CJP2 is connected to the common voltage pad CP so that a common voltage can be applied. there is.

For example, the common voltage is applied to the first common voltage jumping pattern CJP1, the first common voltage jumping pattern CJP1 transfers the common voltage to the common voltage connection pattern CCP, and the common voltage is It can be delivered to the electrode COM.

As described above, the display device 100 may be driven by applying a signal to the pixel electrode PXL and the common voltage COM.

In summary, in the active area AA, the pixel electrode PXL to which the data voltage is applied and the common electrode COM to which the common voltage is applied are disposed.

In the non-active area NA, a data link line DLL connected to the data line DL, a data voltage connection pattern DCP connected to the data link line DLL, and a data link line DLL and data A data voltage jumping pattern (DJP) connecting the voltage connection pattern (DCP) is positioned.

Further, in the non-active area NA, a first common voltage jumping pattern CJP1 connected to the common electrode COM and a common voltage connecting the common electrode COM and the first common voltage jumping pattern CJP1 are connected. The second common voltage jumping pattern CJP2 connected to the pattern CCP and the first common voltage jumping pattern CJP1 is disposed.

Meanwhile, the data link line DLL and the second common voltage jumping pattern CJP2 are located on the first layer, and the data voltage connection pattern DCP is on the first layer with the gate insulating layer GI interposed therebetween. It is located on the second layer, and the overcoat layer (OC) is located on the second layer.

Also, the common voltage connection pattern CCP is connected to the common electrode COM positioned on the third layer on the overcoat layer OC.

In addition, the data voltage jumping pattern DJP is positioned on a fourth layer on the third layer with the second insulating layer PAS2 interposed therebetween, and the first layer of the second insulating layer PAS2 and the overcoat layer OC. It is connected to the data link line DLL and the data voltage connection pattern DCP through the contact hole CNT1 and the second contact hole CNT2.

In addition, the first common voltage jumping pattern CJP1 is located on the fourth layer where the data voltage jumping pattern DJP is located, and covers the third contact hole CNT3 of the second insulating layer PAS2 and the overcoat layer OC. is connected to the second common voltage jumping pattern CJP2 through and the first common voltage jumping pattern CJP1 is connected to the common voltage connection pattern CCP.

Through this structure, the subpixels (SP) of the display device 100 can be smoothly driven.

As described above, the display device 100 according to embodiments of the present invention has an overcoat layer (OC) positioned between the data link line (DLL) and the data voltage connection pattern (DCP) in the non-active area (NA). ) Or a first bank made of the material of the overcoat layer, and a second bank made of the material of the overcoat layer (OC) or the overcoat layer located between the data voltage connection pattern (DCP) and the common voltage jumping pattern (CJP). do.

Meanwhile, in FIGS. 4A and 4B , area A of FIG. 2 is an example where a data link line (DLL) connected to a source driving circuit is disposed, but the present invention is not limited thereto.

For example, region A of FIG. 2 may be a region in which a gate link line connected to a gate driving circuit is disposed. That is, the overcoat layer OC may be disposed or at least one bank made of an overcoat layer material may be disposed even in the non-active area NA where the gate link line connected to the gate driving circuit is disposed.

In addition, as shown in FIG. 4A, the data link line (DLL), the data voltage connection pattern (DCP), the first common voltage jumping pattern (CJP1), and the common voltage connection pattern (CCP) are in the non-active region ( NA) can be randomly placed.

However, the present invention is not limited thereto, and components such as the data link line (DLL), the data voltage connection pattern (DCP), the first common voltage jumping pattern (CJP1), and the common voltage connection pattern (CCP) are non-active regions. (NA) may be regularly arranged.

The structures of the overcoat layer OC or the first and second banks are reviewed with reference to FIGS. 5 to 8 as follows.

FIG. 5 is a plan view of area B of FIG. 4B , FIG. 6 is area C-D of FIG. 5 , FIG. 7 is a plan view of area E of FIG. 4B , and FIG. 8 is area F-G of FIG. 7 . In the description to be described later, contents (configuration, effect, etc.) overlapping those of the above-described embodiments may be omitted.

5 and 6 , a data link line DLL and a data voltage connection pattern DCP are positioned in the non-active area NA of the display panel 110 . And, the overcoat layer (OC) located on these layers has a first contact hole (CNT1) exposing a part of the upper surface of the data link line (DLL) and exposes a part of the upper surface of the data voltage connection pattern (DCP). and a second contact hole (CNT2) for

Also, a data voltage jumping pattern DJP connected to the data link line DLL and the data voltage connection pattern DCP through the first contact hole CNT1 and the second contact hole CNT2 is positioned.

As shown in FIG. 6, the data voltage jumping pattern (DJP) is data voltage along the side surface and upper surface of the overcoat layer (OC, or first bank) located between the data link line (DLL) and the data voltage connection pattern (DCP). It electrically connects the link line (DLL) and the data voltage connection pattern (DCP).

Referring to FIGS. 7 and 8 , the data voltage jumping pattern DJP and the second common voltage jumping pattern CJP2 are positioned in the non-active area NA of the display panel 110 . In addition, the overcoat layer OC located on these layers has a second contact hole CNT2 exposing a part of the upper surface of the data voltage jumping pattern DJP, and the upper surface of the second common voltage jumping pattern CJP2 A third contact hole CNT3 partially exposed is provided.

Also, the second common voltage jumping pattern CJP2 and the first common voltage jumping pattern CJP1 positioned on the overcoat layer OC may be connected through the third contact hole CNT3.

As shown in FIG. 8 , the first common voltage jumping pattern CJP1 is the overcoat layer (OC or second bank) located between the data voltage connection pattern DCP and the second common voltage jumping pattern CJP2. It may extend to the top surface of the overcoat layer OC positioned along the side surface and the top surface and positioned between the data voltage connection pattern DCP and the second common voltage jumping pattern CJP2.

Meanwhile, in FIGS. 7 and 8 , the invention has been described with a focus on the configuration in which the first and second banks are provided in the non-active area NA, but the present invention is not limited thereto, and the non-active area NA includes one A configuration including the above banks (made of overcoat layer material) is sufficient.

Next, with reference to FIGS. 9 and 10 , the active region of the present invention will be specifically reviewed as follows.

FIG. 9 is an enlarged view of region H of FIG. 3 , and FIG. 10 is a cross-sectional view taken along line I-J of FIG. 3 . In the description to be described later, contents (configuration, effect, etc.) overlapping those of the above-described embodiments may be omitted.

9 and 10 , in the active area AA of the display panel 100, the pixel electrode PXL connected to the thin film transistor TR is positioned, and the pixel electrode PXL and the second insulating layer PAS2 are positioned. A common voltage (COM) arranged to overlap with being placed therebetween is located.

Meanwhile, the pixel electrode PXL is connected to the source electrode SE of the thin film transistor TR through the fourth contact hole CNT4 of the second insulating layer PAS1 and the overcoat layer OC.

As shown in FIG. 9 , in the area where the fourth contact hole CNT4 exists, the width of the entrance of the opening of the second insulating layer PAS2 may correspond to the entrance width of the opening of the overcoat layer OC.

Also, the pixel electrode PXL may directly contact the side surface of the overcoat layer OC without intervening an insulating layer. Here, a side surface of the overcoat layer OC contacted by the pixel electrode PXL may be a side surface exposed by the fourth contact hole CNT4 .

Referring to FIG. 10 , a side surface of the common electrode COM may be surrounded by a second insulating layer PAS2. Through the above structure, in the process of forming the common electrode COM, the common electrode COM acts as a protrusion in the fourth contact hole CNT4 due to a process problem, causing damage to the pixel electrode PXL. can prevent

Next, with reference to FIG. 11 , a conceptual structure of a disposition relationship of components of a display panel according to exemplary embodiments of the present invention will be reviewed.

FIG. 11 is a diagram illustrating a conceptual structure of an arrangement relationship of components of a display panel according to embodiments of the present invention.

Referring to FIG. 11 , a display panel 110 of a display device 100 according to example embodiments includes a first pattern P1 positioned on a substrate SUB. And, the first insulating layer (D1) on the first pattern (P1), the second pattern (D2) located on the first insulating layer (D1), and also the overcoat layer located on the second pattern (D2) (OC).

And, it is located on the overcoat layer (OC) and is connected to the first pattern (P1) through the first contact hole (CNT1) of the overcoat layer (OC) and the first insulating layer (D1), and the first pattern (P1) of the overcoat layer (OC). It includes a third pattern P3 connected to the second pattern P2 through two contact holes CNT2, is positioned in a lateral direction with the second pattern P2, and is positioned on the same layer as the first pattern P1. It includes a fourth pattern (P4) to do.

In addition, the common electrode COM located on the overcoat layer OC and the fourth pattern C4 are connected through the third contact hole CNT3 of the overcoat layer OC, and the second pattern P2 and the above A fifth pattern P5 positioned on the side of the overcoat layer OC positioned between the fourth patterns P4 is included.

Here, the first pattern P1 and the fourth pattern P4 may be located on the same layer. Also, the third pattern P3 and the fifth pattern P5 may be located on the same layer and may be located on a layer higher than the layer where the first and fourth patterns P1 and P4 are located. The second pattern P2 may be disposed on a layer positioned between a layer on which the first and fourth patterns P1 and P4 are positioned and a layer on which the third and fifth patterns P3 and P5 are positioned.

As such, the display panel 110 of the display device 100 according to embodiments of the present invention is located on the overcoat layer OC in the non-active area NA and electrically connects the respective patterns to the third and fourth layers. Since the fifth patterns P3 and P5 are included, each component can be easily electrically connected without disconnection.

The display device 100 according to the embodiments of the present invention has an effect of being easy to process, and this effect is reviewed with reference to FIGS. 12 to 19 as follows.

12 to 19 are views of a manufacturing process of a display device according to embodiments of the present invention. In the description to be described later, contents (configuration, effect, etc.) overlapping those of the above-described embodiments may be omitted.

First, referring to FIG. 12 , a gate electrode material is formed on the substrate SUB. Then, the gate electrode GE, the data link line DLL, and the second common voltage jumping pattern CJP2 are formed through an exposure process using the first mask MASK #1. At this time, the gate electrode GE is formed in the active area AA of the display panel 110, and the data link line DLL and the second common voltage jumping pattern CJP2 are formed in the non-active area NA. .

Through this process, the gate electrode GE, the data link line DLL, and the second common voltage jumping pattern CJP2 may be formed of the same material on the same layer.

A gate insulating layer material GIM is formed on the gate electrode GE, the data link line DLL, and the second common voltage jumping pattern CJP2.

An active material and a source-drain material are sequentially stacked on the gate insulating layer material (GIM). Thereafter, the active material and the source-drain material are simultaneously patterned through an exposure process using the second mask (MASK #2). Through this process, as shown in FIG. 12, the active layer ACT, the source electrode SE, and the drain electrode DE are formed in the active area AA, and the data voltage jumping pattern is formed in the non-active area NA. (DCP) is formed.

Thereafter, the first insulating layer material PAS1M, the overcoat layer material OCM, and the common electrode material ( COMM) and common voltage connection pattern material (CCPM) are sequentially formed. Then, a photoresist PR is formed on the common voltage connection pattern material CCPM.

And, as shown in FIG. 13, the photoresist PR is patterned using the third mask MASK #3. In this case, the third mask MASK #3 may include a transmission part 1301 , a semi-transmission part 1302 and a blocking part 1303 .

The transmissive portion 1301 of the third mask MASK #3 is an area that transmits light, the semi-transmissive portion 1302 is an area that transmits only a part of light, and the blocking portion 1303 is an area that does not transmit light.

As shown in FIG. 13, the photoresist PR located in the region corresponding to the transmissive portion 1301 of the third mask (MASK #3) may be dissolved after development, and the semi-transmissive portion 1302 and In the photoresist PR located in the corresponding region, only a portion of the photoresist PR may remain after development, and the photoresist PR located in the region corresponding to the blocking portion 1303 remains as it is after development.

In the above description, the configuration of the photoresist PR is a positive photoresist, but the present invention is not limited thereto, and a negative photoresist may be used. In this case, the transmission portion 1301 of the third mask MASK #3 becomes a blocking portion, and the blocking portion 1303 may be changed to a transmission portion.

After that, as shown in FIG. 14 , the common voltage connection pattern material CCPM is patterned using the photoresist PR as a mask. At this time, the common voltage connection pattern material CCPM located in the region corresponding to the region without the photoresist PR is etched.

In addition, referring to FIG. 14 , in this process, the photoresist PR positioned at a position corresponding to the transflective portion 1302 of the third mask MASK #3 may also be etched, and the third mask MASK #3 may be etched. The photoresist (PR) positioned at a position corresponding to the blocking portion 1303 of ) may also be partially etched, so that the height thereof may be lowered compared to that before etching.

Therefore, only the common voltage connection pattern material (CCPM) in the region corresponding to the transmission portion 1301 of the third mask MASK #3 is etched away, and the semi-transmission portion 1302 and the blocking portion of the third mask MASK #3 are etched away. The common voltage connection pattern material (CCPM) of the region located in the region corresponding to 1303 may remain.

And, as shown in FIGS. 14 and 15 , the common electrode material COMM may be etched using the common voltage connection pattern material CCPM as a mask. At this time, the common electrode material (COMM) of the region located in the region corresponding to the transflective portion 1302 and the blocking portion 1303 of the third mask MASK #3 may remain.

At this time, only the common voltage connection pattern material (CCPM) material located in the region corresponding to the region where the photoresist (PR) remains remains, and the remaining region may be etched along with the common electrode material (COMM).

As shown in FIG. 16, the common voltage connection pattern material (CCPM) remaining in this process becomes the common voltage connection pattern (CCP), and the common electrode material (COMM) remaining in the active area AA is the common electrode ( COM), and the common electrode material COMM remaining in the non-active region NA becomes a floating pattern FP.

Then, a second insulating layer material PAS2M is formed on the substrate SUB on which the common voltage connection pattern CCP, common electrode COM, and floating pattern FP are formed.

And, as shown in FIG. 17, the second insulating layer material PAS2M, the overcoat layer material OCM, and the first insulating layer material PAS1M are formed through an ashing process using a fourth mask MASK #4. ) and the gate insulating layer material (GIM) are simultaneously etched.

Through this process, the gate insulating layer GI, the first insulating layer PAS1, the overcoat layer OC, and the second insulating layer PAS2 may be formed.

In addition, through this process, referring to FIG. 17 , the gate insulating layer GI may form a contact hole exposing a part of the upper surface of the data link line DLL and the second common voltage jumping pattern CJP2. In the first insulating layer PAS1, the overcoat layer OC, and the second insulating layer PAS2, a data link line DLL, a data voltage connection pattern DCP, a second common voltage jumping pattern CJP2, and a source First to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 exposing portions of the upper surface of the electrode SE may be formed.

In this case, the second insulating layer PAS2 may be etched in a form in which side surfaces of the common electrode COM and the floating pattern FP are not exposed. That is, a side surface of the common electrode COM may be surrounded by the second insulating layer PAS2. In this way, since the gate insulating layer GI, the first insulating layer PAS1, the overcoat layer OC, and the second insulating layer PAS2 are formed using one mask, the process can be simplified.

Also, since the second insulating layer PAS2 and the overcoat layer OC are etched in the same process, the entrances of the openings of the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 of the second insulating layer PAS2 are etched. The width may correspond to the entrance width of openings of the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 of the overcoat layer OC.

Also, in this process, the second insulating layer PAS2 may be formed to expose a part of the upper surface of the common voltage connection pattern CCP. In this case, the common voltage connection pattern CCP with a part of the upper surface exposed may be the common voltage connection pattern CCP to be connected to the second common voltage jumping pattern CJP2. That is, the second insulating layer PAS2 may be formed to cover an upper surface of the common voltage connection pattern CCP that is not connected to the second common voltage jumping pattern CJP2.

After that, as shown in FIG. 18 , a pixel electrode material PXLM may be formed on the substrate SUB on which the second insulating layer PAS2 is formed.

At this time, the pixel electrode material PXLM exposes the data link line DLL, the data voltage connection pattern DCP, the second common voltage jumping pattern CJP2, the common voltage connection pattern CCP, and the source electrode PXL. The side surface of the overcoat layer OC, the side surface of the second insulating layer PAS2 and the second insulating layer are formed to contact the upper surface and are exposed by the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 . It may be formed to contact the upper surface of the layer PAS2.

And, as shown in FIG. 19 , the pixel electrode material PXLM may be patterned through exposure fixation using the fifth mask MASK #5.

The patterned pixel electrode material PXLM becomes the pixel electrode PXL in the active area AA. At this time, the pixel electrode PXL may contact the exposed upper surface of the source electrode SE and may contact the side surface of the overcoat layer OC exposed through the fourth contact hole CNT4. Also, the pixel electrode PXL may overlap the common electrode COM with the second insulating layer PAS2 interposed therebetween.

Also, the patterned pixel electrode material PXLM becomes the data voltage jumping pattern DJP and the first common voltage jumping pattern CJP1 in the non-active region NA, respectively.

The data voltage jumping pattern DJP is in contact with the exposed upper surfaces of the data link line DLL and the data voltage connection pattern DCP, respectively, and the overcoat layer OC exposed by the first and second contact holes CNT1 and CNT2. ) is formed to be in contact with the side of the

In addition, the first common voltage jumping pattern CJP1 contacts the exposed top surfaces of the second common voltage jumping pattern CJP2 and the common voltage connection pattern CCP, respectively, and is an overcoat layer exposed by the third contact hole CNT3. It is formed to contact the side of (OC).

Meanwhile, as described above, the entrance widths of the openings of the first to fourth contact holes CNT1 , CNT2 , CNT3 , and CNT4 of the second insulating layer PAS2 and the overcoat layer OC correspond to each other, and the second insulating layer OC The side surface of the layer PAS2 is formed to surround the side surface of the common electrode COM and the floating pattern FP, so that the pixel electrode PXL, the data voltage jumping pattern DJP, and the first common voltage jumping pattern CJP1 are formed. Disconnection due to other configurations may not occur.

Specifically, the pixel electrode PXL, the data voltage jumping pattern DJP, and the first common voltage jumping pattern CJP1 are formed along the side surfaces of the overcoat layer OC and the second insulating layer PAS2, and the second insulating layer PAS2 ) has a structure extending to the upper surface of the

However, when the boundary between the top and side surfaces of the second insulating layer PAS2 where the data voltage jumping pattern DJP and the first common voltage jumping pattern CJP1 are located has a protruding shape, the pixel electrode PXL, the data voltage A disconnection may occur between the jumping pattern DJP and the first common voltage jumping pattern CJP1.

On the other hand, according to the above-described manufacturing process, in the display device 100 according to embodiments of the present invention, disconnection does not occur in the data voltage jumping pattern DJP and the first common voltage jumping pattern CJP1 and the second insulation A structure that can be located at the boundary between the upper surface and the side surface of the layer PAS2 may be provided.

Meanwhile, the common electrode COM may receive a DC common voltage Vcom for forming an electric field with the pixel electrode PXL for display driving. Depending on circumstances, as another example, the common electrode COM may be applied with the common voltage Vcom in the form of a modulation signal having a variable voltage level. As another example, the common electrode COM may receive the common voltage Vcom of DC voltage during the first period, and may receive a signal in the form of a modulation signal having a variable voltage level during the second period.

According to the embodiments of the present invention described above, the substrate SUB may be formed through five mask processes. Accordingly, it is possible to provide a display device having a structure capable of simplifying the process by reducing the mask process.

In addition, another object of the embodiments of the present invention is to simplify the process through the reduction of the mask process, prevent unnecessary protruding parts from being formed, and prevent disconnection or cracks of electrodes or signal wires, and through this, image It is to provide a display device having a structure capable of improving quality.

The above description and accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art can combine the configuration within the scope not departing from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible.

Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driving circuit
130: gate driving circuit
140: controller

Claims (16)

a substrate including an active area and a non-active area that is an outer area of the active area;
In the active area, a data line for transmitting a data voltage to a pixel electrode in each subpixel and a common electrode to which a common voltage is applied are disposed;
In the non-active region, a data link line connected to the data line, a data voltage connection pattern connected to the data link line, a data voltage jumping pattern connecting the data link line and the data voltage connection pattern, A first common voltage jumping pattern connected to a common electrode, a common voltage connection pattern connecting the common electrode and the first common voltage jumping pattern, and a second common voltage jumping pattern connected to the first common voltage jumping pattern are disposed. ,
The data link line and the second common voltage jumping pattern are located on a first layer;
The data voltage connection pattern is located on a second layer on the first layer with a first insulating layer interposed therebetween;
An overcoat layer is located on the second layer,
The common voltage connection pattern is connected to the common electrode located in a third layer on the overcoat layer,
The data voltage jumping pattern is located on a fourth layer on the third layer with a second insulating layer interposed therebetween, and passes through first and second contact holes of the second insulating layer and the overcoat layer. It is connected to a data link line and the data voltage connection pattern,
the first common voltage jumping pattern is located on the fourth layer and is connected to the second common voltage jumping pattern through third contact holes of the second insulating layer and the overcoat layer;
The first common voltage jumping pattern is connected to the common voltage connection pattern located on the third layer.
According to claim 1,
the first layer is composed of a gate material;
the second layer is composed of a source-drain material;
The third layer and the fourth layer are formed of a transparent electrode material.
According to claim 1,
The common electrode and the first common voltage jumping pattern are made of the same material,
The common voltage connection pattern is formed of a material different from that of the common electrode and the first common voltage jumping pattern.
According to claim 1,
In the region where the first to third contact holes are located,
A width of the entrance of the opening of the second insulating layer corresponds to a width of the entrance of the opening of the overcoat layer.
According to claim 1,
Each of the data voltage jumping pattern and the first common voltage jumping pattern contacts a side surface of the overcoat layer.
According to claim 1,
The data voltage jumping pattern,
Connecting the data link line located on the first layer and the data voltage connection pattern located on the second layer,
A display device disposed along side surfaces and top surfaces of the overcoat layer positioned on the second layer.
According to claim 6,
The display device of claim 1 , wherein a material constituting the third layer is positioned in a floating pattern between an upper surface of the overcoat layer and the data voltage jumping pattern.
According to claim 1,
In the active area,
Further comprising a pixel electrode positioned on a fourth layer on the third layer with the second insulating layer interposed therebetween,
the pixel electrode is connected to a thin film transistor under the overcoat layer of the active region through a fourth contact hole of the second insulating layer and the overcoat layer;
The pixel electrode is in contact with the side surface of the overcoat layer.
According to claim 8,
In the area where the fourth contact hole is located,
A width of the entrance of the opening of the second insulating layer corresponds to a width of the entrance of the opening of the overcoat layer.
According to claim 1,
A side surface of the common electrode is surrounded by the second insulating layer.
Board;
a first pattern positioned on the substrate;
a first insulating layer on the first pattern;
a second pattern positioned on the first insulating layer;
an overcoat layer positioned on the second pattern;
A third layer disposed on the overcoat layer, connected to the first pattern through a first contact hole of the overcoat layer and the first insulating layer, and connected to the second pattern through a second contact hole of the overcoat layer. pattern;
a fourth pattern positioned in a lateral direction with the second pattern and positioned on the same layer as the first pattern; and
A fifth pattern positioned on a side surface of the overcoat layer positioned between the second pattern and the fourth pattern and connecting a common electrode positioned on the overcoat layer and the fourth pattern through a contact hole of the overcoat layer. A display device including a.
According to claim 11,
The first to fifth patterns are positioned outside the image display area.
Board;
an overcoat layer positioned on the substrate;
On the overcoat layer, a common electrode located in an active area where an image is displayed, and a pixel electrode located on the common electrode;
a data link line, a data voltage connection pattern, and a common voltage jumping pattern located in a non-active region, which is an outer region of the active region, under the overcoat layer; and
A first bank positioned between the data link line and the data voltage connection pattern and made of the material of the overcoat layer. display device.
According to claim 13,
and a second bank positioned between the data voltage connection pattern and the common voltage jumping pattern and made of a material of the overcoat layer.
According to claim 13,
Further comprising a data voltage jumping pattern electrically connecting the data link line and the data voltage connection pattern,
The data voltage jumping pattern electrically connects the data link line and the data voltage connection pattern along side surfaces and top surfaces of the first bank.
According to claim 14,
Further comprising another common voltage jumping pattern connecting the common electrode on the overcoat layer and the common voltage jumping pattern under the overcoat layer;
The display device of claim 1 , wherein the other common voltage jumping pattern extends along a side surface of the second bank to an upper surface of the second bank.

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