KR102478938B1 - Method and memory device having shared delay circuit - Google Patents

Abstract

A memory device includes a plurality of memory banks and a sense delay circuit. Each memory bank is activated by a row activation command and is configured to perform a sensing operation based on a sensing enable signal. A sense delay circuit including a shared delay circuit and a delay path control circuit may delay the start of a sense enable signal by a sense delay period from execution of a row enable command. A shared delay circuit is shared across memory banks and can generate a plurality of delay signals based on execution of a row active command. The delay path control circuit may control an electrical path between the shared delay circuit and the memory bank based on the row active command and the plurality of delay signals to output a sense enable signal to the memory bank.

Description

METHOD AND MEMORY DEVICE HAVING SHARED DELAY CIRCUIT with shared delay circuit

The present disclosure relates to a memory device, and more particularly to a method and memory device having a shared delay circuit.

A memory device, such as a dynamic random-access memory (DRAM) device, may include multiple memory banks. In memory operation, a sense amplifier is started after sensing a quantity from the assertion of a row active command to perform a sense operation on a memory bank. It is desirable to have the same delay amount for all memory banks included in the memory device.
However, due to inconsistencies in electronic components (e.g., transistors, resistors, bias level noise, etc.) during the manufacturing process, the amount of delay from the execution of the row active command to the start of the sense amplifiers for different memory banks is different. A delay amount difference between memory banks may increase an error rate of a memory operation (eg, a read operation or a write operation), thereby degrading the performance of the memory device.
Recently, as demand for high-quality memory devices increases, creative technologies and designs for improving the performance of memory devices are required.

The present disclosure introduces a method and a memory device capable of improving performance of a memory device.
In one embodiment of the present disclosure, a memory device includes a plurality of memory banks and a sensing delay circuit. Each of the plurality of memory banks is activated by a row active command, and each of the plurality of memory banks is configured to perform a sensing operation based on a sensing enable signal. The sense delay circuit is configured to delay a start of the sense enable signal from assertion of the row enable command by a sense delay period. The sense delay circuit includes a shared delay circuit and delay path control circuitry. A shared delay circuit is configured to generate a plurality of delay signals based on execution of a row active instruction, wherein the shared delay circuit is shared for a plurality of memory banks. A delay path control circuitry is coupled to the shared delay circuit and includes the shared delay circuit and the plurality of memory banks based on the row active command and the plurality of delay signals to output a sense enable signal to the memory bank. It is configured to control the electrical path between them.
In one embodiment of the present disclosure, a method applied to a memory device including a plurality of memory banks and a sense delay circuit. The method includes receiving a row active command configured to activate a memory bank of a plurality of memory banks, and starting a sense enable signal by a sense delay period from execution of the row active command by a sense delay circuit. It includes the operation of the step of delaying. The operation of delaying the start of the sense enable signal by the sense delay period from the execution of the row active command generates a plurality of delay signals based on the execution of the row active command by a shared delay circuit of the sense delay circuit - A shared delay circuit is shared for a plurality of memory banks; and controlling an electrical path between the shared delay circuit and the plurality of memory banks and the plurality of delay signals to output sense enable signals to the memory banks based on the row activation command.
In order to facilitate a better understanding of the above features and advantages provided in one or more embodiments of the present disclosure, several embodiments are described in detail as follows, accompanying drawings.

The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles described herein.
1 is a schematic diagram illustrating a memory device in accordance with some embodiments.
2 is a schematic diagram illustrating a sense delay circuit of a memory device in accordance with some embodiments.
3 is a schematic diagram illustrating a delay path control circuit of a memory device in accordance with some embodiments.
4 and 5 are waveform diagrams illustrating signals of a memory device according to some embodiments.
6A-6B show a flow diagram of a method of a memory device in accordance with some embodiments.

Reference will now be made in detail to preferred embodiments of the present invention, examples of which are shown in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts.
Referring to FIG. 1 , a memory device 100 includes a delay sensing circuit 110 and a plurality of memory banks (B0 to Bm) connected to the delay sensing circuit 110. , where m is a positive integer. Each of the memory banks B0 to Bm may include a memory array (ARR) and a sense amplifier (SA). The memory array ARR includes a plurality of memory cells (not shown) connected to a plurality of bit lines and word lines; The sense amplifier SA is configured to perform a sensing operation on memory cells of the memory array ARR based on the sense enable signal. A memory operation such as a read operation or a write operation on a memory cell may be performed through a bit line and a word line connected to the memory cells of the memory array ARR. In some embodiments, sensing enable signals SE_B0 to SE_Bm for enabling sense amplifiers of each memory bank B0 to Bm are received from the sensing delay circuit 110 . In some embodiments, memory operations may be performed independently in memory banks B0 through Bm. For example, a read operation may be performed on the memory bank B0 and a write operation may be performed on the memory bank B1. In some embodiments, the memory cells of an ARR array are Dynamic Random-Access Memory (DRAM) cells, although the present disclosure is not limited thereto.
In some embodiments, a row active command is used to open a row in a particular memory bank before starting the sense amplifier (SA) to perform a memory operation, such as a read operation or a write operation to that particular memory bank. It is asserted. When a row activation command is executed, cell data of a particular memory bank is transferred to the bit line connected to the sense amplifier SA through charge sharing between the memory cell and the bit line. After a sensing delay period in execution of the row enable command, the sense amplifier (SA) is enabled by the sense enable signal to sense and amplify the data on the bit line. If the sense amplifier 130 is started too early, the cell data will not be completely transferred to the sense amplifier 130. If the sense amplifier 130 is started too late, the sense amplifier 130 will not have enough time to fully amplify the cell data for the memory operation. Therefore, the sensing delay period must be accurate for proper operation of the memory device 100 . In addition, the same sensing delay period is required for all memory banks of the memory device 100 to improve performance of the memory device 100 .
In some embodiments, the sense delay circuit 110 is configured to receive row active commands (ATV_B0 through ATV_Bm) and pre-charge signals (PCG_B0 through PCG_Bm), and the sense delay period for the memory banks (B0 through Bm) is substantially to output the detection enable signals (SE_B0 to SE_Bm) for the same memory banks (B0 to Bm). The sense delay period for a particular memory bank is from the execution of the row active command for that particular memory bank to the start of the sense amplifier (SA) of that particular memory bank.
In some embodiments, sensing delay circuit 110 includes shared delay circuit 112 and delay path control circuitry 114 . Shared delay circuit 112 is shared for all memory banks B0 through Bm and is configured to delay the start of sense amplifier SA by a sense delay period from execution of a row active command. The shared delay circuit 112 may receive a row activation command for a specific memory bank among the memory banks B0 to Bm and generate at least one delay signal based on the row activation command. At least one delay signal generated by shared delay circuit 112 is provided to delay path control circuit 114 . Delay path control circuit 114 is configured to control an electrical path between shared delay circuit 112 and memory banks B1 to Bm. In some embodiments, delay path control circuit 114 may selectively enable or disable an electrical path between shared delay circuit 112 and memory banks B0 through Bm, thereby achieving a desired sense delay period. A sense enable signal having is provided to the memory banks B0 to Bm. In some embodiments, both shared delay circuit 112 and delay path control circuit 114 are shared for all memory banks B0 through Bm.
In some embodiments, the sense amplifiers SA of the memory banks B0 to Bm operate according to the sense enable signals SE_B0 to SE_Bm, respectively. For example, when the sense enable signal is in a first logic state (eg, logic state 1), the sense amplifier SA is activated, and the sense enable signal is in a second logic state (eg, logic state 0). In case of , the sense amplifier (SA) is deactivated. . The start of the sense amplifier SA refers to the timing at which the logic state of the sense enable signal is changed from the second logic state to the first logic state. The present disclosure is not limited to the specific structure or design of the sense amplifier (SA). In some embodiments, memory device 100 includes additional circuit controllers (not shown), row decoders (not shown), column decoders (not shown), read and write circuits (not shown), input/output circuits (not shown). time) or other circuitry necessary for proper operation of the memory device 100 .
2 shows a schematic diagram of a sense delay circuit 210 in accordance with some embodiments. In some embodiments, the sense delay circuit 210 of FIG. 2 is the sense delay circuit 110 shown in FIG. The sense delay circuit 210 includes a shared delay circuit 212 and a delay path control circuit 214, a plurality of latches L0 to Lm and logic circuits 211, 213 and X0 to Xm. can include The logic circuit 211 may receive a plurality of row activation commands ATV_B0 to ATV_Bm for activating the memory banks B0 to Bm, respectively. Logic circuit 211 is configured to perform logic operations on row active commands ATV_B0 through ATV_Bm to generate signal 2111 . Signal 2111 may indicate whether at least one of the row active commands ATV_B0 through ATV_Bm are executed. For example, signal 2111 can have a first logic state (eg, logic state 0) when at least one of the row active commands ATV_B0 through ATV_Bm is executed, and signal 2111 can have a row active command ( A second logical state (eg, logical state 1) when none of ATV_B0 to ATV_Bm) is executed. In some embodiments, logic circuit 211 is a NOR logic circuit configured to perform a NOR logic operation on row active commands ATV_B0 through ATV_Bm to generate signal 2111 .
In some embodiments, logic circuit 213 is coupled to logic circuit 211 to receive signal 2111 and to signal 2111 to generate signal 2131 and output to shared delay circuit 212. It is configured to perform logical operations. Logic circuit 213 may be a NOT logic circuit configured to invert signal 2111 to produce signal 2131 . In some embodiments, signal 2111 output by logic circuit 211 is output directly to shared delay circuit 212 without passing through logic circuit 213 .
In some embodiments, shared delay circuit 212 includes a plurality of delay units 212_0 through 212_n-1 connected in series to form a delay chain, where n is a positive integer. to be. The number of n may be determined according to the specifications of each delay unit 212_0 to 212_n-1 and the length of a desired sensing delay period. Shared delay circuit 212 is configured to delay the start of sense enable signals SE_B0 through SE_Bm from execution of row enable commands ATV_B0 through ATV_Bm by a sense delay period. In some embodiments, shared delay circuit 212 is shared for all memory banks B0 through Bm; The sensing delay periods for the sensing enable signals SE_B0 to SE_Bm are substantially the same. For example, the detection delay period between the execution of the row activation command (ATV_B0) and the start of the detection enable signal (SE_B0) is the detection delay period between the execution of the row activation command (ATV_Bm) and the start of the detection enable signal (SE_Bm). is substantially the same as
In some embodiments, each of the delay units 212_0 to 212_n-1 includes an input terminal (IN) and an output terminal (OUT), and delays a signal of the input terminal (IN) by a delay period to output an output terminal (OUT). ) is configured to generate a signal at For example, the delay unit 212_0 is configured to delay the signal 2131 by the delay period to generate the delay signal Timing_D1; the delay unit 212_1 is configured to delay the signal Timing_D1 by the delay period to generate the delay signal Timing_D2; and the delay unit 212_n-1 is configured to delay a signal input to the delay unit 212_n-1 to generate a delay signal Timing_Dn. Since the delay units 212_0 to 212_n-1 are connected in series, the delay amount of the delay signal Timing_Dn from execution of the row activation command is equal to the sum of the delay periods of all the delay units 212_0 to 212_n-1. is determined according to In some embodiments, the sense delay period between the execution of the row active command and the start of each corresponding sense enable signal SE_B0 through SE_Bm depends on the sum of the delay periods from all delay units 212_0 through 212_n-1. It is decided.
In some embodiments, delay path control circuit 214 is configured to control an electrical path between shared delay circuit 212 and memory banks B0 through Bm. In some embodiments, delay path control circuit 214 activates an electrical path from shared delay circuit 212 to a target memory bank and deactivates an electrical path from shared delay circuit 212 to another memory bank. can do. In some embodiments, delay path control circuit 214 includes a plurality of delay path control circuits 214_0_0 through 214_m_n-1, where m and n are positive integers. The delay path control circuit 214 may selectively activate and deactivate the delay path control circuits 214_0_0 to 214_m_n-1 to control an electrical path between the shared delay circuit 212 and the memory banks B0 to Bm. .
In some embodiments, each of the delay path control circuits 214_0_0 to 214_m_n-1 includes a plurality of input terminals and an output terminal DLY_OUT. The input terminals include an enable input terminal (EN) configured to receive one of the row active commands (ATV_B0 to ATV_Bm), an input terminal (DIS0 to DISm) configured to receive another of the row active commands (ATV_B0 to ATV_Bm), and a share A delay input terminal DLY_IN configured to receive one of the delay signals Timing_D1 to Timing_Dn from the delay circuit 212 may be included. Each of the delay path control circuits 214_0_0 to 214_m_n-1 is enabled or disabled through one of the row activation commands ATV_B0 to ATV_Bm input to the enable input terminal EN. When a specific delay path control circuit among the delay path control circuits 214_0_0 to 214_m_n-1 is activated, a delay signal input to the delay input terminal DLY_IN is output to the output terminal DLY_OUT of the specific delay path control circuit.
In some embodiments, the delay path control circuits 214_0_0 to 214_m_n-1 are divided into a plurality of groups of delay path control circuits, each group having a memory bank B0 to Bm). For example, delay path control circuit groups 214_0_0 to 214_0_n-1 correspond to memory bank B0 and are configured to activate or deactivate an electrical path to memory bank B0; and a group of delay path control circuits 214_m_0 to 214_m_n-1 correspond to a memory bank Bm and are configured to activate or deactivate an electrical path to the memory bank Bm. In some embodiments, a group of delay path control circuits corresponding to the target memory bank are activated and other groups are inactive. For example, when the row enable command ATV_B0 is executed to the sense delay circuit 210, groups of delay path control circuits 214_0_0 to 214_0_n-1 are sequentially activated to generate the sense enable signal SE_B0 and Another group of delay path control circuitry is deactivated. When the row enable command ATV_B0 is executed to the enable input terminal EN of the delay path control circuit 214_0_0, the row enable command ATV_B0 first activates the delay path control circuit 214_0_0 and then the delay path control circuit The output terminal DLY_OUT of 214_0_0 activates the delay path control circuit 214_0_1. Similarly, the delay path control circuits 214_0_2 to 214_0_n-1 are sequentially enabled to generate the sense enable signal SE_B0. In other words, the electrical path between the shared delay circuit 212 and the memory bank B0 is enabled, while the electrical path between the shared delay circuit 212 and the other memory banks B1 to Bm is disabled. In this way, the sense enable signal SE_B0 for the memory bank B0 is generated, and the start of the sense enable signal SE_B0 is delayed from the execution of the row active command ATV_B0 by the sense delay period. In addition, since the same shared delay circuit 212 is used to generate sense enable signals SE_B0 through SE_Bm, from the execution of row active commands ATV_B0 through ATV_Bm to the start of sense enable signals SE_B0 through SE_Bm The sensing delay period is the same regardless of any offset or mismatch present in the delay sensing circuit 210.
In some embodiments, a plurality of latches L0 through Lm are connected between delay path control circuit 214 and logic circuits X0 through Xm (eg, NOT logic circuits) and operate a latch to generate a latch signal. is configured to perform The latching signal may be provided to logic circuits X0 to Xm configured to perform a logic operation on the latching signal to output the sense enable signals SE_B0 to SE_Bm, respectively. In some alternative embodiments, latch signals output from latches L0 to Lm are used as sense enable signals to activate sense amplifier 130 . In other words, it is optional to include the logic circuits X0 to Xm in the sense delay circuit 210. Each of the latches L0 to Lm receives one of the signals ATV_B0_Dn to ATV_Bm_Dn and one of the pre-charge signals PCG_B0 to PCG_Bm, performs a latch operation based on the received signal, and detects One of the enable signals SE_B0 to SE_Bm may be generated. For example, the latch L0 performs a latching operation based on the signal ATV_B0_Dn received from the delay path control circuit 214_0_n-1 and the pre-charge signal PCG_B0 for generating the detection enable signal SE_B0. is configured to In some embodiments, each of latches L0 to Lm includes logic circuits NOR1 and NOR2, and logic circuit NOR1 receives one of the output of logic circuit NOR2 and pre-charge signals PCG_B0 to PCG_Bm. connected to do The logic circuit NOR2 is connected to receive the output of the logic circuit NOR1 and one of the ATV_B0_Dn to ATV_Bm_Dn signals.
In some embodiments, the sense enable signals SE_B0 through SE_Bm are activated on execution of signals ATV_B0_Dn through ATV_Bm_Dn and deactivated on execution of pre-charge signals PCG_B0 through PCG_Bm. For example, the latch L0 activates the sense enable signal SE_B0 when the signal ATV_B0_Dn is applied to the latch L0, and deactivates the sense enable signal SE_B0 when the precharge signal PCG_B0 is applied. is configured to In some embodiments, latches L0 through Lm are connected to logic circuits X0 through Xm (eg, NOT logic circuits), respectively, and logic operations (eg, NOT logic circuits) to generate sense enable signals SE_B0 through SE_Bm. For example, a NOT operation). In this way, sense enable signals SE_B0 through SE_Bm for memory banks B0 through Bm are generated by sense delay circuit 210, where sense enable signals from execution of row active commands ATV_B0 through ATV_Bm The sensing delay period SE_Bm until the beginning of (SE_B0 to SE_B0 to) is substantially the same.
FIG. 3 shows a schematic diagram of a delay path control circuit 214_x, which can be any one of delay path control circuits 214_0_0 to 214_m_n-1 of delay path control circuit 214 shown in FIG. The delay path control circuit 214_x includes a NOR logic circuit 2141, transistors M1 and M2, a buffer 2143, a NAND logic circuit 2145 and A NOT logic circuit 2147 may be included. In some embodiments, transistor M1 is connected between a reference node (GND) and a connection node (Nd), which is a connection node between transistors M1 and M2. The control terminal of transistor M1 is connected to the enable input terminal EN of delay path control circuit 214_x and is configured to receive one of the row active commands ATV_B0 to ATV_Bm. Transistor M1 is configured to electrically connect the reference node GND to the connection node Nd when one of the row activation commands ATV_B0 to ATV_Bm is executed at the enable input terminal EN.
In some embodiments, the NOR logic circuit 2141 is connected to the input terminals DIS0 through DISm of the delay path control circuit 214_x to provide other one of the row active commands ATV_B0 through ATV_Bm and memory banks B0 through Bm ( A precharge signal corresponding to one of the self bank precharge signals) is received. The NOR logic circuit 2141 is configured to perform a NOR logic operation on the signals of the input terminals DIS0 to DISm to generate an output signal, and to provide the output signal to the gate terminal of the transistor M2. Transistor M2 is connected between reference node VDD and connection node Nd to electrically connect reference node VDD to connection node Nd when an output signal from NOR logic circuit 2141 is executed. It consists of As such, the connection node (Nd) is electrically connected to the reference node (GND) when the signal at the enable input terminal (EN) is executed, and the connection node (Nd) is connected to any one of the signals of the input terminals (DIS0 to DISm). When one is running, it is electrically connected to the reference node (VDD).
In some embodiments, buffer 2143 includes NOT logic circuits 2143a and 2143b, where the input of NOT logic circuit 2143a is the output of NOT logic circuit 2143b and the input of NOT logic circuit 2143b. is the output of the NOT logic circuit 2143a. The buffer 2143 may be connected between the connection node Nd and the input terminal of the NAND 2145. In some embodiments, the input terminal of NAND logic circuit 2145 is connected to the delay input terminal (DLY_IN) of delay path control circuit 214_x and buffer 2143, and NAND logic circuit 2145 receives signal DLY_S1. and perform a NAND logic operation on the received signal to generate. A signal of the delay input terminal DLY_IN is one of delay signals Timing_D1 to Timing_Dn received from the shared delay circuit (eg, the shared delay circuit 212 of FIG. 2 ). The NAND logic circuit 2145 activates the signal DLY_S1 when the signal of the enable input terminal EN of the delay path control circuit 214_x is executed, and any one of the signals of the input terminals DIS0 to DISm. It is configured to deactivate the signal DLY_S1 when the signal is executed. In this way, the delay path control circuit 214_x can control the electrical path between the shared delay circuit (eg, the shared delay circuit 212 of FIG. 2 ) and the memory banks B0 to Bm. In some embodiments, NOT logic circuit 2147 performs a NOT logic operation on signal DLY_S1 output by NAND logic circuit 2145 to generate a signal at output terminal DLY_OUT of delay path control circuit 214_x. is configured to perform In some embodiments, the signal at the output terminal (DLY_OUT) of the delay path control circuit 214_x is delayed from execution of the signal at the enable input signal (EN) by the delay period.
FIG. 4 shows example waveforms of signals in a delay sensing circuit (eg, delay sensing circuit 210 of FIG. 2 ) when generating a sensing enable signal SE_B0, in accordance with some embodiments. Referring to FIGS. 2 and 4 , at timing t01, a row activation command (ATV_B0) having a pulse (P1_0) is applied to a memory bank (B0) of a memory device (eg, the memory device 100 of FIG. 1). to the sense delay circuit 210 to activate At timing t02, the pulse P2_0 of the delay signal Timing_D1 output from the delay unit 212_0 is applied to the delay path control circuit 214_0_0 and the delay unit 212_1. Delay path control circuit 214_0_0 is configured to generate signal ATV_B0_D1 having pulse P3_0; The delay unit 212_1 is configured to generate a delay signal Timing_D2 having a pulse P4_0 based on the delay signal Timing_D1. The period between the timings t01 and t02 is the delay period of the signal passing through the delay unit 212_0. Signal ATV_B0_D1 is delayed from row active command ATV_B0 by the time period of delay unit 212_0.
At timing t03, a delay signal Timing_D2 having a pulse P4_0 is outputted from the delay unit 212_1 to the delay path control circuit 214_0_1 and the delay unit 212_2 (not shown). Delay path control circuit 214_0_1 is configured to generate signal ATV_B0_D2 having pulse P5_0. The period between the timings t02 and t03 is the delay period of the signal passing through the delay unit 212_1; and signal ATV_B0_D2 is delayed by the time period of delay unit 212_1 in signal ATV_B0_D1.
Similarly, the signal ATV_B0_Dn of the pulse P6_0 is output from the delay path control circuit 214_0_n-1 at timing t04, and the detection enable signal SE_B0 of the pulse P7_0 is started at timing t5. . A period between timings t1 and t5 is a sensing delay period TD0 from execution of the row enable command ATV_B0 to the start of the sensing enable signal SE_B0. At timing t6, the detection enable signal SE_B0 is deactivated by the execution of the pre-charge signal PCG_B0 having a pulse P8_0. In this way, sense delay circuit 210 can generate sense delay signal SE_B0 for memory bank B0, where the start of sense delay signal SE_B0 is from execution of row active command ATV_B0. It is delayed by the delay period TD0.
FIG. 5 shows example waveforms of signals in a delay sensing circuit (eg, delay sensing circuit 210 of FIG. 2 ) when generating sense enable signals SE_B0 and SE_B1 , in accordance with some embodiments. 2 and 5, row activation commands (ATV_B0 and ATV_B1) for activating memory banks B0 and B1 are executed at timings t01 and t11, respectively. The period between the timings t01 and t11 must satisfy the active-active minimum command period (TRRD) of the memory device to ensure proper operation of the memory device. In response to execution of row enable commands ATV_B0 and ATV_B1, shared delay circuit 212 generates delay signals Timing_D1 through Timing_Dn for generation of both sense enable signals SE_B0 and SE_B1. For example, the delay signal Timing_D1 includes a pulse P2_0 for generating the sensing enable signal SE_B0 and a pulse P2_1 for generating the sensing enable signal SE_B1. Similarly, the delay signal Timing_D2 includes a pulse P4_0 for generating the sensing enable signal SE_B0 and a pulse P4_1 for generating the sensing enable signal SE_B1.
In some embodiments, the signal passing through each delay unit 212_0 through 212_n-1 is such that the length of the delay period is the length of TRRD to avoid collisions of multiple row active commands input to delay units 212_0 through 212_n-1. delayed by a shorter delay period. In some embodiments, delay path control circuit 214 is configured to generate pulses P3_0, P5_0, and P6_0 in signals ATV_B0_D1 through ATV_B0_Dn based on delay signals Timing_D1 through Timing_Dn. Similarly, delay path control circuit 214 is configured to generate pulses P3_1, P5_1 and P6_1 in signals ATV_B1_D1 through ATV_B1_Dn based on delay signals Timing_D1 through Timing_Dn. Signals ATV_B0_D1 to ATV_B0_Dn are for generating a sense enable signal SE_B0 for memory bank B0; The signals ATV_B1_D1 to ATV_B1_Dn are for generating the detection enable signal SE_B1 for the memory bank B1. Pulses P6_0 and P6_1 of signals ATV_B0_Dn and ATV_B1_Dn trigger the start of pulses P7_0 and P7_1 at timings t05 and t15, respectively. In other words, pulses P6_0 and P6_1 of the signals ATV_B0_Dn and ATV_B1_Dn trigger the start of the sense enable signals SE_B0 and SE_B1, respectively. Pulses P7_0 and P7_1 of the sense enable signals SE_B0 and SE_B1 end at timings t06 and t16, respectively.
In some embodiments, the sensing delay period TD0 from execution of the row enable command ATV_B0 at timing t01 to the start of the sense enable signal SE_B0 at timing t05 is the row active command at timing t11. The sensing delay period TD1 from the execution of (ATV_B1) to the start of the sensing enable signal SE_B1 at timing t15 is substantially the same.
6A-6B show a flow diagram of a method adapted for a memory device to generate a delayed activation signal, wherein the start of the sensed delay signal is delayed from execution of a row activation command by a sensed delay period, in accordance with some embodiments. In operation S610, a row activation command configured to activate a memory bank of a plurality of memory banks is received. In operation S620, the start of the sense enable signal is delayed by the sense delay circuit of the memory device by the sense delay period from execution of the row activation command. Operation S620 may include operations S621 and S623. In sub-operation S621, a plurality of delay signals are generated by the shared delay circuit of the sense delay circuit based on the execution of the row active command, where the shared delay circuit is shared for a plurality of memory banks. In operation S623, electrical paths between the shared delay circuit and the plurality of memory banks are controlled based on the row active command and the plurality of delay signals to output a sense enable signal to the memory banks.
According to the above embodiment, a memory device including a sense delay circuit including a shared delay path circuit and a delay path control circuit is introduced. The shared delay path circuitry is shared for all memory banks of the memory device. The sense delay circuit is configured to delay an initiation of a sense enable signal for a particular memory bank by a sense delay period from execution of a row activate command for that particular memory bank. In this way, the sense delay period for all memory banks of the memory device is substantially the same regardless of offsets or inconsistencies in the electronic components of the memory device due to variations during manufacturing. In other words, the same sensing delay period is achieved for all memory banks included in the memory device. Accordingly, an error rate of a memory operation such as a read operation or a write operation for a memory bank of the memory device is reduced, and performance of the memory device is improved.
It will be apparent to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations provided they come within the scope of the following claims and their equivalents.

Claims (16)

In the memory device,
a plurality of memory banks; and
sense delay circuit
including,
Each of the plurality of memory banks,
Activated by the row active command,
Each of the plurality of memory banks,
configured to perform a sensing operation based on a sensing enable signal;
The detection delay circuit,
configured to delay a start of the sense enable signal by a sense delay period from execution of the row active command;
The detection delay circuit,
a shared delay circuit, and
delay path control circuit
including,
The shared delay circuit,
configured to generate a plurality of delay signals based on the execution of the row active command;
The shared delay circuit,
Shared for the plurality of memory banks,
The shared delay circuit,
a plurality of delay units configured to generate the plurality of delay signals;
including,
Each of the plurality of delay units,
configured to delay the start of the detection enable signal by a delay period;
The delay path control circuit,
coupled to the shared delay circuit;
Control an electrical path between the shared delay circuit and the plurality of memory banks and the plurality of delay signals to output the sense enable signal to the memory bank based on the row active command;
The plurality of memory banks,
A first memory bank and a second memory bank activated by a first row activation command and a second row activation command, respectively.
including,
The delay period of each of the plurality of delay units is
less than the active-active minimum command period of the memory device;
The active-active minimum command period is
a minimum period of time between the execution of the first row activation instruction and the execution of the second row activation instruction;
memory device.
According to claim 1,
The sensing delay period from the execution of the row activation command to the start of the sensing enable signal is:
Determined according to the sum of the delay periods of the plurality of delay units
memory device.
According to claim 2,
The first memory bank and the second memory bank are configured to perform a sensing operation based on a first sensing enable signal and a second sensing enable signal, and
A first sense delay period from execution of the first row active command to the start of the first sense enable signal is a second sense delay period from execution of the second row active command to the start of the second sense enable signal. same as period
memory device.
delete According to claim 3,
The plurality of memory banks,
Activated by multiple row activation commands;
The delay path control circuit,
a plurality of delay path control circuits;
Each of the plurality of delay path control circuits,
an enable input terminal, configured to receive one of the plurality of row active commands;
a plurality of first input terminals configured to receive a pre-charge signal of another one of the plurality of row active commands and one of the plurality of memory banks;
a second input terminal connected to one of the plurality of delay units of the shared delay circuit and configured to receive the delay signal output by one of the plurality of delay units; and
An output terminal configured to output a delayed row active command based on one of the plurality of row active commands and the delay signal.
A memory device comprising a.
According to claim 5,
Each of the plurality of delay path control circuits,
a first transistor including a control terminal coupled to the enable input terminal for receiving one of the plurality of row active commands;
a first logic circuit coupled to the plurality of first input terminals and configured to perform a first logic operation on another one of the plurality of row active commands to generate a first logic signal;
a second transistor connected to the first logic circuit, the second transistor including a control terminal receiving the first logic signal output from the first logic circuit, and the second transistor comprising a connection node to the second transistor; connected to the first transistor -,
a second logic circuit coupled to the second input terminal and configured to perform a second logic operation on a delay signal from the second input signal and a signal at the connection node to generate a second logic signal; and
A third logic circuit connected to the second logic circuit and configured to perform a third logic operation on the second logic signal to generate the delay row active command.
A memory device comprising a.
According to claim 6,
the first logic circuit is a NOR logic circuit;
the second logic circuit is a NAND logic circuit;
The third logic circuit is a NOT logic circuit
memory device.
According to claim 5,
The plurality of delay path control circuits,
a first delay path control circuit and a second delay path control circuit;
The output terminal of the first delay path control circuit is
connected to an enable input terminal of the second delay path control circuit;
The second delay path control circuit,
Enabled or disabled according to the delay row active command output by the first delay path control circuit.
memory device.
According to claim 5,
The plurality of delay path control circuits,
a first group of delay path control circuitry, corresponding to the first memory bank, configured to control an electrical path between the shared delay circuit and the first memory bank in accordance with the first row active command; and
a second group of delay path control circuitry configured to control an electrical path between the shared delay circuit and the second memory bank according to the second row active command, corresponding to the second memory bank;
A memory device comprising a.
According to claim 9,
the first group of delay path control circuits is activated to form the electrical path between the shared delay circuit and the first memory bank according to the first row active command;
the first group of delay path control circuits are disabled upon execution of a pre-charge signal of the first memory bank or execution of another row activation command to activate another memory bank different from the first memory bank;
enable to form the electrical path between the shared delay circuit and the second memory bank according to the second row activation command of the second group of delay path control circuits;
The second group of delay path control circuits
Disabled according to execution of a pre-charge signal of the second memory bank or execution of another row activation command to activate another memory bank different from the second memory bank
memory device.
According to claim 10,
Each delay unit of the shared delay circuit is connected to one delay path control circuit of the first group of delay path control circuits and one delay path control circuit of the second group of delay path control circuits, and
The quantity of each delay path control circuit of the first group of delay path control circuits and of the second group of delay path control circuits is equal to the quantity of the delay unit of the shared delay circuit.
memory device.
According to claim 5,
a fourth logic operation configured to receive the plurality of row active commands, perform a fourth logical operation on the plurality of row active commands to generate a delay enable signal, and output the delay enable signal to the shared delay circuit; 4 logic circuits, and
a plurality of latch circuits connected to the delay path control circuit, configured to generate a sense enable signal for each of the plurality of memory banks based on an output of the delay path control circuit;
further comprising
memory device.
According to claim 1,
Each of the plurality of memory banks:
A sense amplifier configured to perform the sensing operation according to the sensing enable signal.
containing
memory device.
A method applied to a memory device including a plurality of memory banks and a sense delay circuit,
The plurality of memory banks,
A first memory bank and a second memory bank activated by a first row activation command and a second row activation command, respectively.
including,
The method,
receiving a row activate command configured to activate a memory bank of the plurality of memory banks; and
delaying, by the sensing delay circuit, the start of a sensing enable signal by a sensing delay period from execution of the row active command;
including,
The step of delaying the start of a sense enable signal by a sense delay period from execution of the row active command,
delaying, by each of a plurality of delay units, the start of the sense enable signal by a delay period;
generating, by a shared delay circuit of the sense delay circuit, a plurality of delay signals based on the execution of the row active command; and
controlling an electrical path between the shared delay circuit and the plurality of memory banks based on the row active command and the plurality of delay signals to output the sense enable signal to the memory bank;
including,
The shared delay circuit,
Shared for the plurality of memory banks,
The shared delay circuit,
the plurality of delay units
including,
The delay period of each of the plurality of delay units is
less than the active-active minimum command period of the memory device;
The active-active minimum command period is
a minimum period of time between the execution of the first row activation instruction and the execution of the second row activation instruction;
method.
According to claim 14,
The sensing delay period from the execution of the row active command to the start of the sensing enable signal is:
Determined according to the sum of the delay periods of the plurality of delay units
method.
According to claim 14,
Controlling an electrical path between the shared delay circuit and the plurality of memory banks comprises:
receiving one of a plurality of row active commands and controlling a first transistor based on one of the plurality of row active commands;
receiving another one of the plurality of row activation commands and performing a first logic operation on the other one of the plurality of row activation commands to generate a first logic signal;
controlling a second transistor based on the first logic signal, the second transistor being connected to the first transistor through a connection node;
performing a second logic operation on a delay signal of the plurality of delay signals and a signal of the connection node to generate a second logic signal; and
performing a third logic operation on the second logic signal to generate a delay row active command;
containing
method.

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