KR102471449B1 - Semiconductor structure and method of manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor structure comprising a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a major dimension perpendicular to a top surface of the semiconductor substrate in a cross-sectional view, and the major dimension and a semiconductor capping layer covering the insulator fins along the. A method of manufacturing a semiconductor structure is also provided in this disclosure.

Description

Semiconductor structure and its manufacturing method {SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME}

CROSS REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of previously filed Provisional Application Serial No. 62/772,994, filed on November 29, 2018 and incorporated by reference in its entirety.

In order to achieve an increase in circuit density of integrated circuits, the size of semiconductor devices such as field effect transistors in such integrated circuits has been reduced. However, if the size of the semiconductor device is reduced, the channel length of the semiconductor device may be reduced. When the channel length is reduced, the source and drain regions of the semiconductor device may come closer to each other, which may cause the source and drain regions to excessively influence the channel or rather the carriers in the channel, which is commonly referred to as short-channel effect. -channel effect). As a result, the gate of the semiconductor device experiencing the short-channel effect has reduced control over the channel, which in particular hinders the ability of the gate to control the on-state and/or off-state of the semiconductor device.

Several aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.
1 is a perspective view of a FinFET structure in accordance with some embodiments of the present disclosure.
2A is a cross-sectional view of a FinFET structure in accordance with some embodiments of the present disclosure.
2B is a cross-sectional view of a FinFET structure in accordance with some embodiments of the present disclosure.
3 is a perspective view of a FinFET structure in accordance with some embodiments of the present disclosure.
4 is a cross-sectional view of a FinFET structure in accordance with some embodiments of the present disclosure.
5A is a cross-sectional view of a FinFET structure according to some comparative embodiments of the present disclosure.
5B is a cross-sectional view of a FinFET structure according to some comparative embodiments of the present disclosure.
6-16 illustrate cross-sectional views of intermediate steps in an example fabrication process for forming a FinFET structure in accordance with some embodiments of the present disclosure.
17A is a cross-sectional view of a FinFET under various fabrication operations in accordance with some embodiments of the present disclosure.
17BA-17BB are cross-sectional views of FinFETs under various fabrication operations in accordance with some embodiments of the present disclosure.
17ca-17cb are cross-sectional views of FinFETs under various fabrication operations in accordance with some embodiments of the present disclosure.
18A is a cross-sectional view of a FinFET structure according to some comparative embodiments of the present disclosure.
18B is a cross-sectional view of a FinFET structure in accordance with some embodiments of the present disclosure.
19A is a cross-sectional view of a FinFET structure according to some comparative embodiments of the present disclosure.
19B is a cross-sectional view of a FinFET structure in accordance with some embodiments of the present disclosure.

The following description provides a number of different embodiments or examples for implementation of several different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These, of course, are merely various examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and the first and second features may not be in direct contact. It may also include embodiments in which additional features may be formed between the first and second features. Additionally, the disclosure may repeat reference numbers and/or letters in the various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatial relational terms such as "below" (eg, beneath, below, lower), "above" (eg, above, upper) refer to other element(s) or feature(s) as illustrated in the figures herein. It can be used for ease of explanation describing the relationship of an element or feature to a relationship. Spatial relational terms are intended to include other orientations of elements in use or operation other than the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relational descriptors used herein may be similarly interpreted accordingly.

Although numerical ranges and parameters representing the broad scope of this disclosure are approximations, numerical values presented in certain embodiments are reported as accurately as possible. Any numerical value, however, inherently contains certain errors resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the term “about” usually means within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean as considered by one skilled in the art. Except for operational/operational examples, or unless expressly stated otherwise, all numerical ranges, amounts, values and percentages (eg, amounts of materials, durations, temperatures, operating conditions, ratios of amounts, etc.) disclosed herein are all It should be understood as modified in all instances by the term "about". Accordingly, unless otherwise indicated, the numerical parameters presented in this disclosure and appended claims are approximate values that can vary as desired. At a minimum, each numerical parameter should be interpreted in light of at least the number of reported significant digits and applying conventional rounding techniques. A range can be expressed as from one endpoint to the other or between two endpoints. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints.

One or more semiconductor devices and techniques for forming such semiconductor devices are provided herein. A semiconductor device, such as a finned field effect transistor (FinFET), includes a fin formed on a semiconductor substrate. A gate structure surrounds at least a portion of the fin, eg, a channel within the top of the fin. A source region is formed in a first portion of the fin on a first side of the channel and a drain region is formed in a second portion of the fin on a second side of the channel. Because the gate structure is formed around the channel on multiple sides, the gate structure has relatively greater control over the channel and the carriers therein, for example with respect to a gate structure formed directly over the channel. With a reduced feature size, a FinFET with a channel length comparable to the depletion layer width can achieve full depletion. However, a FinFET with a channel length greater than the depletion layer width may still experience incomplete depletion at or above the threshold voltage during operation. As a result, a leakage current may be induced due to the short-channel effect. Typically, the fin width of a FinFET having a channel length greater than the depletion layer width may be reduced to achieve complete depletion in the channel during operation. Nevertheless, the carrier mobility decreases as the size of the gate-channel interface decreases.

Accordingly, the present disclosure provides a FinFET device that achieves full depletion in an active region or channel during operation. This effect does not shorten the channel length or reduce the pin width.

Silicon-on-insulator (SOI) technology improves performance by effectively reducing parasitic capacitance. To fully utilize the advantages of SOI technology when manufacturing FinFET devices, a fin-type insulator is designed on the substrate and a semiconductor film is constructed as a cap on top of the fin. In the present invention, a novel structure of FinFET on a fin-type insulator on a substrate is proposed in order to more surely combine the advantages of FinFET and SOI.

Referring to FIG. 1 , FIG. 1 is a perspective view of a FinFET structure 10 in accordance with some embodiments of the present disclosure. A substrate 101 having a dielectric layer 103 formed thereon is illustrated. The substrate 101 may be formed of silicon, for example. Although substrate 101 in FIG. 1 is illustrated as a bulk wafer containing a single material (eg, a bulk silicon wafer), in other examples, a semiconductor-on-insulator or silicon-on-insulator (SOI) wafer, or a glass substrate. this can be substituted. When such an SOI wafer is used, the dielectric layer 103 is an insulating layer (eg, oxide layer) formed between an upper silicon layer (not shown in FIG. 1) and a silicon base layer (eg, lower silicon layer) of the SOI wafer. can be

Any material suitable for the substrate 101 may be used, and the material for the substrate 101 may not be limited to silicon. For example, substrate 101 may be a bulk substrate that may include gallium arsenide, germanium, or any other material or combination of materials. Substrate 101 may also include other features or structures formed on substrate 101 or in substrate 102 . Dielectric layer 103 may include a dielectric material that allows etching of substrate 101 . In one example, substrate 101 may be single crystal silicon, and dielectric layer 103 may substantially include silicon nitride deposited over substrate 101 .

In a perspective view, a plurality of insulator fins 105 positioned over the dielectric layer 103 extend along the first direction 11 over the substrate 101 . As illustrated in FIG. 1 , the plurality of insulator fins 105 may be cores of a first stripe, where the cores are semiconductor caps from at least the top surface 105t and/or sidewalls 105s of the insulator fins 105 . or covered by the capping layer 107 . In combination, the insulator fins 105 and the capping layer 107 form a first stripe extending along a first direction 11 over the substrate 101 . A gate 109 crosses a plurality of insulator fins 105 along a second direction 12 above the substrate 101 . In some embodiments, the second direction 12 is substantially perpendicular to the first direction 11 . The gate 109 forms a second stripe extending along a second direction over the semiconductor substrate 101 . The second stripe is in contact with at least the capping layer 107 of the first stripe. In other words, the gate 109 is in contact with a portion of the capping layer 107 surrounding the top surface 105t and the sidewall 105s of each of the plurality of insulator fins 105 . In some embodiments, insulator fins 105 and dielectric layer 103 may be contiguous regions patterned from an insulator layer of an SOI wafer. In some embodiments, insulator fin 105 and dielectric layer 103 may be composed of an insulating material, a high-k dielectric material, or a semiconductor derivative such as SiO ₂ , HfO ₂ , SiOCN, or GeO.

In some embodiments, the capping layer is a crystalline, polycrystalline, or semi-crystalline semiconductor material such as Si, SiGe, Ge, another III-V material, or a two-dimensional material such as graphene, MoS ₂ , WSe ₂ , or HfTe ₂ . may consist of

In FIG. 1 , the second stripe or the first stripe exposed from the gate 109 or the combination of the insulator fin 105 and the capping layer 107 includes a source or drain (hereinafter referred to as an S/D region). In some embodiments, the S/D region may be a portion of the capping layer 107 exposed from the gate 109 and laterally adjacent to the gate 109 . In some embodiments, the S/D regions may be formed by an ion implantation operation or an etching operation followed by an epitaxial regrowth operation, as described below in this disclosure.

Referring to FIG. 2A , FIG. 2A is a cross-sectional view along line AA of a FinFET structure 10 in accordance with some embodiments of the present disclosure. In some embodiments, capping layer 107 illustrated in FIG. 2A is the S/D region of FinFET structure 10 . The plurality of insulator fins 105 each have a principal dimension A as opposed to a minor dimension B as illustrated in FIG. 2A. The principal dimension A is substantially perpendicular to the upper surface 101t of the substrate 101 . The capping layer 107 covers at least over the sidewall 105s along the major dimension A and the top surface 105t along the minor dimension B of the insulator fin 105 . The value of the major dimension (A) is measured from the top surface 105t of the insulator fin 105 to the bottom, and the value of the minor dimension (B) is measured from one sidewall of the insulator fin 105 to the opposite sidewall. In some embodiments, major dimension (A) ranges from about 5 nm to about 100 nm and minor dimension (B) ranges from about 2 nm to about 30 nm. When the major dimension (A) is greater than 100 nm, while the minor dimension (B) is within the above range, the insulator fin 105 has a high aspect ratio, so that the insulator fin 105 can be removed during a subsequent manufacturing process, for example , it is easy to deform or collapse during the formation of a poly gate over the plurality of insulator fins 105. When the major dimension (A) is less than 5 nm, while the minor dimension (B) is within the above range, the contact area between the capping layer 107 and the insulator fin 105 is too small to make the channel dimension of the FinFET device unreasonable. When the minor dimension (B) is greater than 30 nm, while the major dimension (A) is within the above range, the number of transistors per unit chip area is greatly reduced. If the minor dimension (B) is less than 2 nm, while the major dimension (A) is within this range, the insulator fin 105 will be liable to deform or collapse again during subsequent fabrication operations due to the aspect ratio being too large.

As illustrated in FIG. 2A, the thickness C of the capping layer 107 is determined such that a fully depleted region can be formed in the capping layer 107 under a predetermined operating bias. In some embodiments, the thickness C of the capping layer 107 may range from about 40 Å to about 20 nm. When the thickness C of the capping layer 107 is thicker than 20 nm, the number of transistors per unit chip area is greatly reduced. If the thickness C of the capping layer 107 is smaller than 40 Å, the crystallinity of the capping layer 107, which is a single-crystal epitaxial layer in some embodiments, may be reduced. In addition, capping layer 107 thinner than 40 Å may cause manufacturing difficulties in subsequent manufacturing operations, as further discussed in FIGS. 14 and 15 of the present disclosure.

A dielectric layer 103 is located between the bottom of the insulator fin 105 and the top surface of the substrate 101 . In some embodiments, dielectric layer 103 does not cover sidewalls of insulator fins 105 . Dielectric layer 103 is positioned between substrate 101 and a subsequently formed metal gate in contact with capping layer 107 . In other words, since the capping layer 107 does not contact the substrate 101, leakage current flowing into the substrate 101 is effectively reduced.

Referring to FIG. 2B , FIG. 2B is a cross-sectional view along line AA of a FinFET structure 10 in accordance with some embodiments of the present disclosure. In some embodiments, capping layer 107 illustrated in FIG. 2A is the S/D region of FinFET structure 10 . As illustrated in FIG. 2B , the capping layer 107 covers at least the sidewalls 105s along the major dimension A and the top surface 105t along the minor dimension B of the insulator fin 105 , and have. Values for the major dimension (A), minor dimension (B) and thickness (C) of the capping layer 107 may refer to those discussed in FIG. 2A and are not repeated here for brevity. The deposition of the capping layer 107 may not have the same thickness everywhere along the top surface 105t and sidewalls 105s of the insulator fin 105, for example, the rounded features of the capping layer 107 may It can be observed at the corner of (105). The thickness C of the capping layer 107 under this condition can be measured at the bottom of the capping layer 107 where the capping layer 107 contacts the dielectric layer 103.

3 is a perspective view of a FinFET structure in accordance with some embodiments of the present disclosure. Like numbers in FIGS. 3 and 1 indicate substantially the same components or equivalents thereof and may therefore be referred to as such. In FIG. 3 , an insulator fin 105 and a capping layer 107 are covered under the gate 109 . Compared to FIG. 1 , portions of the insulator fin 105 and the capping layer 107 exposed from the gate 109 are removed and replaced with a conductive region 110 configured as the S/D region of the FinFET structure 10 . A conductive region 110 is disposed over the substrate 101 along a first direction 11 and laterally adjacent to the gate 109 .

Referring to FIG. 4 , FIG. 4 is a cross-sectional view of a FinFET structure 10 in accordance with some embodiments of the present disclosure. The portion of the insulator fin 105 and capping layer 107 covered under the gate 109 as illustrated in FIG. 3 retains the cross-sectional views pre-treated in FIG. 2A or 2B and is not repeated here for brevity. However, the conductive region 110 configured as the S/D region in FIG. 3 has the cross-sectional view illustrated in FIG. 4 . In some embodiments, conductive region 110 may contact a top surface of substrate 101 . In some embodiments, dielectric layer 103 may isolate conductive region 110 from a top surface of substrate 101 .

5A and 5B , FIG. 5A is a cross-sectional view of a comparative FinFET structure and FIG. 5B is a cross-sectional view of a comparative FinFET structure according to some comparative embodiments of the present disclosure. Compared to the FinFET structures of the present disclosure, the FinFET structures illustrated in FIGS. 5A and 5B both include a plurality of semiconductor fins 505 and a dielectric layer 503 . The semiconductor fin 505 in FIG. 5A is patterned from the semiconductor substrate 501 so that the semiconductor fin 505 and the semiconductor substrate 501 form a continuous semiconductor region. A dielectric layer 503 is formed on the upper surface of the semiconductor substrate 501 to partially surround the semiconductor fins 505 . However, the semiconductor fin 505 in Figure 5b is patterned from the top semiconductor layer of the SOI wafer. The dielectric layer 503 of the SOI wafer is disposed between the bottom semiconductor layer of the SOI wafer and the semiconductor fin 505 to electrically insulate the semiconductor fin 505 from the semiconductor substrate 501 .

The two comparative embodiments illustrated in FIGS. 5A and 5 differ from embodiments of the present disclosure in that at least semiconductor fin 505 is constructed of a semiconductor material instead of an insulator. Semiconductor fin 505 is a bulk structure without a core and capping layer as described above in embodiments of the present disclosure.

The present disclosure provides methods of fabricating the FinFET structures described herein. Referring to FIGS. 6-16 , FIGS. 6-16 illustrate cross-sectional views of intermediate steps in an example fabrication process for forming a FinFET structure in accordance with some embodiments of the present disclosure. Referring to FIG. 6 , an upper insulating layer 62 is provided on a semiconductor substrate 60 . In some embodiments, semiconductor substrate 60 and insulating layer 62 may be part of an SOI wafer. In another embodiment, insulating layer 62 is deposited over the surface of semiconductor substrate 60 during a manufacturing operation. A hard mask layer 64 and an antireflective layer 66 are placed over the insulating layer 62 for subsequent patterning of the insulating layer 62 into the insulator fins 105 of FIG. 1 . A masking pattern layer 68 is positioned over the antireflective layer 66, and features of the masking pattern layer 68 are aligned with predetermined positions of the insulator fins on the semiconductor substrate 60.

In some embodiments, insulating layer 62 may be composed of an insulating material, a high-k dielectric material, or a semiconductor derivative such as SiO ₂ , HfO ₂ , SiOCN, or GeO. In some embodiments, the hard mask layer 64 may be composed of a material having physical and/or chemical properties distinct from those of the lower insulating layer 62, for example, a silicon nitride layer. In some embodiments, the antireflective layer 66 is an advanced patterning film (APF) 66A, a silicon oxynitride layer 66B, and an antireflective coating 66C deposited from the hard mask layer 64 to the masking pattern layer 68 . ) may be included. In some embodiments, masking pattern layer 68 may be a conventionally patterned photoresist layer.

In FIG. 7 , an etching process is performed to pattern the hard mask layer 64 . The remaining characteristics of the hard mask layer 64 follow those of the masking pattern layer 68 . Masking pattern layer 68 is then removed, along with APF 66A, silicon oxynitride layer 66B and antireflective coating 66C. In FIG. 8 , the patterned hard mask layer 64 ′ is subjected to different etching operations, eg dry etching operations, wet etching operations, to pattern the insulating layer 62 into insulator fins 63 and dielectric layer 603 . or a combination thereof. The etching operation performed to obtain the insulator fin 63 does not consume the entire thickness of the insulator layer 62 at the masked location. Instead, by implementing time mode etching, a continuous insulating material layer is intentionally preserved to form dielectric layer 603, or dielectric layer 103 of FinFET device 10 of FIG. 1, as described above. Then, as illustrated in FIG. 9, the patterned hard mask layer 64' is removed.

In Fig. 9, each of the plurality of insulator pins 63 has a major dimension A as opposed to a minor dimension B. Principal dimension A is substantially perpendicular to the top surface of the substrate 60 . In some embodiments, major dimension (A) ranges from about 5 nm to about 100 nm, and minor dimension (B) ranges from about 2 nm to about 30 nm. A threshold having a major dimension A and a minor dimension B within the above ranges may refer to FIG. 2A and is not repeated here for brevity. When viewed from a perspective view, the insulator fins 63 of FIG. 9 extend along the first direction 11 (see FIG. 1) over the semiconductor substrate 60 to form an insulator stripe.

In Fig. 10, as viewed from a perspective view, a capping layer 507 is continuously formed over the insulator fins 63, or in other words, continuously formed over the insulator stripes. The top surface 63t and sidewall 63s of the insulator fin 63 and the top surface of the dielectric layer 603 are covered by the deposited capping layer 507 . In some embodiments, capping layer 507 is crystalline, polycrystalline, or semi-crystalline, such as Si, SiGe, Ge, other group III-V materials, or two-dimensional materials such as graphene, MoS ₂ , WSe ₂ , or HfTe ₂ . It can be made of crystalline semiconductor material. In some embodiments, prior to depositing the capping layer material, the insulator fins 63 and the dielectric layer 603 undergo an annealing operation, followed by depositing a crystalline, polycrystalline or semi-crystalline semiconductor material as the capping layer 507 . Alternatively, in some embodiments, a capping layer material, regardless of its crystallinity state, is first deposited over the insulator fins 63 and dielectric layer 603, and then the capping layer material is transferred to a crystalline, polycrystalline or semi-crystalline phase. An annealing operation for crystallization is performed.

11 to 16 illustrate an operation of interrupting or blocking the capping layer 507 between adjacent insulator fins 63. In FIG. 11 , an insulating layer 1101 is a coating formed over the insulator fin 63 covered with a capping layer 507 . The insulating layer 1101 may conform to the shape of the lower insulating fin 63 . To obtain a flat top surface 1103 between the insulating layer 1101 and the portion of the capping layer 507 deposited over the top surface 63t of the insulator fin 63, a planarization operation, such as chemical mechanical polishing (CMP), is performed. ) is performed. In some embodiments, the insulating layer 1101 deposited therein may be composed of substantially the same material as the insulating layer 62 of FIG. 6 .

In FIG. 12 , a hard mask layer 1204 , an antireflective layer 1206 and a masking layer 1208 are formed over the planarized top surface 1103 for subsequent patterning of the capping layer 507 . A masking pattern layer 1208 is positioned over the anti-reflective layer 1206, and features of the masking pattern layer 1208 align with the locations of the insulator fins 63 on the semiconductor substrate 60.

In some embodiments, the hard mask layer 1204 may be composed of a material having different physical and/or chemical properties than the underlying insulating layer 1101 , for example a silicon nitride layer. In some embodiments, the antireflective layer 1206 is an advanced patterning film (APF) 1206A, a silicon oxynitride layer 1206B and an antireflective coating 1206C deposited from the hard mask layer 1204 to the masking pattern layer 1208. ) may be included. In some embodiments, masking pattern layer 1208 may be a conventionally patterned photoresist layer.

In FIG. 13 , an etching operation is performed to pattern the hard mask layer 1204 . The remaining characteristics of the hard mask layer 1204 follow those of the masking pattern layer 1208 . Masking pattern layer 68 is then removed, along with APF 1206A, silicon oxynitride layer 1206B and antireflective coating 1206C. In FIG. 14 , the patterned hard mask layer 1204 ′ is used in another etching operation to remove the insulating layer 1101 , such as a dry etching operation, a wet etching operation, or a combination thereof. The etching operation is stopped until the exposure of the capping layer 507 previously covered by the insulating layer 1101. An etching chemistry with sufficient material selectivity between the insulating layer 1101 and the capping layer 507 can be used. For example, an etchant that removes oxide material at least 10 times faster than it removes semiconductor material can be used in the etching operation of FIG. 14 .

As illustrated in FIG. 2A , capping layers thinner than 40 Å may increase fabrication difficulties in subsequent fabrication operations. For example, in the operation described in FIG. 12, if the capping layer 507 is thinner than 40 Å, the etchant selectivity is not sufficient to perform the etching operation without relatively consuming the thin capping layer 507. may not be As a result, the thin capping layer 507 can be completely consumed at various locations along the top surface 63t and sidewall 63s of the insulator fin 63, damaging the active region or channel of the FinFET device. As a result, it is required to deposit the capping layer 507 with an appropriate thickness, for example greater than 40 angstroms, in consideration of the etching process window or selectivity.

15, to remove a portion of the capping layer disposed on the upper surface of the dielectric layer 603, the patterned hard mask layer 1204' is subjected to another etch operation, such as a dry etch operation, a wet etch operation, or A combination of these is used. The etching operation is stopped until the exposure of the dielectric layer 603 previously covered by the capping layer 507. An etching chemistry with sufficient material selectivity between the dielectric layer 603 and the capping layer 507 may be used. For example, an etchant that removes semiconductor material at least 10 times faster than it removes dielectric material can be used in the etching operation of FIG. 15 . As illustrated in Figure 16, the patterned hard mask layer 1204' is then removed. Gates 609 are formed across a plurality of insulator fins 63 after cutting the capping layer 507 between adjacent insulator fins 63 . When viewed from a perspective view, the gate 609 appears as a gate stripe extending along the second direction on the semiconductor substrate. Gate 609 may include a polysilicon gate or an alternate gate (eg, a metal gate). The second direction 12 may be substantially perpendicular to the first direction 11 as already illustrated in FIG. 1 .

17a, 17ba, 17bb, 17ca and 17cb are cross-sectional views of FinFETs under various manufacturing operations in accordance with some embodiments of the present disclosure. In FIG. 17A , a conductive region 1701 representing the portion of the capping layer 507 not covered by the gate 609 and laterally adjacent to the gate 609 is formed by an ion implantation operation 1703 . For example, a portion of the capping layer 507 is ion-implanted in an amount sufficient to form a source or drain region on the insulator fin 63 . An appropriate annealing operation may be performed after the implant operation in the portion of the capping layer 507 .

17BA and 17BB, the originally deposited capping layer 507 is removed by an etch operation similar to that disclosed in FIG. 15 but without the patterned hard mask layer 1204' followed by epitaxial regrowth to obtain the desired regrowth material or conductivity. A conductive region 1701 is formed with a material. The regrowth material or conductive material may be different from the original capping layer material. The regrowth material or conductive material includes, but is not limited to, SiGe, SiC, Ge, graphene, MoS ₂ , WSe ₂ or HfTe ₂ or combinations thereof. In some embodiments, the insulator fins 63 and the dielectric layer 603 are subjected to an annealing operation prior to depositing the regrowth material or the conductive material, and then depositing the crystalline, polycrystalline or semi-crystalline semiconductor material as the conductive region. Alternatively, in some embodiments, the regrowth material or conductive material, regardless of its crystallinity state, is first deposited over the insulator fins 63 and dielectric layer 603 and then subjected to an annealing operation to make the regrowth material or conductive material crystalline, Crystallizes in a polycrystalline or semi-crystalline phase. When the regrowth material or conductive material is joined, an appropriate etching operation may be performed to cut the regrowth material or conductive material from adjacent insulator fins 63 . The conductive region 1701' can be grown to have several facets (not shown) or a rounded surface as illustrated in FIG. 17B.

17ca and 17cb, the originally deposited capping layer 507 and the original insulator fin 63 are removed by an etching operation, and then the conductive region 1701 is formed with a desired regrowth material or conductive material by an epitaxial regrowth operation. is formed Capping layer 507 and insulator fin 63 may be partially or entirely removed. As illustrated in FIG. 17ca, the capping layer 507 and the removed portions of the insulator fins 63 form a recess 1705 indicated by dotted lines, or the recess 1705 can be seen along the insulator stripe in a perspective view. can A regrowth material or conductive material is then deposited and filled into the recess 1705 to obtain a conductive region 1701' as illustrated in Figure 17cb. In some embodiments, the dielectric layer 603 underlying the recess 1705 may also be removed in another lithography operation to expose the underlying semiconductor substrate 60 . Thereafter, a regrowth material or a conductive material may be epitaxially grown on the exposed semiconductor substrate 60 .

The regrowth material or conductive material may be different from the original capping layer material. The regrowth material or conductive material includes, but is not limited to, SiGe, SiC, Ge, graphene, MoS ₂ , WSe ₂ or HfTe ₂ or combinations thereof. In some embodiments, if dielectric layer 603 under recess 1705 is not removed prior to the regrowth operation, dielectric layer 603 may, following an annealing process, form a crystalline, polycrystalline or semi-crystalline semiconductor material into a conductive region ( 1701), the deposition operation is performed. Alternatively, in some embodiments, the regrowth material or conductive material, regardless of its crystallinity state, is first deposited over the dielectric layer 603 and then subjected to an annealing operation to convert the regrowth material or conductive material into a crystalline, polycrystalline, or semi-crystalline phase. crystallize When the regrowth material or conductive material is combined, an appropriate etching operation may be performed to cut the regrowth material or conductive material in the adjacent conductive region 1701 . The conductive region 1701 can be grown to have multiple facets as illustrated in FIG. 17C″ or to have a rounded surface as illustrated in FIG. 17BB.

Referring to Figures 18a and 18b, Figure 18a is a cross-sectional view of a comparative FinFET structure, and Figure 18b is a cross-sectional view of the FinFET of this embodiment. By using the FinFET structures of the present disclosure, FinFET structures 180A and 180B having the same fin width F1, eg, 8 nm, can have different threshold voltages. The hatched regions associated with fin structures 1805 and 1805' indicate depletion regions created under corresponding critical biases. To achieve full depletion in FinFET structure 180A, threshold voltage Vt1 is required to deplete carriers from the entire semiconductor fin 1805 having fin width F1, for example. To achieve full depletion of the FinFET structure 180B, a threshold voltage (Vt2) is required to deplete carriers from the capping layer 1807' over the insulator fin 1805', and the capping layer 1807' and the insulator The width of the fin 1805' constitutes, for example, the fin width F1. The threshold voltage Vt2 applied to FinFET structure 180B is substantially lower than the threshold voltage Vt1 applied to FinFET structure 180A.

Referring to FIGS. 19A and 19B , FIG. 19A is a cross-sectional view of a comparative FinFET structure, and FIG. 19B is a cross-sectional view of the FinFET of this embodiment. By using the FinFET structures of the present disclosure, FinFET structures 190A and 190B having the same fin width F2 of, for example, 16 nm can have different depletion degrees. The hatched regions associated with fin structures 1905 and 1905' indicate depletion regions created under predetermined biases. When a predetermined bias is applied to the FinFET structure 190A, the semiconductor fin 1905 creates a depletion region on the top surface and sidewall of the semiconductor fin 1905, but the semiconductor fin 1905 is not fully depleted, so a short channel Leakage may occur as a result. Upon application of a predetermined bias to FinFET structure 190B, semiconductor fin 1905' creates a depletion region in capping layer 1907' over insulator fin 1905', and the capping layer achieves full depletion by prevent leaks from occurring.

Some embodiments of the present disclosure provide a semiconductor structure comprising: a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a major dimension perpendicular to a top surface of the semiconductor substrate in a cross-sectional view, and a major dimension and a semiconductor capping layer covering the insulator fin along the surface.

Some embodiments of the present disclosure provide a semiconductor structure comprising a semiconductor substrate, a first stripe extending along a first direction and a second stripe extending along a second direction substantially perpendicular to the first direction. includes The first stripe includes an insulator core and a semiconductor cap covering the upper surface and sidewalls of the insulator core. The second stripe contacts the semiconductor cap of the first stripe.

Some embodiments of the present disclosure provide a method of fabricating a semiconductor structure. The method includes patterning an insulator stripe over a semiconductor substrate, successively depositing a semiconductor capping layer over the insulator stripe, and cutting the semiconductor capping layer between the insulator stripes.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Skilled artisans should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. In addition, those skilled in the art should be aware that equivalent configurations may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure, and without departing from the spirit and scope of the present disclosure.

Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods and steps described herein. Those skilled in the art will, from the disclosure of this invention, recognize existing or later developed processes, machines, manufactures, compositions of matter, means, or devices that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein. It will be readily appreciated that methods or steps may be utilized in accordance with the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions of matter, means, methods or steps.

Examples

Example 1. As a semiconductor structure,

semiconductor substrate;

an insulator fin over the semiconductor substrate, the insulator fin having a principal dimension perpendicular to the top surface of the semiconductor substrate in cross-sectional view; and

a semiconductor capping layer covering the insulator fin along the major dimension;

A semiconductor structure comprising a.

Embodiment 2. The semiconductor structure according to Embodiment 1, wherein the semiconductor capping layer further covers an upper surface of the insulator fin.

Embodiment 3. The semiconductor structure of Embodiment 2, further comprising a gate in contact with the capping layer along a major dimension of the insulator fin at the top surface.

Embodiment 4. The semiconductor structure of Embodiment 1, further comprising an insulator layer between the insulator fin and the semiconductor substrate.

Example 5. The semiconductor structure according to Example 1, wherein the insulator fin comprises SiO ₂ , HfO ₂ , SiOCN or GeO.

Example 6. The semiconductor structure according to Example 1, wherein the semiconductor capping layer includes Si, Ge, SiGe, graphene, MoS ₂ , WSe ₂ or HfTe ₂ .

Example 7. As a semiconductor structure,

semiconductor substrate;

A first stripe extending along a first direction - the first stripe,

insulator core; and

a semiconductor cap covering the upper surface and sidewall of the insulator core; and

A second stripe extending along a second direction perpendicular to the first direction and contacting the semiconductor cap of the first stripe.

A semiconductor structure comprising a.

[0083] [0042] [0041] [0024] [0018] [0019] [0019] [0019] [0018] [0018] [0018] [0019] [0019] [0019] [0019] [0019] [0019] [0019] [0018] [0019] [0017] [0018] [0018] [0027] [0117] The semiconductor structure of Embodiment 7, wherein the thickness of the semiconductor cap allows formation of a fully depleted region within the semiconductor cap under a predetermined bias.

[0080] [0082] [0042] [0044] [0042] [0043] [0043] [0044] [0041] [0042] [0042] [0048] [0043] [0048] [0043] [0043] [0043] [0048] [0048] [0042] [0038] Embodiment 9. The semiconductor structure of Embodiment 7, wherein the semiconductor cap comprises a crystalline material.

Example 10. The semiconductor structure of example 7, further comprising an insulating layer between the first stripe and the semiconductor substrate.

Example 11. The semiconductor structure of example 7 further comprising a conductive region within the semiconductor cap of the first stripe, wherein the conductive region abuts the second stripe.

Example 12. A method for manufacturing a semiconductor structure,

patterning an insulator stripe over a semiconductor substrate;

successively depositing a semiconductor capping layer over the insulator stripe; and

cutting the semiconductor capping layer between the insulator stripes;

Including, a method of manufacturing a semiconductor structure.

Example 13. The method of example 12, further comprising annealing the insulator stripe prior to depositing the semiconductor capping layer.

Example 14. The method of example 12, further comprising annealing the semiconductor capping layer after depositing the semiconductor capping layer over the insulator stripe.

Example 15. The step of cutting the semiconductor capping layer according to Example 12,

forming an insulating layer on the semiconductor capping layer;

leveling the insulating layer with an upper surface of the semiconductor capping layer; and

removing the insulating layer until the semiconductor capping layer between the insulator stripes is exposed;

A method of manufacturing a semiconductor structure comprising a.

Example 16. According to Example 12,

patterning a gate stripe over the insulator stripe and the semiconductor capping layer after cutting the semiconductor capping layer.

Example 17. According to Example 16,

forming a conductive region in a portion of the semiconductor capping layer not covered by the gate stripe by an implantation operation.

Example 18. According to Example 16,

and forming a conductive region in a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.

Example 19. The regrowth operation according to Example 18,

removing a portion of the semiconductor capping layer to expose the insulator stripe; and

forming a conductive layer covering the exposed insulator stripe;

A method of manufacturing a semiconductor structure comprising a.

Example 20. The regrowth operation according to Example 18,

forming a recess by removing a portion of the semiconductor capping layer and a portion of the insulator stripe; and

forming a conductive layer within the recess;

A method of manufacturing a semiconductor structure comprising a.

Claims (10)

As a semiconductor structure,
a semiconductor substrate including a gate region;
an insulator fin over the semiconductor substrate, the insulator fin having a principal dimension perpendicular to the top surface of the semiconductor substrate in cross-sectional view;
a semiconductor capping layer comprising a crystalline material and covering an upper surface of the insulator fin and the insulator fin along the major dimension; and
a gate structure - the gate structure in physical contact with the semiconductor capping layer at the top surface and along a major dimension of the insulator fin over the gate region, and a first portion of the semiconductor capping layer covered by the gate structure is configured as a channel structure -
wherein a second portion of the semiconductor capping layer adjacent to the first portion and covering the insulator fin is configured as a source/drain region, and the second portion of the semiconductor capping layer is exposed from the gate structure and adjacent to the gate structure;
wherein the bottom surfaces of the insulator fin, the semiconductor capping layer and the gate structure are at the same level. The semiconductor structure of claim 1 , wherein the thickness of the semiconductor capping layer allows formation of a fully depleted region in the semiconductor capping layer under a predetermined bias. The semiconductor structure of claim 1 , further comprising a conductive region within the semiconductor capping layer, the conductive region being adjacent to the gate structure. The semiconductor structure of claim 1 , further comprising an insulator layer between the insulator fin and the semiconductor substrate. The semiconductor structure according to claim 1 , wherein the insulator fin comprises SiO ₂ , HfO ₂ , SiOCN or GeO. The semiconductor structure of claim 1 , wherein the semiconductor capping layer includes Si, Ge, SiGe, graphene, MoS ₂ , WSe ₂ or HfTe ₂ . As a semiconductor structure,
a semiconductor substrate including a gate region;
A first stripe extending along a first direction - the first stripe,
insulator core; and
a semiconductor cap covering an upper surface and sidewalls of the insulator core and including a crystalline material; and
A second stripe extending along a second direction perpendicular to the first direction and contacting the semiconductor cap of the first stripe.
including,
The second stripe is configured as a gate structure, and the first portion of the semiconductor cap covered by the second stripe is configured as a channel structure, the semiconductor cap adjacent to the first portion and covering the insulator core. The second part is configured as a source/drain region,
The semiconductor structure of claim 1 , wherein the bottom surfaces of the insulator core, the semiconductor cap, and the gate structure are at the same level. 8. The semiconductor structure of claim 7, wherein the thickness of the semiconductor cap allows formation of a fully depleted region within the semiconductor cap under a predetermined bias. 8. The semiconductor structure of claim 7, further comprising a conductive region within the semiconductor cap of the first stripe, wherein the conductive region is adjacent to the second stripe. As a method of manufacturing a semiconductor structure,
patterning an insulator stripe over a semiconductor substrate, wherein an insulator layer is disposed between the insulator stripe and the semiconductor substrate;
continuously depositing a semiconductor capping layer including a crystalline material on the insulator stripe;
cutting the semiconductor capping layer between the insulator stripes; and
patterning a gate stripe over the insulator stripe and the semiconductor capping layer after cutting the semiconductor capping layer;
including,
The gate stripe is in direct contact with the semiconductor capping layer, and a first portion of the semiconductor capping layer covered by the gate stripe is configured as a channel structure, and the semiconductor adjacent to the first portion and covering the insulator stripe. The second part of the capping layer is configured as a source/drain region,
at least a portion of the insulator layer is not under the cladding of the semiconductor capping layer, and the semiconductor capping layer is not in direct contact with the semiconductor substrate;
wherein the bottom surfaces of the insulator stripe, the semiconductor capping layer and the gate stripe are at the same height.

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